M5M44260CJ-6S

M5M44260CJ MITSUBISHI | Alldatasheet

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FAST PAGE MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM M5M44260CJ,TP-5,-6,-7,-5S,-6S,-7S MITSUBISHI LSIs M5M44260CJ,TP-5,-5S : Under development This is a family of 262144-word by 16-bit dynamic RAMs, fabricated with the high performance CMOS process, and is ideal for memory systems where high speed, low power dissipation, and low costs are essential. The use of double-layer metalization process technology and a single-transistor dynamic storage stacked capacitor cell provide high circuit density at reduced costs. Multiplexed address inputs permit both a reduction in pins and an increase in system densities. Self or extended refresh current is small enough for battery back-up application. This device has 2CAS and 1W terminals with a refresh cycle of 512 cycles every 8.2ms.

DESCRIPTION

FEATURES

Standard 40pin SOJ, 44 pin TSOP (II) Single 5V±10% supply Low stand-by power dissipation CMOS Input level 5.5mW (Max) CMOS Input level 550µW (Max) * Operating power dissipation M5M44260Cxx-5,-5S 688mW (Max) M5M44260Cxx-6,-6S 605mW (Max) M5M44260Cxx-7,-7S 523mW (Max) Self refresh capability * Self refresh current 150µA (Max) Extended refresh capability Extended refresh current 150µA (Max) Fast-page mode (512-column random access), Read-modify-write, RAS-only refresh, CAS before RAS refresh, Hidden refresh capabilities. Early-write mode, LCAS / UCAS and OE to control output buffer impedance 512 refresh cycles every 8.2ms (A0~A 8) 512 refresh cycles every 128ms (A0~A 8) * Byte or word control for Read/Write operation (2CAS, 1W type) * : Applicable to self refresh version (M5M44260CJ,TP-5S,-6S,-7S : option) only XX=J,TP Type name access time (max.ns) RAS access time (max.ns) CAS (max.ns) access time Address time (min.ns) Cycle dissipa- (typ.mW) Power tion M5M44260CXX-7,-7S M5M44260CXX-6,-6S 60 110 130 550 475 access time (max.ns) OE M5M44260CXX-5,-5S 50 13 25 90 62513 APPLICATION Microcomputer memory, Refresh memory for CRT PIN CONFIGURATION (TOP VIEW) DQ 1 (5V)VCC VSS (0V) NC W RAS UCAS OE Outline 40P0K (400mil SOJ) DQ 2 DQ 3 DQ 4 DQ 5 DQ 6 DQ 7 DQ 8 (5V)VCC (5V)VCC NC NC LCAS NC DQ 12 DQ 11 DQ 10 DQ 9 VSS (0V) DQ 16 DQ 15 DQ 14 DQ 13 VSS (0V) DQ 1 (5V)VCC VSS (0V) NC W RAS UCAS OE Outline 44P3W-R (400mil TSOP Nomal Bend) DQ 2 DQ 3 DQ4 DQ 5 DQ 6 DQ 7 DQ 8 (5V)VCC (5V)VCC NC NC LCAS NC DQ 12 DQ 11 DQ 10 DQ 9 VSS (0V) DQ 16 DQ 15 DQ 14 DQ 13 VSS (0V) NC: NO CONNECTION FAST PAGE MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM M5M44260CJ,TP-5,-6,-7, -5S,-6S,-7S MITSUBISHI LSIs PIN DESCRIPTION Pin name A0~A 8 DQ 1~DQ 16 RAS UCAS W OE VCC VSS Function Address inputs Data inputs / outputs Row address strobe input Upper byte control column address strobe input Write control input Power supply (+5V) Ground (0V) Output enable input Lower byte control column address strobe inputLCAS

FAST PAGE MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM M5M44260CJ,TP-5,-6,-7,-5S,-6S,-7S MITSUBISHI LSIs M5M44260CJ,TP-5,-5S : Under development ROW DECODER ROW & COLUMN ADDRESS BUFFER A0~A 8 A0~ (8)LOWER DATA IN BUFFER (8)LOWER DATA OUT BUFFER (8)UPPER DATA IN BUFFER (8)UPPER DATA OUT BUFFER FUNCTION In addition to normal read,write and read-modify-write operations the M5M44260CJ, TP provides a number of other functions, e.g., Table 1 Input conditions for each mode fast page mode, RAS-only refresh and delayed-write. The input conditions for each are shown in Table 1. Note : ACT : active, NAC : nonactive, DNC : don' t care, OPN : open Operation Lower byte read Upper byte read Word read Lower byte write Upper byte write RAS only refresh Self refresh * Word write CAS before RAS (Extended *) refresh RAS LCAS OE Inputs Input/Output W DQ 1~ DQ8 DQ 9~ DQ16 ACT ACT ACT ACT ACT ACT ACT NAC ACT NAC ACT ACT NAC ACT NAC DNC NAC NAC NAC ACT ACT ACT DNC DNC ACT ACT ACT NAC NAC NAC DNC DNC D OUT OPN D OUT D IN DNC D IN OPN OPN OPN D OUT D OUT DNC D IN D IN OPN OPN ACT ACT DNC DNC OPN OPN Stand-by ACT DNC DNC OPN D OUT UCAS NAC ACT ACT NAC ACT ACT NAC DNC ACT ACT ACT Hidden refresh ACT ACT ACTACT D OUT OPN Row address Column address APD APD APD APD APD DNC DNC DNC APD APD APD APD DNC DNC DNC DNC DNC DNC Refresh Remark DNC APD APD APD APD YES YES YES YES YES YES YES YES YES YES No Fast page mode identical BLOCK DIAGRAM ADDRESS INPUTS CLOCK GENERATOR CIRCUIT COLUMN DECODER SENSE REFRESH AMPLIFIER & I /O CONTROL MEMORY CELL (4194304 BITS) VCC (5V) VSS (0V) DQ9 OE DQ10 DQ16 UPPER DATA INPUTS / OUTPUTS OUTPUT ENABLE INPUT LOWER BYTE CONTROL COLUMN ADDRESS STROBE INPUT ROW ADDRESS STROBE INPUT WRITE CONTROL INPUT LCAS W RAS UCAS UPPER BYTE CONTROL COLUMN ADDRESS STROBE INPUT LOWER UPPER DQ 1 DQ 2 DQ 8 LOWER DATA INPUTS / OUTPUTS VCC (5V) VSS (0V) VCC (5V) VSS (0V)

FAST PAGE MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM M5M44260CJ,TP-5,-6,-7,-5S,-6S,-7S MITSUBISHI LSIs M5M44260CJ,TP-5,-5S : Under development3 ABSOLUTE MAXIMUM RATINGS Symbol VCC V I VO I O Pd Topr Tstg Parameter Conditions Ratings Unit V V V mA mW -1~7 1000 0~70 -65~150 With respect to VSS Ta=25˚C Supply voltage Input voltage Output voltage Output current Power dissipation Operating temperature Storage temperature -1~7 -1~7 RECOMMENDED OPERATING CONDITIONS Unit Limits Min Nom Max V V V V 0.8 5.5 2.4 -0.5 * * Parameter Supply voltage Supply voltage High-level input voltage, all inputs Low-level input voltage, all inputs VCC Symbol VSS VIH VIL Note 1 : All voltage values are with respect to VSS. 5.04.5 6.0 (Ta=0~70˚C, unless otherwise noted) (Note 1) * *: VIL(min) is -2.0V when pulse width is less than 25ns. (Pulse width is with respect to Vss.) Note 2: Current flowing into an IC is positive, out is negative. 3: ICC1 (AV), ICC3 (AV), ICC4 (AV), and ICC6 (AV) are dependent on cycle rate. Maximum current is measured at the fastest cycle rate. 4: ICC1 (AV) and ICC4 (AV) are dependent on output loading. Specified values are obtained with the output open. 5: Column Address can be changed once or less while RAS=VIL and CAS=VIH. ELECTRICAL CHARACTERISTICS (Ta=0~70˚C , VCC =5V±10%, VSS =0V, unless otherwise noted) (Note 2) Symbol VOH VOL IOZ I I ICC1(AV) ICC2 ICC3(AV) ICC4(AV) ICC6(AV) High-level output voltage Parameter Limits Min Max UnitTypTest conditions Low-level output voltage Off-state output current Input current Average supply current from Vcc, operating (Note 3,4,5) (Note 3,5) (Note 3,4,5) Supply current from VCC , stand-by Average supply current from Vcc, RAS only refresh mode Average supply current from Vcc Fast page mode Average supply current from Vcc CAS before RAS refresh mode M5M44260C-5,-5S M5M44260C-6,-6S M5M44260C-7,-7S IOH =-5mA IOL =4.2mA Q floating 0V ≤ VOUT ≤ 5.5V 0V ≤ VIN ≤ +6.0V, Other inputs pins=0V RAS, CAS cycling tRC =tWC =min. output open RAS= CAS =V IH, output open RAS cycling, CAS=VIH tRC =min. output open RAS=V IL, CAS cycling tPC =min. output open CAS before RAS refresh cycling tRC =min. output open V V mA mA mA mA mA VCC 0.4 1.0 115 100 2.4 -10 -10 125 110 (Note 6) 125 110 125 110 M5M44260C-5,-5S M5M44260C-6,-6S M5M44260C-7,-7S M5M44260C-5,-5S M5M44260C-6,-6S M5M44260C-7,-7S M5M44260C-5,-5S M5M44260C-6,-6S M5M44260C-7,-7S Average supply current from VCC Extended-refresh mode µA150 Average supply current from VCC Self-refresh mode RAS=CAS ≤ 0.2V output open µA150 (Note 6) RAS= CAS ≥ VCC -0.5V output open 0.1 * µA µA ICC8(AV) * ICC9(AV) * RAS cycling CAS ≤ 0.2V or CAS before RAS refresh cycling RAS ≤ 0.2V or ≥ VCC -0.2V CAS ≤ 0.2V or ≥ VCC -0.2V W ≤ 0.2V or ≥ VCC -0.2V OE ≤ 0.2V or ≥ VCC -0.2V A0~A8 ≤ 0.2V or ≥ VCC -0.2V, DQ=open tRC =250µs, tRAS =tRAS min~1µs (Note 3,5) (Note 6)

FAST PAGE MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM M5M44260CJ,TP-5,-6,-7,-5S,-6S,-7S MITSUBISHI LSIs M5M44260CJ,TP-5,-5S : Under development4 Note 6: An initial pause of 500 µs is required after power-up followed by a minimum of eight initialization cycles (RAS-only refresh or CAS before RAS refresh cycles). Note the RAS may be cycled during the initial pause. And 8 initialization cycles are required after prolonged periods (greater than 8.2ms) of RAS inactivity before proper device operation is achieved. 7: Measured with a load circuit equivalent to 2TTL loads and 100pF. 8: Assumes that tRCD ≥ tRCD(max) and tASC ≥ tASC(max) . 9: Assumes that tRCD ≤ tRCD(max) and tRAD ≤ tRAD(max) . If tRCD or tRAD is greater than the maximum recommended value shown in this table, tRAC will increase by amount that tRCD exceeds the value shown. 10: Assumes that tRAD ≥ tRAD(max) and tASC ≤ tASC(max) . 11: Assumes that tCP ≤ tCP(max) and tASC ≥ tASC(max) . 12: tOFF(max) and tOEZ (max) defines the time at which the output achieves the high impedance state (IOUT ≤ ±10 µA ) and is not reference to VOH(min) or VOL(max). SWITCHING CHARACTERISTICS (Ta=0~70˚C, VCC =5V±10%, Vss=0V, unless otherwise noted, see notes 6,13,14) Limits Min Max Parameter Access time from CAS Access time from RAS Columu address access time Symbol tCAC Unit Min Max Min Max ns ns ns ns ns ns5 60tRAC tAA tCPA tOEA tCLZ Access time from CAS precharge Output low impedance time from CAS low Output disable time after CAS high (Note 7,8) (Note 7,9) (Note 7,10) (Note 7,11) (Note 7) (Note 12) tOFF tOEZ (Note 12) (Note 7) Output disable time after OE high Access time from OE ns ns M5M44260C-5,-5S M5M44260C-6,-6S M5M44260C-7,-7S CAPACITANCE Limits Min Max UnitTyp pF pF pF Input capacitance, address inputsC I (A) C I (CLK) C I / O Symbol Parameter Test conditions Input capacitance, clock inputs Input/Output capacitance, data ports VI=VSS f=1MHz VI=25mVrms (Ta=0~70˚C , VCC =5V±10%, VSS =0V, unless otherwise noted)

FAST PAGE MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM M5M44260CJ,TP-5,-6,-7,-5S,-6S,-7S MITSUBISHI LSIs M5M44260CJ,TP-5,-5S : Under development Read and Refresh Cycles Note 21: Either tRCH or tRRH must be satisfied for a read cycle. Limits Min Max Parameter Read cycle time RAS low pulse width CAS low pulse width Symbol tRC Unit Min Max Min Max ns ns ns ns ns ns tRAS tCAS tCSH tRSH tRCS CAS hold time after RAS low Read setup time before CAS low Read hold time after CAS high (Note 21)tRCH tRRH ns ns tRAL tOCH tORH RAS hold time after CAS low Read hold time after RAS high Column address to RAS hold time CAS hold time after OE low RAS hold time after OE low ns ns ns 10000 10000 10000 10000 10000 10000 110 130 (Note 21) M5M44260C-5,-5S M5M44260C-6,-6S M5M44260C-7,-7S Limits Min Max Parameter Refresh cycle time RAS high pulse width Delay time, RAS low to CAS low Symbol tREF Unit Min Max Min Max ms ns ns ns ns ns tRP tRCD tCRP tRPC tCPN Delay time, CAS high to RAS low Delay time, RAS high to CAS low CAS high pulse width (Note 19) (Note 15) (Note 16) (Note 17) ns ns ns ns ns ns tRAD tASR tASC tRAH tCAH tT Column address delay time from RAS low Row address setup time before RAS low Column address setup time before CAS low Row address hold time after RAS low Column address hold time after CAS low Transition time TIMING REQUIREMENTS (For Read, Write, Read-Modify-Write, Refresh and Fast-Page Mode Cycles) (Note 18) (Note 18)Delay time, data to CAS low Delay time, data to OE low Delay time, CAS high to data Delay time, OE high to data tDZC tDZO tCDD tODD ns ns ns ns Note 13: The timing requirements are assumed tT =5ns. 14: VIH(min) and VIL(max) are reference levels for measuring timing of input signals. 15: tRCD(max) is specified as a reference point only. If tRCD is less than tRCD(max) , access time is tRAC . If tRCD is greater than tRCD(max ), access time is controlled exclusively by tCAC or tAA . 16: tRAD(max) is specified as a reference point only. If tRAD ≥ tRAD(max) and tASC ≤ tASC(max ), access time is controlled exclusively by tAA . 17: tASC(max) is specified as a reference point only. If tRCD ≥ tRCD(max) and tASC ≥ tASC(max) , access time is controlled exclusively by tCAC . 18: Either tDZC or tDZO must be satisfied. 19: Either tCDD or tODD must be satisfied. 20: tT is measured between VIH(min) and VIL(max). (Ta=0~70˚C, VCC =5V±10%, VSS =0V, unless otherwise noted, see notes 6,13,14) (Note 19) (Note 20) M5M44260C-5,-5S M5M44260C-6,-6S M5M44260C-7,-7S 8.2 8.2 8.2 mstREF Refresh cycle time * 128 128 128

FAST PAGE MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM M5M44260CJ,TP-5,-6,-7,-5S,-6S,-7S MITSUBISHI LSIs M5M44260CJ,TP-5,-5S : Under development Read-Write and Read-Modify-Write Cycles Note 22: tRWC is specified as tRWC(min) =tRAC(max) +tODD(min)+tRWL(min)+tRP(min)+4tT. 23: tWCS , tCWD , tRWD and tAWD and tCPWD are specified as reference points only. If tWCS ≥ tWCS(min) the cycle is an early write cycle and the DQ pins will remain high impedance throughout the entire cycle. If tCWD ≥ tCWD(min) , tRWD ≥ tRWD(min) , tAWD ≥ tAWD(min) and tCPWD ≥ tCPWD(min) (for fast page mode cycle only), the cycle is a read-modify-write cycle and the DQ will contain the data read from the selected address. If neither of the above condition (delayed write) of the DQ (at access time and until CAS or OE goes back to VIH) is indeterminate. Limits Min Max Parameter Read write/read modify write cycle time RAS low pulse width CAS low pulse width Symbol tRWC Unit Min Max Min Max ns ns ns ns ns ns tRAS tCAS tCSH tRSH tRCS CAS hold time after RAS low RAS hold time after CAS low Read setup time before CAS low (Note 22) (Note 23) ns ns ns ns ns tCWD tRWD tAWD tCWL tRWL Delay time, CAS low to W low Delay time, RAS low to W low Delay time, address to W low Write pulse width Data setup time before CAS low or W low Data hold time after CAS low or W low OE hold time after W low tWP tDS tDH tOEH 1513 20 ns ns ns ns CAS hold time after W low RAS hold time after W low 10000 10000 10000 1000010000 100 100 150 126 120 120 180 (Note 23) (Note 23) M5M44260C-5,-5S M5M44260C-6,-6S M5M44260C-7,-7S Write Cycle (Early Write and Delayed Write) Limits Min Max Parameter Write cycle time RAS low pulse width CAS low pulse width Symbol tWC Unit Min Max Min Max ns ns ns ns ns ns tRAS tCAS tCSH tRSH tWCS CAS hold time after RAS low Write setup time before CAS low Write hold time after CAS low (Note 23) tWCH tCWL ns ns tRWL tWP tDS RAS hold time after CAS low CAS hold time after W low ns ns ns 10000 10000 10000 10000 10000 10000 ns ns 110 tDH tOEH RAS hold time after W low OE hold time after W low Data setup time before CAS low or W low Data hold time after CAS low or W low Write pulse width 130 M5M44260C-5,-5S M5M44260C-6,-6S M5M44260C-7,-7S 10000

FAST PAGE MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM M5M44260CJ,TP-5,-6,-7,-5S,-6S,-7S MITSUBISHI LSIs M5M44260CJ,TP-5,-5S : Under development Fast-Page Mode Cycle (Read, Early Write, Read -Write, Read-Modify-Write Cycle) (Note 24) Note 24: All previously specified timing requirements and switching characteristics are applicable to their respective fast page mode cycle. 25: tRAS(min) is specified as two cycles of CAS input are performed. 26: tCP(max) is specified as a reference point only. Limits Min Parameter Fast page mode read/write cycle time RAS low pulse width for read or write cycle CAS high pulse width Symbol tPC Unit Min Max Min Max ns ns ns ns ns ns tPRWC tRAS tCP tCPRH tCPWD RAS hold time after CAS precharge (Note 25) (Note 26) Delay time, CAS precharge to W low (Note 23) Fast page mode read write/read modify write cycle time 100000 115 100 M5M44260C-5,-5S M5M44260C-6,-6S M5M44260C-7,-7S 100000 Max 100000 CBR self refresh RAS low pulse widthtRASS µs tRPS tCHS 100100 110 -50 100 -50 130 -50 CBR self refresh RAS high precharge time CBR self refresh CAS hold time Self Refresh Cycle * (Note 28) CAS before RAS Refresh Cycle, Extended Refresh Cycle * (Note 27) Limits Min Max Parameter CAS setup time before RAS low Symbol tCSR Unit Min Max Min Max ns nstCHR 10CAS hold time after RAS low Note 27: Eight or more CAS before RAS cycles instead of eight RAS cycles are necessary for proper operation of CAS before RAS refresh mode. M5M44260C-5,-5S M5M44260C-6,-6S M5M44260C-7,-7S Limits Min Max ParameterSymbol Unit Min Max Min Max ns ns ns20 20 25tCAS CAS low pulse width M5M44260C-5,-5S M5M44260C-6,-6S M5M44260C-7,-7S

FAST PAGE MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM M5M44260CJ,TP-5,-6,-7,-5S,-6S,-7S MITSUBISHI LSIs M5M44260CJ,TP-5,-5S : Under development8 Timing Diagrams (Note 29) Read Cycle tCRP tASR tRAH tRAD tRCD tCSH tASC tCAH tRCS tRAS tRC tRSH tCAS tRAL tCAC tAA tCLZ tRAC tOFF tRCH tRRH tASR tRP Hi-ZHi-Z ROW ADDRESS DATA VALID Note 29 Indicates the don't care input. VIH(min) ≤ VIN ≤ VIH(max) or VIL(min) ≤ VIN ≤ VIL(max) Indicates the invalid output. tDZC Hi-Z tOEZ tODD tOEA tOCH tDZO tCDD tORH tRPC tCRP LCAS/UCAS DQ 1~DQ 16 (INPUTS) RAS W DQ 1~DQ 16 (OUTPUTS) OE A0~A8 VIH VIL VOH VOL VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL ROW ADDRESS COLUMN ADDRESS

FAST PAGE MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM M5M44260CJ,TP-5,-6,-7,-5S,-6S,-7S MITSUBISHI LSIs M5M44260CJ,TP-5,-5S : Under development Byte Read Cycle tCRP tASR tRAH tRAD tRCD tCSH tASC tCAH tRCS tRAS tRC tRSH tCAS tRAL tRAC tRCH tRRH tASR tRP Hi-Z tOEZ tODDtOEA tOCH tDZO tORH tCAC tAA tCLZ tOFF Hi-ZHi-Z tDZC Hi-Z tCDD tRPC tCRP tCPN UCAS (or LCAS) DQ 1~DQ 8 (or DQ9~DQ 16) (INPUTS) LCAS (or UCAS) DQ 1~DQ 8 (or DQ9~DQ 16) (OUTPUTS) DQ 9~DQ 16 (or DQ1~DQ 8) (INPUTS) DQ 9~DQ 16 (or DQ1~DQ 8) (OUTPUTS) RAS W OE A0~A 8 VIH VIL VOH VOL VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VOH VOL ROW ADDRESS ROW ADDRESS DATA VALID COLUMN ADDRESS

FAST PAGE MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM M5M44260CJ,TP-5,-6,-7,-5S,-6S,-7S MITSUBISHI LSIs M5M44260CJ,TP-5,-5S : Under development Write Cycle (Early write) tCRP tASR tRAH tRCD tCSH tASC tCAH tWCS tRAS tWC tRSH tCAS tWCH tASR tRP Hi-Z COLUMN ADDRESS ROW ADDRESS DATA VALID tDS tDH tRPC tCRP tCPN LCAS/UCAS DQ 1~DQ 16 (INPUTS) RAS W DQ 1~DQ 16 (OUTPUTS) OE A0~A 8 VIH VIL VOH VOL VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL ROW ADDRESS

FAST PAGE MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM M5M44260CJ,TP-5,-6,-7,-5S,-6S,-7S MITSUBISHI LSIs M5M44260CJ,TP-5,-5S : Under development Byte Write Cycle (Early write) tCRP tASR tRAH tRCD tCSH tASC tCAH tWCS tRAS tWC tRSH tCAS tWCH tASR tRP Hi-Z COLUMN ADDRESS ROW ADDRESS DATA VALID tDS tDH Hi-Z tRPC tCRP tCPN UCAS (or LCAS) DQ 1~DQ 8 (or DQ9~DQ 16) (INPUTS) LCAS (or UCAS) DQ 1~DQ 8 (or DQ9~DQ 16) (OUTPUTS) DQ 9~DQ 16 (or DQ1~DQ 8) (INPUTS) DQ 9~DQ 16 (or DQ1~DQ 8) (OUTPUTS) RAS W OE A0~A8 VIH VIL VOH VOL VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VOH VOL ROW ADDRESS

FAST PAGE MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM M5M44260CJ,TP-5,-6,-7,-5S,-6S,-7S MITSUBISHI LSIs M5M44260CJ,TP-5,-5S : Under development Write Cycle (Delayed write) tCRP tASR tRAH tRCD tCSH tASC tCAH tRCS tRAS tWC tRSH tCAS tASR tRP Hi-Z ROW ADDRESS DATA VALID tCLZ tWCH tCWL tRWL tDHtDS Hi-Z Hi-Z tWP tDZC tOEZtDZO tODD tOEH tRPC tCRPtCPN LCAS/UCAS DQ 1~DQ 16 (INPUTS) RAS W DQ 1~DQ 16 (OUTPUTS) OE A0~A 8 VIH VIL VOH VOL VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL ROW ADDRESS COLUMN ADDRESS

FAST PAGE MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM M5M44260CJ,TP-5,-6,-7,-5S,-6S,-7S MITSUBISHI LSIs M5M44260CJ,TP-5,-5S : Under development Byte Write Cycle (Delayed write) tCRP tASR tRAH tRCD tCSH tASC tCAH tRCS tRAS tWC tRSH tCAS tASR tRP Hi-Z COLUMN ADDRESS ROW ADDRESS DATA VALID tCLZ tWCH tCWL tRWL tDHtDS Hi-Z Hi-Z tDZC tOEZtDZO tODD tOEH Hi-Z tRPC tCRP tCPN UCAS (or LCAS) DQ 1~DQ 8 (or DQ9~DQ 16) (INPUTS) LCAS (or UCAS) DQ 1~DQ 8 (or DQ9~DQ 16) (OUTPUTS) DQ 9~DQ 16 (or DQ1~DQ 8) (INPUTS) DQ 9~DQ 16 (or DQ1~DQ 8) (OUTPUTS) RAS W OE A0~A8 VIH VIL VOH VOL VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VOH VOL tWP ROW ADDRESS

FAST PAGE MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM M5M44260CJ,TP-5,-6,-7,-5S,-6S,-7S MITSUBISHI LSIs M5M44260CJ,TP-5,-5S : Under development Read-Write, Read-Modify-Write Cycle tCRP tASR tRAH tRCD tCSH tASC tCAH tRCS tRAS tRWC tRSH tCAS tASR tRP Hi-Z COLUMN ADDRESS ROW ADDRESS DATA VALID tCLZ tCWL tRWL tDHtDS Hi-Z Hi-Z tWP tDZC tOEZ tDZO tODD tOEH tAWD tCWD tRWD DATA VALID tAA tCAC tRAC tOEA tRAD tRPC tCRP LCAS/UCAS DQ 1~DQ 16 (INPUTS) RAS W DQ 1~DQ 16 (OUTPUTS) OE A0~A 8 VIH VIL VOH VOL VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL ROW ADDRESS

FAST PAGE MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM M5M44260CJ,TP-5,-6,-7,-5S,-6S,-7S MITSUBISHI LSIs M5M44260CJ,TP-5,-5S : Under development Byte Read-Write, Read-Modify-Write Cycle tCRP tASR tRAH tRCD tCSH tASC tCAH tRCS tRAS tRWC tRSH tCAS tASR tRP Hi-Z COLUMN ADDRESS ROW ADDRESS DATA VALID tCLZ tCWL tRWL tDH tDS Hi-Z Hi-Z tWP tDZC tOEZ tDZO tODD tOEH tAWD tCWD tRWD DATA VALID tAA tCAC tRAC tOEA tRAD Hi-Z tRPC tCRP tCPN UCAS (or LCAS) DQ 1~DQ 8 (or DQ9~DQ 16) (INPUTS) LCAS (or UCAS) DQ 1~DQ 8 (or DQ9~DQ 16) (OUTPUTS) DQ 9~DQ 16 (or DQ1~DQ 8) (INPUTS) DQ 9~DQ 16 (or DQ1~DQ 8) (OUTPUTS) RAS W OE A0~A 8 VIH VIL VOH VOL VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VOH VOL ROW ADDRESS

FAST PAGE MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM M5M44260CJ,TP-5,-6,-7,-5S,-6S,-7S MITSUBISHI LSIs M5M44260CJ,TP-5,-5S : Under development RAS-only Refresh Cycle tCRP tASR tRAH tRAS tRC tASR tCRPtRPC tRP ROW ADDRESS Hi-Z LCAS/UCAS DQ 1~DQ 16 (INPUTS) RAS W DQ 1~DQ 16 (OUTPUTS) OE A0~A8 VIH VIL VOH VOL VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL ROW ADDRESS

FAST PAGE MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM M5M44260CJ,TP-5,-6,-7,-5S,-6S,-7S MITSUBISHI LSIs M5M44260CJ,TP-5,-5S : Under development CAS before RAS Refresh Cycle, Extended Refresh Cycle * tRAS tRC tASR tCRPtRPC tRP ROW COLUMN ADDRESSADDRESS tRPC tRC tRAS tCSR tCHR tCSRtRPC tCPN tRCH tRCS tOFF Hi-Z tOEZ tRP tCHR tCDD tODD Hi-Z LCAS/UCAS DQ 1~DQ 16 (INPUTS) RAS W DQ 1~DQ 16 (OUTPUTS) OE A0~A 8 VIH VIL VOH VOL VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL

FAST PAGE MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM M5M44260CJ,TP-5,-6,-7,-5S,-6S,-7S MITSUBISHI LSIs M5M44260CJ,TP-5,-5S : Under development18 Hidden Refresh Cycle (Read) (Note 30) Note 30: Early write, delayed write, read write or read modify write cycle is applicable instead of read cycle. Timing requirements and output state are the same as that of each cycle described above. tCRP tASR tRAH tRAD tRCD tCAH tRCS tRAS tRC tCHR tCAC tAA tCLZ tRAC tOFF tRRH tASR tRP Hi-Z COLUMN ADDRESS ROW ADDRESS DATA VALID tRAS tRC tRP tRSH tASC tRAL Hi-Z tDZC tCDD Hi-Z tDZO tOEA tORH tODD tOEZ LCAS/UCAS DQ 1~DQ 16 (INPUTS) RAS W DQ 1~DQ 16 (OUTPUTS) OE A0~A 8 VIH VIL VOH VOL VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL ROW ADDRESS

FAST PAGE MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM M5M44260CJ,TP-5,-6,-7,-5S,-6S,-7S MITSUBISHI LSIs M5M44260CJ,TP-5,-5S : Under development Fast Page Mode Read Cycle tCRP tASR tRAH tRAD tRCD tCAH tRCS tRAS tCP tCAC tAA tCLZ tRAC tOFF Hi-Z ROW ADDRESS tASR tRP tCAS tASC Hi-Z tDZC tDZO tOEA tOCH tCSH tPC tCAS tCP tCAS tRSH tCAHtASC tCAHtASC tRCH tRCStRCH tRCH tRRH tDZC tCDD Hi-Z tOFF tAA DATA VALID-2 tCLZ tCAC DATA VALID-3 tAA tCLZ tCAC tOFF tCPA tOEZ tOCH tOEA tCPA tOEA tOEZ tODD tOCH tORHtDZOtODD tOEZ tDZOtODD tDZC tRCS tCPRH Hi-Z Hi-Z Hi-Z LCAS/UCAS DQ 1~DQ 16 (INPUTS) RAS W DQ 1~DQ 16 (OUTPUTS) OE A0~A 8 VIH VIL VOH VOL VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL ROW ADDRESS tRAL DATA VALID-1 COLUMN ADDRESS1 COLUMN ADDRESS3 COLUMN ADDRESS2

FAST PAGE MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM M5M44260CJ,TP-5,-6,-7,-5S,-6S,-7S MITSUBISHI LSIs M5M44260CJ,TP-5,-5S : Under development Fast Page Mode Byte Read Cycle tCRP tASR tRAH tRAD tRCD tCAH tRAS tCP tCAC tAA tCLZ tRAC tOFF tASR Hi-Z COLUMN ROW ADDRESS DATA VALID-1 tRP tCAS tASC Hi-Z tDZO tOEA tOCH tCSH tPC tCAS tCP tCAS tRSH COLUMN tCAHtASC tCAH tRCH tRCH tRAL tRCH tDZC tDZC tCDD Hi-Z tOFF tAA DATA VALID-2 tCLZ tCAC DATA VALID-3 tAA tCLZ tCAC tOFF tCPA tOEZ tOCH tOEA tCPA tOEA tOEZ tODD tOCH tORHtDZOtODD tOEZ tDZOtODD ADDRESS1 ADDRESS2 Hi-Z tCPRH tASC ROW ADDRESS UCAS (or LCAS) DQ 1~DQ 8 (or DQ9~DQ 16) (INPUTS) LCAS (or UCAS) DQ 1~DQ 8 (or DQ9~DQ 16) (OUTPUTS) DQ 9~DQ 16 (or DQ1~DQ 8) (INPUTS) DQ 9~DQ 16 (or DQ1~DQ 8) (OUTPUTS) RAS W OE A0~A 8 VIH VIL VOH VOL VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VOH VOL COLUMN ADDRESS3 tRCS tRRHtRCS tDZC tRCS

FAST PAGE MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM M5M44260CJ,TP-5,-6,-7,-5S,-6S,-7S MITSUBISHI LSIs M5M44260CJ,TP-5,-5S : Under development Fast Page Mode Write Cycle (Early Write) tCRP tASR tRAH tRCD tCAH tWCS tRAS tCP tASR Hi-Z tRP tCAS tASC tCSH tPC tCAS tCP tCAS ADDRESS COLUMN ROW ADDRESS ROW COLUMN ADDRESS2 COLUMN tCAHtASC tCAHtASC tWCH tRSH tWCH tWCS tWCStWCH DATA VALID-1 DATA VALID-2 DATA VALID-3 tDS tDH tDS tDH tDS tDH ADDRESS1 ADDRESS3 LCAS/UCAS DQ 1~DQ 16 (INPUTS) RAS W DQ 1~DQ 16 (OUTPUTS) OE A0~A 8 VIH VIL VOH VOL VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL

FAST PAGE MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM M5M44260CJ,TP-5,-6,-7,-5S,-6S,-7S MITSUBISHI LSIs M5M44260CJ,TP-5,-5S : Under development Fast Page Mode Byte Write Cycle (Early Write) tCRP tASR tRAH tRCD tCAH tWCS tRAS tCP tASR Hi-Z tRP tCAS tASC tCSH tPC tCAS tCP tCAS tRSH ADDRESS ROW ADDRESS ROW tCAHtASC tCAHtASC tWCHtWCH tWCS tWCStWCH DATA VALID-1 DATA VALID-2 DATA VALID-3 tDS tDH tDS tDH tDS tDH Hi-Z COLUMN COLUMN ADDRESS2 COLUMN ADDRESS1 ADDRESS3 UCAS (or LCAS) DQ 1~DQ 8 (or DQ9~DQ 16) (INPUTS) LCAS (or UCAS) DQ 1~DQ 8 (or DQ9~DQ 16) (OUTPUTS) DQ 9~DQ 16 (or DQ1~DQ 8) (INPUTS) DQ 9~DQ 16 (or DQ1~DQ 8) (OUTPUTS) RAS W OE A0~A 8 VIH VIL VOH VOL VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VOH VOL

FAST PAGE MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM M5M44260CJ,TP-5,-6,-7,-5S,-6S,-7S MITSUBISHI LSIs M5M44260CJ,TP-5,-5S : Under development Fast-Page Mode Write Cycle (Delayed Write) tCRP tASR tRAH tRCD tCAH tRAS tCP tASR Hi-Z tRP tCAS tASC tCSH tPC tCAS tRSH ADDRESS COLUMN ROW ADDRESS ROW tCAHtASC tRCS tWCH DATA VALID-1 tDZC tDS COLUMN tRWL tCWL tWP tRCS tWP tCWL Hi-Z Hi-Z tDHtDS tDZC tWCH DATA VALID-2 tDH Hi-Z Hi-Z tCLZ tCLZ tDZO tOEZ tODD tDZO tOEZ tODD tOEH ADDRESS1 ADDRESS2 LCAS/UCAS DQ 1~DQ 16 (INPUTS) RAS W DQ 1~DQ 16 (OUTPUTS) OE A0~A 8 VIH VIL VOH VOL VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL

FAST PAGE MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM M5M44260CJ,TP-5,-6,-7,-5S,-6S,-7S MITSUBISHI LSIs M5M44260CJ,TP-5,-5S : Under development Fast-Page Mode Byte Write Cycle (Delayed Write) tCRP tASR tRAH tRCD tCAH tRAS tCP tASR Hi-Z tRP tCAS tASC tCSH tPC tCAS tRSH ADDRESS ROW ADDRESS ROW tCAHtASC tRCS tWCH DATA VALID-1 tDZC tDS tRWL tCWL tWP tRCS tWP tCWL Hi-Z Hi-Z tDH tDS tDZC tWCH DATA VALID-2 tDH Hi-Z Hi-Z tCLZ tCLZ tDZO tOEZ tODD tDZO tOEZ tODD tOEH Hi-Z UCAS (or LCAS) DQ 1~DQ 8 (or DQ9~DQ 16) (INPUTS) LCAS (or UCAS) DQ 1~DQ 8 (or DQ9~DQ 16) (OUTPUTS) DQ 9~DQ 16 (or DQ1~DQ 8) (INPUTS) DQ 9~DQ 16 (or DQ1~DQ 8) (OUTPUTS) RAS W OE A0~A 8 VIH VIL VOH VOL VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VOH VOL COLUMN ADDRESS2 COLUMN ADDRESS1

FAST PAGE MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM M5M44260CJ,TP-5,-6,-7,-5S,-6S,-7S MITSUBISHI LSIs M5M44260CJ,TP-5,-5S : Under development Fast Page Mode Read-Write, Read-Modify-Write Cycle tCRP tASR tRAH tRCD tCAH tRAS tCP tASR Hi-Z tRP tCAS tASC tCSH tPRWC tCAS tRWL ADDRESS COLUMN ROW ADDRESS ROW tCAHtASC tRCS tRWD DATA VALID-1 tDZC tDS tCWL tWP tRCS tWP tCWL Hi-Z Hi-Z tDHtDS tDZC tCPWD DATA VALID-2 tDH Hi-Z Hi-Z tCLZ tDZO tOEZ tODD tDZO tOEZ tOEH tRAD tCWD tAWD tAWD tCWD tAA tCAC DATA VALID-1 tAA tCAC DATA VALID-2 tCLZ tRAC tOEA tCPA tOEA tODD ADDRESS1 LCAS/UCAS DQ 1~DQ 16 (INPUTS) RAS W DQ 1~DQ 16 (OUTPUTS) OE A0~A 8 VIH VIL VOH VOL VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL COLUMN ADDRESS2

FAST PAGE MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM M5M44260CJ,TP-5,-6,-7,-5S,-6S,-7S MITSUBISHI LSIs M5M44260CJ,TP-5,-5S : Under development Fast Page Mode Byte Read-Write, Read-Modify-Write Cycle tCRP tASR tRAH tRCD tCAH tRAS tCP tASR Hi-Z tRP tCAS tASC tCSH tPRWC tCAS tRWL ADDRESS ROW ADDRESS ROW tCAHtASC tRWD DATA VALID-1 tDS tCWL tWPtWP tCWL Hi-Z Hi-Z tDS tCPWD DATA VALID-2 tDH Hi-Z Hi-Z tCLZ tDZO tOEZ tODD tDZO tOEZ tOEH tRAD tCWD tAWD tAWD tCWD tCAC DATA VALID-1 tAA tCAC DATA VALID-2 tCLZ tRAC tOEA tCPA tOEA tODD Hi-Z tDZC UCAS (or LCAS) DQ 1~DQ 8 (or DQ9~DQ 16) (INPUTS) LCAS (or UCAS) DQ 1~DQ 8 (or DQ9~DQ 16) (OUTPUTS) DQ 9~DQ 16 (or DQ1~DQ 8) (INPUTS) DQ 9~DQ 16 (or DQ1~DQ 8) (OUTPUTS) RAS W OE A0~A 8 VIH VIL VOH VOL VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VOH VOL COLUMN COLUMN ADDRESS1 ADDRESS2 tRCStRCS tDHtDZC tAA

FAST PAGE MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM M5M44260CJ,TP-5,-6,-7,-5S,-6S,-7S MITSUBISHI LSIs M5M44260CJ,TP-5,-5S : Under development Self Refresh Cycle * (Note28) tRPC tRPS tASR tCRP ROW COLUMN ADDRESSADDRESS tRASS tCSR tCPN tRCH tRCS tOFF Hi-Z tOEZ tRP tCHS tRPC Hi-Z tCDD tODD LCAS/UCAS DQ 1~DQ 16 (INPUTS) RAS W DQ 1~DQ 16 (OUTPUTS) OE A0~A 8 VIH VIL VOH VOL VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL

FAST PAGE MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM M5M44260CJ,TP-5,-6,-7,-5S,-6S,-7S MITSUBISHI LSIs M5M44260CJ,TP-5,-5S : Under development Switching from read/write operation to self refresh operation. The time interval from the falling edge of RAS signal in the last CBR refresh cycle during read/write operation period to the falling edge of RAS signal at the start of self refresh operation should be set within tNSD (shown in table 2). Note 28 : Self refresh sequence Two refreshing methods should be used properly depending on the low pulse width (tRASS ) of RAS signal during self refresh period. 1. Distributed refresh during Read/Write operation (A) Timing Diagram Read / Write Cycle Self Refresh Cycle Read / Write Cycle tNSD tRASS ≥100µs tSND last refresh cycle first refresh cycle Table 2 Definition of CBR distributed refresh (Including extended refresh) Switching from self refresh operation to read/write operation. The time interval from the rising edge of RAS signal at the end of self refresh operation to the falling edge of RAS signal in the first CBR refresh cycle during read/write operation period should be set within tSND (shown in table 2). Switching from read/write operation to self refresh operation. The time interval tNSD from the falling edge of RAS signal in the last RAS only refresh cycle during read/write operation period to the falling edge of RAS signal at the start of self refresh operation should be set within 16µs. Switching from self refresh operation to read/write operation. The time interval tSND from the rising edge of RAS signal at the end of self refresh operation to the falling edge of RAS signal in the first CBR refresh cycle during read/write operation period should be set within 16µs. RAS Read / Write Cycle CBR distributed refresh RAS only distributed refresh Read / Write Self Refresh tNSD ≤16µs tSND ≤16µs (B) Definition of distributed refresh tREF tREF / 512 refresh cycle read/write cycles RAS tREF / 512 read/write cycles refresh cycle refresh cycle Note: Hidden refresh may be used instead of CBR refresh. RAS/CAS refresh may be used instead of RAS only refresh.

1.1 CBR distributed refresh

1.2 RAS only distributed refresh

The CBR distributed refresh performs more than 512 constant period (250µs max.) CBR cycles within 128 ms. All combinations of nine row address signals (A0~A8) are selected during 512 constant period (16µs max.) RAS only refresh cycles within 8.2 ms. Definition of RAS only distributed refresh tNSD ≤250µs tSND ≤250µs Self Refresh Read / Write

FAST PAGE MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM M5M44260CJ,TP-5,-6,-7,-5S,-6S,-7S MITSUBISHI LSIs M5M44260CJ,TP-5,-5S : Under development All combination of nine row address signals (A0~A8) are selected during 512 continuous RAS only refresh cycles within 8.2 ms. 2. Burst refresh during Read/Write operation (A) Timing diagram Read / Write Self Refresh Read / Write tNSB tRASS ≥100µs tSNB last refresh Cycles first refresh cycles Table 3 Read / Write Cycle CBR burst refresh RAS only burst refresh tNSB +tSNB ≤8.2ms Definition of CBR burst refresh Switching from read/write operation to self refresh operation. The time interval tNSB from the falling edge of RAS signal in the first CBR refresh cycle during read/write operation period to the falling edge of RAS signal at the start of self refresh operation should be set within 8.2 ms. Switching from self refresh operation to read/write operation. The time interval tSNB from the rising edge of RAS signal at the end of self refresh operation to the falling edge of RAS signal in the last CBR refresh cycle during read/write operation period should be set within 8.2 ms. Switching from read/write operation to self refresh operation. The time interval from the falling edge of RAS signal in the first RAS only refresh cycle during read/write operation period to the falling edge of RAS signal at the start of self refresh operation should be set within tNSB (shown in table 3). Switching from self refresh operation to read/write operation. The time interval from the rising edge of RAS signal at the end of self refresh operation to the falling edge of RAS signal in the last RAS only refresh cycle during read/write operation period should be set within tSNB (shown in table 3). RAS refresh cycles 511 cycles refresh cycles 511 cycles (B) Definition of burst refresh 8.2ms read/write cycles RAS refresh cycles 512 cycles 2.2 RAS only burst refresh 2.1 CBR burst refresh The CBR burst refresh performs more than 512 continuous CBR cycles within 8.2 ms. Definition of RAS only burst refresh tSNB ≤8.2mstNSB ≤8.2ms Read / Write Self Refresh Self Refresh Read / Write