M5M44170-6S

M5M44170AJ MITSUBISHI | Alldatasheet

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preiminay M5M44170AJ,L,TP,RT-6,-7,-8,-10,-6S,-7S,-8S,-10S "y FAST PAGE MODE 4,194,304-BIT(262,144-WORD BY 16-BIT) DYNAMIC RAM

DESCRIPTION

e@ This is a family of 262144-word by 16-bit dynamic RAMS, fabricated with the high performance CMOS PIN CONFIGURATION (TOP VIEW) process, and is ideal for large-capacity memory systems where high speed, low power dissipation, vec | 1 ae, 40] vss and low costs are essential. DQi} 2 39 | DQ16 The use of quadruple-layer polysilicon process bQ2| 3 38 | DQ15 combined with silicide technology and a single- pe 3 4 % pe 13 transistor dynamic storage stacked capacitor cell vec] 6 35 | vss provide high circuit density at reduced costs. pas| 7 34] DQ12 Multiplexed address inputs permit both a reduction DQ6} 8 jog MIL 33 | DQ 11 in pins and an increase in system densities. 0Q7| 9 00 32 | DQ10 This device has 1CAS and 2W terminals. Refresh ba 8 10 sou 31 bas cle is 1024 cycles every 16.4 ms. NG. . near 5 y' Ty iw 12 40 PIN 29 NC. TURE: we} 13 281 CAS — —— RAS | 14 27 OE RAS CAS Address | Cycie Power AQ 15 26 A8 Type name | “Ss | “ces | acess ose AO | 16 25) A7 time time | time | time im | 47 24 AG (maxas) | (max.as) | (max.ns) | (min.ns) |(¥P-™) m2 | 18 23| AS fama] 60 | 15 | 20 | 120 | 500] As | 16 a) fmwronvase] 80 | 20 | 40 | 160 | 440 | (M5M44170AJ) [ewe] 400 | 25 | 50 | 190 [375 | @ XX=JLTPRT pin Geom l 39p PIN CONFIGURATION (TOP VIEW) e4 pin 400mil TSOP @eSingle 5V+10% supply vi 1 44] Vv @ Low stand-by power dissipation veo 2 WN 43 ass, Low operating power dissipation 4| 5 40 13 @ M5M44170Axx-6,68.. 770mW (Max) BOC) 8 2 NSS, M5M44170Axx~7,7S. . 660mW (Max.) paée| 8 37 | DQtt1 M5M44170Axx-8,-8S.. 578mW (Max.) pq7} 9 36 | DQ10 M5M44170Axx—10-10S. . 49 5mW (Max.) DQ8} 10 35 | DQG @ Fast-page mode (256-bit random access _), Read -modify- NL. 1 34 NL. write, RAS-only refresh, CAS before RAS refresh, Hidden NL. | 12 400 MIL 33 | NL. refresh capabilities, NC, | 13 TSOP 32 NC. @ Self reflesh capability LWE | 14 31 NC. Self retlesh current..200us We| 15 44PIN 30 | GAS @ Extended reflesh capability RAS | 16 29| OE Extended reflesh current..250us AQ 17 28 AS @ Early write mode and LW/UW and OE to control output AO 18 27 AZ buffer impedance . . Al 19 26] AS @ All inputs, output TTL compatible and low capacitance A2 20 25 AS @ 1024 refresh cycles every 16.4ms (AO — A9) a3 | 21 oa | Ad @ 1024 refresh cycles every 128 ms (AO — A9y* vec | 22 23 | vss APPLICATION Main memory unit for computers, Microcomputer (M5M44170ATP) e@ memory, Refresh memory for CRT NL=NO LEAD | *: Applicable to self refresh version(M5M44170AJ,L,TP,RT | 6S,-7S,-8S,-10S:option)only. 9 MITSUBISHI | rev.B ELECTRIC

rei, M5M44170Ad,L,TP,RT-6,-7,-8,-10,-6S,-7S,-8S,-10S Preliminary FAST PAGE MODE 4,194,304-BIT(262,144-WORD BY 16-BIT) DYNAMIC RAM PIN CONFIGURATION (TOP VIEW) PIN CONFIGURATION (TOP VIEW) vss [1 \\_ 7 44] vec pag [7 @ 0a 16} 2 43 | DO1 DQ 11] 3 2 | baie 0Q15} 3 42 | DQ2 vss | 5 6 | pais pai4| 4 41 | 0Q3 DQ 14) 7 8 | Dats DQ13} 5 40 | 0Q4 pa 16] 9 10 | vss vss | 6 39 | VCC. vec | 11 12! pai DQ12| 7 38 | DQ5 Da2 | 13 14) DQ3 DQ11| 8 37 | DQ6 Da4 15 16 | voc DQ10} 9 36 | DQ7 pas | 17 475 MIL i DQg | 10 35 | DAB pay | 19 ZIP bs DQ6 NL, | 11 34) NL. NC. 21 Bs 0Q8 NL. | 12 400 MIL 33 | NL. uw | 23 40PIN 22 | tw Nc. | 13 TSOP 32 | NG. Ag 25 Bs Ras NC. 14 44 PIN 31 | LWE Al 27 28 | A2 CAS | 15 30 | UWE A3 29 30 | VCC OE 16 29} RAS vss 31 32 | Ad AB | 17 28) Ag AS 33 A7 | 18 27 | Ao Az | 35 oa | AS AB | 19 26] A OE | 37 3 fs A5 | 20 25 | A2 NC. 39 40] NC Ag | 2t 24| a3 NC. VSS |_22 23 | VOC (M5M44170AL) (M5M44170ART) NL=NO LEAD FUNCTION The MSM44170AJ, TP,RT provide, in addition to normal read, write, and read-modify-write operations, a number of other functions, e.g., fast page mode, RAS-only refresh, and delayed-write. e@ The input conditions for each are shown in Table 1. Table 1 Input condition for each mode crnen is [es| arr Foon [ono | Pato ; Fast Lower byte write ACT | ACT] ACT|NAC|NAC] DIN DNC YES page com [osteo] ow | ow | ves | Renmin [er] weloefowion| om | om | ves |_| rama [ror |r weer] oor | mr [ves |_| CAS before RAS a [| rfoefowlow| om | om [ves |_| sont frr[rfpelneine| ow [ow [ves [| for [nem nelnelne| om | ew | wo | | © Note _ACT:active, NAC:nonactive, DNC:don't care, O PN:open ae. MITSUBISHI rev.B ELECTRIC

FAST PAGE MODE 4,194,304-BIT(262,144-WORD BY 16-BIT) DYNAMIC RAM BLOCK DIAGRAM ; Ovgc SmRoseinror RAS CLOCK GENERATOR Ovss con NRORE InruT CAS C) —_ ; i LOWER : —?¢ 1 Bote do) DQ ; DQ3 : pee H DQs ; : DER SElE < e | HUTT |e [eo -| LOL 8 AMPLIFIER & YO CONTROL [= al Om PrrErid pee a OZ Piiiiid Del ADDRESS =i titeete

3 O85 DQl

INPUTS : aD zg|.58 DQl

4 O88 5718 Co Ese EE Dol

Za] lac} o [| BS <SI5S AS O28] filo a aise H a6 Om 88 si] & [-e} MEMORY CELL i AT ona “xz 5 [|] 194,304 Brrs) i as Oe 27 : Ag Or OE ee TT INPUT ee : MITSUBISHI rev.B ae ELECTRIC

_ M5M44170Aud,TP,RT-6,-6S,-7,-7S,-8,-8S,-10,-10S Preliminary FAST PAGE MODE 4,194,304-BIT(262,144-WORD BY 16-BIT) DYNAMIC RAM ABSOLUTE MAXIMUM RATINGS [_Symbor [Parameter [Conditions Ratings unit Supply vollage @ With respect to Vss [to [ Ouputcurenn Pa [pa | Powerdissipaion [ra=2se | ew [ Topr | Operating emperamre[ Ltstg | Storagetemperanre [T5150 RECOMMENDED OPERATING CONDITIONS (Ta=0~ 70 C, unless otherwise noted ) (Note 1) Ua [om |e ee oe] | [ vec [Supplyvotage as Ps ss Tv | [vss [Suppiyvotage To Po Po VIH [High-level input voltage, all inputs [24 | | es |v VIL TLowever input votiag Oe Dad LO [TT 08 | a Note 1: All voltage values are with respect to Vss. ELECTRICAL CHARACTERISTICS (Ta=07 70°C, Veo =5V + 10%, Vss = OV, unless otherwise noted ) (Note 2) Foret [mer | tn Pr do TOH=3mA__ 2a | vec] v_] [VOL | tow-level ouputvoluge | TOL=aama__f 0 | | 04 _[V] Q floating 1OZ | Off-state output current oVeVeutsssv 10 Jud r ) li Input current OSV IHS6SY. 10 uA Other inputs pins = OV , a ee bey | Average supply curent from Raseavestag To] Wee operating (Note 3.4.5) eaten ee ee ee ee RAS = CAS = VIA, 3 1CC2 | Supt from Vee, stand-by (Note 6) Fee A ely caren: fom Vee andy (Note 6) TRS ecaSE veCOs|_ || 1] ™ output op a a ae Average supply current from RAS cycling i 1cC3 ee supply SERS = VI ARC= min, LTO ag Veo refreshing (Note3, 3) MSMAATTOAS-85| ut open re ee ee Average supply current from RAS = VIL re ee 1CC4 | Vec Fast-Page-Mode TAS cycling poof 20a (Note 3, 4,5) tPC = min, , output open |__| 105 | re a a [720] Average supply current from CAS before RAS refresh |_| | i“ 1.606 | Veo TAS before RAS refresh MMAIIOAT S| scting c= min [| J 105 | ma ee es mode (Note 3, 5) output open a a MITSUBISHI 1 ev.B ae ELECTRIC

M5M44170Ad,TP,RT-6,-6S,-7,-7S,-8,-8S,-10,-10S Preliminary FAST PAGE MODE 4,194,304-BIT(262,144-WORD BY 16-BIT) DYNAMIC RAM ELECTRICAL CHARACTERISTICS ( continued) (Ta=07 70 C, Voc = 5V + 10%, Vss = OV, unless otherwise noted ) (Note 2) RAS cycling TAS £0,2V or CAS befor . Averange supply current | x5 yefresh cycling OES 0.2V or® Vee recs |" vcc = 0.2V WEE 0.2V or = Vee - 0.2V Extended refresh mode | 4o~ 49£0.2V or® Vee - 0.2V 250 | uA (Note 6) | DQ = open IRC = 125 us tRAS = tRAS min~ lus TCA Averange supply current RAS=TAS £02 * | om VCC DEE 0.2V or® Vee - 0.2V 200 | uA Icc 9 Self fresh mode (Note 6) | WES 02¥ or ® Veo-0.2V elf refresh mode (Note 6)} 49 ~ 49 € 0.2 or® Vee -0.2V Note 2: Current flowing into an IC is positive. out is negative. 3: Tec] (AV), Iec3(AV) and Ice4(AV) arc dependent on cycle rate. Maximum current is measured at the fastest cycle rate, 4; Icel(AV) and Icc4(AV) are dependent on output loading. Specified values arc obtained with the output open. 5: Column Address can be changed once or less while RAS = VIL and CAS = VIH. CAPACITANCE (Ta =07 70°C, Voc = SV + 10%, Vss = OV, unless otherwise noted ) symbol par Test cond Uni ym ameter ‘est conditions Init t ) [Min [tye [Ma . Input capacitance, MSM44170AL,TP.RT | | [s [or soos noma ERC | 2 MITSUBISHI rev. B ELECTRIC

Pretminary MSM44170AJ,L,TP,RT-6,-7,-8,-10,-6S,-7S,-8S,-10S FAST PAGE MODE 4,194,304-BIT(262,144-WORD BY 16-BIT) DYNAMIC RAM SWITCHING CHARACTERISTICS (Ta=0~ 70 C, Vec=5V + 10%, Vss = OV, unless otherwise noted ) (Note 5, 12,13) e Po] Panmetr RRR RE [Min [Max [Min [Max | Min [Max [Min |” Max | [tCAC [AccesstimefromCas (Nowe7.8) Ps [20 | 20 TT 25 Tins | [RAC [Access time fromRAS (Nore7.9Y_ | 60_ | [70 [| 80 [| 100 | ns | [tAA [Column Address access time (Note 7,10} | 30_[ [35 [| [40 [| 50 | liCPA [Access time from CAS precharge (Noe 7.1] | 35_[ [40 [| [45 TT 55 | OBA [AccesstimefromOE (Nowe 7] 1ST 20 TT 20 25 | [iCLz [Output low impedance from CAS tow (Nowe7¥5 | TS TT Ss TST ns | OFF [Output disable time after CAS high (Noe 1230 [15 [0 | 20 [0 [20 [ol 25 [ns] [0ez [ouput sible ine ater OF nigh oe 3]0_[ 15 [0 [20 | 0 | 20 | of 25| | Note 6: An initial pause of 500 ys is required after power-up followed by a minimum of eight initialization cycles (any combination of cycles containing a RAS clock such as RAS-Only tefresh ), Note the RAS may be cycled during the initial pause. And any 8'RAS or RAS/CAS cycles are required after prolonged periods ( greater than 16.4 ms of RAS inactivity before proper device operation is achieved. 7: Measured with a load circuit equivalent to 2TTL loads and 100pF. 8: Assumes that (RCD 2 tRCD(max) and tASC2 tASC (max). 9: Assumes that (RCD S tRCD(max) and tRADS tRAD(max). If tRCD or tRAD is greater than the maximum recommended value shown in this table, (RAC will increase by amount that (RCD or tRAD exceeds the value shown, 10: Assumes that (RAD 2 tRAD(max) and tASC & tASC (max). 11: Assumes that tCP & tCP(max) and ASC 2 tASC (max). t ) 12; tOFF(max) and tOEZ(max) defines the time at which the output achieves the high impedance state (lout S | +10 A | )and is not reference to VOH(min) or VOL(max). 9 MITSUBISHI Tev.B ELECTRIC

TARGET SPEC. M5M44170Au,TP,RT-6,-6S,-7,-7S,-8,-8S,-10,-10S Preliminary FAST PAGE MODE 4,194,304-BIT(262,144-WORD BY 16-BIT) DYNAMIC RAM eee eee Se ee @ TIMING REQUIREMENTS ( For Read, Write, Read-Modify-Write, Refresh, and Fast Page Cycles ) (Ta=07 70°C, Veo =5V + 10%, Vss = OV, unless otherwise noted ) (Note 12, 13) vin [va [in [ses [ a | ra | | es [REF [Refresh oycletime | GAT tc. a] fi6.a] [16.4 [ms| fap _[RAShigh pulsewidth SOT oot 70 f ToT Tas] [wRCD | Deiay time, RAS low ioCRSIow Now 5} 20 | 45] 20] 50] 20 | ool 25 | 75 |ns| [ICRP [Delay time, CAShighwoRASIw | 10; [40] [tof [10{ Ins [uRPC [Delay ume, RAS high wCAStow | o] Jo] | 0] 10] Ins] [CPN [CAS high pulsewidth io Tio fT io Tio TT ns] [uRAD | Column address delay ume from RAS Tow NOT] 15 | 30] 15] 35] 15} 40] 20 | 50[ ns J(ASR | Row address setup time before RASIow | Of [of | 0] | -o{ [ns] [cASC | Column address setup ume before CASIO (Now TT] OT TOL O| 1] Of 15} 0| 20] ns| [RAH [Row address holdumeaTierRASIow ‘Tot iol [io is | [ns [ICA Column address hoid time after CAS iow [15] [1s] 1s} [20 | [ns [ZC [Delay ume, datatotasiow Now 18] 0] | o| 1 0] | 0} Ins] [tDZ0 [Belay tine, dala Clow Woe 8] 9 | | of 10} 10 fT Ins [iCDD| Delay une, CAS high io data (Nowe 19] is] | 0] | 20] | 25 | [ns [ODD] Delay ume, Oz high iodaa Wee} 15 [20/20] _[ 25 | [ns QE restore rie 20 SOT STS | Note 13: The timing requirements are assumed tT = Sns. 14: VIH(min) and VIL(max) are reference levels for measuring timing of input signals. 15: tRCD(max) is specified as a reference point only. If (RCD is less than (RCD(max), access time is (RAC. If (RCD is greater than t(RCD(max), access time is controlled exclusively by (CAC or tAA. 1tRCD(min) is specified as (RCD(min) = tRAH(min) + 2tT + tASC(min). 16; tRAD(max) is specified as a reference point only. If (RAD 2 tRAD(max) and tASC & tASC(max), access time is controlled exclusively by LAA. 17: tASC(max) is specified as a reference point only. If RCD 2 (RCD(max) and tASC = tASC(max), access time is controlled exclusively by CAC. 18: Either t(DZC or tDZO must be satisfied. 19: Either tCDD or tODD must be satisfied. 20: tT is measured between VIH(min) and VIL(max). 9 MITSUBISHI rev. B ELECTRIC 731

TARGET SPEC. Preliminary | NSM44170AJ,L,TP,RT-6,-7,-8,-10,-6S,-7S,-8S,-10S FAST PAGE MODE 4,194,304-BIT(262,144-WORD BY 16-BIT) DYNAMIC RAM Read and Refresh Cycles @ Bees Symbol Parameter uni om [ie] vr [on] moe [aie | rox [in] | IRC [Read cyclerime 20] Cig _—ifiof __figof__[ns] [mas [RASiow puse wian | 600000] 70 [0000] 8010000[100|70000[ ns cas [eaS tw pose wien | 130000] 20f 0000 20 0000) 2510000] ns fest [EAS neater Siew | 60| [70 [80] 00] [ns [sti [RAS oldie ater Siow} 13] 20} _] 20) >5| [ns jwxcs [Read seuprime befowTASiow | Off of of of Ins] [RCH |Readhotd time after TAS high Nore 20] Of | OFT of Of ns| tt [Reads ine aterRAS en eve 20] 10] | 10[ | 10] [10] [| [RAL |Cotunnasiress wRAS how ine [30] | 55] | 40] [50] |] focu [EAS aa ine aterEiow [15] 20] | 20] [25] [ns [oR RAStat ineaterOFiow sf [20] [20] as[ | Note 20: Either tRCH or tRRH must be satisfied for a read cycle. Write Cycle ( Early Write and Delayed Write Cycles ) e@ symbol Parameter Unit Se secs [wo [Write cycleime ffs fr60]_f190f__ as [uRas [RAS tow pulsewian | 60|1.0000] 70|1.0000) 80 fi 0000]100]10000 | ns [:CaS [EAStow puieewian | 1510000] 20/1000] 20}r0000] 25/1000) ns| [:CsH [CAShowimeaterRASiow Of | 70 sof foo] [as] [xsi [RAStoidimeaterTASiow ts] 20] 20] as] fas [WS [Write setup time before CASow ore 25] Of | Off of as] [wH|write hold imeaferCASiow to] ts] as] 20] [| [cw [CAS how imearerWiow ts] 20] | 20] 25] [ns |RWL|RAShoIddmeaterWiw 15] 20 20] 25] [ns | [we [write poise win toast fas] 20f [ns] fos [Daamup ane wioetiSowawew | of | of | of | of os [oH [baa al in afer CAS ow or Wow [10] 15| | 15] | 20] [aa fost foctouinestewiw [sl [>of [of | as] fm

Panes! SYS MBM44170AJ,TP,RT-6,-68,_-7,-7S,-8,-8S,-10,-10S Preliminary FAST PAGE MODE 4,194,304-BIT(262,144-WORD BY 16-BIT) DYNAMIC RAM @ Read-Write and Read-Modify-Write Cycles symbol [snerrovees Pane. evans omarion of tee EET [RWC [Read Write/read modify write cycle ime (Nowe 22160] [185] [205] [245|_ ns [mAs [RASiow pose wah —__—_—_|95|10000|115|10000}125 10000|155] 10000 ns [CAS [CASiow puke wis. | 5010000] 65[10000) 650000) 0 10000[n| [RSH [RAS ho ine ater T= iow | 30] | 65 | as] | so] __|s| [eRCS [Read sewp time before TAS iow | OT Of of of Tas] [own [Dey ine, CASIow wWiow Woe] 35] | 40 [ao] | 50] [a [WD [Delay time, RAS iow wWiow Nore 23 80] 90[_fuoof [a2s[ [ns] [tAWD|Detay time, addressioWhow Nowe 25) SOL 55[ [oof 75] as] [iow |eaS hoistimeaterWiow | is| | 20] | a0f | 25] __|ns| [awe [RStadineaterWaw ———*f as! 20f | anf | 2s] [os [Ds [DaaseupinetcioeWiow —-|_of | of | of | of [ms] [ub _[Datahold tine aferWiow | 10 | 15] _] 45] ] 20] [ms e@ [LEH [OE hold time afterWlow Past fast [20] asf as] Note 22: (RWC is specified as (RWC(min) = tRAC(max) + tODD(min) + tRWL(min) + tRP(min) + 4tT. 23: tWCS, tCWD, tRWD and tAWD and tCPWD are specified as reference points only. If tWCS 2 tWCS(min) the cycle is an early write cycle and the DQ pins will remain high impedance throughout the entire cycle. If (CWD 2 tCWD(min), RWD & (RWD(min), AWD 2 tAWD(min), and tCPWD 2 tCPWD(min) (for fast page mode cycle only ), the cycle is a read-modify-write cycle and the DQ will contain the data read from the selected address. If neither of the above condition ( delayed-write ) of the DQ ( at access time and until CAS or OE goes back to VIH ) is indeterminate. Fast-Page Mode Cycle ( Read, Write, Read-Write, and Read-Modify-Write Cycles) (Note 24) Symbol Parameter Unit I [ec _[Fatrasemaderadirieoeeime [aol] 45| | sol ___| | [as] [eRWC|Fagemode rad wriciond moiy wate guleind 75] | 95] 00] 15] [ns [as [EaSinw pubs wa frredwrie oleae 250000000] 1000003510000} 60100000 ns [ce [CAShion pose wie vve2s4 10{ 15] 10] 15[ 10| 20/10] 25] ns| ico RAStold ime ater AS pmcaree [35] 40] [as] [55] [ns @ cribhonts tine. THT eta wWiow awa] 35] [ao Pas Ts To eee

TARGET SPEC. _, M5M44170AJ,TP,RT-6,-6S,-7,-7S,-8,-8S,-10,-10S Preliminary _ FAST PAGE MODE 4,194,304-BIT(262, 144-WORD BY 16-BIT) DYNAMIC RAM Note 24: All previously specified timing requirements and switching characteristics are applicable to their respective @ fast page mode cycle. __ 25: tRAS(min) is specified as two cycles of CAS input are performed. 26: tCP(max) is specified as a reference point only. CAS before RAS Refresh Cycle ,Extended Refresh (Note 27) symbot Parameter ne [icsk [TAS sewptimebeforeRASlow 10 | 10 | to | fo Tas] [cH [CAStoid ime aerRAS oy 10 |] 5] us |] 20 | [as] {cas [CASiow pe wah fas |] 30 | P30 | 35 | [as] Note 27: Eight or more CAS before RAS cycles instead of eight RAS cycles are necessary for proper operation of CAS before RAS refresh mode. TAS before RAS Self Refresh Cycle (Note 28) symbot Parameter on [oem [es [acm noes [vm [oer Yate [ a | lease [oR ait ten RAS iow pase wah [00] uo - 100) 00] a [Res [ook set tes RAS nigh precharge me 120 [140 | [160] 190] Jn crs [cor safriesr AS notune [30] 50] [50] —] -s0] [as] MITSUBISHI .B ae MTB wy.

e@ ae —e — aor BY 16-BIT) DYNAMIC RAM m crete —s ~ Xs WC = HONE ww an | es w een Al | XXX ° i= ree Oe | = anette @ ee ELECTRIC

• MITSUBISHI LSIs Preliminary M5M44170AJ,L,TP,RT-6,-7,-8,-10,-6S,-7S,-8S,-10S FAST PAGE MODE 4,194,304-BIT(262,144-WORD BY 16-BIT) DYNAMIC RAM Write Cycle ( Early write ) we @ ns a : | eOONO — @ m= XXX =e KKK [or wncitz nn a = KKK KKKKKEXER ee

Prelminay exe MODE 4194,908-BIT(202144:WORD BY 16 Bf?) DYNAMIC RAM @ Upper/(Lower) Byte Write Cycle ( Early write ) jp} ale = coral oon cone = SRY ION JOE = HOOT = OMCMO CCA MMNCAUKRUNIIIONNN Pa cuaienennennnnnenennn

Preliminary M5M44170AJ,L,TP,AT-6,-7,-8,-10,-6S,-7S,-8S,-10S. FAST PAGE MODE 4,194,304-BIT(262,144-WORD BY 16-BIT) DYNAMIC RAM Write Cycle ( Delayed write ) wwe r ) oY x 4 at 5 caso J en @ Tos CS = ER RE He KO = YOOX ONY es | ade NETSUBISHI Rev

FAST PAGE MODE 4,194,304-BIT(262,144-WORD BY 16-BIT) DYNAMIC RAM » Upper/(Lower) Byte Write Cycle ( Delayed write ) in ns a =) —. ¥ = oF SS 7 ~ Ew = wineplan OXY tT OOO @® = YYW NYY MAMA ee Le . wan | DAA ie Gr = HEROIN =e XO | OOOO ee. wrk XXXXXXXXXN | 15/31

Preliminary M5M44170AJ,L,TP,RT-6,-7,-8,-10,-6S,-7S,-8S,-10S FAST PAGE MODE 4,194,304-BIT(262,144-WORD BY 16-BIT) DYNAMIC RAM Read-Write, Read~Modify-Write Cycle ¢q we Whee HL se _ KKK ae oF He | _x» : SOE Nou e P LIQ spt KR males PO pe oo oot eel Be LPS MDAKAAA = XXXXXKN \\XXXXKXY es |

Preliminary sat 70AJ,L.TP.AT-6,7,-8,-10,-68,-78,-8S,-108 FAST PAGE MODE 4,194,304-BIT(262,144-WORD BY 16-BI ) DYNAMIC RAM MITSUBISHI (MEMORY/ASIC) . . Read-Upper/(Lower) Write, Read-Modify-Upper/(Lower) Write Cycle oe | Came == LIE “Fel 2 yj a = em) |

7 EOE = eon

= XXX | og LER TNO ie = KO Reso AA meg OHA e wml OOOO we ieee neve

Preliminary MEN4¢170AJL,TP,AT-8-7-8,10,-68,-75,-86,-108 7 FAST PAGE MODE 4,194,304-BIT(262,144-WORD BY 16-BIT) DYNAMIC RAM RAS-only Refresh Cycle 1 = —— os wa Nf ats KX XKAXMAMAXMAXAKD atts) B XMXXXXXXXXAXXMAXMAXMAAMAA om KKK KKK = XRRNEREXXXR RMR re |

Preliminary M5M44170AJ,TP,RT-6,-6S,-7,-7S,-8,-8S,-10,-10S FAST PAGE MODE 4,194,304-BIT(262,144-WORD BY 16-BIT) DYNAMIC RAM @ CAS before RAS Refresh Cycle ,Extended Refresh Cycle* " Tt LN Vera el ee = XXXKRAXRXKKKAXXRKKKXAN ; — TP ROIREERHXREXRKXXXXKERK ESR DQI-DQIé | AV AV AN | 7 » __ AXXXXKRXXXXKKRXXNKKHXNN

MITSUBISHI (MEMORY/ASLO) bit pv m= cee een isn mes Preliminary M5M44170AJ,TP,RT-6S,-7S,-8S,-10S. FAST PAGE MODE 4,194,304-BIT(262,144-WORD BY 16-BIT) DYNAMIC RAM Self Refresh Cycle *( Note 28) @ he Sgt wo XXX = XXX AMAA = + EARNER ° DaQI-DQIs ® _ AXXXXXXXXKKA AMAA

PrelITINATY Bae MODE 4,194,904 B28 4-WORD BY 16 BT) DYNAINE RAM @ Hidden Refresh cycle ( Read ) ( Note 30) ees fr deka ble vos ae si ER ES ww my t Feo e ‘cop s fe DQ1-DQi6 at 5 whe ELECTRIC nes

Preliminary 7 M5M441 TOALAL.TP.AT6,7.8-10-68;78,88,-108 FAST PAGE MODE 4,194,304-BIT(262,144-WORD BY 16-BIT) DYNAMIC RAM Fast Page Mode Read Cycle @ _ IRAS 1CPRH ARP : "Teal Et Ut stealhen|| dla) Al “Tl | et z cot tH Ril fini ay LE ea |e Ite lal ay © KAKA ‘i : X sl) Sa | ae eine ®XKXXAMXA __ANXDN amin Ks ee

Preliminary M5M44170AJ,L,TP,RT-6,-7,-8,-10,-6S,-7S,-8S,-10S FAST PAGE MODE 4,194,304-BIT(262,144-WORD BY 16-BIT) DYNAMIC RAM e Fast Page Mode Write Cycle ( Early Write ) | eh Sy ete |_| sit | pir =o)Le DOT se KT = KN ae 1 = Ker vont oslo e [RO KO 0 = KO ; VYVY —_ pa ps Pee orn JOE seers IOXXE seers DEX = XW AXEKXXKANREND e a ae eRe Revs

Fast Page Mode Upper/(Lower) Byte Write Cycle ( Early Write ) @ _——— a a ee Jt bt dae a tg a oh “Whe Gel eae eh. _ Ostet rt — * XXX Lee Le NA @ DH ws} ‘DH ws| DH FO IL WE WO {2 race be KKK EKKO ("= HIGHZ = AXXXKXKKXKXEKXEKERKKRENO 24731

Preliminary M5M44170AJ,L,TP,RT-6,-7,-8,-10,-6S,-7S,-8S,-10S FAST PAGE MODE 4,194,304-BIT(262,144-WORD BY 16-BIT) DYNAMIC RAM e Fast Page Mode Write Cycle ( Delayed Write ) ==) se O00: KOO Ww aa! N Ee A iN AK/IA/V/ A . 4 » DQ9-DQ16 Cl Teme TET 2 ene ae cs VY x yu XX e

MLTSUBLSHL (MEMORY/AS1C) bbe Do Mm BOW OL Vem es wee Preliminary M5M441 OAM LTP.AT-8-7,8-10-68;78,/88-1 os FAST PAGE MODE 4,194,304-BIT(262,144-WORD BY 16-BIT) DYNAMIC RAM Fast Page Mode Upper/(Lower) Byte Write (Delayed Write) ow e@ __ a — Fie ee —poe a Pn oot cipal se LY Peepers iy 7 , WY) el ae es | he Hectic nev

Preliminary M5M44170AJ,L,TP,RT-6,-7,-8,-10,-6S,-7S,-8S,-10S FAST PAGE MODE 4,194,304-BIT(262,144-WORD BY 16-BIT) DYNAMIC RAM @ Fast Page Mode Read-Write, Read~Modify-Write Cycle ‘com Ras {RAS a i eel ————-==s CAS” +—t 1CAS } 3 8 = OY T= Ne | athe | o OES eR tial a Fe nee cp x muna ae A OK oe

Preliminary M5M44170AJ,L,TP,RT-6,-7,-8,-10,-6S,-7S,-8S,-10S. FAST PAGE MODE 4,194,304-BIT(262,144-WORD BY 16-BIT) DYNAMIC RAM Fast Page Mode Read-Upper/(Lower) Write, Read-Modify-Upper/(Lower) Write Cycle @ fi Ves gi ha ——] pe Pama an eal ~ (= J6f == KO se 10 = eeees [<a — YOON EE ‘ wip k/ SNe Pe ee EE ee ° Roa ae COMO RE OHNO EO tA r } oe MR Rev.8 |

IANVO! orcy. _ M5M44170AJ,L,TP,RT-6,-7,-8,-10,-6S,-7S,-8S,-10S Preliminary FAST PAGE MODE 4,194,304-BIT(262,144-WORD BY 16-BIT) DYNAMIC RAM Note 28 Self refresh sequence MITSUBISHI (MEMORY/ASIC) @ Two refreshing ways shoud be used properly depending on the low pulse width (tRASS) of RAS signal during self refresh period . 1. In case of tRASS < 300 ms

1.1 Distriduted refresh during Read / Write operation

(A) Timing Diagrams Read / Write Cycle Self Refresh Cycle Read / Write Cycle NSD tSND tRASS<300ms RAS Table 2 last refresh cycle first refresh cycle Read / Write Cycle Read / Write -m Self Refresh | Self Refresh —m Read / Write t ) (B) Definition of distributed refresh Definition of CRR distributed refresh (Including extended refresh ) The CBR distributed refresh performs more then 1024 constant period (125 us max) CBR cycles within 128 ms. All combination of nine row adress signals (AO - A9) are selected during 1024 constant period (16 us max ) RAS only refresh cycles within 16.4 ms. Note : Hidden refresh may be used instead of CBR refresh [RAS /TAS refresh may be used instead of RAS only refresh . 1.1.1. CBR distributed Refresh @ Switching from read / write operation to self refresh operation. The time interval from the falling edge of RAS signal in the last CBR refresh cycle during read / write operation period to the falling edge of RAS signal at the start of self refres operation should be set within tNSD (shown in table 2) ®@ Switching from self refresh operation to read / write operation. The time interval from the rising edge of RAS signal at the end of self refresh operation to the falling edge of RAS signal in the first CBR refresh cycle during read / write operation period should be set within tSND (shown in table 2) 1.1.2 . RAS only distributed refresh ’ @ Switching from read / write operation to self refresh operation. The time interval tNSD from the falling edge of RAS signal in the last RAS only refresh cycle during read / write operation period to the falling edge of RAS signal at the start of self refresh operation should be set within l6 ys. @ Switching from self refresh operation to read / write operation. The time interval tSND from the rising edge of RAS signal at the end of self refresh e operation to the falling edge of RAN signal in the first CBR refresh cycle during read / write operation period should be set within 164s. MITSUBISHI ae ELECTRIC rv.B

TARGET SPEC. mp DT. £e_7 48. . M5M44170AJ,TP,RT-6,-6S,-7,-7S,-8,-8S,-10,-10S Preliminary FAST PAGE MODE 4,194,304-BIT(262,144-WORD BY 16-BIT) DYNAMIC RAM ee cc i ea aE

1.2 Burst refresh during Read / Write operation @

(A) Timing diagram Read / Write Self Refresh Read _/ Write a“ {RASS < 300 ms SNE RAS refresh cycles refresh cycles first 1023 cycles 1023 cycles ast Table 3 refresh cycles refresh cycles Read / Write Cycle Read / Write > Self Refresh | Self Refresh —m Read / Write (B) Definition of burst refresh The CBR burst refresh performs more then 1024 continuous CBR cycles within 16.4 ms. Definition of RAS only burst refresh ‘All combination of ten row adress signals (AO - A9) are selected during 1024 continuous RAS only refresh cycles within 16.4 ms. 1.2.1. CBR distributed Refresh @ Switching from read / write operation to self refresh operation. The time interval tNSB from the falling edge of RAS signal in the first CBR refresh cycle | during read / write operation period to the falling edge of RAS signal at the start of self refresh operation should be set within 16.4 ms . | @ Switching from self refresh operation to read / write operation. The time interval tSNB from the rising edge of RAS signal at the end of self refresh operation to the falling edge of RAS signal in the last CBR refresh cycle during read / write operation period should be set within 16.4 ms. 1.2.2. RAS only distributed refresh | @ Switching from read / write operation to self refresh operation. The time interval from the falling edge of RAS signal in the first RAS only refresh cycle during read / write operation period to the falling edge of RAS signal at the start of self refresh operation should be set within tNSB (shown in table 3) @ Switching from self refresh operation to read / write operation. The time interval from the rising edge of RAS_ signal at the end of self refresh operation to the falling edge of RAS signal in the last RAS only refresh cycle during read / write operation period should be set within tSNB (shown in table 3) bd MITSUBISHI : ae VERS rev. B

, fewer eee nee e | TARGET SPEC ‘ Preliminary FAST PAGE MODE 4,194,304-BIT(262,144-WORD BY 16-BIT) DYNAMIC RAM rr reOorroona r ) 2. In case of tRASS 23 0 Oms Timing diagram - (A) | Read / write Self Refresh Read_/_ write wsp£164ms SDS 164 ms (RASS 2300ms RAS last first refresh cycle refresh cycle Timing diagram - (B) Read / write Self Refresh Read _/ write IREF=16.4 ms iRASS = 300 ms IREF£16.4 ms RAS refresh cycle refresh cycle Table 4 1024 cycles 1024 cycles e RAS only distributed . CBR burst refresh Timing Diagram —B Timing Diagran—B only burst refresh (B) Definition of refresh The same as 1.1-(B) and 1.2-(B).

2.1.1 CBR distributed refresh

© Switing from read / write operation to self refresh operation . The time interval tNSD from the falling edge of RAS signal in the last CBR refreh cycle during read / write operation period to the falling edge of RAS signal at the start of self refresh operation should be set within 16.4 ms . © Switing from self refresh operation to read / write operation . The time interval tSND from the rising edge of RAS signal at the end of self refresh operation to the falling edge of RAS signal in the first CBR refresh cycle during read / write operation period should be set within 16.4 ms .

2.1.2 RAS only distributed , CBR burst , RAS only burst refresh

@ Before and after the self refresh , 1024 refresh cycles should be executed within 16.4 ms for each refresh operation . Oo MITSUBISHI ae ELECTRIC rev. B