M5M4416P-15

M5M4416P MITSUBISHI | Alldatasheet

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MSM4416P-12, -15 65 536-BIT (16 384-WORD BY 4-BIT) DYNAMIC RAM DESCRIPTION PIN CONFIGURATION (TOP VIEW) This is family of 16348-word by 4bit dynamic RAMs, fabricated with the high performance N-channel silicon-gate MOS process, and is ideal for large-capacity memory | apie &NABLE OE [i] I) vcs (ov) systems where high speed, low power dissipation, and low pata ny ]OO1 EB} ++ Doe Boy WOATA costs are essential. The use of double-layer polysilicon DATA OUT Log, [3] fa cas covumn aooness process technology and a single-transistor dynamic storage contao. TE WE [J++ D3 DATA IN/DATA cell provide high circuit density at reduced costs, and the ROW ADORESS RAS —=+[F Fae a0) oo use of dynamic circuitry including sense amplifiers assures STROBE INPUT ° tow power dissipation, Multiplexed address inputs permit nooaess | “* Fr ** | scones inputs both a reduction in pins to the standard 18-pin package inpuTs } As +E] [Be Aa ite & A-ROW configuration and an increase in system densities. The vere [sas Say) M5M4416P operates on a 5V power supply using the (sv) Veo ne ae on-chip substrate bias generator. FEATURES Outline 18 P4 @ Performance ranges © All Inputs, outputs TTL compatible and low capacitance Aeces ume | Cycle tine | Powerdisization| © 3-State unlatched outputs Type name tan) nid iv ‘© 128 refresh cycles/2ms. Pin 10 is not needed for refresh wemaiiee _ * . @ Early write or OE to control output buffer impedance 120 © Read-Modify-Write, RAS-only refresh, Hidden refresh mmeaiep-is [iso [260150] and Page mode capabilities © Industry standard 18-pin dual in line package © Single 5V +10% supply APPLICATION © Low standby power dissipation: 25mW (max) © Refresh memory for CRT © Low operating power dissipation: ! M5M4416P-12 275mW (max) M5M4416P-15 _250mW (max) BLOCK DIAGRAM COLUMN ADDRESS __ {3) Voo(5V) stnose near GS 6 so censor | STROBE INPUT ware WO dD CONTROL. INPUT a | — Dara ft Sense RerresH = ge | oaTa 6 [anise Ft A | ER oe ae und rs I [5209 20 [ ovreuts amd Et (i) 00 Ae (2) 34 Fa (a) as 1 82 3 oata ADORESS INPUTS. emma et 8 MEMORY CELL our Came nee Ae 2 ome Cb oe ourrur ence te _ ccc

9 MITSUBISHI

MSM4416P-12, -15 65 536-BIT (16 384-WORD BY 4-BIT) DYNAMIC RAM ee ee eeeeeeoreeaeasete FUNCTION The M5M4416P provides, in addition to normal read, write, and _read-modify-write operations, a number of other functions, e.g., page mode, RAS-only refresh, hidden refresh, and delayed-write. The input conditions and output states for each are shown in Table 1, Table 1 Input conditions for each mode ration Refresh Remarks ~ =[=[- |< (see Wie (arly Write) acT YES | Page modo identical | asoivvten [aor | nao ono | owe [aro ove | one | ow | ves [| [Sey Tnx [one [one | owe [one one | ono | omw | ne) Note. ACT active, NAC nonactive, ONC don't care, VLD valid, APD applied, OPN open SUMMARY OF OPERATIONS the data will be strobed in by W with setup and hold times address (AO through A7) referenced to this signal. In delayed or read-modify-write, Fourteen address bits are required to decode 1 of 16,384 OE must be high to bring the output buffers to high storage locations. Eight row-address bits are set up on pins impedance prior to impressing data on the 1/0 lines. AO through A7 and latched onto the chip by the row-address strobe (RAS). Then the six column-address bits data-out (DQ1 through DQ4) are set up on pins A1 through A6 and latched onto the chip The three-state output buffer provides direct TTL compati- by the column-address strobe (CAS). All addresses must be bility (no pull-up resistor required) with a fan-out of two stable on or before the falling edges of RAS and CAS. RAS Series 74 TTL loads. Data-out is the same polarity as is similar to a chip enable in that it activates the sense data-in. The output is in the high-impedance (floating) state amplifiers as well as the row decoder. CAS is used asa chip _until CAS is brought low. In a read cycle the output goes select activating the column decoder and the input and active after the access time interval t,(C) that begins with output buffers. the negative transition of CAS as long as t,(R) and t,(OE) are satisfied. The output becomes valid after the access time write enable (W) has elapsed and remains valid while CAS and OE are low. The read or write mode is selected through the write enable CAS or OE going high returns it to a high impedance state. (W) input. A logic high on the W input selects the read In an early-write cycle, the output is always in the mode and a logic low selects the write mode. The write high-impedance state. In a delayed-write or read-modify- enable terminal can be driven from standard TTL circuits write cycle, the output must be put in the high impedance without a pull-up resistor. The data input is disabled when state prior to applying data to the DQ input. This is the read mode is selected. When W goes low prior to CAS, accomplished by bringing OE high prior to applying data, data-out will remain in the high-impedance state allowing @ thus satisfying tocup- : write cycle with OE grounded. output enable (OE) data-in (DQ1 through DQ4) The OE controls the impedance of the output buffers. Data is written during a write or read-modify write cycle. When OE is high, the buffers will remain in the high Depending on the mode of operation, the falling edge of impedance state. Bringing OE low during a normal cycle CAS or W strobes data into the on-chip data latches. These will activate the output buffers putting them in the low latches can be driven from standard TTL circuits without a impedance state. It is necessary for both RAS and CAS to pull-up resistor. In an early-write cycle, W is brought low —_be brought low for the output buffers to go into the low Prior to CAS and the data is strobed in by CAS with setup _ impedance state. Once in the low impedance state, they will and hold times referenced to this signal. In adelayed write remain in the low impedance state until OE or CAS is or read-modify-write cycle, CAS will already be low, thus brought high. To SSSSSsSssSsssesesssssSSSssSSSsssSsSSSSSsssesee

MSM4416P-12, -15 65 536-BIT (16 384-WORD BY 4-BIT) DYNAMIC RAM Page-Mode Operation Power Dissipation This operation allows for multiple-column operating at the Most of the circuitry in the M5SM4416P is dynamic, and same row address, and eliminates the power dissipation most of the power is dissipated when addresses are strobed. associated with the cycling of RAS, because once the row Both RAS and CAS are decoded and applied to the address has been strobed, RAS is maintained. Also, the time | M5M4416P as chip-select in the memory system, but if required to strobe in the row address for the second and RAS is decoded, all unselected devices go into stand-by subsequent cycles is eliminated, thereby decreasing the independent of the CAS condition, minimizing system access and cycle times. power dissipation. Refresh Power Supplies Each of the 128 rows (Ay~A) of the M5M4416P must be The M5M4416P operates on a single 5V power supply. refreshed every 2 ms to maintain data. The methods of A wait of some 500us and eight or more dummy cycles refreshing for the M5M4416P are as follows. is necessary after power is applied to the device before 4. Normal Refresh memory operation is achieved, Read cycle and Write cycle (early write, delayed write or read-modity-write) refresh the selected row as defined by the low order (RAS) addresses. Any write cycle, of course, may change the state of the selected cell. Using a read, write, or read-modify-write cycle for refresh is not recom- mended for systems which utilize “wired-OR" outputs since output bus contention will occur. 2. RAS Only Refresh A RASonly refresh cycle is the recommended technique for most applications to provide for data retention. A RASonly refresh cycle maintains the outputs in the high-impedance state with a typical power reduction of 20% over a read or write cycle. 3. Hidden Refresh A features of the MSM4416P is that refresh cycles may be performed while maintaining valid data at the output pin by extending the CAS active time from a previous memory read cycle. This feature is refered to as hidden refresh, Hidden refresh is performed by holding CAS at V,, and taking RAS high and after a specified precharge period, executing a RAS-only cycling, but with CAS held low. The advantage of this refresh mode is that data can be held valid at the output data ports indefinitely by leaving the CAS asserted. In many applications this eliminates the need for off-chip latches. de MITSUBISHI ELECTRIC 2-67

MITSUBISHI LSis. MSM4416P-12, -15 65 536-BIT (16 384-WORD BY 4-BIT) DYNAMIC RAM ABSOLUTE MAXIMUM RATINGS a [to | ower anes Operating tebe ener fee oe | Soroge temperature range = é5=180 RECOMMENDED OPERATING CONDITIONS (Ta =0 ~ 70°C, uniess otherwise notes) (Note 1) [om [me eee | Supp voltage Sh — Highevel input voltage, all inputs [pes Tv | Low.tevel input voltage, ll inputs [jreo [fos |v | Tote 1 All voltage values are with respect (0 Vos, ELECTRICAL CHARACTERISTICS (Ta=0~10°c, Voo=5V +10%, Vss=0V, unles otherwise noted) (Note 2) Symvot Test condition u ba Parameter fs consis tee oe] Low-level Output voltage [tou=4zma Po oa Q tating OVS VouT=5.5V i [tT epu curene | ov Vin SV, Atontersine ov [<1 [0 [aa | 1 ‘Avorage supply current (rom Vee, | MSM4416P-12 | RAS, CAS cycling es es a | SOAD | cpeauing (Nore 34) [MBM4416P-15 | to(cd)—toiw) = min ourpuronen [| 50 Tooe ‘Spoly current om Vee standby | RAS=Vin oviputopen 45. a ‘Average supply current from Von, [MSM4416P-12 | RAS cycling CAS=Vuy rt. ps | ma _| C6RCAV) | cexrahing (Note 3 [MSM4416P-15 | to(er) = min, ovtout open a ee COMAD | _sure moe (Note 34) [ MSM4416P-15 | to (ers) = rin output open re Note 2 Current lowing into an 1G & postive out negative 3: Teencav), leea( AV}. 8 Ieca av) ae dependent on cycle rate. Maximum currents measure atthe fastest cycle rote. 2 Iccwav) and Ieca(v) ate dependent on output loading. Spectied values are obtained with the output open. CAPACITANCE (Ta=0~70°C, Voc=SV + 109%, Vss=0V, unless otherwise noted ) a a ee Wess rs iq) t=1MHz es ee | Cicnas) | Inout capacitonee, BAS inost_—— |i mV ms Giccas) | tnoutcapsctance. CAS rout [eyo | imourvouurcapacnance.darapors PT

MSM4416P-12, -15 65 536-BIT (16 384-WORD BY 4-BIT) DYNAMIC RAM SWITCHING CHARACTERISTICS (Ta=0~ 70°C, Voc=Sv +108, Vss=0V, uniess ormerwise noted) iNote 5) [__Msmasigp-12 ‘Symbol Parameter Alternative it Limits Unit symbol a | ‘cose time trom CAS Nove 6.7) | [Tam | Acces tie trom FAS ‘Now 68)] Trac | 20 150 tacoe) Access time from OF (Note 6) = | 30 40 Tais(cH) | Output disabie time after CAS high (Note 9 | Corr: Lo 25 of 3 | ns Tois(oe) | Gurput disable tne after OF high Now) Ps sos Note 5 An initia! pause of 500s is required after power-up followed by any 8 RAS or RASICAS cycles before proper device operation is achieved. Zand ary 8 BAS or RASICAS cycles are required after prolonged periods reser than 2ms) of RAS inactivity betore proper device operation is achieved 6: Measured wth a toad creuit equivalent to 27 loads and 1006

7 Assume that tnoce 2 Yauce 3%

@ Assume that taLce <tavce max. If tauce is greater than taveL max then ta A) will increase by the amount that trucy exceeds tact ™3X. 9 taisceu) MAK afd tg (OE) MAX define the time at which the output achieves the high impedance state {our |#10uAl ) and are not raference to Vow min or Vou max TIMING REQUIREMENTS (For Read, Write, Read-Modify-Write, Refresh, and Page-Mode Cycles) (Ta=0~70°C, Voc=5V+10%, Vss=OV, unless otherwise noted, See notes 10.11) MS5M4416P-12 M5M4416P- 15, mt meter Auernative vi imits Symbol Paramet Symbol Liruts Limits | tocar) | fetesn eve ne ter TT [ms | Tworny | RAS high oulee wiatn [tae so [ns] Truot. | Oeey time, AAS low to CAS low ‘Wow 12) taco [es [oo | ToHRL Delay time, CAS high to RAS tow (Note 13)| tone _ 20 Tsu(Ra) | Row address sewn time before RASIow Tas ° a Tsu(eay_| Column adress setup time betore CAS iow [tao Te Ps] [ incnay | Row acess hold tine atte RAS tow [tran | ts To Ts Goturnn adress hold time after CAS tow Column address hold time after AS low TAR 80 100 ns Transition time (re and fal ove 18) | tr 3 30 3 30 ns Tote 10 The timing requirements are assumed ty=Bns 12 tact max is specified as 2 reference point only if tac. i les than taLcL MaK, secss time's tacm) if TRLCL FHA Ahan tac, MAK, aces time tacce + tacc). taALCL Min is specitied as tarce Min. = thcna) +217 * tsu(CA). ee __ 13° tcHAL requirement is only applicable for RAS/CAS cycles preceeded by a CAS only cycle {i.e., For systems where CAS has not been decoded with RAS), 14 tyismaasured between Vu min and Vip m9 Read and Refresh Cycles eran > —sMaatensia [ msmearee-is | Seen Parameter symbol Unit ee _ a toway | Read cycle sme tac [zo fT aeo Ps | [twin | RAS iow pose wom tas | 20 to000 [180 | 10000 [ne [Rwccuy [EAS tow ose wm tons TPs ns [con [CAS han pute warm toes a0 | 0 [ns CAS hold time after RAS tow ee 150 | ns RAS hoid time atter CAS low tas 60 75 [ns | [tsuccoy | Read wun tine betoreCASiow tres | TP Ps [incouray | era hols ime ater CAS hgh Nowe THY tren FTPs [ence | Arad hold ame ater RAS hgh Now tof Tamm | tT oT ns CAS howd time after OE tow | AS noid ume after OE tow —| tnccuo) | OE noid time atter CAS jow ee Oe OC thevoe) | OE hold time after RAS low a OO SO Delay time. OE high to Date a TAHoL | Delay time. RAS high to CAS low eee es Nowe 15: Either thou) 9F thr a) Must be satisfied for area cycle —_—

M5M4416P-12, -15 65 536-BIT (16 384-WORD BY 4-BIT) DYNAMIC RAM Write Cycles (Early Write and Delayed Write) ec ee ee] He Ha sa Ps ie Twoau) | RAS iow pul wih Tras tree} i000 | 15010000 | [iscen castor be wa Reng [sccm | casa ee wap ge eo Ce Write sup time belore CAS ow Wow | twos iY 8 =~ = [inten [We id teat RAE we yen 00 a Twow) | Wie pose wish _ ~ [we : ps [ns | [iscway | on tow ee Wie | tg eS a Sa mie fe Read-Write and Read-Modify-Write Cycles [Tama] asm] a ee [isco | RAS hi ine te HS 6m tg as] [isto eas hypo way Reg [isc [ Ra wp tine bles ion tres Tew | Deby tine, ERS tw to Wie toe 17 town oe ee a cc Tawi | Oday tne, RAS Tow 10 Writs low tnere 17 | Tew [150 | [oes [es Ce [isc we oie wa Ree [inst [Be ne neta FAS top eo 80] [Reock [ox ie br 08 ew eS remain high impedance throughout the entire cycle. f tecwe 2 tewe Min and triw, 2 taLWL Min. the cycle is a read-modify write cycle and the OO

MSM4416P-12, -15 65 536-BIT (16 384-WORD BY 4-BIT) DYNAMIC RAM Page-Mode Cycle tov 13) [__smasiep-i2 T Msmaatep-15 Symbol Parameter “Syreot Unit [win [Mex [win [vx] ead cycle time a | twine) | RAS iow pute wats Note | tras | 2030000 [295 [30000 [ns | | tocerawi [Reed writereed modity write cycle ome f= na Paso et | twcnuy [AS iow oui wath Note 201| tans [380 | s0000 [505 | 30000 [ns | [iwc [GAS righ poise wigin | top 50 cos Note 18° All previously specified timing requirements and switching characteristics ae applicable to ther respective page mode timing 19, Soecified tor read or write evel 20° Specified for read-write or readhmodity-urite cycle

MSM4416P-12, -15 6S 536-BIT (16 384-WORD BY 4-BIT) DYNAMIC RAM CSS 536-BIT (16 384-WORD BY 41OOoEEEer TIMING DIAGRAMS ‘now 21) Read Cycle Towra) Thiawon twa thiawca) as OM vi = h Twinn ro eas ve OY tsu(nad tsucca) tsucray via YY) kX cou RL RO OO ROW tniowe w vin TREK RRO LOS FA RRNA | | | RRM 001-004 Ym RXR R RAIN : XVIII CnbuTes ye RRSXRARN SAAN “ee SEXXAAANNK tao (OUTPUTS) Vou — | tooeL, ,tacoe)| dis (oe) ThioeRH) TOKO ZYLKRALO ‘niceow OK xe Vie KERR EAraceunnneeticnns o Mi RRR RRR ROMANS KORA thicoe) Thenvoe)

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7 MSM4416P-12, -15

65 536-BIT (16 384-WORD BY 4-BIT) DYNAMIC RAM _____ «SS 536-8 IT (16 384-WORD BY 4-BIT) DYNAMIC RAM Write Cycle (Early Write) towa) Ni ToAL thicpan twee taLou tsucaa ] Tsuen) tevinay an SOY AX) YY YK OA) SRT, Cee 0) GRE Hein, aaa tsucwou| tr(ouw) Le | two) — vn RTD AZRRRXRRRRRKERREEARER ERR EER ¥ vin QORRRORRNAL PINRO AK thea), | teu | throu Dae YH —RERRTXY ARRAY SRR AMER REAR UKER SME LA, CRM NGeianrononneniieuin thao) DQ:~005 You a NE (OUTPUTS) Voy — ae ™ RUSE RARERARKBER RRO RARE REIT o Vin. “SRS RA KEXRR ERAN RAEN KK RAO RANA KR ORK a (De MITSUBISHI ELECTRIC 2-73

M5M4416P-12, -15 65 536-BIT (16 384-WORD BY 4-BIT) DYNAMIC RAM Write Cycle (Delayed Write) tow —— aaa Ow aaS twin) ee 7 | ox XML | tion Tsucra) | tsuccay . vn SRR ES: AN) SIYKRRRRRERREREKY now tomar ne RRA cress ARN Sooess ARAN RRR RKO mE w vn SERRA (KXXKERKERRA YOKE KKK RG vv CHS thaw |_| tsu (0) | th (woo) 09:~D00 ¥™ -SRRROKKO _ 1: AY) (Cox ) REL iia a. AOKI RINIRD "2 RAMSAR NO te ; fac) cara | ters oe) ToeHo th (woe) = Vin, XXXXKASAA AAA ROOK CME AAU NNNNIACUNCNIUNG ROR MITSUBISHI 2% ae tizerne

MSM4416P-12, -15 65 536-BIT (16 384-WORD BY 4-BIT) DYNAMIC RAM —_____ 85 536-BIT (16 384-WORD BY 4-BIT) DYNAMIC RAM Read-Write and Read-Modify-Write Cycles teow ™ m v= } —— = Tsucra) [| Tsuccm thicica) | Tsuna) toes 0 RD it IRE Sates ERE Ss torwe th (wAH)| thiwor & We -IRERERERR EERE RRR RRR = . vin ROS RRS ONAN NANNING RRR RRA,

1 Vin XXX KREIS \\ EN, [ oara vaio NANO

“RPOTS vik RRR RROD raed ss, Galan O00 taw| [| toe. peon 1giscoe) ToeHD oe vu = thinoe) ee

MSM4416P-12, -15 65 536-BIT (16 384-WORD BY 4-BIT) DYNAMIC RAM RAS-Only Refresh Cycle ior 22) lowe) —— Vin = RAS Vi = Co 4-— Tow Tron TowAL __ vie, SORRERY OOK my, Ie amen TD i vie SARRKX) AX KKKLK KKK Ww Vin SRRRRKRKK RN RR OY Fe RAR RRNA ROXANNA RAR KARR ASR 001-004 Ym ~ARAXAXMRR RR RR RN RNY TRS V XRRMRIRININ NORRIE RAN ON ROU XNA IANKAAIRR SOOO Yo 8 _ vin RRRRRK ROAR IORI FA ARERR RRIRN XN XARA a

MITSUBISHI LSIs. MSM4416P-12, -15 65 536-BIT (16 384-WORD BY 4-BIT) DYNAMIC RAM Page-Mode Read Cycle twiAL) thinuca) = = pa Vin -2RX Lae TXXXKK PYYYYYY 7.0.9, tomas RY WY) RRR S858 RRR QAM aSSess teu) tsucay We tsuca He treme thicHre) thictied) Uh icHe a) — Vin OOO ACO 900! ROKK? COV DQ~ Vin KY eee eee rm Box vi ROXRNOYRRN YI — Hon? —— A hs uy tae [7] | 7 | =a) +F | qe va ERS DE te RE) | (ourPuTs) | TOES fay 2608 TpoeL tao) tai coe) OR S,ta08] tdis oe) se MH -Brrrnr OOTY CORY IKTKT) FE Ry BQN AYN BY a

MSM44.16P-12, -15 65 536-BIT (16 384-WORD BY 4-BIT) DYNAMIC RAM _ 5 5 36-BIT (16 384-WORD BY 4-BIT) DYNAMIC RAM Page-Mode Write Cycle twiRD) tavon. ee twioud Vin PIS a Rca RD OOD TRE SORE ERR hess we VMTKRRREER Saaaracacenene'e a KXXXKKKKKKY a LN TOUue ees ¥ “RRR VERO _ OU Th (RLW), in (WRH) DQi~ Vin-AXRXRR AAA LOO AKA Kos | YYNV rn RS CONN GRR CON RM LCG Gl RENE ASLO Oe 6 ~ en (ourPuTs) Toeno thowoey toewo th woe toeno thowoe = — Vin-2 ROY BLK AH CHONECOLOEE RRL RKRRY ERY RORY RORY RRS ce

M5SM4416P-12, -15 65 536-BIT (16 384-WORD BY 4-BIT) DYNAMIC RAM Hidden Refresh Cycle tetra) tows) thiaura) twiRH) tw cRH A Ssu(ca) Tsu (na). Tsu cna) m-YO RY’ KO BOOKA HOW sonar RR cnt I OY EEE Sones, Canes — Vi — PORERRIUS RRR WW ORRRRRY | | RRR RIERA RR RNR RRO OQ1~ Von RARER RRR Lon | EXXON. ots RRR ANN Wane RUE " TL | taco _ Vin ~ RXR KK S Oe ERTS SW NUN Nuoane ON ate MITSUBISHI ELECTRIC 2-19