M5M28F101AFP

M5M28F101AFP MITSUBISHI | Alldatasheet

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1048576-BIT (131072-WORD BY 8-BIT) CMOS FLASH MEMORY M5M28F101AFP,J,VP,RV-85,-10 (970407)1 MITSUBISHI LSIs

DESCRIPTION

The MITSUBISHI M5M28F101A is high-speed 1048576-bit CMOS Flash Memories. This is suitable for the applications with micro- processor or micro-controller where on-board reprogramming is required. The M5M28F101A is fabricated by N-channel double polysilicon gate for memory and CMOS technology for peripheral circuits, and is available in 32pin plastic molded packages.

FEATURES

PIN CONFIGURATION (TOP VIEW) Outline 525mil 32pin SOP (32P2M-A) A14 NC A16 A15 A12 VPP A10 A11 OE WE ADDRESS INPUTSADDRESS INPUTS 13 20 14 19 D 0 GND CE D 7 NC : NO CONNECTION Byte program and Chip erase Auto program and Auto erase Program/erase operation controlled by software command Program/erase pulse controlled by an embedded timer 10000 program/erase cycles Tri-state output buffer TTL-compatible input and output in read and write mode Contained device-identifier code Incorporated data-protection Available packaging for Surface Mount 1048576-BIT (131072-WORD BY 8-BIT) CMOS FLASH MEMORY M5M28F101AFP,J,VP,RV-85,-10 A13 D 6 WRITE ENABLE INPUT VCC APPLICATION Micro-computer system and peripheral equipment 15 18 16 17 D 5 D 4 D 3 D 1 D 2 M5M28F101AFP OUTPUTS DATA INPUTS/ OUTPUT ENABLE INPUT CHIP ENABLE INPUT ADDRESS INPUT 13D 0 21 Outline 32pin PLCC (32P0) A14 A13 A11 OE A10 CE D 7 A12 A15 A16 VPP VCC WE NC D 1 D 2 GND M5M28F101AJ Outline32pin TSOP type-I (8x20mm) 32P3H-F (reverse bend) A12 A15 A16 VPP VCC WE NC A14 A13 A11 D 0 D 1 D 2 GND D 3 D 4 D 5 D 6 D 7 CE A10 OE M5M28F101ARV Outline32pin TSOP type-I (8x20mm) 32P3H-E (normal bend) A11 A13 A14 NC WE VCC VPP A16 A15 A12 OE A10 CE D 7 D 6 D 5 D 4 D 3 GND D 2 D 1 D 0 M5M28F101AVP OUTPUTS INPUTS/ DATA D 6 D 5 D 4 D 3

1048576-BIT (131072-WORD BY 8-BIT) CMOS FLASH MEMORY M5M28F101AFP,J,VP,RV-85,-10 (970407)2 FUNCTION BLOCK DIAGRAM DATA PROTECTION Power Supply Voltage When the power supply voltage (Vcc) is less than 2.5V, the device ignores WE signal. Write Inhibit In the cases, as below, write mode is not set. 1) When OE is terminated to the low level. 2) From each mode beginning through finish after 2nd rising edge of WE for program, auto-program, erase, and auto- erase. Over-erase Protection Just after powering up, if erase command is inputted, erase operation is not executed. Once byte-program is performed or verified data is not FFH in the erase-verify mode, successive command input for erase will be accepted. Because of this, it is applicable to the case of multi-chip erasing simultaneously. PROGRAM VOLTAGE SW. X-DECODER Y-DECODER CHIP ENABLE OUTPUT ENABLE CIRCUITS ERASE VOLTAGE SW.

131072 WORD

SW. TIMER CONTROL CIRCUITS COMMAND LATCH D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7 CE OE WE VPP (5V, 12V) VCC (5V) GND (0V) ADDRESS INPUTS CHIP ENABLE INPUT OUTPUT ENABLE INPUT WRITE ENABLE INPUT DATA INPUTS/OUTPUTS M5M28F101A are set to the Read-only mode or Read-write mode by applying the voltage of VPPL or VPPH , respectively, to VPP pin. In Read-only mode, three operation modes, Read, Out-put disable and Stand-by are accessible. While, in Read-Write mode, four operation modes, Read, Output disable, Stand-by and Write are functional. Read Set CE and OE terminals to the read mode (low level). Low level input to CE and OE, and address signals to the address inputs (A0~A16) make the data contents of the designated address location available at data input/output(D0~D 7). Output Disable When OE is at high level, output from the devices is disabled. Data input/output are in a high-impedance (High-Z) state. Stand-by When CE is at high level, the devices is in the stand-by mode and its power consumption is substantially reduced. Data input/output are in a high-impedance (High-Z) state. Write Software command accomplishes program and erase operations via the command latch in the device, when high voltage is supplied to VPP . The contents of the latch serve as input to the internal controller. The controller output dictates the function of device. The command latch is written by bringing WE to low level, while CE is at low level and OE is at high level. Addresses are latched on the falling edge of WE, while data is latched on the rising edge of WE. Standard micro-processor write timings are used.

1048576-BIT (131072-WORD BY 8-BIT) CMOS FLASH MEMORY M5M28F101AFP,J,VP,RV-85,-10 (970407)3 When V PP is low (VPP = VPPL ), the contents of the command latch are fixed to 00H, and the device is in read-only mode. When VPP is high (VPP = VPPH ), the device enters read/write mode. The device operations are selected by writing specific software command into the command latch. Read Command The device is in read mode after writing Read Command (00H) to the command latch. The device continues to be in read mode until the other commands are written. When VPP powers-up to high voltage (VPP = VPPH ), the default contents of the command latch is 00H. So it is ensured that the false alteration of memory data does not occur during VPP power transition. Program Command Program Command is the command for byte-program, and program is initiated by twice of write cycles. Program Command (40H) is written to the command latch in first write cycle, and the address and data to be programmed are latched in second write cycle. Then the address and data are latched on the falling edge and the rising edge of WE pulse, respectively. The byte- program operation is initiated at the rising edge of WE in second write cycle, and terminates in 10 µs, controlled by the internal timer. Program Verify Command Following byte program, the programmed byte must be verified. The program-verify is initiated by writing Program Verify Command (C0H) to the command latch. After writing Program Verify Command, programmed data is verified in read mode. Then the address information is not needed. Auto Program Command Auto Program Command is the command for automated program and program-verify of one byte, and Auto Program is initiated by twice of write cycles. Auto Program Command (10H or 50H) is written to the command latch in first write cycle, and the address and data to be programmed are latched in second write cycle. Then the address and data are latched on the falling edge and the rising edge of WE pulse, respectively. The program operation is initiated at the rising edge of WE in second write cycle, and program-verify begin auto- matically. So it is not necessary to program-verify mode after this. And the complete of Auto Program can be indicated by data polling. Data polling is the indication of the complete of Auto Program. During the Auto Program, on WE=VIH and CE=OE=V IL , the data of D 0~D 7 are the inverse of written datum. When Auto Program is completed, the written datum will be output. It is necessary to fix the address of written byte during data polling. Erase Command Erase Command is the command for chip-erase, and chip-erase is initiated by writing twice of the Erase Command (20H) consecutively to the command latch. The erase operation is initiated with the rising edge of the WE pulse and terminates in 9.5ms, controlled by the internal timer. This two-step sequence for chip-erase prevents from erasing accidentally. Erase Verify Command Following each erase, all bytes must be verified. The erase verify is initiated by writing Erase Verify Command (A0H) to the command latch, while the address to be verified is latched on the falling edge of the WE pulse. The erase verify command must be written to the command latch and each address is latched before each byte is verified. The operation continues for each byte until a byte is not erased, or the last address is accessed. Auto Erase Command Auto Erase Command is the command for automated erase and erase-verify of all bytes, and Auto Erase is initiated by twice of the Erase Command (30H) consecutively to the command latch. First, the preprogram operation is initiated at the rising edge of WE in second write cycle, and so all byte become zero data. Second, erase and erase-verify begin, automatically. So it is not necessary to preprogram and erase-verify mode. And the complete of Auto Erase can be indicated by status polling. Status polling is the indication of the complete of Auto Erase. During the Auto Erase, on WE=VIH and CE=OE=V IL , the data of D 7 is "0". When Auto Erase is completed, the data of D7 is "1". (D0~D 7 are "FFH". ) Reset Command Reset Command is the command to safely abort the erase or program sequences. Following erase or program command in first write cycle, the operation is aborted safely by writing the two consecutive Reset Commands (FFH). Then the device enters read mode without altering memory contents. Read Device Identifier Code Device Identifier operation is initiated by writing 80H into the command latch. Following the command write, the manufacturer code (1CH) and the device code (D9H) can be read from address- 00000H and 00001H, respectively. The M5M28F101A is supported with the Common Device Identifier Code of MITSUBISHI 1M Flash memory (x8) family. Common Device Identifier operation is initiated by writing 90H into the command latch. Under this case, following the command write, the manufacturer code (1CH) and the device code (D0H) can be read from address-00000H and 00001H, respectively. Additionally, Common Device Identifier operation is initiated by rising A9 to high voltage for PROM programmers. SOFTWARE COMMAND

1048576-BIT (131072-WORD BY 8-BIT) CMOS FLASH MEMORY M5M28F101AFP,J,VP,RV-85,-10 (970407)4 MODE SELECTION Mode Read Output disable Stand by Read Output disable Stand by Write Read/Write Read-Only Pins CE OE WE VPP Data I/O VIL VIL VIH VIL VIL VIH VIL VIL VIH X VIL VIH X VIH VIH VIH X VIH VIH X VIL VPPL VPPL VPPL VPPH VPPH VPPH VPPH Data out Hi-Z Hi-Z Data out Hi-Z Hi-Z Data out ABSOLUTE MAXIMUM RATINGS Parameter All input or output voltage except VPP /A9 VPP supply voltage A9 supply voltage Operating temperature Storage temperature Unit V V V Conditions With respect to Ground –10~80 –65~125 RatingsSymbol VI1 VI2 VI3 Topr Tstg –0.6~7 –0.6~13.5 –0.6~14.0 Note 1 : X can be VIL or VIH SOFTWARE COMMAND DEFINITION Command Read Program (Byte Program) Program verify Auto Program Erase (Chip Erase) Erase verify Data I/O ––– Program Data Verify Data Program Data 20H Verify Data 30H FFH DDI1 Address ––– Program Address X X X X ADI Mode ––– Write Read Write Write Read Write Write Read Second bus cycle Program Address Data I/O 00H 40H C0H 10H or 50H 20H A0H 30H FFH 80H Address X X X X X Verify address X X Mode Write Write Write Write Write Write Write Write Write First bus cycle Auto Erase Reset Read device identifier code Read common device identifier code DDI2ADIRead90HWrite Note 2 : Write and read mode are defined in mode selection table. ADI = Address of Device Identifier : 00000H for manufacturer code, 00001H for device code. DDI1 = Data of Device Identifier : 1CH for manufacturer code, D9H for device code. DDI2 = Data of Common Device Identifier : 1CH for manufacturer code, D0H for device code. COMMON DEVICE IDENTIFIER CODE (not use the software command) Code Manufacturer Code Device Code Pins Hex. Data 1CH D0H D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7 VIL VIH CAPACITANCE Symbol Parameter Test conditions pF pF UnitMax TypMin Limits Ta = 25°C, f = 1MHz, Vin = Vout = 0VInput capacitance (Address, CE, OE, WE) Output capacitance C IN C OUT Note 3 : A9 = 11.5V~13.0V A1~A8, A10~A16, CE, OE = VIL, WE = VIH VCC = VPP = 5V±0.5V X X X

1048576-BIT (131072-WORD BY 8-BIT) CMOS FLASH MEMORY M5M28F101AFP,J,VP,RV-85,-10 (970407)5 DC ELECTRICAL CHARACTERISTICS (Ta = 0~70°C, Vcc = 5V±0.5V, unless otherwise noted) ILI ILO ISB1 Symbol Parameter Max Typ Limits MinTest conditions Unit Input leakage current Output leakage current VCC stand-by current VCC = 5.5V, CE = VIH ISB2 ICC1 µA 100 100 Vcc+0.5 VCC active read current VPP read current VCC = 5.5V, CE = VCC± 0.2V VCC = 5.5V, CE = VIL, f = 11.8MHz, IOUT = 0mA VPP = VPPH 0.8 100 ICC2 ICC3 IPP1 IPP2 IPP3 VIL VIH VOL VOH1 VOH2 VPPL VPPH VCC program current VCC erase current VPP program current VPP erase current Input low voltage Input high voltage Output low voltage Output high voltage VPP voltage during read-only mode VPP voltage during read/write mode µA mA µA mA mA mA µA mA mA V V V V V V 0V≤VIN≤VCC 0V≤VOUT ≤VCC VPP = VPPH 0V≤VPP ≤VCC VCC< VPP ≤6.5V VPP = VPPH VPP = VPPH VPP = VPPH IOL = 5.8mA IOH = –2.5mA IOH = –100µA 0.45 6.5 12.612.011.4 Vcc–0.4 2.0 – 0.5 Read-Only Mode tRC ta (AD) ta (CE) ta (OE) tCLZ tOLZ tDF tOH tWRR Read cycle time Address access time Chip enable access time Output enable access time Chip enable to output in low Z Output enable to output in low Z Output enable high to output in low Z Output hold from CE, OE, addresses Write recovery time before read ns ns ns ns ns ns ns ns µs6 100 100 100 Symbol Parameter Unit MaxMinMaxMin Limits M5M28F101A-85 M5M28F101A-10 AC ELECTRICAL CHARACTERISTICS (Ta = 0~70°C, Vcc = 5V±0.5V, unless otherwise noted) Note 4 : VCC must be applied simultaneously or before VPP and removed simultaneously or after VPP . Timing measurements are made under AC WAVEFORMS FOR READ OPERATIONS. 2.4 tAVAV tAVQV tELQV tGLQV tELQX tGLQX tGHQZ tOH tWHGL

1048576-BIT (131072-WORD BY 8-BIT) CMOS FLASH MEMORY M5M28F101AFP,J,VP,RV-85,-10 (970407)6 Read/Write Mode tWC tAS tAH tDS tDH tWRR tRRW tCS tCH Write cycle time Address set-up time Address hold time Data set-up time Data hold time Write recovery time before read Read recovery time before write Chip enable set-up time Chip enable hold time ns ns ns ns ns µs ns ns Symbol Parameter Unit MaxMinMaxMin Limits M5M28F101A-85 M5M28F101A-10 Note 5 : a. Read timing parameters during read/write mode are the same as during read-only mode. b. VCC must be applied simultaneously or before VPP and removed simultaneously or after VPP . tWP tWPH tDP tDE tOEH Write pulse width Write pulse width high Duration of program operation Duration of erase operation Output enable hold time before status / data polling ns ns ns ms ns 100 100 9.5 100 9.5 tDAEC tDAP Duration of auto erase operation Duration of auto program operation tVSC tOWP tOWS VPP set-up time to chip enable low Write pulse width (optional write) Write enable set-up time (optional write) tOWH Write enable hold time (optional write) tOAH tODS Address hold time (optional write) Data set-up time (optional write) s µs µs ns ns ns ns ns 1.7 1.7 400 12.5 400 12.5 AC WAVEFORMS FOR READ OPERATIONS DUT 3.3kΩ HIGH-Z tDF tRC VIH VIL VIH VIL VIH VIL VIH VIL VOH VOL 5.0V GND ADDRE- SSES CE OE WE DATA VCC ADDRESS VALID TEST CONDITIONS FOR AC CHARACTERISTICS Input voltage : VIL = 0.45V, VIH = 2.4V Input rise and fall times : ≤10ns Reference voltage at timing measurement : 1.5V Output load : 1TTL gate + CL (= 100pF) or tOH tOLZ ta (CE) tWRR tCLZ ta (AD) ta (OE) HIGH-Z 1N914 1.3V C L = 100pF µs tOAS Address set-up time (optional write) ns tODH Data hold time (optional write) ns2020 OUTPUT VALID tAVAV tAVWL tWLAX tDVWH tWHDX tWHGL tGHWL tELWL tWHEH tWLWH tWHWL tWHWL1 tWHWL2 tVPEH

1048576-BIT (131072-WORD BY 8-BIT) CMOS FLASH MEMORY M5M28F101AFP,J,VP,RV-85,-10 (970407)7 AC WAVEFORMS FOR PROGRAM OPERATIONS C0H PROGRAM VERIFY tOWP tOWS tOWH tVSC 40H DIN DATA SET DATA TO BE VERIFIEDCOMMAND SET ta (OE) ta (CE) tWRRtDPtWPHtRRW tWP tDS tDH tCS tCH tWC tAS tAH VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL 5.0V 0.0V VPPH VPPL VIH VIL VIH VIL ADDRESSES CE OE WE DATA WE CE OPTIONAL WRITE PROGRAM AC WAVEFORMS FOR ERASE OPERATIONS A0H ERASE VERIFY tVSC 20H 20H COMMAND SET COMMAND SET DATA TO BE VERIFIEDCOMMAND SET ta (OE) ta (CE) tWRRtDEtWPHtRRW tWP tDS tDH tCS tCH tWC tAH VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL 5.0V 0.0V VPPH VPPL ADDRESSES CE OE WE ERASE tAS VCC VPP DATA VCC VPP tOAS tODS tOAH tODH COMMAND SET

1048576-BIT (131072-WORD BY 8-BIT) CMOS FLASH MEMORY M5M28F101AFP,J,VP,RV-85,-10 (970407)8 AC WAVEFORMS FOR AUTO PROGRAM OPERATION AC WAVEFORMS FOR AUTO CHIP ERASE OPERATION ADDRESSES ADDRESSES CE OE WE DATA VCC VPP CE OE WE DATA VCC VPP tVSC 10H or 50H Din COMMAND SET OUTPUT ta (OE) ta (CE) tDAP tWPHtRRW tWP tDS tDH tCS tCH VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL 5.0V 0.0V VPPH VPPL tOEH ADDRESS VALID Din tWC tAS tAH ADDRESS VALID PROGRAM / DATA POLLING ta (AD) DATA SET ADDRESS VALID DinDin OUTPUT tVSC 30H 30H COMMAND SET COMMAND SET D 7OUTPUT ta (OE) ta (CE) tDAEC tWPHtRRW tWP tDS tDH tCS tCH tWC VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL 5.0V 0.0V VPPH VPPL ERASE / STATUS POLLING tOEH "0" D 7 / (D0~D 7)OUTPUT "1" /(FFH) "0" D 7OUTPUT

1048576-BIT (131072-WORD BY 8-BIT) CMOS FLASH MEMORY M5M28F101AFP,J,VP,RV-85,-10 (970407)9 PROGRAMMING AND ERASE ALGORITHM FLOW CHART PROGRAM : VCC = 5V, VPP = VPPH ADDR = FIRST LOCATION X = 0 WRITE PROGRAM COMMAND DURATION = 10µs X = X + 1 DURATION = 6µs WRITE PROGRAM- VERIFY COMMAND X = 25? VERIFY BYTE? NO PASS LAST ADDR? YES VPP = VPPL WRITE PROGRAM DATA WRITE READ COMMAND START DEVICE PASSED 40H DIN C0H VERIFY BYTE? YES PASS FAIL DEVICE FAILED INPUT DATA INC ADDR NO FAIL ERASE : VCC = 5V, VPP = VPPH START INPUT DATA ALL BYTES = 00H? NO PROGRAM ALL BYTES = 00H ADDR = FIRST LOCATION X = 0 WRITE ERASE COMMAND WRITE ERASE COMMAND DURATION = 6µs X = 1000? NO VERIFY BYTE? PASS LAST ADDR? YES VPP = VPPL WRITE READ COMMAND DEVICE PASSED DEVICE FAILED VERIFY BYTE? PASS FAIL INC ADDR NO DURATION = 9.5ms X = X + 1 WRITE ERASE-VERIFY COMMAND FAIL YES 20H 20H A0H YES (Erase Complete)

1048576-BIT (131072-WORD BY 8-BIT) CMOS FLASH MEMORY M5M28F101AFP,J,VP,RV-85,-10 (970407) AUTO PROGRAM AND AUTO ERASE OPERATION AUTO PROGRAM : VCC = 5.0V, VPP = VPPH DATA POLLING LAST ADDR? START PROGRAMMING COMPLETE 10H OR 50H DIN INPUT DATA INCREMENT ADDR NO AUTO ERASE : WRITE AUTO PROGRAM SETUP COMMAND WRITE AUTO PROGRAM ADDRESS DATA YES VCC = 5.0V, VPP = VPPH STATUS POLLING START ERASURE COMPLETE 30H 30H INPUT DATA WRITE AUTOERASE SETUP COMMAND WRITE AUTOERASE COMMAND