M5K4164AL-12

M5K4164AL-12 MITSUBISHI | Alldatasheet

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ys M5SK4.164AL-12, -15 65 536-BIT (65 536-WORD BY 1-BIT) DYNAMIC RAM. DESCRIPTION PIN CONFIGURATION (TOP VIEW) This is a family of 65 536-word by 1-bit dynamic RAMs, fabricated with the high performance N-channel silicongate MOS process, and is ideal for large-capacity memory avoness wor Ae +P systems where high speed, low power dissipation, and low | couuvay anoness gee fs, Ge] 7 @ PATA OUTPUT costs are essential. The use of double-layer polysilicon strope out CAS "Hg rat ves cov) Process technology and a single-transistor dynamic storage Rerness INPUT REF 122 & rede DATA INPUT cell privide high circuit density at reduced costs, and the wre CONTS WHE Bot ROW Appness use of dynamic circuitry including sense amplifiers assures Ao -ofa3 2 S strose iput low power dissipation, Multiplexed address inputs permit iy fay B ONT 42 AOORESS iNPuT both a reduction in pins to the 16-pin zigzag inline package mes ES Ba veo «sv configuration and an increase in system densities. The TEE & de As) pooness M5K4164AL operates on a 5V power supply using the Ae dag } INPUTS on-chip substrate bias generator. = FEATURES Outline 16P5A © High speed fecom sine Cycle ume Power disioaton © All input terminals have low input capaciatance and are in Sone mematble i “ ww © Output is three-state and directly TTL-compatible }eeraene | © 128 refresh cycles every 2ms MBKAIGAAL “15 180 ao || (16K dynamic RAMs MSK4116P, S compatible) © 16 pin zigzag inline package © TAS controlled output allows hidden refresh © Single 5V+10% supply © Output data can be held infinitely by CAS. © Low standby power dissipation: 22mW (max) © Low operating power dissipation: APPLICATION MBK4164AL-12 275mW (max) © Main memory unit for computers MBK4164AL-15 250mW (max) © Refresh memory for CRT © Unlatched output enables two-dimensional chip selec- tion and extended page boundary © Early-write operation gives common 1/0 capability @ Read-modify-write, RAS-only refresh, and page-mode capabilities BLOCK DIAGRAM 7 avant ae we q Put WRITE CONTROL INPUT WAT D EMSPREE FAS ©) acu 4) Vss (ov) Becoved i] tt ows. 756° COLUMNS) | Sooo Sli MEMORY Ci 3 SBOE Peet nm | | E a Gy 484) o| [.. 3 eyes As SEL! row IEMORY CE 6a g8 9 460 lROw T MEMORY CELL j se) [unser

9 MITSUBISHI

MSK4164AL-12, -15 65 536-BIT (65 536-WORD BY 1-BIT) DYNAMIC RAM FUNCTION The MSK4164AL provides, in addition to normal read, write, and read-modify-write operations, a number of other functions, e.g., page mode, RAS-only refresh, and delayed- write, The input conditions for each are shown in Table 1. Table 1 Input conditions for each mode » fend mer | ac | ove | aro | aro | Nac] wo | ve Readimoaiywite met pact Pact | ved) ae | AO wo” [ves FRE ony reves ~ act | nac | onc | onc | apd | onc | nac | OPN | ves : Autom reash "nac_[ onc | onc | one | onc | ONC tae | ene [ene | ove [one [ar | vio ves Now ACT actwe, NAC nonactive ONC don't care, VLD valid, APD. applied, OPN : open SUMMARY OF OPERATIONS _ Addressing or read-modify-write cycles, however, when the W input To select one of the 65536 memory cellsin the MSK4164AL makes its negative transition after CAS, the W negative the 16-bit address signal must be multiplexed into 8 address _—transition is set as the reference point for setup and hold signals, which are then latched into the on-chip latch by times. two externally-applied clock pulses. First, the negative. Data Output Control going edge of the row-address-strobe pulse (RAS) latches The output of the MSK4164AL is in the high-impedance the 8 row-address bits; next, the negative-going edge of the state when CAS is high. When the memory cycle in progress column-address-strobe pulse (CAS) latches the 8 column- is a read, read-modify-write, or a delayed-write cycle, the address bits, Timing of the RAS and CAS clocks can be data output will go from the high-impedance state to the selected by either of the following two methods: active condition, and the data in the selected cell will be 1, The delay time from RAS to CAS tainas-cas) '$ Set read. This data output will have the same polarity as the between the minimum and maximum values of the — input data. Once the output has entered the active limits. In this case, the internal CAS control signals are condition, this condition will be maintained until CAS goes inhibited almost until tymas-casimax (‘gated CAS’ high, irrespective of the condition of RAS. operation). The external CAS signal can be applied with The output will remain in the high-impedance state a margin not affecting the on-chip circuit operations, €.9. throughout the entire cycle in an early-write cycle. access time, and the address inputs can be easily changed These output conditions, of the MBK4164AL, which can from row address to column address. readily be changed by controlling the timing of the write 2. The delay time tamas-cas) is set larger than the pulse in a write cycle, and the width of the CAS pulse in a maximum value of the limits. In this case the internal read cycle, offer capabilities for a number of applications, inhibition of CAS has already been released, so that the as follows. internal CAS control signals are controlled by the — 1, Common I/O Operation externally applied CAS, which also controls the access if all write operations are performed in the early-write time, mode, input and output can be connected directly to give a Data Input common I/O data bus. Date to be written into a selected cell is strobed by the later 2. Data Output Hold of the two negative transitions of W input and CAS input. The data output can be held between read cycles, without Thus when the W input makes its negative transition prior lengthening the cycle time. This enables extremely flexible to CAS input (early write), the data input is strobed by _clock-timing settings for RAS and CAS. CAS, and the negative transition of CAS is set as the reference point for set-up and hold times, In the read-write ey ate MITSUBISHI ELECTRIC 2~35

MSK4164AL-12, -15 65 536-BIT (65 536-WORD BY 1-BIT) DYNAMIC RAM 3. Two Methods of Chip Selection 4, Self-Refresh Since the output is not latched, CAS is not required to keep The other function of pin 5 (REF) is self-refresh. Timing the outputs of selected chips in the matrix in a high- for selt-refresh is quite similar to that for automatic refresh. impedance state, This means that CAS and/or RAS can As long as RAS remains high and REF remains low, the both be decoded for chip selection. MSK4164AL will refresh itself. This internal sequence re- 4, Extended-Page Boundary peats asynchronously every 12 to 16 ys. After 2 ms, the on- By decoding CAS, the page boundary can be extended chip refresh address counter has advanced through all the row beyond the 256 column locations in a single chip. In this addresses and refreshed the entire memory. Self-refresh is case, RAS must be applied to all devices. primarily intended for trouble free power-down operation. Page-Mode Operation For example, when battery backup is used to maintained This operation allows for multiple-column addressing at the data integrity in the memory. REF may be used to place same row address, and eliminates the power dissipation the device in the self-refresh mode with no external timing associated with the negative-going edge of RAS, because signals necessary to keep the information alive. once the row address has been strobed, RAS is maintained. In summary, the pin 5 (REF) refresh function gives the ‘Also, the time required to strobe in the row address for the USEF @ feature that is free, save him hardware on the board, second and subsequent cycles is eliminated, thereby de- and in fact, will simplify his battery backup procedures, creasing the access and cyele times, increase his battery life, and save him overall cost while giving him improved system performance. Refresh There is an internal pullup resister (* 3MQ) on pin 5, so Each of the 128 rows (Ao ~ As) of the MSK4164AL must i¢ the pin 5 (REF) function is not used, pin 5 may be left be refreshed every 2 ms to maintain data. The methods Of open (not connect) without affecting the normal operations. refreshing for the M5K4 164A are as follows. 5. Hidden Refresh 1. Normal Refresh A feature of the MSK4164ALL is that refresh cycles may Read cycle and Write cycle (early write, delayed write Of be performed while maintaining valid data at the output pin read-modify-write) refresh the selected row as defined by by extending the CAS active time from a previous memory the low order (RAS) addresses. Any write cycle, of course, read cycle, This feature is refered to as hidden refresh. may change the state of the selected cell. Using a read, Hidden refresh is performed by holding CAS at Vj, and write, or read-modify-write cycle for refresh is not recom: taking RAS high and after a specified precharge period, mended for systems which utilize “wire-OR" outputs since gyecuting a RAS-only cycling, automatic refresh. and output bus contention will occur. self-refresh, but with CAS held low. 2, RAS Only Refresh The advantage of this refresh mode is that data can be A RAS-only refresh cycle is the recommended technique reig valid at the output data port indefinitely by leaving for_most applications to provide for data retention. A the GAS asserted. In many applications this eliminates the RASonly refresh cycle maintains the output in the ‘"° Y 29P! need for off-chip latches. high-impedance state with a typical power reduction of ene 20% over a read or write cycle. Power Dissipation 3. Automatic Refresh Most of the circuitry in the MBK4164AL is dynamic, and Pin 5 (REF) has two special functions. The MSK416AL ‘Most of the power is dissipated when addresses are strobed has a refresh address counter, refresh address multiplexer Both RAS and CAS are decoded and applied to the and refresh timer for these operations, Automatic refresh is MSK4164AL as chip-select in the memory system, but if initiated by bringing REF low after RAS has precharged RAS is decoded, all unselected devices go into stand-by and is used during standard operation just like RAS-only independent of the CAS condition, minimizing system refresh, except that sequential row addresses from an Power dissipation. external counter are no longer necessary. Power Supplies At the end of automatic refresh cycle, the internal The MBK4164AL operates on a single 5V power supply. refresh address counter will be automatically incremented. A wait of some 500us and eight or more dummy cycle is The output state of the refresh address counter is initiated necessary after power is applied to the device before by some eight REF, RAS or RAS/CAS cycle after power is memory operation is achieved. applied. Therefore, a special operation is not necessary to initiate it. RAS must remain inactive during REF activated cycles, Likewise, REF must remain inactive during RAS generated cycle. Oo MITSUBISHI 2-36 ELECTRIC

MSK4164AL-12, -15 65 536-BIT (65 536-WORD BY 1-BIT) DYNAMIC RAM ABSOLUTE MAXIMUM RATINGS Smeal Pararater Condinons mis Unt Veo Suppivvwiuge t es] Vv i Input voltage With respect 10 Vss =1-7 Vv Vo_ ‘Output voltage “a7 v To Oatpur carrent Te 7A Pa | Powe disipation ta =25% 700 nw Toor | Goering te wr tereratte ange _ de 0-70 *c Tstg Storage temperature range —65—150 *c RECOMMENDED OPERATING CONDITIONS (1a —0~70°c, sniess otherwise noted) (Note 3) ren | Prone Lee | Veo [Srey sotae _ fas | s [ss] vf Vss Supply vchage o | o v Vin tah -evel vai voltage, al inputs pes) ov Vie Low level input voltage, al inputs o8 v Note |All voltage values ove with expect to Vs ELECTRICAL CHARACTERISTICS (Ta =0~ 70°C, voc =5V + 10%, Vss=0V, unless otherwise noted) (Note 2) symbot Parameter Test conditions nit Vou _|._bov eve output voltage Lou =4.2mA [of [oa Tv] Toz Oita output erent Q toons OV SVour SS SV ee 1 Tirpet caret : | avs Vins 6.5V, Allott prs-ov | = | 10) wa | Vecwayy | Dram sweety corent rom Vec, [MSKAIB4AL-12) RAS, CAS cycing so | ma operating (Note 3. 41 MSK4164AL-15| lon =tow = mun outout ooen 45 | ma Suopiy carent Wom Veo sandy RAS = Vin ovtout oven a] ma veonany | Aton sunlv caren tom Vee. [MBKAIGAAL=12| RAS cing CAS =Vin rr retreating (Note 3 MSKAIG4AL=15] toinee)= mn, output open es | veoutayy | a ay Voc. [MSK416¢AL-12| RAS =Vic vet [ma | base mote (Note 3.4)[MSKAIG4AL=15|_tope= or. outout open _ werage supply current from 5 RAS=Vin. ‘cycling Toman) | Baal Veo [MBKAI64AL-121 RAS=Vin, REF cine | utomaticretvening (Note 3) TMBKAIGAAL=I5] Uc (AEF)=mIn . oviout open [fas [ma _| RAS = Vin, REF = Vi. Yooecav) | Average supoly curren from Voc. sl eleshing anna rio Input capacitance, data input Vi=Vss Craw) | Inout capacitance, write control input 1=1MHz (see | [Cr tmagy | teow canciance, AAS npn Y= 25mvems rs | Co Outout capacitance Vo=Vss.1=IMHz Vizsmvems [| | | 7-4 Note 2 Current lowng ito an ICs positive. out ws negative 3 tecrtavn lecatavy. lecacavy and Leoscav) ae dependent on cycle rate, Maximum cutret is mestured a he fastest cycle rave, 4 Ic itav) ard Iecacay) ate devendent on outout leading, Specified values are obtained withthe output open SSS

M5K4164AL-12, -15 65 536-BIT (65 536-WORD BY 1-BIT) DYNAMIC RAM TIMING REQUIREMENTS (For Read, Write, Read-Modify-Write, Refresh, and Page-Mode Cycle) (Ta=0~70C, Voo=$V + 10%, Vs5=OV. unless otherwise noted, Se notes 5, 6 and 7) “MBKATG4AL- 15 Symbol anna Lins Unit a ws [Moe | twimasin | RASrian poisewigm tae gto Ts | twonasy | RAStowpulsewam tras [t20 | t0000 {80 | yo000 Twicas.d TRSiow pulse mdr tas [es 2 ns Twicasn) CAB righ pulse wath ore 8) top a ns Tncnas-cas) | CASraidwpeater RAS tose [eo sos Twreas.aas) | FASroidumentin CAS | tse [go PTs Tsucna.nas) | Row ates stu wre baore AAS [tase | Column addres setup time before CAS ey re [Tncrasinay [Row ettrnshoia meatier RAS [tna Tso Ts Tnieasica) | Cohmnaairessnotumestie CAS [town [zo Ps ns | Trinas.ca) | Column address hola tie ater FAS 135 _| tom Transition time trun Note ® Ar ital pause of S0Qus is required after power up followed by any eight FEF, RAS or RAS/CAS cycles betore proper device operation vs achieved 6 The switching characteristics are detined 36 ty, = rum = 508. 7 Relerence levels of put signals 3f€ Vinee, 399 Vin mas Reterence levels for transition time ate also between Viy4 3d Vie Except for page mode 8 tgicas mas) requirement is only aoplicable for RAS/CAS cycles preceeded by 2 TAS onty cycle (ve. For systems where CAS has not been decoded with AAS) 10 Operation within the £6 (Rias-Cas) ax iit insures that La (Ras) max can be wet. Ld (Ras.cas)max ss specitied relerence point nly {a cwas-cas) 1 eater than the speciied Yd (pas-cas) Mae liat, then acess time is cont oiled exclusnely by 1eicas td (nas-cas}min = th (pas-naymin + 2t Tw. ren) * Usu(ca-casymin SWITCHING CHARACTERISTICS (12 =0~ 70°C .. Voc =5V + 10%. Vsg=OV, unless otherwise noted) Read Cycle Avenaiwe [__MSKA1E4AL=12 MSKAI64AL- 15 Svebo! Pararveter Limits Gts Unit a Mo] Mex | Min Max ter Read cycle me Tac 220 a ee | isucmcas) | Reedwivprinenetore CaS | tos Ps [ thrcasny [ Reaahoiatimeatie€aS Now) | tow PT ns [ thinas-n) | Readhoidtime attr RAS Note i [trams | to Tao Ouibut disable time - sNow 121 [oo CAS access time (Note 13) | [tecnasy | RAS accom tine Now vat | trae Pte 50s Note 11 Euther th (nasa) or th (CAaS-A) Must be satisfied fora read cycle Note 12. 1dis (cag)max defines the time at which the output achieves the apen circuit condition and is not reference to Vow OF Vou Note 13. This isthe valve when td (Ras-cas)='d(nas-casimax. Test conditions, Load = 27 TLC, = 100pF Note 14 This me value when td ¢nas-cas)<1d(nas-cas)max. When td (RAs-cAs)ztd (Ras-casimax, te (Aas) will inciease dy the amount that 1a mas-cas) *acreds eval show Test conditions Coad = 2T TL, Cy * 1000F Write Cycle Aienatne MSK4T64AL-12 MBKAT64AL-15 | Symbol Parameter Limits i Lins Unit Symbol ee tin = We im tow Wie cycle nme tre 220 260 ns Thicas-w) | Wrte hold ume after CAS twow | a Les Theaas-w) | Write hold ume afer RAS twer | 90 _s as Thow-nas) | RAShold ume after write Tawe 40 45 ins Thiw-cas) | CAB hold tne after wre Tow. 0 6 Ths two) Waive pute width twe [ao as ns Tsu (p-cas) _| _Datainsetup time before CAS ___ | tos of ° ns Th(cas-0) | _Datain hold time after CAS Tox 0 5 ns Th nas-0) | Dataun ole we after RAS Tour 0 [35 as

MSK4164AL-12, -15 65 536-BIT (65 536-WORD BY 1-BIT) DYNAMIC RAM Read-Write and Read-Modify-Write Cycles | ‘Altemative MSK4164AL-12 MSK4164AL-15 Symbol Parameter Limats vs it “ es ec js teaw ead-waite cycle time Wove 18) tawe 245 T2a0 | [hs thow-nas) _|_FAS hold we ater write tam | 40 | ee t i [ 45 I [triw-cas) | CAS rotd timeaterwne tome | ~[as Twow) [wre ou mom _ “tw o | ~o ) as Tsu (p-cas) | Reed setup time before CAS tres o of as Ta nas-w) | Delay time, RAS ca waite Woe 17) | tawo | 100 120 ns to(cas-w) _|_Oelay ume CAS to write wow [town [oT eo ns [ isu iom) | Daainsewptineretoremie | tos | thow-0) Datasin hold tire after wee : Tow 0 Tas (cas) | _Outbut disable time 7 torr, 0 Ta cas) CAS access time (wore 13) | __toac [romasy | AASwcewtine Wow [tae To Tso] Note 18 t cawmin isdetined as tonw mn = td (ras.w) + thwenas) + tw (RasH) + IUTLM (tr) 16 temmw min is detined as tonmw min = ta (Rasimax + th ow-nas) + tw (Ras H)+ TTL Ctra) 17 tsu(w-cas). '8(nas-w), and £6 (cas-w) 89 "0t define the limits of operation, but ate included as electrical characteristics ly When tsu (w-cas)2tSU (w-cas yin, an earlywrite cycle is performed, and the data output Keeps the highimpedance state Wen td (aas-wi2td cras-wymin. and td (cas-w)ZtSUW-CAS ymin a aadwrite cycle is performed, and he data ofthe velected address wil be read out on the data output For all conditions other than those described above, the condition of data output (at access time and until CAS goes back to Vix) is not defined. Page-Mode Cycle ‘Alternative MSK4164AL-12 MSK4164AL-15 Symbol Parameter Senta Limuts Limits une min | Man Nin Man topon Page-mode read oycle ime 145 as toraw Page Mode write cycle time 145 [ns Te ponmw | Page Mode ead-modiy. wi evle une [= ee [iwicasiy | EaSramounewan toe Pn Automatic Refresh Cycle |__MSK4I64AL-12 | MS5K4164AL-15 Anernatie Srbo! ad simbol ee Lost [ tornasiner) | Osayime RACIOREF | tro | ST Too | Twines.) | REF tow pulse wath [tre [60 | s000 [60 8000 Tw (Aer FEF high pulse wath tr 3 | 30 (neem) "ah pal _ tr Teiner-nas) | Deavime AEF IORAS Z Trsa 30 30 {su (per-eas)| REF pulse setup time before RAS [tras [aso Tes Ts Self-Refresh Cycle Alternative MSK4164AL-12 | MSK4164AL-15 Symbo! Parameter Limits Lins Unit symbol |. = Nd cmas-ner) | Delay tine, RAS to REF [two se fT too Ts tw cnere) | REF low pul math | tree | 000 [ef s000 Te ns [Ltacnce-nas) | Osov ume, REF vo FAS tran | 250 ee a

MSK4164AL-12, -15 65 536-BIT (65 536-WORD BY 1-BIT) DYNAMIC RAM TIMING DIAGRAMS rr 18 Read Cycle inove 19) tg nas vs : \\ thinas. | Ta(cas-ras) | | | Twirasny: Td (ras-cas): | thicas-aas ——-a Tsuna-ras) [trecas a) tsu(ca-cas) - tnvoas-cay r teuie oval | aos ineeas n) woe RX WV Write Cycle (Early Write) nore 19) taccas-nas) | thcas-ras ! Lwcaash. tocnas-cas) ; tw casi; ———o| Tsucna-nasy [themas. nay tsu(ca-cas) throas-cay | im RX XY COLUMN AXXKK KK KKK YY KE KRY eR ROW | | thiw-cas): tsu(w-cas) ‘ thicas-w) — Vin. —SOYIERRRA RRA tw cw BADLY RONERE ARERR ERR RRR RRB TR RRS RANA th¢nas-w of newinis— Tsu(o-cas thicas-o) Vis SRY EXER RRA RK, {omc RIO OOK RIOR © TERRE KXAN KAA R ORION

M5K4164AL-12, -15 65 536-BIT (65 536-WORD BY 1-BIT) DYNAMIC RAM Read-Write and Read-Modify-Write Cycles inote 19) a ——-'himas-cas)——. 1 1eccas-nas) | th(oas-nas) oJ twirase)- toucranas)| |tncras-aay tsu(ca-cas) | Intense . vin — 3 C scetss AXX C) Some) SCCM U UIE YOUU | KOKA RRS ae w) —thow-cas) tsuca-cas) LL tavoas w es mas) a w Vin ~ TR RO ROOK it RRR RY i BOR twiw)al ———ta(cas)- tdis(cas) — ume TSU (0-W) ped thew) AT ied 66:00 0:0,00:0:0. Ces POM 4s Tees ys {oar vai AY YY PSCCTN O0.9.6:4 | On RRR RRR A Re AA Dare vac KERR ARS RAS-Only Refresh Cycle wove 20) _ ——ter. - vin SEERA a. ORION ROW Note 18. Nowe 19. REF - Vig

MSK4164AL-12, -15 AM 65 536-BIT (65 536-WORD BY 1-BIT) DYNAMIC R. Page-Mode Read Cycle ise 19: a mM = ThcRas- Ca). 'g(Gas-RAS) TT tepon —th(cas-nas)——§——_] “ “ thanas-nay \\ thicas-ca) Swcoasiy ithicas-ca) | thicas-ca) | m PRY OLTRL ATR Fac oN IYI ‘ees a OOK moves | | Ltarcas)— | Leta rcas). be taccasy—ey H lais(cas) L ta(nas)~— + tais(cas) tais(cas) | ~ | SerNy | Vi. TaN Vig You = A q < y | 0 (en cn “ne stare > Go» Gacy —. ] Tsu(a-cas) } on — TOK Y EN 3 Page-Mode Write Cycle waves) ae vn - th mas:CA) “| | ; i 1g (cas-RAS) spew —_t n(CAS- Ras) Taaascasy) fT twccase. twicasw. | S(RAS:CAS) Twieast) ~twies y} oY > Afiwcasn NY | j we Ansa nay fealtnicascay | MOAS thccas-ca) thcoas-cay - Nx WGN ONES », LOTR or OTT vi = gPAgDRESS NPM oo nt I RL) contin Tnicas.wike—oy iaaarens wel ~thcw-cas): as . ony 7 ry ROOT KTIVINR Ht fi 4 Mi Wh , twow new) “tnewcas) teow) — Or KI AT ne EE Xone o KR © A SERS oer vac ERRER on cao ORREORRE DM oa waco RRRRRRRRERE th (RAS-D)- eee MITSUBISHI onae ate MITSUBIS

MSK4164AL-12, -15 65 536-BIT (65 536-WORD BY 1-BIT) DYNAMIC RAM Automatic Pulse Refresh Cycle (Multiple Pulse) ior 21) q Td (RAS-REF) to(REF) su (REF-RAS) Twi REEL). twiREFL) Tw(REFL). poner nas) =e UN Automatic Pulse Refresh Cycle (Single Pulse) (sow 21) a 7 FAS Ta( RAS-REF) Tsu(REF-RAS) 1g (REF-AAS) twcREFL Self-Refresh Cycle nore 2) vu [lgcras: REF) fairer, nas)! | twinere a Hidden Automatic Pulse Refresh Cycle __ READ CYCLE REFRESH CYCLE REFRESH CYCLE PO mas Ym twonase . ta (casvnas) tatras-cas) Pe a tsuina-ras) P thicas-oa) ag Ye IRF raw APTA ARAL KEKE RA KRIRE RIARRY r woo 2 RD eee yom tsycn-cas, ~ vin —PYYVYYXY OVYVV VY VU V YR EVP we i NIINNNUN AUN NNN NNN iN a | twererey be BEES tacras) | taisicas) Yon N\\ eee fe MITSUBISHI ELECTRIC 2-43

MSK4164AL-12, -15 65 536-BIT (65 536-WORD BY 1-BIT) DYNAMIC RAM Hidden Self-Refresh Cycle Ve tira) RRS es td (cas AAS? pon ¥™ WAR F FO LIV XO frow ro REM core con ee tsuncas), || thoras-A) cae w via —YYVVVH “CNCCOCOCOEEOSOYOOS 8000 009,090,0,9 66 we RY Oe reeeecaceeee ee 1 _faas) tars (cas) — NN V7) Hidden Refresh Cycle iow 19) Aw (pase) twiAase) twirast) as Ys i ca i thicas-ca) | tncnas-Ra) |. ~Toucra wu ane na) tyucranas) as vn RD ra KR) ul LORRY m8 WORK RO coe WRK om ee RX cone) ia Ian Recon RANA ANANN cco sRN RN ANIOOK aes tsu(CA-Cas) au ws) - vin, — RXR BARK RAR OY ve nl nn Vou — Wk , Vl fe MiTsuesH 2-44 ELECTRIC