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Document overview
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- PDF pages: 70
Technical content
Datasheet sections
- 1 Description
- 1.1 Block protection
- 2 Signal descriptions
- 2.1 Address inputs (A0-A18)
- 2.2 Data inputs/outputs (DQ0-DQ31)
- 2.3 Chip Enable (E )
- 2.4 Output Enable (G )
- 2.5 Output Disable (GD )
- 2.6 Write Enable (W )
- 2.7 Reset/Power-down (RP )
- 2.8 Latch Enable (L )
- 2.9 Burst Clock (K)
- 2.10 Burst Address Advance (B
- 2.11 Valid Data Ready (R)
- 2.12 Write Protect (WP
- 2.13 Supply voltage (V DD)
- 2.14 Output supply voltage (V DDQ)
- 2.15 Input supply voltage (V DDQIN)
- 2.16 Program/erase supply voltage (V PP)
- 2.17 Ground (V SS and VSSQ)
- 2.18 Don’t use (DU)
- 2.19 Not connected (NC)
- 3 Bus operations
- 3.1 Asynchronous bus operations
- 3.1.1 Asynchronous bus read
- 3.1.2 Asynchronous latch controlled bus read
- 3.1.3 Asynchronous page read
- 3.1.4 Asynchronous bus write
- 3.1.5 Asynchronous latch controlled bus write
- 3.1.6 Output Disable
Datasheet sections
- 5.6 Program suspend status (bit 2)
- 5.7 Block protection status (bit 1)
- 6 Maximum ratings
- 7 DC and AC parameters
- 8 Package mechanical
- 9 Ordering information
- 10 Revision history
Features
/square6 Supply voltage –V DD = 2.7 V to 3.6 V for program, erase and read –V DDQ = VDDQIN = 2.4 V to 3.6 V for I/O buffers –V PP = 12 V for fast program (optional) /square6 High performance – Access times: 70, 80 ns – 56 MHz effective zero wait-state burst read – Synchronous burst read – Asynchronous page read /square6 Hardware block protection –W P pin for write protect of the 2 outermost parameter blocks and all main blocks –R P pin for write protect of all blocks /square6 Optimized for FDI drivers – Fast program / erase suspend latency time < 6 µs – Common Flash interface /square6 Memory blocks – 8 parameters blocks (top or bottom) – 31 main blocks /square6 Low power consumption – 5 µA typical deep power-down – 60 µA typical standby for M58BW016DT/B 150 µA typical standby for M58BW016FT/B – Automatic standby after asynchronous read /square6 Electronic signature – Manufacturer code: 20h – Top device code: 8836h – Bottom device code: 8835h /square6 100 K write/erase cycling + 20 years data retention (minimum) /square6 High reliability level with over 1 M write/erase cycling sustained /square6 RoHS packages available PQFP80 (T) LBGA80 10 × 12 mm LBGA www.numonyx.com
M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB Contents 5.5 V
Table 24. LBGA80 10 × 12 mm - 8 × 10 active ball array, 1 mm pitch, package mechanical data . . 54
M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB Description
1 Description
The M58BW016DT, M58BW016DB, M58BW016FT and M58BW016FB are 16-Mbit non- volatile Flash memories that can be erased electrically at the block level and programmed in-system on a double-word basis using a 2.7 V to 3.6 V V DD supply for the circuit and a VDDQ supply down to 2.4 V for the input and output buffers. Optionally a 12 V V PP supply can be used to provide fast program and erase for a limited time and number of program/erase cycles. The devices support asynchronous (latch controlled and page read) and synchronous bus operations. The synchronous burst read interface allows a high data transfer rate controlled by the burst clock, K, signal. It is capable of bursting fixed or unlimited lengths of data. The burst type, latency and length can be configured and can be easily adapted to a large variety of system clock frequencies and microprocessors. All writes are asynchronous. On power-up the memory defaults to read mode with an asynchronous bus. The devices have a boot block architecture with an array of 8 parameter blocks of 64 Kbits each and 31 main blocks of 512 Kbits each. In the M58BW016DT and M58BW016FT the parameter blocks are located at the top of the address space whereas in the M58BW016DB and M58BW016FB, they are located at the bottom. Program and erase commands are written to the command interface of the memory. An on- chip program/erase controller simplifies the process of programming or erasing the memory by taking care of all of the special operations that are required to update the memory contents. The end of a program or erase operation can be detected and any error conditions identified in the status register. The command set required to control the memory is consistent with JEDEC standards. Erase can be suspended in order to perform either read or program in any other block and then resumed. Program can be suspended to read data in any other block and then resumed. Each block can be programmed and erased over 100,000 cycles. All blocks are protected during power-up. The M58BW016DT, M58BW016DB, M58BW016FT and M58BW016FB feature two different levels of block protection to avoid unwanted program/erase operations: /square6 The WP pin offers an hardware protection on two of the parameter blocks and all of the main blocks /square6 All program or erase operations are blocked when Reset, RP, is held Low. A reset/power-down mode is entered when the RP input is Low. In this mode the power consumption is lower than in the normal standby mode, the device is write protected and both the status and the burst configuration registers are cleared. A recovery time is required when the RP input goes High. The memory is offered in a PQFP80 (14 x 20 mm) and LBGA80 (10 × 12 mm) package. The memories are supplied with all the bits erased (set to ’1’). In the present document, M58BW016DT, M58BW016DB, M58BW016FT and M58BW016FB will be referred to as M58BW016 unless otherwise specified.
Figure 1. Logic diagram
Table 1. Signal names
Figure 2. PQFP connections (top view through package)
Figure 3. LBGA connections (top view through package)
1.1 Block protection
The M58BW016 feature two different levels of block protection. program or erase operations can be performed on any block. a flexible block protection.
Table 2. M58BW016DT and M58BW016FT top boot block addresses
Table 3. M58BW016DB and M58BW016FB bottom boot block addresses
Signal descriptions M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB
2 Signal descriptions
See Figure 1: Logic diagram, and Table 1: Signal names for a brief overview of the signals connected to this device.
2.1 Address inputs (A0-A18)
The address inputs are used to select the cells to access in the memory array during bus operations either to read or to program data. During bus write operations they control the commands sent to the command interface of the program/erase controller. Chip Enable must be Low when selecting the addresses. The address inputs are latched on the rising edge of Latch Enable L or Burst Clock K, whichever occurs first, in a read operation.The address inputs are latched on the rising edge of Chip Enable, Write Enable or Latch Enable, whichever occurs first in a write operation. The address latch is transparent when Latch Enable is Low, V IL. The address is internally latched in an erase or program operation.
2.2 Data inputs/outputs (DQ0-DQ31)
The data inputs/outputs output the data stored at the selected address during a bus read operation, or are used to input the data during a program operation. During bus write operations they represent the commands sent to the command interface of the program/erase controller. When used to input data or write commands they are latched on the rising edge of Write Enable or Chip Enable, whichever occurs first. When Chip Enable and Output Enable are both Low, V IL, and Output Disable is at VIH, the data bus outputs data from the memory array, the electronic signature, the CFI information or the contents of the status register. The data bus is high impedance when the device is deselected with Chip Enable at V IH, Output Enable at VIH, Output Disable at VIL or Reset/Power-down at VIL. The status register content is output on DQ0-DQ7 and DQ8- DQ31 are at VIL.
2.3 Chip Enable (E )
The Chip Enable, E, input activates the memory control logic, input buffers, decoders and sense amplifiers. Chip Enable, E, at VIH deselects the memory and reduces the power consumption to the standby level.
2.4 Output Enable (G )
The Output Enable, G, gates the outputs through the data output buffers during a read operation, when Output Disable GD is at VIH. When Output Enable G is at VIH, the outputs are high impedance independently of Output Disable.
M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB Signal descriptions
2.5 Output Disable (GD )
The Output Disable, GD, deactivates the data output buffers. When Output Disable, GD , is at VIH, the outputs are driven by the Output Enable. When Output Disable, GD, is at VIL, the outputs are high impedance independently of Output Enable. The Output Disable pin must be connected to an external pull-up resistor as there is no internal pull-up resistor to drive the pin.
2.6 Write Enable (W )
The Write Enable, W, input controls writing to the command interface, Address inputs and Data latches. Both addresses and data can be latched on the rising edge of Write Enable (also see Latch Enable, L
2.7 Reset/Power-down (RP )
The Reset/Power-down, RP, is used to apply a hardware reset to the memory. A hardware reset is achieved by holding Reset/Power-down Low, VIL, for at least tPLPH. Writing is inhibited to protect data, the command interface and the program/erase controller are reset. The status register information is cleared and power consumption is reduced to deep power-down level. The device acts as deselected, that is the data outputs are high impedance. After Reset/Power-down goes High, V IH, the memory will be ready for bus read operations after a delay of tPHEL or bus write operations after tPHWL. If Reset/Power-down goes Low, VIL, during a Block Erase, or a Program the operation is aborted, in a time of tPLRH maximum, and data is altered and may be corrupted. During power-up power should be applied simultaneously to VDD and VDDQ(IN) with RP held at VIL. When the supplies are stable RP is taken to VIH. Output Enable, G, Chip Enable, E, and Write Enable, W, should be held at VIH during power-up. In an application, it is recommended to associate reset/power-down pin, RP, with the reset signal of the microprocessor. Otherwise, if a reset operation occurs while the memory is performing an erase or program operation, the memory may output the status register information instead of being initialized to the default asynchronous random read. See Table 22: Reset, power-down and power-up AC characteristics and Figure 17: Reset, power-down and power-up AC waveforms - control pins low , for more details.
2.8 Latch Enable (L )
The bus interface can be configured to latch the address inputs on the rising edge of Latch Enable, L, for asynchronous latch enable controlled read or write or synchronous burst read operations. In synchronous burst read operations the address is latched on the active edge of the Clock when Latch Enable is Low, V IL. Once latched, the addresses may change without affecting the address used by the memory. When Latch Enable is Low, VIL, the latch is transparent. Latch Enable, L, can remain at VIL for asynchronous random read and write operations.
Signal descriptions M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB
2.9 Burst Clock (K)
The Burst Clock, K, is used to synchronize the memory with the external bus during synchronous burst read operations. Bus signals are latched on the active edge of the Clock. The Clock can be configured to have an active rising or falling edge. In synchronous burst read mode the address is latched on the first active clock edge when Latch Enable is Low, V IL, or on the rising edge of Latch Enable, whichever occurs first. During asynchronous bus operations the Clock is not used.
2.10 Burst Address Advance (B )
The Burst Address Advance, B, controls the advancing of the address by the internal address counter during synchronous burst read operations. Burst Address Advance, B, is only sampled on the active clock edge of the Clock when the X-latency time has expired. If Burst Address Advance is Low, VIL, the internal address counter advances. If Burst Address Advance is High, VIH, the internal address counter does not change; the same data remains on the data inputs/outputs and Burst Address Advance is not sampled until the Y-latency expires. The Burst Address Advance, B , may be tied to VIL.
2.11 Valid Data Ready (R)
The Valid Data Ready output, R, is an open drain output that can be used, during synchronous burst read operations, to identify if the memory is ready to output data or not. The Valid Data Ready output can be configured to be active on the clock edge of the invalid data read cycle or one cycle before. Valid Data Ready, at V IH, indicates that new data is or will be available. When Valid Data Ready is Low, VIL, the previous data outputs remain active. In all asynchronous operations, Valid Data Ready is high impedance. It may be tied to other components with the same Valid Data Ready signal to create a unique system Ready signal. The Valid Data Ready output has an internal pull-up resistor of around 1 M Ω powered from V DDQ, designers should use an external pull-up resistor of the correct value to meet the external timing requirements for Valid Data Ready going to VIH.
2.12 Write Protect (WP )
The Write Protect, WP, provides protection against program or erase operations. When Write Protect, WP, is at VIL the first two (in the bottom configuration) or last two (in the top configuration) parameter blocks and all main blocks are locked. When Write Protect WP is at VIH all the blocks can be programmed or erased, if no other protection is used.
2.13 Supply voltage (V DD)
The supply voltage, VDD, is the core power supply. All internal circuits draw their current from the VDD pin, including the program/erase controller.
M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB Signal descriptions
2.14 Output supply voltage (V DDQ)
The output supply voltage, VDDQ, is the output buffer power supply for all operations (read, program and erase) used for DQ0-DQ31 when used as outputs.
2.15 Input supply voltage (V DDQIN)
The input supply voltage, VDDIN, is the power supply for all input signal. Input signals are: K, B, L, W, GD, G, E, A0-A18 and DQ0-DQ31, when used as inputs.
2.16 Program/erase supply voltage (V PP)
The program/erase supply voltage, VPP, is used for program and erase operations. The memory normally executes program and erase operations at V PP1 voltage levels. In a manufacturing environment, programming may be speeded up by applying a higher voltage level, V PPH, to the VPP pin. The voltage level VPPH may be applied for a total of 80 hours over a maximum of 1000 cycles. Stressing the device beyond these limits could damage the device.
2.17 Ground (V SS and VSSQ)
The ground VSS is the reference for the internal supply voltage VDD. The ground VSSQ is the reference for the output and input supplies VDDQ, and VDDQIN. It is essential to connect VSS and VSSQ together. Note: A 0.1 µF capacitor should be connected between the supply voltages, V DD, VDDQ and VDDIN and the grounds, VSS and VSSQ to decouple the current surges from the power supply. The PCB track widths must be sufficient to carry the currents required during all operations of the parts, see Table 15: DC characteristics, for maximum current supply requirements.
2.18 Don’t use (DU)
This pin should not be used as it is internally connected. Its voltage level can be between VSS and VDDQ or leave it unconnected.
2.19 Not connected (NC)
This pin is not physically connected to the device.
Bus operations M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB
3 Bus operations
Each bus operation that controls the memory is described in this section, see Table 4, Table 5 and Table 6 Bus operations, for a summary. The bus operation is selected through the burst configuration register; the bits in this register are described at the end of this section. On power-up or after a hardware reset the memory defaults to asynchronous bus read and asynchronous bus write, no other bus operation can be performed until the burst control register has been configured. The electronic signature, CFI or status register will be read in asynchronous mode regardless of the burst control register settings. Typically glitches of less than 5 ns on Chip Enable or Write Enable are ignored by the memory and do not affect bus operations.
3.1 Asynchronous bus operations
For asynchronous bus operations refer to Table 4 together with the following text.
3.1.1 Asynchronous bus read
Asynchronous bus read operations read from the memory cells, or specific registers (electronic signature, status register, CFI and burst configuration register) in the command interface. A valid bus operation involves setting the desired address on the address inputs, applying a Low signal, V IL, to Chip Enable and Output Enable and keeping Write Enable and Output Disable High, VIH. The data inputs/outputs will output the value, see Figure 8: Asynchronous bus read AC waveforms, and Table 16: Asynchronous bus read AC characteristics, for details of when the output becomes valid. Asynchronous read is the default read mode which the device enters on power-up or on return from reset/power-down.
3.1.2 Asynchronous latch controlled bus read
Asynchronous latch controlled bus read operations read from the memory cells or specific registers in the command interface. The address is latched in the memory before the value is output on the data bus, allowing the address to change during the cycle without affecting the address that the memory uses. A valid bus operation involves setting the desired address on the address inputs, setting Chip Enable and Latch Enable Low, V IL and keeping Write Enable High, VIH; the address is latched on the rising edge of Latch Enable. Once latched, the address inputs can change. Set Output Enable Low, V IL, to read the data on the data inputs/outputs; see Figure 9: Asynchronous latch controlled bus read AC waveforms , and Table 17: Asynchronous latch controlled bus read AC characteristics, for details on when the output becomes valid. Note that, since the Latch Enable input is transparent when set Low, VIL, asynchronous bus read operations can be performed when the memory is configured for asynchronous latch enable bus operations by holding Latch Enable Low, V IL throughout the bus operation.
M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB Bus operations
3.1.3 Asynchronous page read
Asynchronous page read operations are used to read from several addresses within the same memory page. Each memory page is 4 double-words and is addressed by the address inputs A0 and A1. Data is read internally and stored in the page buffer. Valid bus operations are the same as asynchronous bus read operations but with different timings. The first read operation within the page has identical timings, subsequent reads within the same page have much shorter access times. If the page changes then the normal, longer timings apply again. Page read does not support latched controlled read. See Figure 10: Asynchronous page read AC waveforms, and Table 18: Asynchronous page read AC characteristics, for details on when the outputs become valid.
3.1.4 Asynchronous bus write
Asynchronous bus write operations write to the command interface to send commands to the memory or to latch addresses and input data to program. Bus write operations are asynchronous, the clock, K, is don’t care during bus write operations. A valid asynchronous bus write operation begins by setting the desired address on the address inputs, and setting Chip Enable, Write Enable and Latch Enable Low, V IL, and Output Enable High, VIH, or Output Disable Low, VIL. The address inputs are latched by the command interface on the rising edge of Chip Enable or Write Enable, whichever occurs first. Commands and input data are latched on the rising edge of Chip Enable, E , or Write Enable, W, whichever occurs first. Output Enable must remain High, and Output Disable Low, during the whole asynchronous bus write operation. See Figure 11: Asynchronous write AC waveforms, and Table 19: Asynchronous write and latch controlled write AC characteristics, for details of the timing requirements.
3.1.5 Asynchronous latch controlled bus write
Asynchronous latch controlled bus write operations write to the command interface to send commands to the memory or to latch addresses and input data to program. Bus write operations are asynchronous, the clock, K, is don’t care during bus write operations. A valid asynchronous latch controlled bus write operation begins by setting the desired address on the address inputs and pulsing Latch Enable Low, V IL. The address inputs are latched by the command interface on the rising edge of Latch Enable, Write Enable or Chip Enable, whichever occurs first. Commands and input data are latched on the rising edge of Chip Enable, E , or Write Enable, W, whichever occurs first. Output Enable must remain High, and Output Disable Low, during the whole asynchronous bus write operation. See Figure 12: Asynchronous latch controlled write AC waveforms , and Table 19: Asynchronous write and latch controlled write AC characteristics , for details of the timing requirements.
3.1.6 Output Disable
The data outputs are high impedance when the Output Enable, G, is at VIH or Output Disable, GD, is at VIL.
3.1.7 Standby mode
Write Enable or Output Disable inputs.
3.1.8 Automatic low power mode
output data if a bus read operation is in progress. Automatic low power is only available in asynchronous read modes.
3.1.9 Power-down mode
3.1.10 Electronic signature
Memory Array command to return to read mode. Table 4. Asynchronous bus operations (1)
3.2 Synchronous bus operations
For synchronous bus operations refer to Table 6 together with the following text.
3.2.1 Synchronous burst read
synchronized to an external reference clock. Caution: The M58BW016DT and M58BW016DB are not concerned by the paragraph above. register. Refer to Figure 4 and Figure 5 for examples of synchronous burst operations. beginning at address 000000h. depending on the value of M6) or on the rising edge of Latch Enable, whichever occurs first. Table 5. Asynchronous read electronic signature operation
- BCR = Burst configuration register.
immediately at the valid clock edge or one data cycle before the valid clock edge. Synchronous burst read will be suspended if Burst Address Advance, B , goes High, VIH. If Output Enable is at VIL and Output Disable is at VIH, the last data is still valid.
3.2.2 Synchronous burst read suspend
the data bus for other higher priority devices. synchronous burst read operation can be resumed by setting Output Enable Low. Table 6. Synchronous burst read bus operations (1)(2)
- X = don't care, V IL or VIH.
- M15 = 0, bit M15 is in the burst configuration register.
- T = transition, see M6 in the burst configuration register for details on the active edge of K.
M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB Bus operations
3.3 Burst configuration register
The burst configuration register is used to configure the type of bus access that the memory will perform. The burst configuration register is set through the command interface and will retain its information until it is re-configured, the device is reset, or the device goes into reset/power- down mode. The burst configuration register bits are described in Table 7. They specify the selection of the burst length, burst type, burst X and Y latencies and the read operation. Refer to Figure 4 and Figure 5 for examples of synchronous burst configurations.
3.3.1 Read select bit (M15)
The read select bit, M15, is used to switch between asynchronous and synchronous bus read operations. When the read select bit is set to ’1’, bus read operations are asynchronous; when the read select bit is set to ’0’, bus read operations are synchronous. On reset or power-up the read select bit is set to’1’ for asynchronous accesses.
3.3.2 X-Latency bits (M14-M11)
The X-Latency bits are used during synchronous bus read operations to set the number of clock cycles between the address being latched and the first data becoming available. For correct operation the X-Latency bits can only assume the values in Table 7: Burst configuration register. The X-Latency bits should also be selected in conjunction with Table 8: Burst type definition to ensure valid settings.
3.3.3 Y-Latency bit (M9)
The Y-Latency bit is used during synchronous bus read operations to set the number of clock cycles between consecutive reads. The Y-Latency value depends on both the X- Latency value and the setting in M9. When the Y-Latency is ‘1’ the data changes each clock cycle; when the Y-Latency is ‘2’ the data changes every second clock cycle. See Table 7: Burst configuration register, and Table 8: Burst type definition for valid combinations of the Y-Latency, the X-Latency and the clock frequency.
3.3.4 Valid data ready bit (M8)
The valid data ready bit controls the timing of the valid data ready output pin, R. When the valid data ready bit is ’0’ the valid data ready output pin is driven Low for the active clock edge when invalid data is output on the bus. When the valid data ready bit is ’1’ the valid data ready output pin is driven Low one clock cycle prior to invalid data being output on the bus.
3.3.5 Burst type bit (M7)
The burst type bit is used to configure the sequence of addresses read as sequential or interleaved. When the burst type bit is ’0’ the memory outputs from interleaved addresses; when the burst type bit is ’1’ the memory outputs from sequential addresses. See Table 8: Burst type definition, for the sequence of addresses output from a given starting address in each mode.
Bus operations M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB
3.3.6 Valid clock edge bit (M6)
The valid clock edge bit, M6, is used to configure the active edge of the Clock, K, during synchronous burst read operations. When the valid clock edge bit is ’0’ the falling edge of the clock is the active edge; when the valid clock edge bit is ’1’ the rising edge of the clock is active.
3.3.7 Wrap burst bit (M3)
The burst reads can be confined inside the 4 or 8 double-word boundary (wrap) or overcome the boundary (no wrap). The wrap burst bit is used to select between wrap and no wrap. When the wrap burst bit is set to ‘0’ the burst read wraps; when it is set to ‘1’ the burst read does not wrap.
3.3.8 Burst length bit (M2-M0)
The burst length bits set the maximum number of double-words that can be output during a synchronous burst read operation before the address wraps. Burst lengths of 4 or 8 are available for both the sequential and interleaved burst types, and a continuous burst is available for the sequential type. Table 7: Burst configuration register gives the valid combinations of the burst length bits that the memory accepts; Table 8: Burst type definition, gives the sequence of addresses output from a given starting address for each length. If either a continuous or a no wrap burst read has been initiated the device will output data synchronously. Depending on the starting address, the device activates the valid data ready output to indicate that a delay is necessary be fore the data is output. If the starting address is aligned to an 8 double-word boundary, the continuous burst mode will run without activating the valid data ready output. If the starting address is not aligned to an 8 double- word boundary, valid data ready is activated to indicate that the device needs an internal delay to read the successive words in the array. M10, M5 and M4 are reserved for future use.
Table 7. Burst configuration register
0 Synchronous burst read
1 Asynchronous read (default at power-on)
- X latencies can be calculated as: (t AVQV – tLLKH + tQVKH) + tSYSTEM MARGIN < (X -1) tK. (X is an integer
000 Reserved (default value)
001 Reserved
- This feature is available for the M58BW016F version up to the full operative frequency of 56 MHz, and for
the M58BW016D version only if the operative frequency is below 45 MHz.
- The M58BW016F version has a maximum operative frequency of 66 MHz, fully factory tested.
111 Reserved
- Y latencies can be calculated as: t KHQV + tSYSTEM MARGIN + tQVKH < Y tK.
0 One burst clock cycle (default value)
1 Two burst clock cycles
0 R valid Low during valid burst clock edge (default
1 R valid Low 1 data cycle before valid burst clock edge
0 Interleaved (default value)
1 Sequential
0 Falling burst clock edge (default value)
1 Rising burst clock edge
00 Reserved (default value)
01 Reserved
10 Reserved
11 Reserved
0 Wrap (default value)
1 No wrap
011 Reserved
100 Reserved
101 Reserved
110 Reserved
111 Continuous
Table 8. Burst type definition
Command interface M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB
4 Command interface
All bus write operations to the memory are interpreted by the command interface. Commands consist of one or more sequential bus write operations. The commands are summarized in Table 9: Commands. Refer to Table 9 in conjunction with the text descriptions below.
4.1 Read Memory Array command
The Read Memory Array command returns the memory to read mode. One bus write cycle is required to issue the Read Memory Array command and return the memory to read mode. Subsequent read operations will output the addressed memory array data. Once the command is issued the memory remains in read mode until another command is issued. From read mode bus read commands will access the memory array.
4.2 Read Electronic Signature command
The Read Electronic Signature command is used to read the manufacturer code, the device code or the burst configuration register. One bus write cycle is required to issue the Read Electronic Signature command. Once the command is issued subsequent bus read operations, depending on the address specified, read the manufacturer code, the device code or the burst configuration register until another command is issued; see Table 5: Asynchronous read electronic signature operation .
4.3 Read Query command
The Read Query command is used to read data from the common Flash interface (CFI) memory area. One bus write cycle is required to issue the Read Query command. Once the command is issued subsequent bus read operations, depending on the address specified, read from the common Flash interface memory area. See Appendix A: Common Flash interface (CFI), Table 26, Table 27, Table 28, Table 29 and Table 30 for details on the information contained in the common Flash interface (CFI) memory area.
M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB Command interface
4.4 Read Status Register command
The Read Status Register command is used to read the status register. One bus write cycle is required to issue the Read Status Register command. Once the command is issued subsequent bus read operations read the status register until another command is issued. The status register information is present on the output data bus (DQ1-DQ7) when Chip Enable E and Output Enable G are at VIL and Output Disable is at VIH. An interactive update of the status register bits is possible by toggling Output Enable or Output Disable. It is also possible during a program or erase operation, by deactivating the device with Chip Enable at V IH and then reactivating it with Chip Enable and Output Enable at VIL and Output Disable at VIH. The content of the status register may also be read at the completion of a program, erase or suspend operation. During a Block Erase or Program command, DQ7 indicates the program/erase controller status. It is valid until the operation is completed or suspended. See the section on the status register and Table 11 for details on the definitions of the status register bits.
4.5 Clear Status Register command
The Clear Status Register command can be used to reset bits 1, 3, 4 and 5 in the status register to ‘0’. One bus write is required to issue the Clear Status Register command. Once the command is issued the memory returns to its previous mode, subsequent bus read operations continue to output the same data. The bits in the status register are sticky and do not automatically return to ‘0’ when a new Program or Erase command is issued. If any error occurs then it is essential to clear any error bits in the status register by issuing the Clear Status Register command before attempting a new Program, Erase or Resume command.
Command interface M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB
4.6 Block Erase command
The Block Erase command can be used to erase a block. It sets all of the bits in the block to ‘1’. All previous data in the block is lost. If the block is protected then the erase operation will abort, the data in the block will not be changed and the status register will output the error. Two bus write operations are required to issue the command; the first write cycle sets up the Block Erase command, the second write cycle confirms the Block Erase command and latches the block address in the program/erase controller and starts it. The sequence is aborted if the Confirm command is not given and the device will output the status register data with bits 4 and 5 set to '1'. Once the command is issued subsequent bus read operations read the status register. See the section on the status register for details on the definitions of the status register bits. During the erase operation the memory will only accept the Read Status Register command and the Program/Erase Suspend command. All other commands will be ignored. The command can be executed using either V DD (for a normal erase operation) or VPP (for a fast erase operation). If VPP is in the VPPH range when the command is issued then a fast erase operation will be executed, otherwise the operation will use VDD. If VPP goes below the VPP lockout voltage, VPPLK, during a fast erase the operation aborts, the status register V PP status bit is set to ‘1’ and the command must be re-issued. Typical erase times are given in Table 10. See Appendix B: Flowcharts, Figure 24: Block erase flowchart and pseudocode, for a suggested flowchart on using the Block Erase command.
4.7 Program command
The Program command is used to program the memory array. Two bus write operations are required to issue the command; the first write cycle sets up the Program command, the second write cycle latches the address and data to be programmed in the program/erase controller and starts it. A program operation can be aborted by writing FFFFFFFFh to any address after the program set-up command has been given. Once the command is issued subsequent bus read operations read the status register. See the section on the status register for details on the definitions of the status register bits. During the program operation the memory will only accept the Read Status Register command and the Program/Erase Suspend command. All other commands will be ignored. If Reset/Power-down, RP , falls to VIL during programming the operation will be aborted. The command can be executed using either VDD (for a normal program operation) or VPP (for a fast program operation). If VPP is in the VPPH range when the command is issued then a fast program operation will be executed, otherwise the operation will use VDD. If VPP goes below the VPP lockout voltage, VPPLK, during a fast program the operation aborts and the status register VPP status bit is set to ‘1’. As data integrity cannot be guaranteed when the program operation is aborted, the memory block must be erased and reprogrammed. See Appendix B: Flowcharts on page 59, Figure 22: Program flowchart and pseudocode, for a suggested flowchart on using the Program command.
M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB Command interface
4.8 Program/Erase Suspend command
The Program/Erase Suspend command is used to pause a program or erase operation. The command will only be accepted during a program or erase operation. It can be issued at any time during a program or erase operation. The command is ignored if the device is already in suspend mode. One bus write cycle is required to issue the Program/Erase Suspend command and pause the program/erase controller. Once the command is issued it is necessary to poll the program/erase controller status bit (bit 7) to find out when the program/erase controller has paused; no other commands will be accepted until the program/erase controller has paused. After the program/erase controller has paused, the memory will continue to output the status register until another command is issued. During the polling period between issuing the Program/Erase Suspend command and the program/erase controller pausing it is possible for the operation to complete. Once the program/erase controller status bit (bit 7) indicates that the program/erase controller is no longer active, the program suspend status bit (bit 2) or the erase suspend status bit (bit 6) can be used to determine if the operation has completed or is suspended. For timing on the delay between issuing the Program/Erase Suspend command and the program/erase controller pausing see Table 10. During Program/Erase Suspend the Read Memory Array, Read Status Register, Read Electronic Signature, Read Query and Program/Erase Resume commands will be accepted by the command interface. Additionally, if the suspended operation was erase then the Program and the Program Suspend commands will also be accepted. When a program operation is completed inside a Block Erase Suspend the Read Memory Array command must be issued to reset the device in read mode, then the Erase Resume command can be issued to complete the whole sequence. Only the blocks not being erased may be read or programmed correctly. See Appendix B: Flowcharts, Figure 23: Program suspend & resume flowchart and pseudocode, and Figure 25: Erase suspend & resume flowchart and pseudocode , for suggested flowcharts on using the Program/Erase Suspend command.
4.9 Program/Erase Resume command
The Program/Erase Resume command can be used to restart the program/erase controller after a program/erase suspend operation has paused it. One bus write cycle is required to issue the Program/Erase Resume command. See Appendix B: Flowcharts, Figure 23: Program suspend & resume flowchart and pseudocode, and Figure 25: Erase suspend & resume flowchart and pseudocode , for suggested flowcharts on using the Program/Erase Resume command.
4.10 Set Burst Configuration Register command
synchronous/asynchronous read mode and the valid clock edge configuration. Two bus write cycles are required to issue the Set Burst Configuration Register command. as if a Read Memory Array command had been issued. M1 on A1, etc.; the other address bits are ignored. Table 9. Commands (1)
- X = Don’t care; RA = Read Address, RD = Read Data , ID = Device Code, SRD = Status Register Data, PA
Block, BCR = Burst Configuration Register value.
Table 10. Program, erase times and program, erase endurance cycles (1)
Status register M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB
5 Status register
The Status register provides information on the current or previous program or erase operation. The various bits in the status register convey information and errors on the operation. They are output on DQ7-DQ0. To read the status register the Read Status Register command can be issued. The status register is automatically read after Program, Erase or Program/Erase Resume commands. The status register can be read from any address. The contents of the status register can be updated during an erase or program operation by toggling the Output Enable or Output Disable pins or by deactivating (Chip Enable, V IH) and then reactivating (Chip Enable and Output Enable, VIL, and Output Disable, VIH.) the device. The status register bits are summarized in Table 11: Status register bits. Refer to Table 11 in conjunction with the following text descriptions.
5.1 Program/erase controller status (bit 7)
The Program/erase controller status bit indicates whether the program/erase controller is active or inactive. When the program/erase controller status bit is set to ‘0’, the program/erase controller is active; when bit7 is set to ‘1’, the program/erase controller is inactive. The program/erase controller status is set to ‘0’ immediately after a Program/Erase Suspend command is issued until the program/erase controller pauses. After the program/erase controller pauses the bit is set to ‘1’. During program and erase operations the progra m/erase controller status bit can be polled to find the end of the operation. The other bits in the status register should not be tested until the program/erase controller completes the operation and the bit is set to ‘1’. After the program/erase controller completes its operation the erase status (bit5), program status bits should be tested for errors.
5.2 Erase suspend status (bit 6)
The erase suspend status bit indicates that an erase operation has been suspended and is waiting to be resumed. The erase suspend status should only be considered valid when the program/erase controller status bit is set to ‘1’ (program/erase controller inactive); after a Program/Erase Suspend command is issued the memory may still complete the operation rather than entering the suspend mode. When the erase suspend status bit is set to ‘0’, the program/erase controller is active or has completed its operation; when the bit is set to ‘1’, a Program/Erase Suspend command has been issued and the memory is waiting for a Program/Erase Resume command. When a Program/Erase Resume command is issued the erase suspend status bit returns to ‘0’.
M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB Status register
5.3 Erase status (bit 5)
The erase status bit can be used to identify if the memory has failed to verify that the block has erased correctly. The erase status bit should be read once the program/erase controller status bit is High (program/erase controller inactive). When the erase status bit is set to ‘0’, the memory has successfully verified that the block has erased correctly. When the erase status bit is set to ‘1’, the program/erase controller has applied the maximum number of pulses to the block and still failed to verify that the block has erased correctly. Once set to ‘1’, the erase status bit can only be reset to ‘0’ by a Clear Status Register command or a hardware reset. If set to ‘1’ it should be reset before a new Program or Erase command is issued, otherwise the new command will appear to fail.
5.4 Program status (bit 4)
The program status bit is used to identify a program failure. Bit4 should be read once the program/erase controller status bit is High (program/erase controller inactive). When bit4 is set to ‘0’ the memory has successfully verified that the device has programmed correctly. When bit4 is set to ‘1’ the device has failed to verify that the data has been programmed correctly. Once set to 1’, the program status bit can only be reset to ‘0’ by a Clear Status Register command or a hardware reset. If set to ‘1’ it should be reset before a new Program or Erase command is issued, otherwise the new command will appear to fail.
5.5 V PP status (bit 3)
The VPP status bit can be used to identify an invalid voltage on the V PP pin during fast program and erase operations. The VPP pin is only sampled at the beginning of a program or erase operation. Indeterminate results can occur if V PP becomes invalid during a fast program or erase operation. When the VPP status bit is set to ‘0’, the voltage on the VPP pin was sampled at a valid voltage; when the VPP status bit is set to ‘1’, the VPP pin has a voltage that is below the VPP lockout voltage, VPPLK. Once set to ‘1’, the VPP status bit can only be reset to ‘0’ by a Clear Status Register command or a hardware reset. If set to ‘1’ it should be reset before a new Program or Erase command is issued, otherwise the new command will appear to fail.
5.6 Program suspend status (bit 2)
operation rather than entering the suspend mode. has been issued and the memory is waiting for a Program/Erase Resume command.
5.7 Block protection status (bit 1)
tried to modify the contents of a protected block. been attempted on a protected block. or Erase command is issued, otherwise the new command will appear to fail. All others bits are reserved. Table 11. Status register bits
7 Program/erase controller
6 Erase suspend status
5 Erase status
4 Program status,
2 Program suspend status
1 Erase/program in a protected
6 Maximum ratings
and other relevant quality documents. Table 12. Absolute maximum ratings
- Cumulative time at a high voltage level of 13.5 V should not exceed 80 hours on V PP pin.
7 DC and AC parameters
Figure 6. AC measurement input/output waveform Table 13. Operating and AC measurement conditions
Figure 7. AC measurement load circuit Table 14. Device capacitance (1)(2)
- Sampled only, not 100% tested.
Table 15. DC characteristics
- I DDP-UP is defined only during the power-up phase of the M58BW016FT/B, from the moment current is applied with RP Low
to the moment when the supply voltage has become stable and RP is brought to High.
Figure 8. Asynchronous bus read AC waveforms Table 16. Asynchronous bus read AC characteristics
- Output Enable G may be delayed up to tELQV - tGLQV after the falling edge of Chip Enable E without
Figure 9. Asynchronous latch controlled bus read AC waveforms Table 17. Asynchronous latch controlled bus read AC characteristics
Figure 10. Asynchronous page read AC waveforms Table 18. Asynchronous page read AC characteristics (1)
- For other timings see Table 16: Asynchronous bus read AC characteristics .
Figure 11. Asynchronous write AC waveforms
Figure 12. Asynchronous latch controlled write AC waveforms
Table 19. Asynchronous write and latch controlled write AC characteristics
Figure 13. Synchronous burst read (data valid from ‘n’ clock rising edge)
- The M58BW016F first data output is synchronized with the clock’s active edge, while the M58BW016D first
data output is not synchronized with the clock’s active edge.
- In the M58BW016F devices the right access time depends on the clock frequency.
- For further details, please refer to the section 3.2 Clock signal in burst mode in the application note
Note: n depends on Burst X-Latency.
Figure 14. Synchronous burst read (data valid from ‘n’ clock rising edge)
- For set up signals and timings see synchronous burst read.
Table 20. Synchronous burst read AC characteristics (1)
- For other timings see Table 16: Asynchronous bus read AC characteristics .
- Data output should be read on the valid clock edge.
Figure 19. Power supply slope specification
- Please refer to the application note AN2601.
Table 21. Power supply AC and DC characteristics Table 22. Reset, power-down and power-up AC characteristics
- This time is t PHEL + tAVQV or tPHEL + tELQV.
8 Package mechanical
maximum ratings related to soldering conditions are also marked on the inner box label. Figure 20. PQFP80 - 80 lead plastic quad flat pack, package outline
Table 23. PQFP80 - 80 lead plastic quad flat pack, package mechanical data
Figure 21. LBGA80 10 × 12 mm - 8 × 10 active ball array, 1 mm pitch, package Table 24. LBGA80 10 × 12 mm - 8 × 10 active ball array, 1 mm pitch, package
9 Ordering information
Note: Devices are shipped from the factory wi th the memory content bits erased to ’1’. of this device, please contact the Numonyx Sales Office nearest to you. Table 25. Ordering information scheme
- Qualified & characterized according to AEC Q100 & Q003 or equivalent, advanced screening according to
AEC Q001 & Q002 or equivalent.
software to upgrade itself when necessary. show the addresses used to retrieve the data. Table 26. Query structure overview
- Offset 15h defines P which points to the primary algorithm extended query address table.
- Offset 19h defines A which points to the alternate algorithm extended query address table.
Table 27. CFI - query address and data output (1)(2)
- The x 8 or byte address and the x 16 or word address mode are not available.
- Query data are always presented on DQ7-DQ0. DQ31-DQ8 are set to '0'.
Table 28. CFI - device voltage and timing specification
- Bits are coded in binary code decimal, bit7 to bit4 are scaled in Volts and bit3 to bit0 in mV.
- Bit7 to bit4 are coded in hexadecimal and scaled in Volts while bit3 to bit0 are in binary code decimal and
Table 29. Device geometry definition 28h 03h Device interface sync./async. 29h 00h Organization sync./async.
Table 30. Extended query information
Figure 22. Program flowchart and pseudocode
- If an error is found, the status register must be cleared before further program/erase operations.
Figure 23. Program suspend & resume flowchart and pseudocode
Figure 24. Block erase flowchart and pseudocode
- If an error is found, the status register must be cleared before further program/erase operations.
Figure 25. Erase suspend & resume flowchart and pseudocode
Figure 26. Power-up sequence followed by synchronous burst read
Figure 27. Command interface and program/erase controller flowchart (a)
Figure 28. Command interface and program/erase controller flowchart (b)
Figure 29. Command interface and program/erase controller flowchart (c)
Figure 30. Command interface and program/erase controller flowchart (d)
Table 31. Document revision history January-2001 01 First Issue. 05-Jun-2001 02 Major rewrite and restructure. 15-Jun-2001 03 Nd and Ne values changed in PQFP80 package mechanical table. 17-Jul-2001 04 PQFP80 package outline drawing and mechanical data table updated. tLEAD removed from absolute maximum ratings ( Table 12). Table 19 and Table 20 clarified accordingly). Figure 13, Figure 14, Figure 15 and Figure 16 clarified. Temperature range 3 and 6 added. Table 29, Table 30 clarified. Document status changed from Product Preview to Preliminary Data. PP, IPP1 and IDD1 clarified. AC Bus Read characteristics timing t GHQZ clarified. units digit of the previous version (e.g. revision version 06 becomes 6.0). PP pin used for block protection purposes removed. Datasheet status changed from Preliminary Data to full Datasheet. controlled write AC characteristics . added to DC characteristics table. Timing tKHQV modified. 16-Oct-2003 7.2 Silicon Version added to Ordering Information Scheme. root part numbers M58BW016BT/B have been removed. LBGA80 package (ZA) removed. Lead-free option added. 90 and 100 ns access times removed and 70 ns added. Disclaimer information. Converted document to new template.