M58990P

M58990P MITSUBISHI | Alldatasheet

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OO re OS = __M58990P,-1 | - CMOS 8-BIT 8-CHANNEL A-D CONVERTER ” DESCRIPTION ‘The M58990P,-1 is used to convert analog signals to 8-bit PIN CONFIGURATION (TOP VIEW) digital values. - : The MS8990P,-1 is fabricated using silicon-gate CMOS . : technology. The M58990P,-1 can select multiplex 8 chan- m1] Ea)— ine nels of analog input. in Ea] fzd— ms | ANALOG . ANNOrS | INE] Eze — No FEATURES . iNe —-[4] [5|— ao A w—B] = Ezal— ap B | ADDRESS} . te tes Boorcane coc] Bl ave ARES prorat oureur 2*—[B] - fall—- 2" mse [_mssooor-1 [et P| urPuT ENE of —[3] 4S. Ber A CLOCK INPUT CLK —[f9} lig] 23 BGT © Single 5V supply voltage (Vee MH [Tal 2* @ TTL compatible Vere rer) [J 2* tsp © Conversion resolution of 8 bits (ven fl fie) © rerc—) SSfSRRCE, © Multiplex 8 channels of analog input oso 27—T] [is 2° DIGITAL © Broad range of analog input voltages: 0V~Voo © Conversion time: 608 © Conversion by successive approximation Outline 26P4 © Can be used online through the data bus of a micro- processér APPLICATION are read and latched in the internal address latches by the Used with microcomputers to contro! analog systems ALE signal. When the OE terminal is at low-level, the out- put terminals 2~'~27® are in a floating state so they can be FUNCTION connected directly to the data bus of a microcomputer. The The M58990P,-1 has eight analog input terminals that are * input terminal START Is used to call for the start of an ana- selected by the input signals to the 3 address terminals —_ log to digital conversion and a signal Is output through ter- (ADD A~ADD ©). The address signals of these terminals minal EOC when the conversion is completed. BLOCK DIAGRAM . " REFERENCE(+) REFERENCE(—) OUTPUT . VOLTAGE VOLTAGE ENABLE INPUT REF(+) ” ‘REF(-) OE oR @) Veo(Sv) me S [ fraszer | i tw: @—| $8] - b ot is O—] 289 LO? anaLoa ruts im, (| 232 | [coumaRNTGR 6 [-@7 IN oO—| 323 3 eg5 [8 5+ [pirat me O— [> 5 $3) 87) fourrurs ; » @ 385] 8 ; rd aos 5 28s aa Le 2 ADDRESS INPUTS 4 ADD B o— {ee . lanrve @ DECODER; . Hi ADDRESS LATCH ie (EOC END OF ENABLE’INPUT CONVERSION ee 6—b _ OUTPUT START CLK : START CLOCK INPUT . ‘CONVERSION . . INPUT : aha Mizgupise 6-3 . ELECTRIC

‘These aro analog signal Input pins. Which of the 8 Inputs Is selected, Is determined by ADD A~ADD C. An ‘analog voltage applied at the selactod pin Is converted to a digital value In the range of 2"~ 2* and output. ‘ADD A ‘ ‘The input is used for selecting which of the 8 terminals INo~IN; Is to be converted from analog to digtal. App ¢ ‘The addross input through ADD A~ADD © Is read to the address latch by the rising edge of ALE. ALE ‘Address tatch This Is the strobe signal which causes the address slgnal Input through ADD A~ADD C to be read and enable signal latched for use as an intemal address, : . This Is one of the input terminal for the rétorence voltage that Is applied to the 256A resistor ladder elult REF(+) | Roforence voltage(+) ‘The other terminal Is REF(—) and the voltage levels of theso two inputs must meet the condition: REF(-+) . > REF). 4 . This is one of the Input terminals for the reference voltage that Is applied to the 256R resistor ladder circuit | —_ REF(—) | Reference voltege(—) Tho other terminal Is REF(+) and the voltage levels of those two inputs must meet the condition: REF(-+) >REF(—). A ‘The signal at this pin controls the digital output. When the signal Is low-level, pins Z™~ 2* are in a floating 2 ‘Tho analog signal, which was input through INo~IN;, Is converted to digital data and Is output trom those 5 terminals. When OE Is tow-level, these terminals are floating. When OE Is high-level, the converted digitat 2 data is output. The MSB is 2" and the LSB Is 2%. End of conversion ‘This terminals Is used to indicate the competion of an analog to digital conversion. It ls reset by @ START signet ‘signal (high-level to low-level) and is set on completion of the conversion (iow-level to high-level). This hl ‘output is normally used to generate an interrupt request for the CPU. ‘The Input signal at this terminal Is used to start @ conversion cycle by sotting the successive approximation START | Start conversion signal ‘register. The successive approximation register Is reset by rising ftom low-level to high-level and conver sion Is started alter being-set by falling from high-level to low-ovol, [ik [cnn | pt We sgt oni te od cig ea we tripe Ra ang |

BASIC FUNCTION BLOCKS 256R Ladder Network And Switch Tree 8-channel Multiplexer Fig. 3 shows the 256R resistor ladder’ and switch tree cir- The M58990P,-1 has eight input pins (INo~IN7) used for cuit. The 256R ladder network is created in the diffusion entering analog signals. When analog signals are present process by forming 256 individual resistors into the subs- at INo~INz, the 8-channe! multiplexer selects one of those _trate. 264 of these resistors have the same value R, while signals and converts it into a digital signal. the resistor on each end of the ladder carries the value 3/ The address decoder contains an input latch circuit which 2R and 1/2R tespectively. The reference voltage source is functions to hold the input signal present at pins ADD A~ —_ applied to both ends of the ladder, and the reference vol- ADD C. This circuit is illustrated in Fig. 1, while timing of tage used to compare analog input voltages Is output at the address latch is shown in Fig.2. - each of the steps. . - The reason for using different resistance values on the | ALE ALE ends of the ladder network is illustrated in Fig. 9 (a) show- we { { ing the 1/O characteristics of the A-D converter. The diffe- ALE rent resistance values provide symmetry between the zero & { point and full scale point in the output characteristics trans- app Pos, — To fer curve. As noted in this diagram, the width of the hori- ~ADD C . decoder} Zonal axis of each step Is determined by the potential dif- ference created by each ladder resistor. The step widths Fig.1 Address latch circuit for the zero and full scale points are respectively 1/2 and Control code from successive approximation register 5 TT ALE ye tome tt Address input latched here. brs} tn ADDA —_—— ~ADD C 1 won =?) °° - Veer to Fig.2 Address latch timing za lo ' _ Input ar ke When the ALE signal is “L”, S; and S, (Fig. 1) are closed, rer: a and Sp and S3 are open. At this time, external input is inhi- eC) - bited at Sz, and the previous data is ‘sent to the decoder. When ALE transits from “L” to “H”, S, and S, open, and S, F193. 256R ladder network and switch tree and Sq close, This simultaneously latches the address data, and enables output to the decoder. At this point, the new data arriving at ADD A~ADD C is blocked at S;. Subse- _3/2-times that of the intermediate steps. : quent transition of ALE from “H” to “L” does not produce a_—‘The switch tree is an analog switch network made up of change; the latched data remains held. 510 MOSFETs, and is used to output the ladder step vol- The method for determining selection of the analog input at_ tage selected by successive approximation register INo~IN; is by reading the value of the latched address sig- © (S.A.R.) code to the comparator. The output voltage nal. Value allocations are shown in Table 1. . obtained from the 256R ladder and switch tree is increased Table 1 Address signals as related to selected or decreased in accordance with the S. A. R. code, with the analog signal pin monotonicity of the 256R ladder. [0c [ano] Tao AT Analog taput ] a Se a a a A 9 ft] 9 te . a a ee - a a ee . a . a Se a a

The comparator used In M58990P,-1 has a chopper type ~ os . Fo amplifier used to minimize input offset voltage and drift, from { p---- -{- -4 This circuit is illustrated in Fig. 4. Fig. 6 shows the oper- analog Input i ' ational timing of the comparator. vn STi At the start of the comparing cycle, Sp and S; close on the from 1 t 4 TOSAR. Positive edge of ¢ and ¢,. Analog input voltage Viv is then ladder output [ne | sent to the comparator. At the same time, the Input of the Vase Se ‘AC amplifier AC amplifier is biased at point A shown In the I/O charac- teristics curve of Fig. 6. - Fig.4 Comparator When S> and S; open, $2 closes on the positive edge of ¢2, and the difference voltage A V derived from comparing : analog input voltage Vw. and reference voltage Vaer from ee osaenatce the ladder appears at AC amplifier input. Amplification of on S oo this difference voltage causes a voltage saturated at “H” or 1 YO. “L" level to appear at output. (This is shown as point B or . ' 4 C in Fig. 5.) ' / it Offset and drift are blocked by the AC amplifier. The com- i When AY<0} /~\\ input ouput Parator results are stored in the successive approximation 3 a aa _fegister at the end of the comparing cycle. 3 AV=Vner—Vin a v ~ ve 7 i When Av>0 ? ! ~ fo, ' . ¥ q] a B «yp Bea ° Vee . Input voltage” . Fig.5 AC amplifier 1/0 characteristics pit ip Io | Compering cycle ‘Sp closes, short-circulting | rot | : | ACampiier Input and output || | H I | rot 1 ! | | | fo ‘S, closes, entering | ! | analog signal in empiiior tt ; lo - toy . i! . 1 # | | ‘2 closes, entering output from ladder In | i ; { 1 { empitier | be ! : . 5 _ \\ Comparator onus stored in SAR. 1 | Fig.6. Comparing cycle timing - - See

Successive Approximation Register When each digit (bit) in the right half of equation (3) is (S.A.R.) - weighted from 1/2 to 1/2°, the value relative to full scale The S.AR. takes the results from the comparator and con- _can be obtained. With the successive comparator method, verts them to an 8-bit binary code for use in determining _—_ successive approximations are made from MSB to LSB un- the reference voltage value that should be used in the next _ til reference’ voltage Vrer is as close to Vix as it can get. input comparison. The relationship between reference vol _The following explanation provides more specifics. tage Vrer and the binary code Is as follows: When the start pulse entered at the START pin transitions i? st from “L” to “H", the S.A.R. sets only the MSB “1”, the other =(2e, ve rs : Veer = (2'Cr+2°0s+~-2°Co) X 956 bits being reset to “0”. As a result, the voltage selected for . - . 512 and this Is used to compare with analog input Vix. Where C7+Cet +0 +0. The conversion Is started when the start pulse transition When C7=Cg=--=Co=0, Vaer=REF(—) from “H” to “L”, and the first comparing cycle is entered. Here, Vesa stands for full scale range of analog voltage, At this time, should Viy be smaller than Vaer, MSB will be which indicates the range between minimum and maximum reset to “O"..If larger, the MSB will remain “1” and the next value, or Vesn=REF(-+)—REF(—)---(2) comparing cycle will be entered. For this cycle, the bit next Cy, Ces"Co are each represented by a0 or 1 digit in the to MSB, Cg will be set, and the previous results will be car- binary code, with C; the MSB and Co the LSB. Consequent- “ried up. In other words, taking the next selected reference ly, from equation (1), we have: voltage as Vaer’, when 1,41 1 Vin>Vaer, then: Vance (Zr geCot~-t pxCo) XVesa iti hie Vea y, Vnee'= (+3) Vise “549° HREF (—) —) — SSR... HREF(—) —og(3) v . v FSR FSR ~ Vow <= WAVesn - - . Veer] Vac : , Vu 25 - 1AVien ; TTS 4 ~~ rr ‘ . + Comparing cycle . ‘Comparing cycle . c(MsB) 1 1 1 1 c(mMsB) 1 0 0 0 Ce 0 1 0 o Ce 0 1 oO 0 se Cy 0 0 1 1 Cs 0 0 1 1 Ce 0 LJ J Vanes a 0 0 0 Ve sane Cy 0 0 0 0 Cy 0 0 0 0 coy 0 ° 0 0 ~ Ce 0 0 0 0 Gy -0 0 oO 0 - Cy 0 0 0 0 (LSB) 0 o 0 0 . Co(LSB) 0 0 0 0 (0) When Vin>Vner . (0) When Viv<Vner Fig.7 Changing reference voltage during A-D conversion °

And when Vin<Vaere ERRORS AND ACCURACY OF THE A-D 1 Vesa - CONVERTER . ~ Vnee'= Veen = gig) REF (—) Resolution In the second comparing cycle, Vix [s compared with Vpes’, The analog Input voltage range over which conversion op- and the results for Cy are obtained. From there, the compa. _Fations are possible is referred to as the full scale range rator cycles are repeated until the value for Cy is obtained. (FSR), and resolution defines the number of “steps” that This process Is illustrated in Fig. 7. FSR can be broken down into. In general, n-bits of resolu- There are eight comparing cycles for each conversion cy- tion indicates that FSR can be resalved into 1/2" steps. cle, and one comparing cycle requires elght clocks. This Al80, resolution can be arrived at by taking FSR divided by means that each conversion cycle requires 64 clocks, and 2” a8 the size of the LSB. since clock frequency is 640kHz, each conversion oycle re- Consequently, for 8-bits, FSR is divided into 256 steps, and quires 100s. (Note 1)” if FSR is referenced to 5.12V, then the LSB will be 20mV. When the comparison has been made, results are latched in the output circuit, and the EOC signal is sent. The EOC : _ signal is reset to “L” by the start pulse, then set “H” when 1 The EOC signal has interrupt capability with regards to the ‘AcD ocewarter heving ! CPU, and can be tied to the start pulse for continuous con- N10} infinite rosolution | version. . 101 t to. If @ new start signal is entered during conversion, the SAR. 3 . it Is reset and starts over from that point. % 100} +1/2 188 -1/2 LB} 1 Note 1: Conversion time te, a characteristics value that will be con- g quantizing foo J” feolquantizing 1 vored later, Is defined as the time between the positive edge ony enor \\ om | othe start pulse and the positive eage of EOC. Consequent- ovo pene sab odovere | ly, to Is a combination value of conversion cycle time, EOC i 1 : delay time (1 to8 clocks), and latch cycle time applied to the 001] 7 . 1 1 ‘output circuit (1 clock). onal Hi i ! vy “EOC delay time Is determined by the state of the internal cir- 0051152 3 4 5 6657 8 ™ cuit and start pulse timing. Consequently if continuous con- Loe ‘Analog Input versions are to be run at a fixed conversion time, the start (2) A-D converter /O characteristics pulse must be applied synchronized with the positive edge of . 0G. “Enror Output Circuit +yve.sel ¢--p-4--p-4-4-4-- — As illustrated in Fig. 8, the output circuit consists of a D latch and a 3-state buffer. At the end of a conversion cycle, ° Yow the converted data is latched in the D fatch. Then when OE transits “H", the latched data Is output to pins 2~'~2~*. Wa Lap EN When OE Is “L”, pins 2-'~2"* are in a floating state. During the conversion cycle, the previous data is held in : _ theDiatch |. (©) Quantizing error : Fig.9 A-D converter I/O characteristics and quantizing ‘Signal from SAR. [> atnent errors T Quantizing Error . An inherent error in the A-D conversion process develops Internellatching signal ==“ OE signal Ss due to the fact that analog input values of less than the LSB must be rounded off. Figure 9 shows the quantizing errors Fig.8 Output clrcult occurring in a 3-bit A-D converter. The I/O characteristics : . . of a perfect 3-bit A-D converter are illustrated in Fig. 9 (a). 7 . . Where FSR is 8 and LSB is 1, as shown in the diagram, . i . . analog input voltage Viy is rounded off to n in the range of . , o—Tise < Vins $LS8 (0<n37).

• In this case; a quantizing error of 1/2 LSB is produced on ne one of the two ends of the step. : 7 Fig. 9 (b) shows how quantizing_errors are produced. Each a step is shown like the tooth of a saw, centered on 0. An in- Full ecalo error | put of full scale becomes —1 LSB. This is because output 10 y 4 codes can only be produced up to 1112=7%0, so when us- Z { ing the converter near full scale should be took care. In wi t order to reduce quantizing errors, resolution must be In- 3 100] . i creased. Perfect A-D conversion! 5 on characteristics: 1 Non-linearity Errors ord 4 1 Non-linearity error is the portion of A-D converter I/O char- * + pp conversion! acteristics that indicate the amount of deviation from the oo 4h A characteristics showing zero ideal line. These errors can be expressed as total linearity, Zero error 0 Full scale errors j or for only a portion of the scale, as differential nonlinearity. ond fear This is shown in Fig. 10. . ‘Analog input ~ Linearity indicates the amount of deviation from a straight line drawn from the start to the end of a step. Differential —_Fig.11 Zero and full scale error linearity indicates the amount that an actual step differs . from 1 LSB of perfect step width. Monotonicity is the term — Absolute Accuracy used to express the fact that rises and falls in output follow "Absolute accuracy accounts for the various errors occurring rises and falls in input, and monotonicity cannot be assured —_in the A-D conversion, and indicate how closely the output unless differential nonlinearity is tess than 1/2 LSB. code represents the analog input. Where the output cade is absolute accuracy = N—-M . Q y LSB : 1b ~ “sarc paves Sonar 1 This Is shown in Fig. 12. . "OF otterential nontinearity ! > i 101 PS H . 1 e “He cal Nonlinearity indicates m $ 10d Tusa] AT the deviation Avsolute ; H i Inearly trom this line TOF accuracy I . on = t 1 6 : 1 101 | 010) Perfect A-D ion! ry A-D converter | ae characteisiog a g 100 newing inte I oot ‘A-D conversion characteristics with | i ition nonlinear error 1 on f I “9 ren © ao Actual A comeson | - : ‘Analog Input cheracteristics ' oot l Fig.10 Nonlinearity in A-D conversion characteristics x0! v

0 FSR ™

Zero Error And. Full Scale Error ‘ (0) AD converter VO shaatentis Zero error is the error relative to the input voltage required . ° to bring the output code to alll “0"s, and full scale error is +usap ~~ ++ the error relative to the input voltage required to bring the . : 1 output code to ali “1"s. These errors are expressed as the - ‘amount of deviation from the perfect A-D conversion curve, ° \\, and are illustrated in Fig. 11., - " . : ee ee . (&) Absolute accuracy - . . o ; Fig.12 A-D converter absolute accuracy

PRECAUTIONS REGARDING REFERENCE For ladder network and switch tree structures like this, the VOLTAGE POWER SUPPLIES following precautions should be observed in the design of Fig. 13 shows a portion of the 256R ladder network and _ the reference voltage supply. : - switch tree, and Fig. 14 illustrates the turn-on resistance 1. REF (+) potential must not exceed Veo. characteristics for MOSFETs. 2. REF (—) potential must not go below GND. —- As Fig. 14 shows, where drain potential Vo approaches Vcc, 3. The value for (REF (+) + REF(—))/2 must not differ the turn-on resistance of n-channel MOSFETs Increases. greatly from the value of Voo/2. ‘On the other hand, when Vp approaches GND, turn-on re- 4. REF(+)>REF(—) must be observed. sistance for p-channel MOSFETs increases. The reason for 1 and 2 is that for MOS switches located Where threshold voltage for the two transistor types Is near the Vrer pin, their souces and substate PN junctions taken as VthN and VthP respectively, when Vp is between . are likely to forward bias, with the resulting current flow GND and VthN, p-channel MOSFETs will not turn on, and changing ladder potentials. when Vp Is In the range Voo— VthP ~Voc, n-channel ‘In 3, (REF (+) + REF(—))/2 Is the potential for the center MOSFETs.will not turn on. Due to this fact, the border of the ladder, and as shown in Fig. 13, this is the borderline formed by (REF(-++) + REF(—))/2 in the switch tree of Fig. between p-channel and n-channel switch operations. Con- 43 Is an operating limit for MOSFETs. Above this line, p- sequently, if this potential varies greatly from Vco/2, turn-on channel devices are used, and below this fine n-channel _ resistance of the n-channel swiches near the center of the devices are used. ladder will Increase. (See Fig. 14.) On the other hand, if : this value Is smaller than Vcc/2, the turn-on resistance of . ‘Control code trom SA.R. the p-channel switches will increase. REF(+) © 1 _, ‘Where turn-on resistance is high, the required settling time Bip ky after fully charging the comparator’s input capacitor becom- . | 3 an es too long, and accuracy cannot be maintained. = Fi In 4, if REF(+) < REF(—), the up-down transients of the . ' t i" t control signals from the S.A.R. will be reversed relative to . tot t t HH bon the up-down transients of the reference voltage from ladder hoy Ay ‘switch to comparator. In this case, instead of the approximations ; e || circuit converging, the bits will diverge all “O's or all “1"s. Also, as rer(+)+rer(—-) [FR noted previously, where REF (+) and REF (—) approach 2 wor GND and Vog respectively, the switches will not turn on. bated LT |e . —t+ Mos Fig.13 256R ladder network and switch tree Ton 7 1\\ Pen MosreT 1 [vo . 1 i Neh | Veo H . | | Pen |ono - ao | Noh MOSFET | . vane H Vth beoX\\ ! ||. GND es Veo ¥? . =2 Fig.14 MOS switch turn-on resistance -

ABSOLUTE MAXIMUM RATINGS . OS a van expe aNd [vo [oupitvenge A | Foor [epcuingtooarienpamuermge [tig | Sovge tenpererange PCS RECOMMENDED OPERATING CONDITIONS (1.=0~700, unless otherwise noted) | om | Loe el erence | veo | suppiyvotuse | as | | st | Guo [sumpiyvotge To | vrercy | Maxetreternce votane(+) || Moo Mectn | vf | Veeri-> | wincreencevotet-) | as] of |v - Pewee eel | Avner | Bettrentat tretorence vonage | ta] 8.25] | [Vw [rretoainputvotage TOL [Venn TV . . ELECTRICAL CHARACTERISTICS (Te=0~700 , Voo=5v +5%, unless otherwise noted) [tite ee eee ee a v [Va [Lowiovetinowtvotinge | Macey | | sft | vou | Hishiovel euputvatege | Vou) | low —60#A,Tam706 Meera] | |v | Vor | towievel ouputveiage.2"~2* ouput | Vourcor | tousteema ||| as | | Vouceoca| Lowievel oupuvatage. £06 oMput | Vouroy | loo=e2ma ||| as fv [tw [Hoover innit umont | tts | MowS.sv TT ofa | [ta | eewieverinpatcuront | twcon | Muay TT of na [tos | Ose arinesterese rtoupe| tor | vomsv | TL a [ton [om OPERA cstaga| tor | very | | tao | a rN | [te [eet nat cores (ne-Rir apa) | tonne | Veomsv.viesv ||| ato [he [otsae put caren (nev Wow) | Tore | Veo=sv.virov |__| | 200 [ — foonenieorscuin PTS [wees [=| [as] 33] [| — [omens sees] Lee | [ewww eevee [ee | So Ft ew | ‘ose i a as] | Rssoen [indorranwcs | vee [er [mrwcapectnss | Gus | Mim GN Vonainime, tims | |_| [oo [oupstcenctoncs | Cour | Vo=GND, Vomtsnvins, inte | | | _12| Note 1: Current flowing Into an IC Is positive, and Min and Max show the absolute limit. . .

TIMING REQUIREMENTS (a=256 . Voc=Vrer(+)=5V, Vaeri—1=GND unless otherwise néted) [ om [rome ‘ [enn ee oat conditions : Symbat [win [we [wax | | tworanm| sian puee wan ws | | to | [wane [Atepuve wisn | wwe | | to |e a a Lic» [etewoeo PT tc tte [nes [ns SWITCHING CHARACTERISTICS (1a=25° , Voo=Vner+)=5V, Vncr(—1=GND, unless otherwise noted) Symbol [win [ye] wox_| | iorsal Rononintnetonocwaua ae meer || | [ troroo| Penegston inetem OF teouputteaing | tw.tow | ||| so | ne tc [oweume ef feemmeatrie | |e Note 2 : A.C Testing waveform 24 Input pulse lovel 0.45~2.4V : Input pulse rise time Tons 0.45 —e.8 X Input pulse fall ime 10ns Reference level input Vir=2V, Vi=0. 8 . : output Von 2V, Vor™0.8V TIMING DIAGRAM . tors) Whos) : ue _| o: twos) ADD A VALID _¥ ‘~ADD C A soopess A eo Tougher START a twcsrane) . te : oF ee o ; . : ‘tpzxtoe-oo) tpxzcor-00) gt ny

APPLICATION EXAMPLE —. 5 5 5.120V Vi ‘Sp . T zoo Veo} <q _ 7 a . REF(+)| rour| ) » wsseooe ; Wwf—o vir) ° RD 1) OE INJ-—o Vina p= thi tft _ ' Input voltage wal q tdi START oD | yi i) I ALE y, IN] © Vine An > . ALE) ~ ‘STB Do, ~DO3| ADD A . Di; ~ADD C o [tbe . M5L8212P 8 : $ Hinge ADo~ADy tae 59409P : cuxt—2Mtz 15 qf 250 Tou AD st a ADs Ves Cy Guo