M56692FP MITSUBISHI | Alldatasheet

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Bi-CMOS & DMOS 32BIT SERIAL-INPUT LATCHED DRIVER M 56692FP MITSUBISHI <CONTROL / DRIVER IC> DES CRIPT IO N The M56692FP is a semiconductor integrated circuit that has a built-in, 32-bit shift register and a latch of CMOS structure with serial input and serial/parallel output, and a 32-bit totem-pole-type parallel output driver of high pressure proof DMOS structure. Employed are Bi-CMOS and high pressure proof DMOS processing technology. FEAT URES l Serial input - serial/parallel output l Bidirectional shift register (controlled at F/R terminal) l Cascade connections possible through serial output. l Latch circuit included for each stage. l Driver supply voltage: VH =90V l Operating temperature: -40 – 85°C APP LICAT IO N Vacuum Fluorescent Display GRID DRIVER PIN C O N FIG URAT IO N (TO P VIEW) VH SOUT(SIN) VDD F/R LGND CLK LAT SIN(SOUT) VH BLK PGND HVO 1 HVO 2 HVO 3 HVO 4 HVO 5 HVO 6 HVO 7 HVO 8 HVO 9 HVO 10 HVO 11 HVO 22 HVO 21 HVO 20 HVO 19 HVO 18 HVO 17 HVO 16 HVO 15 HVO 14 HVO 13 HVO 12 44PGND HVO 32 HVO 31 HVO 30 HVO 29 HVO 28 HVO 27 HVO 26 HVO 25 HVO 24 HVO 23 Outline 44P6N-A M5 6692FP 3-58 B LOC K D IAGR A M HVO 32HVO 31HVO 30HVO 3HVO 2HVO 1 PGND SOUT (SIN) Output protect circuit Q T D Q L D Q T D Q L D Q T D Q L D Q T D Q L D Q T D Q L D Q T D Q L D 42 4341141312 BLK LAT SIN (SOUT) CLK VH VDD LGND

4 F/R

Bi-CMOS & DMOS 32BIT SERIAL-INPUT LATCHED DRIVER M 56692FP MITSUBISHI <CONTROL / DRIVER IC> HVO1–32 Output driver (push-pull) FunctionPin name PIN FUNCT IO N D ESCRI PTIO N V DD LGND V H PGND CLK SIN SOUT LAT BLK F/R Serial data output Latch input. When the LATCH is set to “H”, the data in the shift resister will enter the each latch circuit. When the LATCH input is set to “L”, the data will be held. Enable input for output control. When the BLK input is set to “L”, data in the latch circuit will appear at outputs. When the BLK input is set to “H”, all outputs will be set to “L”. Direction Control for the internal shift resister Logic stage supply voltage Logic stage ground Output stage supply voltage Output stage supply ground Clock input for the internal shift resister. The data enter the internal shift resisters and the data in the shift registers wi ll be shifted in order by High to Low change of the clock. Serial data input Logic inputs voltage Output voltage Power dissipation range Storage temperature range Logic output voltage Logic stage supply voltage Output stage supplyvoltage VI V HV O Tstg -0.3 – 90 V O -0.3 – V DD +0.3 V DD -0.3 – 7 V H Pd -0.3 – V DD +0.3 -0.3 – V H -55 – 150 850 High supply voltage output pin Symbol Ratings UnitParameter Conditions ABS O LUT E M AXIM UM RAT ING S (Ta=25 C, unless otherwise noted) V V V V V C mW Ta £ C Data output Truth table2.Latchand driversections HVOn Dn LAT BLK X H L X Dn=nth bit DFF retention data HVOn=nth bit driver output L = “L” level H = “H” level X = “L” level or “H” level Truth table1.Shiftregistersection CLK fl H or L Shift register DATA is shifted. No changes. TRUT H TABL E X H H L H L L L Output all “L” H L Latch’s data output. fl H or L F/R H H L L Input Input/output SIN(SOUT) IN IN OUT OUT SOUT(SIN) OUT OUT IN IN DATA is shifted. No changes. Serial-output SOUT is used by connecting to the next stage M56692FP SIN when more than one M56692FP is used to expand bits in the series. In accordance with truth table 2, parallel output allows the latch to pass data through if LAT input is turned to “H”, and data to be retained if LAT input is turned to “L”. Driver output HVOn allows data from the latch to be output if BLK input is turned to “L”, and “L” to be output if BLK input is turned to “H” irrespective of data from the latch. FUNCT IO N The M56692FP comprises a 32 bit bidirectional shift register, a 32 bit latch, and a parallel output HVO 1 – HVO32 connected to its output. In accordance with truth table 1, the data transfer direction of shift register depends upon F/R input, and F/R being at “H” or open allows pin 9 to turn to SIN and pin 2 to turn to SOUT, and F/R being at “L” allows pin 2 to turn to SIN and pin 9 to turn to SOUT, permitting data transfer from SIN to SOUT, respectively. Inputting data to SIN and clock pulse to CLK allows SIN signal to be put into the internal shift register when the clock changes from “H” to “L”, and shift register data to be shifted sequentially.

Bi-CMOS & DMOS 32BIT SERIAL-INPUT LATCHED DRIVER M 56692FP MITSUBISHI <CONTROL / DRIVER IC> RO = 220KW CO = 50pF Driver output propagation time t PLH(SO) Logic output propagation time V -500 SIN, LAT, CLK BLK, F/R VTH VTL Output protect operating voltage IHVOH “H” output current VOH VOL Logic output voltage VHVOH Driver output voltageVHVOL IH Supply current 2 1 bit “H”, no load Operating temperature Supply voltage Supply voltage Topr 40 – 90 VDD 4 – 6 VH -40 – 85 Symbol Ratings UnitParameter Conditions REC O M M ENDE D O PERAT IN G C O NDITIO N S V V Limits Min. Typ. Max.Symbol Test conditions UnitParameter EL ECT R ICAL CHARACT ERISTICS (VDD =5V, VH =80V and Ta=25°C, unless otherwise noted) IDD IHVOL Supply current 1 “L” input current “L” output current IOH = -0.1mA 4.5 0.4 0.4 -250 75.5 4.9 3.3 3.0 2.5 mA mA mA V V IIH IIL “H” input current No load Output all “L”, no load IHVOH = -50mA IHVOL = 10mA VIH=5V input pin IOL = 0.1mA VIL = 0V 01 mA 0.5 0.1 -50 0.4 mA mA V mA mA Limits Min. Typ. Max.Symbol Test conditions UnitParameter SW ITCHING CHARA CT ER ISTICS (VDD =5V, VH =80V and Ta=25°C, unless otherwise noted) fCLK t PHL(SO) tPH L(O U T) trout tfout Clock frequency Driver output rise and fall time Duty = 45 – 55% 180 180 MHz ns ns ns tPLH (O U T) CL = 15pF 95 ns ns ns TEST CIRCUI T PG DUT CL CO 50W SOUT HVOn VHVDDINPUT RO (1)Characteristics of pulse generator (PG) tr£20ns tf £20ns (2)Capacitance CL includes connection floating capacitance and probe input capacitance. : RO=220KW : CO=50pF Duty cycle £ 2.5%* -100 * Maximum numbers of Outputs High State are two at the same time.

Bi-CMOS & DMOS 32BIT SERIAL-INPUT LATCHED DRIVER M 56692FP MITSUBISHI <CONTROL / DRIVER IC> TIM ING WAV EFO RM SOUT HVOn SIN BLK CLK 1/fmax thtsu tfso trso trOUT tfOUT tPLH(OUT) 50% 50%50% 50% 50% 50% tPHL(SO) 50% 50% 50% tPHL(OUT) 90% 10% 90% 50% 10% tPLH(SO) 90% 10% 90% 10%50%

Bi-CMOS & DMOS 32BIT SERIAL-INPUT LATCHED DRIVER M 56692FP MITSUBISHI <CONTROL / DRIVER IC> (Note) Duty cycle vs Permissible output current 100 0 20 40 60 80 100 Output current IOH (mA) Duty cycle (%) 100 0 204 0 608 0 100 Duty cycle vs Permissible output current Note 2432 Duty cycle (%) TYPICAL CHARAC TER ISTIC S Power dissipation Pd(W) 0.0 0.2 0.4 0.6 0.8 1.0 0 25 50 75 100 125 150 Thermal derating Temperature Ta (°C) Driver output VON –IOH -100 -80 -60 -40 -20 0 2 468 10 Ta=25°C “H” output ON voltage VON (V) “H” output current IOH (mA) Ta=-40°C Ta=85°C Output current IOH (mA) 1. VDD =5V and VH =80V unless otherwise noted. 2. Thermal derating curve represents that of an individual IC unit. 3. Allowable duty cycle output curve represents that when a standard substrate is mounted.(Standard substrate: 70x70x1.6mm glass epoxy)

  • Ta=25°C
  • Repeated frequency>100Hz
  • Figure in the circle represents the number of concurrently operating output circuits.
  • Current value denotes a numerical value per circuit. Note • Ta=85°C
  • Repeated frequency>100Hz
  • Figure in the circle represents the number of concurrently operating circuits.
  • Current value denotes a numerical value per circuit.