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MITSUBISHI <Dig./Ana. INTERFACE> +5V CONSTANT-VOLTAGE POWER SUPPLY INCORPORATED WATCHDOG TIMER IC

DESCRIPTION

The M5S296FP is a watchdog timer semiconductor integrated PIN CONFIGURATION (TOP VIEW) circuits which incorporates a 5V constant-voltage power supply. P-RUN INPUT [7 ]O. Viet: To check for system failure and assure safe system opera- cApaciTAnGe 3 Viet tions, the M5296FP has three sequential outputs (HALT, caracrneake’, 1Adj STBY, and RESET) and a watchdog timer output which cay A z : ; TEY OUTPUT a VoAdj intermittently generates a reset pulse when pulse width or DELAY 38 cycle abnormalities are found in the clock signal from the caeacirance 1 [5] $ Vo microcomputer. (The watchdog output terminal is shared by fact oureur [6] 9 file the watchdog timer output and sequential output RESET.) RESET OUTPUT 1] tor Further, each output retains the Low reset feature at crouno [BI [3] Ve supply voltages down to 0.8V, thereby preventing system malfunctioning upon power ON. - alfunctioning upon power Outline 16P2N-A

FEATURES

© Watchdog timer (clock pulse width and cycle are monitored at the same time). © Power ON reset timer. © Three outputs (HALT output for holding, RESET output for reset, and STBY output for return). © Output voltage (can be fine-tuned with an external resistor) bbe eeeet teen eteeeserereeees BVEO.25V @ The delay time can be set using an external capacitor (the setting can be varied from about 1msec to 1sec). @ Built-in overcurrent protection circuit (which can be set up with an external resistor). APPLICATION Home and industrial microcomputer systems. BLOCK DIAGRAM — Ve lor B Vo VoAdj HALT fe} {CURRENT LIM TER) << | COMPARATOR 1 1.24V REFERENCE . _ wen © Pee | be ' ComeaRATORD moog) : hiae winter Motte TR DEA P-RUN (1) rc] ps} SD 1Adj con C2 Cy ae WO ELECTRIC 165

MITSUBISHI <Dig./Ana. INTERFACE> MS5296FP +5V CONSTANT-VOLTAGE POWER SUPPLY INCORPORATED WATCHDOG TIMER IC ABSOLUTE MAXIMUM RATINGS (ta=25't unless otherwise noted) [Ve | Suppiyvorage Po | veact | RAT ouput weakiownvotage “|S | verey | STBY output beatdown votage =| SSS | vaeser | RESET eupet beatdown vine [8 [scr | PRCT ovowewent =i [ister SY oupwewen Pt | ineses | ESET ouput eunent’ ———SSSSC*iSSSSCSCSCS~CS~SSSSSSS | | Pa | Invert power consumption Pe [tstg | Storage temperature ssw eres Te] ELECTRICAL CHARACTERISTICS (vs=12v, 1o=50mA. Ci=224F, Co=1004F, Ta=25°C unless otherwise noted) [Terminal [Min [tye [Max Bies current [oe is | eo Tm vo Output votage | Wari, versseov | | | Rest | tons sapiny So sc SCSCSCSCSC*id eo [ao | ing prongs oe ee Hae ata we sts —___2ttaetaep | Veer | FACT outpu sawatenvotage =| war=@ma—SSSSSCSC~SCS@ | | | vsois | STB¥ ouput enuretonvotage | isisv=sma—SSCS™~S@SSS*d ee [via | FACT owen vote SOC oo avo] vo |v [ian | RESET output lek cure Sd Smee SSC*dC [mmr | Fattoupw soucscwren 2 | SSC*~C~SS@ | | [ine | PauNinpwewert | Vs a | 200 500 Ta [vive | PRUNH moa votage [View PRUNT npstvolage SSS [Thinwy | Wendog set vse wah SCE SSCSCSCSC~wCSSYC ||| [iatw | Wariogune im OTS nF Opea.tene | | a0 | aw | OTs | [tay | RESET ouou devi ——SC*dC OO «YS | Ss SC ec [ef a} a0 | 620s | | stews [PRON input ranmum game wah | en0 soo 880 Ts | [vou | Yarnmumopermngvotge —e# | | oT | [von | Vomnmsn opretngvotwge #8 | we Oe | | [Wie | Covent ner dsecion votoge wT) 0 | ae Pa [200 || Note #1. Vin 15 the threshold voltage for Vrety. Its 10 be Set up Ly an external resistor. The setup must be such that Vii >Vin2 #2: A curtent that source when the HALT terminal s grounded in the HIGH HALT output mode (when Vo 1s normal) #3) When Ta= ~20 to +75'C, Is(H| > laa) #4 The Va minimum operating voitage at which each function works ___ _ #5: The Vo minimum operating voltage at which the HALT output, RESET output, and STBY output stay Low. 86. In the overcurrent operation state, the current limiter works when the external resistor (Rs) vottage (voltage developed between terminals @ and £8) drops 130 mv (TYP) oF more Output peak curent —lop= 9513 tah MITSUBISHI 7-66 oot

MITSUBISHI <Dig./Ana. INTERFACE> MS296FP +5V CONSTANT-VOLTAGE POWER SUPPLY INCORPORATED WATCHDOG TIMER IC DEFINITION OF TERMS ts(H) : HALT output delay time. trinw) : Watchdog reset pulse width. The time interval between the instant Vg is restored to The width of an about 50% duty intermittent pulse that the Vru1 £AVrH1 level and the instant the HALT is generated from the RESET terminal when the clock output is remove signal input to the P-RUN terminal has alow input level, te(pw)_: P-RUN input minimum pulse width. an insufficient pulse width, an excessively long period, The minimum pulse width for clock signal normality or other problem. detection. Vin-e P-RUN H input voltage. Cycle t= 2-tiaw) The minimum input voltage for P-RUN terminal input clock signal High level detection. tainw) : Watchdog time. Vin-pL : The maximum input voltage for P-RUN terminal The time for clock signal monitoring or the maximum input clock signal Low level detection. clock cycle during which clock signal normality is de- tected. tain) * RESET output delay time. The delay time from the instant the STBY output is remove to the moment the RESET output is remove. tain) ‘ RESET output delay time. The time interval between HALT output fall/rise and RESET output fall/rise in cases where the STBY output is not generated (when Vo does not drop below V2). APPLICATION CIRCUIT EXAMPLE Rs Veo OVo oe a se @ lop RESET RESET OUTPUT o-aow YY} war ovr INPUT. CO} P-RUN STBY Cam ‘SYBY OUTPUT pk ee oI ad) Veet i at (so Vr HO I] | ua | OO“F Oc alsl| a] c oe eli“ /e Fa m GNO 2 lies si2]2]8] > ig is|sis oGND Cj, Co Necessary for oscillation prevention and input/ If the watchdog timer function is not to be used, ground output stabilization. Be sure that these devices are used terminal ©). near the IC pins. Cy + Required for watchdog time setup. If the watch- Rg s+ Required for current limiting setup. If the dog timer function is not to be used, ground terminal current limiting function is not to be exercised, short @. terminals @ and @. C3 +s Required for reset delay time setup for STBY Riagj ‘Resistor for delay time (ty(Rw) to tecpw)) setup output generation (Vz}42 detection). When terminal @ constant current determination. A standard setting of is open, the delay time for STBY output is equal to that 18k.Q should be employed. for HALT output. Ri, Ry-Resistor for threshold voltage Vy setup. t3iR)= tar) “PERIPHERAL CIRCUIT CONSTANT SETUP AND load resistor R,_ is needed. USAGE PRECAUTIONS.” Cr, , Cr, --Used when voltage detection terminals @ and Cy + Necessary for watchdog reset pulse width setup. @ are unstable due to power line noise or other factor.

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MITSUBISHI <Dig./Ana. INTERFACE> +5V CONSTANT-VOLTAGE POWER SUPPLY INCORPORATED WATCHDOG TIMER IC These devices are not needed when no such problems teipw)) that are not to be detected as the clock signal, exist. intermittent pulses (pulse width t1(aw) having a duty ratio CR Necessary for RESET output chattering pre- of about 50% are outputted from the RESET terminal. vention. The setup must be such that Cr - Ri24.0x When the entered clock signal has a pulse width of ts (pw) 10-5 (F+Q). or more, the RESET intermittent operation stops and the signal goes High so that the watchdog timer (time setting: TIMING DIAGRAMS toimw) actuates. If no clock signal having a pulse width of 1. Watchdog Timer te (pw) OF more is entered for a time period of tz (Rw) after When the clock signal input is not give to the P-RUN input —_clock signal input, the RESET output starts an intermittent terminal or the entered signal has pulse widths (less than operation. \\ 1 H ' Ltktstacmwe) 1 kU tame) te ecw) \\ t i it H t H ' uw mo 1 ‘ T<tecow) T>tecrwo 'y>tecpw ! (teow 1 1 i 1 { RESET OUTPUT \\ toaw) (1) The clock signal input is give to the P-RUN input ter- However, as the clock signal cycle is rendered longer minal. However, as the pulse width is smaller than than the watchdog time to (Rw). RESET starts an inter- te (pw), the clock signal input is not detected as a signal mittent operation. so that RESET generates intermittent pulsing. (4) The RESET intermittent operation starts tz (jw) after (2) As the signal input has a pulse width of tsipw) or clock signal input due to the same operations as more, the RESET intermittent operation stops and the indicated in paragraph (3) above. Even if the clock High output is generated. Further, as the clock signal signal input is fed while the RESET level is Low with cycle is not longer than the watchdog time tz(aw), intermittent operations performed, RESET does not RESET keeps its High output. immediately go High so that the Low pulse width (3) RESET maintains its High output by performing the (ti (aw) is assured. same operations as indicated in paragraph (2) above. VOLTAGE MONITORING TIMING DIAGRAM (P-RUN INPUT NORMALITY) “ Joo NAN ° LW, Ven ' vi 1 1 H im mt to ' 1! vit an HALT ourrut sco Hoge 1 Hoc ' | i uit i Tt r 7 STey output 14 H H ' i ! i I i 1th ee te ! RESET OUTPUT ' t . TO H Hy ‘Lo i tun tm tun tun

MITSUBISHI <Dig./Ana. INTERFACE> +5V CONSTANT-VOLTAGE POWER SUPPLY INCORPORATED WATCHDOG TIMER IC 2. Voltage Monitoring Timing Diagram NOTE 1: Vyy1 must be set up so that Viw1 > Vrn2- (P-RUN Input Normality) NOTE 2: If malfunctioning occurs due to noise or other HALT output problem, connect an about 1000pF capacitor When Vo drops below the threshold voltage VTHi, between terminals @ and GND to assure HALT generates a Low level. HALT is reset ts (1H) after stable operations. Vo is restored to the VTH: +AVTH; level. | STBY output 2. Delay Time Setup When Vo drops below the threshold voltage VTH; The M5S296FP uses an external capacitor to set up three (VTH, <VTH;), STBY generates a Low level. When Vo __ different delay times {watchdog reset pulse width ti (aw). is restored to the VTH; level, STBY is reset. watchdog time t2(pw), and RESET output delay time RESET output tain) When the decreased Vo level is between VTH2 and VTH: (VTH2 < Vo < VTHi), RESET output genera- tion takes place tam) after HALT fall/rise. When Vo is (1) tiaw) Setup lower than VTH>, RESET rise occurs t3(R) after STBY | When the clock signal input to the P-RUN terminal is rise. abnormal, intermittent pulsing having a duty ratio of about However, t3(a)> ts (H)- 50% is generated from the RESET terminal. The oscillation cycle 2- ti jaw) is to be set up using C; as PERIPHERAL CIRCUIT CONSTANT SETUP indicated below. AND USAGE PRECAUTIONS 2-tyaw)=6.72% 10®x Cr (s) 1. Threshold Voltage Setup ‘As indicated in the timing diagram on the preceding page, (2) tairw) Setup ; ; the M5296FP checks for output voltage decrease on the The watchdog time taiqw) is used for clock signal moni- basis of two preset values (threshold voltages 1 and 2 toring purposes. It denotes the clock signal cycle limit. If (Vru1 and Vru2l). Viri1 can be set as desired with an the clock signal cycle becomes longer than tzipaw), inter external resistor (however, Vru1 > Vin2). Ving is set to _—‘mittent pulses preset by Ci are generated from the RESET 3.0V Typ by the built-in resistor; however, it is possible terminal. The value ta(nw) is to be set up by C2. to raise it slightly using the Vref2 terminal. tainw)=trrw)+ 1.53% 10° C2 (s) (3) tain) Setup © Vo The RESET output delay time tap) refers to the elapsed time from the instant the STBY output is reset to the oD) ® Re moment RESET output is reset. It is to be set up by C3. tain)= 1.18 10° C3 (s) (5) 3. Output Voltage Vo Adjustment Vo © " J ©) @ O In the above circuit, Vrw1 is calculated as follows. | <A ® ' 1,24 1. 24k 5 Vrni=0.63x tF2 (y) | For Vry1 detection purposes, hysteresis is provided to @) avoid operation instability which may be caused by noise ripple or other factor, and its value is as indicated below. As shown above, the VoAgqj terminal permits output AV 7x ER my) voltage fine adjustment. However, as a 8.2k® resistor is 8 series-connected to the Voagj terminal, the approximate adjustment range is from -20% to +10%.

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7 ELECTRIC : 7-69

MITSUBISHI <Dig./Ana. INTERFACE> MS296FP +SV CONSTANT-VOLTAGE POWER SUPPLY INCORPORATED WATCHDOG TIMER IC 4. Overcurrent Protection Setup (Io Peak Current Setup) Ve opt OV. © ¢ © © In the circuit shown at left, the load current flowing ‘ 1 through the detection resistor Re is detected as a voltage | value (detection voltage: 130mV) for current limiting purposes. 7 j 130 (mV i | lop = (ma) 7 - Ss © NOTE 3: The current flowing through Rg contains the IC bias current Ig. Therefore, the setup must be such that Ig <130/Rs (mA). TYPICAL CHARACTERISTICS THERMAL DERATING (MAXIMUM RATING) BIAS CURRENT VS. INPUT VOLTAGE i” Seo = 800 z ot TCP) 3 = SCCOCoCCee PA 2 ott A TET & cof —} = ACCA g NJ 2 eo ° LIN a oe 2 eee

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zo *s SEE ee et 4 oO 2 50 75 100 125 o 2 4 6 8 10 12 14 16 AMBIENT TEMPERATURE Ta (°C) INPUT VOLTAGE Vg (V) OUTPUT VOLTAGE (Vo) VS. OUTPUT VOLTAGE (Vo) VS. INPUT VOLTAGE (Vg) LOAD CURRENT (i,) 10 8 a LT TT tease] et tes s (OPCs BORER EEE 2 CCPC es 8

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MITSUBISHI <Dig./Ana. INTERFACE> MS296FP +5V CONSTANT-VOLTAGE POWER SUPPLY INCORPORATED WATCHDOG TIMER IC CRITICAL OPERATION VOLTAGE CRITICAL OPERATION VOLTAGE CHARACTERISTICS CHARACTERISTICS 1.0 1.0 Bos Saeen Fos oye Per errr ye 2 ool 1 tt el alle a S06 AN Ry -* < 06 \\\\ Gime ce AA 2 LLL AW Rae 5 oat LW, se ee e.e\\\\ew s ELTA IWR. E SEe788)\\\\\\ ar pel ZW eee eee|\\ ee ETAT TTT RAEI z BZSSERi\\\\== Mitt Ss. MITT) SS OUTPUT VOLTAGE Vo (V) OUTPUT VOLTAGE Vo (V} CRITICAL OPERATION VOLTAGE CHARACTERISTICS SATURATION VOLTAGE VS. SINK CURRENT . “OTT _ Ee s Ta=25C Coon 5 Nalipiieasinseessscemestinn # 0.8 ~ Co By rrr eeeere yd 3 ro HITT

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OUTPUT VOLTAGE Vo (V) SINK CURRENT sink (A) WATCHDOG RESET PULSE WIDTH VS. DELAY CAPACITANCE WATCHDOG TIME VS. DELAY CAPACITANCE é Bagi 18K OH ; ——— © room| UT TT A S [Rasim 18k a an = es Fy _ a SO RAE PRP EE 6 eee i SES LMAliiMallll L == Ann

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MITSUBISHI <Dig./Ana. INTERFACE> MS296FP +5V CONSTANT-VOLTAGE POWER SUPPLY INCORPORATED WATCHDOG TIMER IC RESET OUTPUT DELAY TIME VS. OUTPUT VOLTAGE VS. DELAY CAPACITANCE AMBIENT TEMPERATURE > “OORT * Taw 111d 5 55 £ vom LU est ttT TTT tt Pee ESTES Seay! Gees Spe $ ERRRS ESRB ae Oe ee 00 40 ee a 2 om Yi “TT TTT.

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A re o 47) b at oft | | mZLUTTT PTE TT ALi] tt Tt | 0.001 0.01 Ot 1.0 —60—-40-20 0 20 40 60 80 100 DELAY CAPACITANCE C3 wF) AMBIENT TEMPERATURE Ta (°C) THRESHOLD VOLTAGE VS. WATCHDOG RESET PULSE WIDTH VS. AMBIENT TEMPERATURE AMBIENT TEMPERATURE zg” z Ci=0. 15 e fq) Tt Tt 2 in eee fof |i |] t Eg EL) | TTT | ., eo | TTT | < 4.0) pt aS a B80 aes 2 CCCP ed ee eq] i tT oy gq 1] | ttt —60—40 —20 0 20 40 60 80 100 g —60—40 —-20 0 20 40 60 80 100 AMBIENT TEMPERATURE Ta (°C) AMBIENT TEMPERATURE Ta (°C) RESET OUTPUT DELAY TIME VS. WATCHDOG TIME VS. AMBIENT TEMPERATURE AMBIENT TEMPERATURE 400 1104 = 300) = <= Foo | | Poe 2 gf Pe ew ttt ty Pt 5 set | | tT | ei i tT tT Ty Pott TT pep atti |i ft | tL TTT TT | —60—40-—20 0 20 40 60 80 100 60-40-20 0 20 40 60 80 100 AMBIENT TEMPERATURE Ta (°C) AMBIENT TEMPERATURE Ta (°C) 1-12 (AP CELECTRIC ;

MITSUBISHI <Dig./Ana. INTERFACE> MS296FP +5V CONSTANT-VOLTAGE POWER SUPPLY INCORPORATED WATCHDOG TIMER IC RESET OUTPUT DELAY TIME vs. HALT OUTPUT DELAY TIME VS. AMBIENT TEMPERATURE AMBIENT TEMPERATURE 400; 500, a [Par= 160] 3 PE ee potter Fed SL = 209 ee ? ot +t} ] tt | ee > a 300 5 gt eS 2 CP et | CE Sof | PT ty tT ee 2 -L_] TTT tt | 3 0 ae bof} j tit tt ag a F LLIE TTT I 4 rr 60-40-20 0 20 40 60 80 100 —60—40—20 0 20 40 60 80 100 AMBIENT TEMPERATURE Ta (°C) AMBIENT TEMPERATURE Ta (°C) P-RUN INPUT MINIMUM PULSE WIDTH VS. = AMBIENT TEMPERATURE BIAS CURRENT VS. AMBIENT TEMPERATURE 2 600 16 : eer [DLL = 2 sol ttt {4 oe SRE, EON = | 2 of NL PRRREEERE} ea z : “CEP (eee ee a4 SH ee ttt 2 gttrrrrey ttt it tt | @ —60—-40-20 0 2 40 60 80 100 —60—40—20 0 20 40 60 80 100 AMBIENT TEMPERATURE Ta (°C) AMBIENT TEMPERATURE Ta (°C) MITSUBISHI Pa MEne ten

Product Information

M5296FP specifications and overview.

Summary

+5V CONSTANT-VOLTAGE POWER SUPPLY INCORPORATED WATCHDOG TINER IC

Description

+5V CONSTANT-VOLTAGE POWER SUPPLY INCORPORATED WATCHDOG TINER IC

Source title M5296FP Datasheet(PDF) - Mitsubishi Electric Semiconductor

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