M52795FP

M52795SP MITSUBISHI | Alldatasheet

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MITSUBISHI ICs (AV COMMON) M52795SP/FP AV SWITCH with I2C BUS CONTROL PRELIMINARY Notice. This is not a final specification. Some parametric limits are subject to change. AUG.'98

DESCRIPTION

PIN CONFIGURATION ( TOP VIEW )

FEATURES

• Video and stereo sound switches in one package
• High separation ( video switch )
• Two types of packages are provided : SDIP with a lead pitch of 1.778mm ( M52795SP ) ; and SOP with a lead pitch of 1.27mm ( M52795FP ) . APPLICATION Video equipment RECOMMENDED OPERATING CONDITION Supply voltage 4.7V~9.3V Rated supply voltage 5V,9V Maximum output current 32mA(at 9V) Outline 28P4B (Lead pitch :1.778mm) PIN CONFIGURATION ( TOP VIEW ) Outline 28P2W-A (Lead pitch :1.27mm) The M52795 is AV switch semiconductor integrated circuit with I2C bus control . This IC contains 2-channels of 4-input audio switches and 2- channels of 4-input video switches. Each channel can be controled independently . The video switches contain amplifiers can be controled a gain of output 0dB or 6dB . Rch T IN Lch T IN Lch 3 IN Rch 1 OUT V 2 OUT TUNER IN Lch 1 OUT DC VIDEO 2 IN Rch 2 IN Lch 2 IN VCC Rch 4 IN VIDEO 3 IN Lch 4 IN VIDEO 4 IN Rch 3 IN SDA DD SCL V 1 OUT Lch 2 OUT Rch 2 OUT BIAS CHIP SELECT GND Rch T IN Lch T IN Lch 3 IN Rch 1 OUT V 2 OUT TUNER IN Lch 1 OUT DC VIDEO 2 IN Rch 2 IN Lch 2 IN VCC Rch 4 IN VIDEO 3 IN Lch 4 IN VIDEO 4 IN Rch 3 IN SDA DD SCL V 1 OUT Lch 2 OUT Rch 2 OUT BIAS CHIP SELECT GND

MITSUBISHI ICs (AV COMMON) M52795SP/FP AV SWITCH with I2C BUS CONTROL PRELIMINARY Notice. This is not a final specification. Some parametric limits are subject to change. AUG.'98 BLOCK DIAGRAM V 1 OUT V 2 OUT BIAS I C Control CHIP SELECT DDDC Rch 1 OUT Lch 1 OUT Rch 2 OUT Lch 2 OUT L R M R L R L M R L R L M L R M Rch T IN Lch 3 IN Rch 2 IN Rch 3 IN Rch 4 IN Lch 4 IN Lch 2 IN Lch T IN 0/6dB 0/6dB 0dB 0dB 0dB 0dB 13 16 V-SW1 V-SW2 R-SW1 R-SW2 L-SW1 L-SW2 R-MODE1 R-MODE2 L-MODE1 L-MODE2 VCC VIDEO 2 IN TUNER IN VIDEO 3 IN VIDEO 4 IN BIAS GND SDA SCL

MITSUBISHI ICs (AV COMMON) M52795SP/FP AV SWITCH with I2C BUS CONTROL PRELIMINARY Notice. This is not a final specification. Some parametric limits are subject to change. AUG.'98 DESCRIPTION OF PIN Lch 3 IN5 Rch 2 IN VCC VIDEO 2 IN Lch 2 IN

7 Rch 3 IN

9 VIDEO 4 IN

11 SCL

12 SDA

24 Rch T IN

25 TUNER IN

26 Lch T IN

3.6V 5~9V 4.7V VILmax.=1.5V VIH min.=3.0V 13 DC 14 DD 27 D4 28 D5 30K Pin No. Name Peripheral circuit pins DC voltage(V) Remarks Clamp in VILmax.=1.5V VIH min.=3.0V VOL max.=0.4V (at Iin=3mA) VOL max.=0.4V (at Iin=1mA)

MITSUBISHI ICs (AV COMMON) M52795SP/FP AV SWITCH with I2C BUS CONTROL PRELIMINARY Notice. This is not a final specification. Some parametric limits are subject to change. AUG.'98

15 GND

16 CHIP

17 BIAS 4.2V

18 Rch 2 OUT

23 Lch 1 OUT

19 V 2 OUT

22 V 1 OUT

4.0V 70K 30K 30K 1.5K 1.5K 15K 5K 5K Pin No. Name Peripheral circuit pins DESCRIPTION OF PIN (cont.) DC voltage(V) Remarks SLAVE ADDRESS 2.5V~Vcc----92H SYNC CHIP DC=2.9V

MITSUBISHI ICs (AV COMMON) M52795SP/FP AV SWITCH with I2C BUS CONTROL PRELIMINARY Notice. This is not a final specification. Some parametric limits are subject to change. AUG.'98 Every byte put on the SDA line must be 8-bits long . Each byte has to be followed by an acknowledge bit. Data is transferred with the most significant bit (MSB ) first . The data on the SDA line must be stable during the HIGH period of the clock . The HIGH or LOW state of the data line can only change when the clock signal on the SCL line is LOW . S ; Start condition, a high to low transition of the SDA line while SCL is high P ; Stop condition, a low to high transition of the SDA line while SCL is high A ; Acknownledge CONTROL This IC controls 2-channel switchs with 2-byte data ( DATA1 and DATA2 ) . SW1 is controled by DATA1 , SW2 is controled by DATA2 . I C BUS I C BUS(Inter IC BUS)is multi master bus system developed by PHILIPS . Two wires ( SDA - serial data, SCL - serial clock ) realize functions of start , stop , transferring data , synchronization and arbitration. The output stages of device connected to the bus must have an open drain or open collector in order to perform the wired-AND function . 1 2 3 4 5 6 7 8 9 1 2 9 LSB A MSB SDA SCL MSB S P A LSB S SLAVE ADDRESS A DATA1 DATA2 PA A S : Start A : Acknowledge P : Stop SLAVE ADDRESS 1 0 0 1 0 0 X 0 R/W bit Usually \ 0 \ ( W : Master transmitter transmits to slave receiver ) Possible to select 16PIN Hi:1,Lo:0

MITSUBISHI ICs (AV COMMON) M52795SP/FP AV SWITCH with I2C BUS CONTROL PRELIMINARY Notice. This is not a final specification. Some parametric limits are subject to change. AUG.'98 Data byte format M52795 FUNCTION TABLE S SLAVE ADDRESS A DATA(D7~D0) A DATA(DF~D8) A P SLAVE ADDRESS SLAVE ADDRESS A6 A5 A4 A3 A2 A1 A0 R/W 1 0 0 1 0 0 0 / 1 0 DATA1(D7~D0) CONT DATA D7 D6 D5 D4 D3 D2 D1 D0 CONT AUDIO MODE I/O I/O V AMP1 SW1 CONT VIDEO SW1 CONT OUT1 AMP GAIN CONT. DATA OUT DATA AMP V-SW1 V OUT1 D3 V AMP1 D1 D0 0 0dB 0 0 T IN 1 6dB 0 1 V 2 IN 1 0 V 3 IN 1 1 V 4 IN AUDIO MODE1 CONT DATA MODE I/O CONT. D7 D6 DATA OUT DATA OUT 0 0 MUTE D5 D5 OUT D4 D4 OUT 0 1 R/R

0 HI 0 HI 1 0 L/L

1 LO 1 LO 1 1 NORMAL

D1 D0 Lch OUT 1 Rch OUT 1 Lch OUT 1 Rch OUT 1 Lch OUT 1 Rch OUT 1 Lch OUT 1 Rch OUT 1 0 0 MUTE MUTE Rch T IN Rch T IN Lch T IN Lch T IN Lch T IN Rch T IN 0 1 MUTE MUTE Rch 2 IN Rch 2 IN Lch 2 IN Lch 2 IN Lch 2 IN Rch 2 IN 1 0 MUTE MUTE Rch 3 IN Rch 3 IN Lch 3 IN Lch 3 IN Lch 3 IN Rch 3 IN 1 1 MUTE MUTE Rch 4 IN Rch 4 IN Lch 4 IN Lch 4 IN Lch 4 IN Rch 4 IN DATA2(DF~D8) CONT DATA DF DE DD DC DB DA D9 D8 CONT AUDIO MODE I/O I/O V AMP2 SW2 CONT VIDEO SW2 CONT OUT2 AMP GAIN CONT. DATA OUT DATA AMP V-SW2 V OUT2 DB V AMP2 D9 D8 0 0dB 0 0 T IN 1 6dB 0 1 V 2 IN 1 0 V 3 IN 1 1 V 4 IN AUDIO MODE CONT DATA MODE I/O CONT. DF DE DATA OUT DATA OUT 0 0 MUTE DD DD OUT DC DC OUT 0 1 R/R D9 D8 Lch OUT 2 Rch OUT 2 Lch OUT 2 Rch OUT 2 Lch OUT 2 Rch OUT 2 Lch OUT 2 Rch OUT 2 0 0 MUTE MUTE Rch T IN Rch T IN Lch T IN Lch T IN Lch T IN Rch T IN 0 1 MUTE MUTE Rch 2 IN Rch 2 IN Lch 2 IN Lch 2 IN Lch 2 IN Rch 2 IN 1 0 MUTE MUTE Rch 3 IN Rch 3 IN Lch 3 IN Lch 3 IN Lch 3 IN Rch 3 IN 1 1 MUTE MUTE Rch 4 IN Rch 4 IN Lch 4 IN Lch 4 IN Lch 4 IN Rch 4 IN

MITSUBISHI ICs (AV COMMON) M52795SP/FP AV SWITCH with I2C BUS CONTROL PRELIMINARY Notice. This is not a final specification. Some parametric limits are subject to change. AUG.'98 Parameter Symbol Test condition Min. Max.Typ. Unit Supply voltage Vcc V Circuit current VIDEO Voltage gain Frequency characteristics Dynamic Range Input impedance Crosstalk AUDIO Icc G F D CT mA dB dB Vp-p kΩ dB Vcc=9V,Vin=0Vp-p,Rl=∞Ω Vcc=5V,Vin=0Vp-p,Rl=∞Ω f=100kHz Maximum with distortion<1.0% ZIV 4.7 9.3 32 42 28 37 -0.5 0 0.5 5.5 6 6.5 -2.0 0 2.0 -2.0 -60 -54 (Ta=25°C,Vcc=9V,unless otherwise noted) ---

ELECTRICAL CHARACTERISTICS

G F THD D VOFF CT dB dB dB kΩ mV Vp-p f=1kHz ,1Vp-p (Vcc9V)(RT R 1OUT ) f=1kHz ,1Vp-p (Vcc5V)(RT R 1OUT ) f=100kHz/1kHz , 1Vp-p(RT R 1OUT ) f=1kHz ,Maximum with distortion<0.5% (RT R 1OUT ) f=1kHz,2Vp-p,at 400HzHPF+30kHzLPF (RT R 1OUT ) 1kHz,1Vp-p RT R 1OUT (at R2 mode) -0.5 0 0.5 -0.5 0 0.5 -2.0 0 1.0 0.01 0.05 5.5 -20 0 20 22 30 38 -90- -84 6.0 (MODE:R T,R2,R3,R4 R 1OUT ) (RT,R2,R3,R4,LT,L2,L3,L4 ) Clamp in(T,V2,V3,V4) f=1MHz,1Vp-p T V1OUT (at V2 mode) Vcc=9V(0dB)(T V1OUT ) Vcc=5V(0dB)(T V1OUT ) f=10MHz/100kHz,1Vp-p (0dB)(T V1OUT ) f=10MHz/100kHz,1Vp-p (6dB)(T V1OUT ) f=100kHz,1Vp-p (0dB)(T V1OUT ) f=100kHz,1Vp-p (6dB)(T V1OUT ) 0 2.0

MITSUBISHI ICs (AV COMMON) M52795SP/FP AV SWITCH with I2C BUS CONTROL PRELIMINARY Notice. This is not a final specification. Some parametric limits are subject to change. AUG.'98 tBUF P S tHD;STA tLOW tR tHD;DAT tHIGH tF tSU;DAT tSU;STA Sr tHD;STA tSU;STO P SDA SCL I C BUS CONTROL SIGNAL2 I2C BUS CONTROL SIGNAL Min. input low voltage (Ta=25°C,Vcc=9V,unless otherwise noted)ELECTRICAL CHARACTERISTICS Max. input high voltage Low level output voltage(SDA) fSCL tBUF tHD;STA tLOW tHIGH tSU;STA tSU;DAT tR tF tSU;STO 4.7 4.0 4.7 4.0 4.7 5.0 250 4.0 100 1000 300 kHz µS µS nS tHD;DAT High level input current Low level input current SCL clock frequency Time of bus must be free before Hold time at start condition The low period of the clock The high period of the clock Setup time for start condition Hold time DATA Setup time DATA Rise time of both SDA and SCL line Fall time of both SDA and SCL line Setup time for stop condition VIH VIL VOL IIH IIL µA V SDA = 3mA SDA , SCL = 4.5 V SDA , SCL = 0.4 V 3.0 0.0 0.0 -10 -10 5.0 1.5 0.4 0.0 Parameter Symbol Test condition Min. Max.Typ. Unit a new transmission can start

MITSUBISHI ICs (AV COMMON) M52795SP/FP AV SWITCH with I2C BUS CONTROL PRELIMINARY Notice. This is not a final specification. Some parametric limits are subject to change. AUG.'98 Application Circuit Example Note how to use this IC Input signal with sufficient low impedance to input terminal. The capacitance of output terminal as small as possible. Set the capacitance between Vcc and GND near the pins if possible. Assign an area as large as possible for grounding. Power-on Reset The M52795 has an intermal power-on reset function that sets each control r egister to "0" during IC power ON. The power-on reset VTH has 2.5V. 1 D5 Rch T IN Lch T IN Lch 3 IN Rch 1 OUT V 2 OUT TUNER IN Lch 1 OUT DC VIDEO 2 IN Rch 2 IN Lch 2 IN VCC Rch 4 IN VIDEO 3 IN Lch 4 IN VIDEO 4 IN Rch 3 IN SDA DD SCL V 1 OUT Lch 2 OUT Rch 2 OUT BIAS CHIP SELECT GND 100µ 10µ VCC 0.01µ slave address Change(VCC/GND) 10K 220 10K 220 10µ 0.47µ 10µ 10µ 0.47µ 10µ 10µ 0.47µ 10µ 10µ 0.47µ 7510µ 10K 10K 10K 10K