M51362SP

M51362SP MITSUBISHI | Alldatasheet

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MITSUBISHI ICs (TV) - PLL-SPLIT VIF/SIF DESCRIPTION ; PIN CONFIGURATION (TOP VIEW) The M51362SP is a semiconductor IC consisting of IF signal processor suitable for color TV sets and VCRs with AV ese of ra : AF AGC OUTPUT ) [55 VIDEO INPUT which is a revision of M51365SP. VIDEO NEGATIVE FEEDBACK [3] CONTROL OUTPUT The circuit includes VIF amplifier, Video detector, VCO, APC | equatizeR OUTPUT [a] fs] VIDEO OUTPUT detector, AFT, video equalizer, IF/RF AGC, SIF detector, RF AGC DELAY [4] (27) SIF limiter, FM detector functions veo WF) Gl i) J AFT COL , IF AGC FILTER [6] = [Bs] APC FILTER GND mF) 7] Sf Gnd wvco) FEATURES ; we neur{ } veo con PA @ A full synchronous detector circuit using PLL as video eno (sii fo) SE Vee we) detector provides excellent DG, DP, 920kHz beat and SIF det. INPUT fu] (0) CONTROL FILTER cross color characteristics. Vec (SIF) [2] [i] AUDIO OUTPUT @ The PLL-SPLIT method in which video IF and audio IF UTE ee Ea a }rm det. COIL signal processings are separated and VCO output is used SIF det, OUTPUT [BI fig} AFT OUTPUT to obtain intercarrier provides good sound sensitivity and reduces buzz. In consumer sets, intercarrier is also available from the video detector output. Outline 30P4B © Built-in video equalizer is suitable for VCRs and color TV sets equipped with video output terminals. @ The quadrature detector circuit for FM detector has good linearity with a simple coil. © The M51362SP has better video S/N ratio than M51365SP by 2~4dB

APPLICATIONS

TV sets, VCR tuners RECOMMENDED OPERATING CONDITIONS Supply voltage range... nocssnesutassaeseeB=10V BLOCK DIAGRAM AUDIO AFT vco OUTPUT FM DET. VIDEO co APC COIL. CONTROL colt OUTPUT —~ FILTER a aT” | ~ ' GND (veo) “Surrur CI ao vee (veo) Lock PHASE FM nL ee BH | VIDEO INPUT GO) ce tt (16) AFT OUTPUT! ! I LIMITER GND (VIF) (7) 2ND IF (2) vec (SIF) ih AMPLIFIER It EQUALIZER RE 1 ' GND (SIF) (0) > AGC AGC TT Y 1ST IF SIF | (9 SF ET RE AGC AMPLIFIER | | DETECTOR oureuT ourput (1) H os [_] | VIDEO EQUALIZER | IF AGC —_ SIF DET. UMITER BYPASS NEGATIVE OUTPUT pe lage FILTER IF INPUT INPUT INPUT FEEDBACK DEL MITSUBISHI 2-176 pales

MITSUBISHI ICs (TV) PLL-SPLIT VIF/SIF Oe ABSOLUTE MAXIMUM RATINGS Ratings | Pa | Power dissipation 1250 = 20~75 : =40~125 ELECTRICAL CHARACTERISTICS (Ta = 25°C, Vcc = 9V unless otherwise noted) VIF SECTION Tres Test conditans Symbol Parameter : Switches should T Unit point ViF [SIFI usually be set to 1. ye. toc (VIF) Circuit current (VIF) [1] AT | — | = [3 [= | = |swi=2 [33 | 45 [57 | ma | Video detector output - [v= [betes [frre = | - [3 | o | - [swane |e [ar| ai] v | voltage 2 Video detector output _i]1 |TP9|SGi] = | 3 | = | = | [7.15 [1.45 | 1-75 | Ve-r | | Vo cox | Video detector outout 41 [TP2|sci] - | 3 |= | = | | 16 [1.95 |" 23 | Ve-r | Video S/N [i frPigscs] — | 3 | - | = |sw6=2 coon] a4] 52] | a8 | | Bw | vieeo traueey characteristics [1 [TP9|SG3[— [3 [= | — | Goon] 65 | 75 || MHz | | Vin nin) [input sensitivity [i |TPa|sc4] = [3 [= | = | ce) a Maximum allowable input | 1 |TP9|sc5| - [3 | - | = | coe a] ior | 110 || abu | AGC control range _|1/ - | -|-|-|-|-| coed] 68 | 64 [|B | IF AGC maximum voltage [1 [TP3] - | - | 3 | = |= | | 65] ee{ | Vv | IF AGC miniaun voltage |i |TP3|sc7| - | 3 [= | = | SIF det. 1a orca | [49s 2 | =| =| | 104 | 100 4 | aoe SIF det. [Vis | AFT outout voltage [7 [TPS] - | = | 3 [0 | =| | «| AFT detector sensitivity 1[TP5|scio| = | 3 [= | = | ate [48 [70 [92 [avi | [ View [AFT maximum voltage |i [TPs|sc10o| - [3 | — | — | cawnl 8] a7{ [vf | View| AFT minimum voltage |i [TP5|scio| - | 3 | — | - | cawo] | 038 | 10] Vv | RF AGC maximum voltage |1|TP1|SG2[— | 2 | - | — [7 [7es[ |v] RE AGC minimum voltage |1|TPI[SG2{ — | 4 | - | = | [fof of Vv] Capture range (U) | |TPa|seri| - | 3 | - | | oe 9 [0.45 | 08 || MHz | Capture range (L) [i [rra|saii[ = | 3 | = | = | cote 14 | 20 [| Mz | Capture range (T) fi] = | = |= | - [= [=| Gore] 20 | 28 [| MHz | CL-U2 | Capture ranoe (U) |i [rpg|scii| — | 3 | = |= [swe=2 coe 9 [0.45 [08 | 1.2 | MHz | CL=L2 | Capture range (L) |i |TPo|scii| - | 3 | - | - |swo=2 ow | 1.0 | 1.6 | 22 | Mbz | | Waors | vest detector tests vrtewe [7 TPS] - [= [3 [5S [we [SW345=2 wowin| 36 [ 40 | 44 | V_| | Veo. | Minimum voltage at sin @|1[TP8] - | - | 3 [5 | wa [sw345=2 coera| [005 | os] Vv | EQ frequency Teg feter to fe [eee [hee [>]-[-[ eel af oe EQ frequency TP9 fete to rea [Senses 2 _|'frrae9| = | 3 | - | =| cers] 42[ sr] 72 | a | EQ frequency TPO feter to rea [Senses 2 [Tread =| 3 | | -| ird|_ 28 | 120 | 45 | os | [Bef oe fr se] == PI wil | 35 | Lop op Ti frpalscis) 3 T= T= | Gop] 2 Ts | des. | eee oan" ELECTRIC 2-177

MITSUBISHI ICs (TV) : PLL-SPLIT VIF/SIF VIF SECTION (cont.) Test Test_conditions Symbol Parameter [input sional] eave” | Switches should Typ. Unit papel nt Vir [SIF1 usually be set to 1. yp. Black spot inverter Vari = : Black spot inverter Vari . | Vsvnc | Syne tip level at pin @[1 |TP2|sG2] - | 3 |= |= | [ 21 | 25 [29 | Vv | | Rin (Vy | VIF input resistance [2["leoeu| - [3 | - [= | | fog | ke | [ Cin (W) | ViF input capacitance [2{—faweu| - | 3 [= |= | [| 6s TT oF | Rin (S1)| SIF1 input resistance [2] | = Jowou| 3 [= |= | {of 21 Pf ka | Cin (S1)] SIFi_input capacitance |2{ | = lenssu| 3 [ - | — | | 25 [oF | SIF SECTION Test Test_conditions Symbol Parameter . %* Switches should Ty M Unit Pipontsir2y | Vi | Ve | Vz20| usually be set to 1. yp. | Max. Ico (SIF)| Cirouit current (SIF)_[1 [a2] = [| 0 | = |= [sw2=2 | 61 [ 87 | 114 | ma | AF output OC voltage |1[TP6] = | [0 | = |= | | Voarwax | Maximum AF outout_|1|TP6|s6I7| | O [= | = | [ 225 | 300 |” 375_|mVrms| AF output distortion [1 [TP6|sezi[ [0 | = | = | [ [oa ToT % | Vin (lim)| Input limiting sensitivity] 1|TP6|sc1| [oO | = | = |] cow [| 34 [42 [Bu | [AMR [AMR i {rpajssig[ [0 | = T= | co] 58] ea | | a8 | AF S/N [ifrre|sczof | o | = T= | (ow 2) | 58 [ 73] [8 | ELECTRICAL CHARACTERISTICS TEST METHOD Notes. Maximum allowable input “Vin (max” Note1. Video S/N “P/N” a.Set SG5 to 90dBp and input it in VIF IN. a.Input SG6 in VIF IN. b.Detector output at pin @ at this time is defined as b. The noise appearing at pin @ is determined by measur- V2. ing the r.m.s. voltage at TP10 through low pass filter c. Increase the voltage of SGS and voltage at which detector (-3dB at 5MHz) output reaches 3dB less than V2 is defined as maximum _ Vodet 1 (Vee) x 0.7 allowable input. c.PIN = 20 log { noise (Vrms) }. NoteS AGC control range “GR” where Vodet 1 denotes video detector output 1 a.AGC control range is defined as follows: Note2. Video frequency characteristics “Bw” GR = Maximum allowable input - Input sensitivity a.Set SG3 as follows: Note6 AFT detector sensitivity “1” fi = 58.75MHz‘ Vi = S0dBy a.Input SG10 in VIF IN. fo = 57.75MHz Vi = 70d8p } mixed signal b.Méasure difference cf frequency between 3.0V and 6.0V of DC voltage at TPS and the difference is defined b.Measure the element of 1MHz at TP9 and the result as Af, is defined as V1. c.AFT detector sensitivity 1 is defined as follows: c. Decrease the frequency until element (f-fa) at TPS 3000MV fener) teaches 3dB less than Vi. Then, read the frequency. B= TF ka) d.Bw = 58.75 - fe (MHz) at Note3. Input sensitivity “Vin (min)” vis a.Input SG4 in VIF IN. wv cotta b. Decrease the SG4 level and the level at which detector output at pin @ reaches 3d8 less than Vodet 1 is defined Viex ' as input sensitivity. av cin ie { View fo 58.75MiHz (wi) MITSUBISHI 2-178 pa lens

MITSUBISHI ICs (TV) M51362SP - PLL-SPLIT VIF/SIF eee Note7. AFT maximum voltage “Viex” c. Observe TP9 with spectrum analyzer at this time, and a.Maximum DC voltage in the figure on the previous the ratio of the 920kHz level to the 3.58MHz level is page is defined as Vien. defined as intermodulation. Note8. AFT minimum voltage “Vie.” b. Minimum DC voltage in the figure on the previous page is defined as Vis. Note9. Capture range (U) “CL-U-1,” “CL-U-2” oy a. Input SG11 in VIF IN and increase the frequency till VCO lock is released. b.Decrease the frequency of SG11 and the frequency Note16.DG, DP “DG, DP” at which VCO locks again is defined as fv (MHz) a, Modulated waves of $616 is generated by 87.5% video c.Capture range (U) is defined as fv - 58.75 (MHz). modulation of the 10-step waves as shown in the figure Note10.Capture range (L) “CL-L-1,” “CL-L-2” below. a.Input SG11 in VIF IN and decrease the frequency till b.Measure DG and DP at TP9 with vectorscope. VCO lock is released. b.Increase the frequency of SG11 and the frequency at 4 which VCO locks again is defined as f. (MHz). 10% c.Capture range (L) is defined as 58,75 — fi (MHz). T Note11.Capture range (T) “CT-T" a a."CL-T” is defined as “CL-U-1" + “CL-L-1" (MHz) a 100%, Note12.Lock detector threshold voltage “Vaori” a.Set the voltage at Vz0 to 3V and observe TP b.Increase the voltage at Vzo and the point at which SUBCARRIER 3.58MHz 40% TPB voltage changes drastically is defined as V2om (threshold 1V) Note17. Black spot inverter threshold level, clamp level 1P8 “Ve mH, Ve cu” VOLTAGE a.Input SG1 in VIF IN. b. By varying Ve, output the waveform as shown in the Ves. figure below to TP2 and measure each DC voltage. V20 Veet ----- V20TH Note13. Minimum voltage at pin @ “Vzo” TEST POINT a.Minimum voltage in Note12 is defined as Vz. Note14. EQ frequency characteristics “FC1"“FC2"“FC3” —Notetg input limiting sensitivity “Vie am" a.Input SG12, SG13 or $G14 to VIF IN ; a.Set SG18 to 80dBy and input it in SIF2 IN. b.Measure the level of element (fr-fz) et TP9 and it is, Decrease the output level of SG18 until detector output defined as Veo w (dBy) ; at TP6 becomes 3dB smaller than Vo ar Max. ¢.Measure the level of element (f-fa} at TP2 and it is The level of SG18 at this time is input limiting sensitivity. defined as Veo ovr (By). Note19.AMR “AMR” d,EQ frequency characteristics is defined as follows: ttnput $619 in SIF2 IN. FC1~3 = Veo our ~ Veo w (dB) b.Measure the output voltage at TP6 and it is defined Note15. intermodulation “IM” as Vam. a.Input SG15 in VIF IN c.AMR is defined as follows: b. Observe TP9 with oscilloscope, and adjust the voltage Vo ae tnt enVems) of Ve so that the minimum level of detector output AMR = 20 log { SA Mes RVI). (gp) waveform will come to 2V. SSS

9 MITSUBISHI

MITSUBISHI ICs (TV) - PLL-SPLIT VIF/SIF _—— Note20.AF S/N “S/N” INPUT SIGNAL a.Input SG20 in SIF2 IN. Signals (609 termination) ae Corresponding to OT. b.Measure the output voltage at TP6 and it is defined o=58, TE Vie90d8 77. 7aKAM (sis wandirg to ) as Vw. fn 20e c.AF S/N is defined as follows: aoe oe i 1 = 58.75MHz Vi=90dBu Ys SIN = 20 log (See (a8) f2= 83 5MHe Vie 008 u } xed sional ‘Ww (mers) fo= 58.75MHz Vi=Vaviable fm=20kHz 17.78%Al fo = 58.75MHz Vi= Vaviable fm = 20kHz 16%AM © Amplitude level of all AM modulated waves are the | SG6_| fo= 58.75MHz Vi= 60d8 u peak level of modulated waves. fo = 58.75MHz Vi= 11008 * The following is used for the mixer: | SG8_| fo =54.25MHz Vi= 100dB u [ SG9_| fo = 54.25MHz Vi = 80dB fo = 58.75MHz + 5MHz Vi = 90dB uw 25 f0=58. 75MHz + 5MHz Vi=90dB yu fn=20kKHz 77. 78KAM #1 = 58.75MHz Vi=90dBU Yo wi WA fe = 58.25MHz Vi= 60dB w. } mixed signal #1 = 88.75MHz Vi=90dBu 26 f2= 55:75MHe Vi= 6008 u_} Mixed sional fi = 58,75MHz Vi=90dBu Yo f2= 54:7oMHe Vi= 6008 y_} Mixed sional * With Vco coil, IF AGC OV and non-input condition, adjust f1 = 58,75MHz Vi = 8008 p free run frequency to 58.75MHz. $G15 | f2=55.17MHz Vi = 800B rived signal fa = 54.25MHz Vi= 8008 9616 | f° =58.75MHz standard 10- step modulation m = 87.5% video modulation, sync tip level 90d8 u| fo = 45MHz +25kHz dev Vi=100d8 u fm =400Hz fo = 4.5MHz +25kHZ dev Vi =Vaviable fm =400Hz fo = 4.5MHz Vi= 100dB un 30% AM fm = 400Hz fo = 4.5MHz Vi= 100dB u S621 [ fo=4.5MHz Vi=1000Bu fm =400H2+7.5kHz dev eee MITSUBISHI 2 - 180 wees

MITSUBISHI ICs (TV) PLL-SPLIT VIF/SIF TEST CIRCUIT 1 vee me TPS i ? 2k 560 2 P10 {! ia 100 1 sé ‘85-1 $5-2 TP6 910 ta 0.015» 12 3 yaad ot 0.47 cotuy, ne Fess r Veo ASMHz oTPa a7 a ol TOUS g ! IL FOR TRAP 3 3 22] 75k, tits 300k of Te7 o Tex oTPS i A ed (20]_fes]_ [26] [27] [es] fe5) (24) [ea] f22) [21] 20] [is fie) fiz] fis] LJ ‘Halee| [s] Ts] Ww bo Ty] aE [15] TP1o—468 ve 5/8 oot wt t+ 7 |TP3 [| 3 Lor = S810 = | S150 |! p{sast | (ory fit 3681 bei] 27, + aie 50 50 TP4 36K 5 Troop rir | azok] ve Oz50 777 SIFAIN as aoe Oru 0.01 un] 2747p 82u th £68» + a! al sp on ° 6: ° veo ° 02 Ai? Aa Units Resistance: 2 Capacitance: F TEST CIRCUIT 2 Vee = 8V 6 0.01 w 0.01 4

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MITSUBISHI ICs (TV) M51362SP . . PLL-SPLIT VIF/SIF TYPICAL CHARACTERISTICS THERMAL DERATING (MAXIMUM RATING) a ett INE TT 1.0 \\ Zz gf | A] | | oti | IN I | FA 0.6 Ro eof | | 24) i tt : “te 25 0 25 «50 7 100 125 AMBIENT TEMPERATURE Ta (°C) APPLICATION EXAMPLE vec 9Vo i ‘OOP rome ant [so]_fes]_[28]_fe7] fee) [25] [24] fe3) [22] [21] feo) [is] [ra] [17] [ig] Pp ce SES cI —7 LOCK PHASE U beretroak | = oes fp en oe ee Leteffoet os RFE IF |AMPLIFIER| re Le 3 ten Titel [etal gue pee Ls] RE AGC Ws GND No. a OUT x RF AGC th == j peeve [33 3 he

3 Vcc ‘SIF vec

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MITSUBISHI ICs (TV) M51362SP - PLL-SPLIT VIF/SIF DESCRIPTION OF PIN 8 3 8 ao et mo S 62 i} 2 5 8 5 © 8 ® © © O83 ° lls : oe 2 = 5 pes f | = 2 Cm wee g s ns = awe s vy ® . = . Le & a fel + a id x ®@ @ # ie s 35 8 : x 2 en Pea A : 3 a 3S : ois * | ffi z1. A] apa : ee ee Eal,| (he 5 we an ve Reese car a ee © © ) ©@ 8 z 6 85 3 Bs S s g #° 28 ge? SO

MITSUBISHI ICs (TV) M51362SP . PLL-SPLIT VIF/SIF __. PRECAUTIONS FOR APPLICATION The lock detector determines locked/unlocked conditions “~ 4.VIF Amplifier by the average level of detector output. The VIF amplifier is a two-stage amplifier without DC In pin @, the threshold is 3.2V. feedback. The time constant switch is pin @. With a gain of approx. 40dB, the VIF amplifier is connected The VCO circuit diagram is shown to the right, and illustrates to @ video detector via an internal capacitor. how sinking current is varied to adjust frequency. Maximum input amplitude is determined by the input The variable range falls between -1.7MHz and +1.3MHz dynamic range of the VIF amplifier, allowing up to 110dBu at capacity of 27PF (45.75MHz). input, During excessive input, surpassing this limit will cause The variable range widens as the capacity decreases, while the linearity to worsen, while leaving amplitude unchanged. _the temperature drift cheracteristic and harmonics worsen. Since gain control has the characteristic that AGC speed Vcc and GND of the VCO section are independent of those is fastest in the range 50~60dBp, to prevent sag, select of the VIF, while the same DC voltage must be supplied an appropriate filter time constant. as for the VIF. IF input impedance is approx. 1KQ and must be input in balanced type. { 2.Video Detector, PLL Section Veo The PLL system produces a pure carrier wave. The PLL is locked as shown in the diagram below. The VIDEO DET and APC DET employ a double balanced mixer. Detector output (pin @) is 1.5Ve-r (Vcc = QV, negative sync). Detector output is almost proportional to supply voltage. Pin ® is an emitter follower, containing a 2KQ emitter { resistor, and requires an externally attached resistor (2KQ~1KQ) as it is insufficient alone to drive a 4.5MHz 1mA imA trap. Pin28 output waveform EE 3.SIF Det. 4.5MHz issues from pin @, however, for M51362SP, torasaadacpansana = 3.20 Peel det. inputting 41.25MHz thru pin @ causes 4.5MHz to be output from pin ®, the product of multiplying 45.75MHz by the carrier wave gained at the VCO. Since conversion gain is 18dB, which is constant, note that at a lower level than the delay point, the output level is --- ov also lowered linearly. Input impedance is approx. 2KQ, output pin ® is an emitter VIDEO _DET follower type circuit, current sink is 0.6mA, and a 3002 resistor is connected in series. 7 The AFT circuit is of the conventional type. Output is also . bss [5 of the conventional current-drive type. APC Since internal operating current is reduced, use a load resistor DET three times larger than the conventional one. A defeat vco | +3 terminal is not provided here. Therefore, using the middle point in the coil between pins @ and @, lower the voltage of pins @ and @ to less than 1V. The internal resistor of pins @ and @ is 6KQ. eee MITSUBISHI 2 - 184 oes

MITSUBISHI ICs (TV) M51362SP PLL-SPLIT VIF/SIF ——— 5.IFIRF AGC terminal ~" “IF AGC input is applied from pin @ Video Out. > 4.5MHz The resistor between pins © and @ is provided to prevent trap > pin @ to PNP emitter follower. parasitic oscillation. The IF AGC amplifier is a two-stage amplifier, with pin © The FM detector employs a quadrature detection method & pin @ serving as a filter terminal. and requires a tank coil and damping resistor at pins @ Output to pin © is a current-drive type, and a current sink and ®. is 0.5mA. Note that use of a ceramic discriminator would not obtain The RF AGC is a reverse output type; its pin © output a good characteristic. is illustrated in the figure to the right. Pin ® audio output also employs an emitter follower and Output voltage is (7.8V~OV) at Vcc = 9V. the output impedance is approx. 700Q. Black spot inverter works before EQ amp. Voltage lower than syne chip by 0.45V (pin @) is to be threshoid. Principle of M51362SP PLL Section Clamp voltage is nearly at the white level. M51362SP’s PLL section is formed as shown in Fig. 1. Vee The locked loop is indiceted by broken lines. The APC and video detector are double balance-type 290 13k multipliers, and the LPF 's a lag-ead filter with external CR. The APC detector is a phase comparator and outputs voltage corresponding to the phase difference between the IF signal and VCO output (output through +45° phase shift device). 200 10k Video det. output

330 Foo =

signal det. 6.EQ Amplitier B yas" Basically, the EQ amplifier is as shown in the diagram to Sooo the right. get]! ' device Providing the feedback to pin @, it has the frequency t ' characteristic. en It can also be used as an amplifier with a fixed gain Vee HH Fig.1 20 The phase comparator usually has such a characteristic as 18k the one illustrated in Fig. 2: When the phase angle of B is +90° out-of-phase for the IF signal, the APC output current @ becomes 0, while APC output current becomes positive 500 2) when the phase angle lags. APC output current 3 8 8 + @ 500 2.5k 0.75mA 0.25mA . —90° o C) 180° 7.SIF Section 80° B point relative As Vcc and GND of the SIF section are independent of phase for IF signal those of the VIF, the supply voltage of the SIF section can be changed, The limiter amplifier is a triple amplification device, including an internal differential amplifier. Pin @ is a DC feedback Fig.2 APC Detector ~ eee MITSUBISHI ae iaEs! 2 - 185

MITSUBISHI ICs (TV) * PLL-SPLIT VIF/SIF LN Output current is converted into voltage, and unnecessary When the M51362SP’is in the non-locked state and a locked ~"~ frequency is cut off via LPF. Then, the voltage is applied condition is detected, the LPF time constant is reduced to VCO as controlled voltage. Here, the VCO characteristic to widen the capture range. is shown in Fig. 3, and for the IF signal, the phase at The frequencyresponse characteristic under the locked state B relative to the IF signal is -90°. is shown in Fig. 4; cut-off frequency is approx. 100KHz, The procedure by which the VCO follows the IF signal is and is equivalent to the bandwidth of the carrier wave described below: For example, when the phase of the IF reproduced from the IF signal. signal lags (the phase at B relative to the IF signal leads Here, the AM detector section is now described. If, in Fig. more than -90°), APC output current becomes positive, 5, the phase at point B is locked at -90°, phase lags by controlled current increases, frequency tends to decrease 45° at point A, this means the IF signal carrier wave will and, consequently, the phase lags. be -135°. So at point B, the VCO locked in phase angle is -90°. Consequently, the carrier wave phase at point C, where Meanwhile, when the frequency of the IF signal becomes the signal is input into the video detector, lags by an additional high, APC output is negative, controlled voltage decreases, 45°, producing -180° (out-of-phase). and the VCO frequency becomes higher, because the A correct phase produces the most complete and effective instantaneous phase is equivalent to leading. demodulation of the video signal. (See Fig. 6). However, with phase error inversely proportional to loop Each P gain, the VCO locks. Phase at Each Point Phase of IF Oscillation c > signal carrier frequency 80° wave A Freerun fot-~----~ ~135° ' 8 t 90" ' Fig. 5 H Controlled ‘ voltage Fig.6 illustrates the basic circuit of the phase shift device. Reference Each phase shift device comprises an LPF (~45°), an HPF voltage {+45°) having simple C and R and set so that the phase Fig..3 VCO Characteristic will rotate by +45° at 45.75MHz. Free-run frequency is oscillation frequency produced when Consequently, although the phase rotation varies in the other center voltage is applied to the VCO. IF band, the relative phase angle is 90°, independent of When locked, the input frequency lock range depends on _frequency, as the values of R and C are set equal to one the variable frequency range, and the lower loopgainnarrows —_ another. this range. Description of the capture procedure for the VIDEO IF signal is omitted here due to its complexity. The capture DET range is narrower than that of the lock in relation to loop ‘ pc —45° vco gain, and narrower than the LPF bandwidth. " bias fk output Detector output Cc Ra 5° after LPF Non-locked TT R Cc TT APC ~ DET” 100KH2 FM modulation Fig.6 frequency Fig. 4 MITSUBISHI 2 - 186 a MBS

MITSUBISHI ICs (TV) M51362SP PLL-SPLIT VIF/SIF ——$S ___ SPECIAL PARTS Coil Specification f = 45.75MHz ‘ 1) VCO coil pin @, @ Qu ColpF) Turns Bobbin Wire 92420% 27 (1-6) 61+ 10K type 0.120 Stray 2 OuEW Variable range widens as Co is reduced. 2) AFT coil pin @, @ Qu ColpF) Turns Bobbin Wire 84220% 5946% (1-6) 4 t 10K type 0.120 ,

4 OUEW

3) SIF coil pin @ Filter passing only 41.25MHz. Can be used in AFT coil. When SAW filter (41.25MHz) is used, compensation for loss is necessary. 4) SIF FM det. coil pin ®, ® Qu ColpF) Turns Bobbin Wire 60+20% 68pF (4-6) 36t_ 10K type 0.120 OUEW -.——— eee MITSUBISHI wales 2 - 187