M50423FP

M50423FP MITSUBISHI | Alldatasheet

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Technical content

MITSUBISHI SOUND PROCESSOR ICs |

DESCRIPTION

The M50423FP is a CMOS IC developed for compact disc (CD) sound reproducing applications. It has adjustment-free PLL, error correction circuitry, etc. and is used in a CD digital signal processing section. Applications include also CD-ROM and CD-G, as well as CD-DA.

FEATURES

WAdjustment free EFM-PLL circuit (builtin VCO) M+ 8 frames jitter margin WEasy-to-handle CLV servo commands WSubcode parallel/serial interface WSelection available from 2 times and 4 times over sampling ™18/20bit output available (with 4 times oversampling) MDual DAC output available (with 4 times oversampling) RECOMMENDED OPERATING CONDITIONS Outline 80P6-B Supply voltage rangers: Von = 4,5~5.5V 0.8mm pitch QFP Reted supply voltagessssssssssssesssessessseeesnseeeennes Vp = 5V (20.0mm x 14.0mm x 2.15mm) SYSTEM CONFIGURATION . M50423FP DISPLAY Co) DIGITAL | J oiGrraL SUBCODE | INTERFACE inteneAce] [OUTPUT OPTICAL PRE. eM o = Hee] EI cLv DIGITAL | SERVO Leo | PICK-UP SERVO | Lama a @ mmsusisHi

MITSUBISHI SOUND PROCESSOR ICs M50423FP CD PLAYER DIGITAL SIGNAL PROCESSOR — eee Oe PIN CONFIGURATION FESS skkas. 23993 EE GSSERSS 2 BS8S Emp [1] 164] DOFK PwM1 [2] 63] Voor PWM2 62] EST: DOTX 61] EST2 acrcy [5] (60) RADo Test [6] [59] RADs DOBSEL [58] RADs DASEL: [8] 57] RAD4 DASEL2 [9] [56] RAO7 DASEL3 [19 55] RAD3 DASEL4 F 4] RAD2 Msp [12] 4 (53) RAD! MCK [13} 8 52] NC MAtd 3 iS] WE ACER [is [50] RDBs FFD [tel [ag CAS HF [17] 48] RDB IREF (18) 147] ROB1 tuclig fag] NC LPF 20 [45] ROB2 LOCK/DRD [21] faa] NC SyCLK 2a) C) lig) RAS Vopz [23} 142] SBCP DAD 24) f47] saca : PSPS ILeZISAS BASICS Sas Meaeaeg HELSSOR RSG ERRERESSOGRRR RES Outline 80P6-B NC: NO CONNECTION

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MITSUBISHI SOUND PROCESSOR ICs M50423FP CD PLAYER DIGITAL SIGNAL PROCESSOR oR PLAYER DIGITAL SIGNAL PROCESSOR PIN DESCRIPTION [Name [/O[ suction’ = |S [Name [I1/OT Function [ewe | 0 | Emphasis fag cutout tmphasis=1 | | $80 | © | Subsode ch output fain o-[bse maar anes Pinta 2 a] [S| ° |petwarsest sa out | [PWMe| 0 | Dise-motor driving PWM output 2. + | Peh="Weh serial data outout 1 | DOTX | O | Output of digital interface | «=| RAS | 0 | Row address strobe to RAM | [ACRCY [1 | Cock accuracy input] [NC | -[NO CONNECTION J Crest [1 | Test control input. Nowmal=0 [DOBSEL| | Dste bit select 1ebt=1 | [nc | - ['NO GONNECTION DASELr| | DAC interface format eeect T | DASELe| I DAC interface format select 2 | ect ereess ee —| [os [o [ron [ DASELs| 1 | DAC interface format select 4 | RAM [MSO [1] Wierocomouter interece serial date Tout | [McK —[ | Microcomputer interface shift cloc Inout | [WE | 0 | Write enable outout to RAM | [RCA —| 1 Microcomputer inerfoce-date latch clock] ['NC——| -[ NO CONNECTION] [ACER | 1 Microcomputer interface register clear inowd [RADI | O-| Address output 1 to RAM | LAPS [1 High treauency sional detect | [ RAD2 | 0 | Address_outout 2 to RAM] LHF [1] High-frequency sional input | [[RADs | 0 Adgress_output 3 to RAM | [ime [1 current reference] RADr | 0 Address output 7 to RAM | [ric [0 Outout from sioon lever control] [RADe | 0 | Address_outout 4 to RAM | [RADs | 0” | Address output Sto RAM | ee oleae a | Hee ee eee DRO outout TRAD» |_O-| Address output 0 to RAM | [Sv {O [Fane sans ame ta=T | [esr | o | Ere ute 2, Err 0b ena [ove [1 | Voo for data sieer and VOO | detected at C2 [oR |" | Dise rotation down sional outsut | [EST | 0 | Emor suatus 1, Eror detected at OT | LeFrK | 0-[ EFM frame clock cutout duty=S0% | [Voor | 1] Power sunshy BV LSONT [0 Interunt outout of subcode G | [DFR | 0] GSC frame clock cutout 7, Stl, dity-50H [Sand -0-| Subcode-@ register output] [ FSCK | | Clock output 44.kre is) [SaRcK | 1 | Subcode resister | ~—‘([Caa6 | 0 | Crock outout 8 4672uHa | [ScoR [0 Subcode syne cutout. So*Si | -—‘[eaes | 0] Chock cutout. 4 2096MH | Subcode Q CRC check flag output. 1/2 divider input with internal feedback fonor_| 0 | Basgee$ OPE chk te ovens | Lorem | 1 | are ok ih ia snk | Sot x | | eso em [vee [1 Ground, 9} feedback resistor [par | ee O: High Z Loo; | 0" Buel DAC Reh serial deta output | 1 | Ege of bts P= oi | sooe: | | On [Osck | 0] Osta shift cock te DAG] [seaW [OT Scbcode Woh ovtpat——] | LRCK "0 Len/Rch dock to DAC or APTL cook _| [Sacv—|-0-| Subcode Veh ovinut | [002 [0] Bual DAG Loh serial cata outout | -—— F$ecU [0 SubsodeUch cutout |_| WOO | 0" Word lock to DAC or APTL clock | ['sact_[ 0 | Subcode Teh output |‘ [OLRCK | O | LetV/Rch cock [Secs [0 [ Subcode Sch ovtout | «LAPTL [0 | DAC somping dock toh [Sack [0_| Subcode Rech output] LABTR [| BAC" samping cook Reh]

MITSUBISHI SOUND PROCESSOR ICs CD PLAYER DIGITAL SIGNAL PROCESSOR S)].) ABSOLUTE MAXIMUM RATINGS (Ta = 25°C, unless otherwise noted) | VooVss | Supply voltage PT 08H TO (Re = 09) Vss-0.3S Vis Voo+0.3| V_ | (Re=0Q) Vss-0.38 Vo $ Voo Pull_up voltage pve V00 + 2mA Re | Toor | Operating temperature | 10 +70 | To | Storage temperature | SAO IS OTCOOC [Pa | Power dissipation 8 | RP: Pull up resistor RECOMMENDED OPERATING CONDITIONS | Yoo | Supply voltage Pas 50 Ts Tv | ‘ High level input voltage 1 p20 05 |= Von [VY Highlevel input voltage 2 [00 90:7 = Voo [Vv Low/evel_input_voltage 1 ee Lowdevel_input_voltage 2 pss [= [000.37 Oscillation frequency (tal) ee Oscillation frequency (VCO) a ks Note 1. Applied pin 1) DASEL1~DASEL4, ACRCY, DOBSEL, TEST 2) AFD, SCOE1, SCOE2, SCCK, MSD, MCK, MLA, ACLR, RDB!1~RDB4, SQRCK ELECTRICAL CHARACTERISTICS (Ta = 25°C, Voo = 5V, unless otherwise noted) ti Applied] Test [emin| ree | owen DoT Gireuit control fosc = 8.4672MHz 2 mA fvco = 8.6436MHz Highlevel_output voltage Voo=4.5V, lon=-0.8mA | 3) [| 3 | 35 [| - [| - | v | Low-level output voltage Voo=45V, la=0.8mA | 3) [| 3 [= [= Toa [ov] | in| Hightevel_intout_current Vin= 4.5V a | lozw | Off state hiohlevel output current | Vou= 4.5V fs | 5 | - | - [| 2] ual Off state low-level output current | Vo.= 0.5V | s) [5 [= | = 2 Tua | oO (EFFK) VuPe= 1,0V ee See ETE aqueroy [Mers2sv Oe re es = ee | Virr = 4.0V pT 6 os TT ke | Note 2. Apphed pin 3) Output and input/output pin except Xo, TLC, LPF 4) Input pin except Xi, CIGMI, IREF 5) RDB1~RDB4, SBCP~SBCW ——}— @ aera rics:

MITSUBISHI SOUND PROCESSOR ICs CD PLAYER DIGITAL SIGNAL PROCESSOR TEST CIRCUIT ry = top o VOD (a) Voi Voo2 ok Vvoo2 8.46MHz © Xi . REF O ° TO 8.46MHz © xi LPF i oF OUTPUT] | ouT inpurd | | INPUT PINS]! [PUT | | PINS ! eM oy o- —o HF SIGNAL ° 5 Law tc Vssi Vss2 Vsst Vss2

6 VoD 6 Vo

Voor voo2 | ‘OH or !oL Von! Vop2 WH or lL TESTED TESTED PIN ° 7 —O- ein ) Vi or Vi Vssi Vss2 | Vsst Vss2

6 VoD ° ° VoD

voi voo2 vob? vob2 lozH or loz feo TESTED spn | O92 IREF EFFK © (FREQUENCY) LPF Von VLPF © or Vou vss Vss2 I Vss1 Vss2

MITSUBISHI SOUND PROCESSOR ICs CD PLAYER DIGITAL SIGNAL PROCESSOR FUNCTIONAL DESCRIPTION 1. Data slicing/PLL The M50423FP has an analog front-end for incoming HF the M50423FP with a wide capture/lock range. There is no (EFM) signal. Using CMOS-Analog technology, the front-end need to adjust the VCO. LPF is the charge-pump output and comprises an automatic slice level control circuit and EFM- same-time control voltage input to the VCO. LPF turns off PLL circuit with internal adjust-free VCO. The block-diagram when HFD goes High. shows the analog frontend. The HF signal is sliced by the IREF is the reference current input used to determine the HF comparator and a DC level is feed back from TLC to current of charge pumps TLC and LPF, operating point of HF through the external CR. If HFD goes High because of HF comparator, and VCO free running frequency. If IREF is a defect an disc, then TLC time off and holds the DC level. connected to a noisy power supply through a resistor, VCO EFM-PLL extracts the EFM clock signal from the HF signal. is modulated and the error-rate increases. Therefore, power The PLL circuit has a phase/frequency comparator not provides supply noise at IREF must be held to a minimum. BLOCK DIAGRAM (Data slicing/PLL) Hs ls F-& TLC LPF HF COMPARATOR HF SIGNAL oH) HE CHARGE} PHASE CHARGE: | |CHARGE} z= PUMP, aie PUMP pump T_| »—— . HF. 1/2 veo ° C) TIMER 12] LOW FREO LIMITTER HF COMPARATOR FREQ TIMER TIMER CURRENT ne [we me ©) SOURCE LPF (REF CONTROL |_. yoo EFM DATA| | EFM CLOCK ASYNC. FRAME SYNC. PROTECTION — POUNTEF ' to EFM DEMODULATOR BLOCK r MITSUBISHI

MITSUBISHI SOUND PROCESSOR ICs M50423FP CD PLAYER DIGITAL SIGNAL PROCESSOR (1) Automatic slice level control 2. Demodulatlon/Decoding The EFM signal converted to logic level and the EFM clock HF signal O——{ HE extracted from the EFM signal are input to the demodulator or Ms0423FP and decoder block. The EFM demodulator must be Te synchronized to the EFM clock. The decoder uses the clock from the X'tal oscillator. Jitter between the EFM signal and ce output of the decoder is absorbed by external RAM. I (1) Clock generator Ci : 0.0022 uF C2: 0.022 uF R:33kQ Vin: HFO.SVP-P Min M50423FP The slice level control circuit is formed by connecting a resistor and capacitors to the HF (High-Frequency signal i ice I i ins. input) and TLC (slice level contro! oputput) pins. | oy . Xtal : 8.4672MHz (2) PLL R3 co C2 C1 : 30pF I i C2: 30pF Re iT (a) The oscillation circuit can be formed by connecting a LPF 50429FP Xtal oscillator (8.4672MHz) and load capacitors to pins Xi and Xo. : | l M50423FP ce C1: 470pF ~ ud Ri: 2.2kQ 8.4672kHz Vin > 1VP-P Re: 2.2MQ Ra: 1kQ Since the adjustment-free VCO is built in, the adjustmentfree (b) When the system contains a clock (8.4672MHz), the PLL circuit can be formed by connecting a resistor and clock can be input to pin Xi via a capacitor without using capacitors to the LPF (low-pass filter) pin. the X’tal oscillator. lf the input signal is logic level, the capacitor is not (3) Reference current necessary M50423FP R IREF s0423FP crew xt 1000pF Ri: 120k J 16.9344MHz Vin > 1VP-P A resistor must be connected between the IREF pin and Voo in order to set the reference current used in determining the current values of the TLC pin and LPF pin, the (c) When the system contains a clock (8.4672 x 2 = 16. comparator operating current of the slice level control circuit, 9344MHz), the internal 1/2 divider can be used by and the VCO free-run frequency. connecting pin Xi to pin C8MO and inputting the clock to pin CI6MI via a capacitor. The 1/2 divider between C16MI and C8MO can be used for any purpose, independent of other functions.

MITSUBISHI SOUND PROCESSOR ICs CD PLAYER DIGITAL SIGNAL PROCESSOR (2) Frame Synchronization EFM demodulating is done by Programmable Logic Array holds the synchronization and prevents false synchronization conversion table. The demodulator must be synchronized to of the demodulator when bit-slipping or missynchronization EFM signal for each frame. The frame sync protection circuit occurs. EFM—*+SYMBOL veo

23 BIT S/R EFM TIMING GENERATOR

DET. [-=] SYNC. + 588 foo | WINDOW GENERATOR| SYNC. Lock SYNC. CONTROL spare WINDOW} oe ASYNC. FRAME ° we merconnes Sri Fig. 1 Frame synchronization block diagram The generating condition of the counter reset signal LOCK/DRD pin outputs DRD signal (see Sec. 3) when the (Reset) in the EFM timing generator is indicated as follows: disemotor is braking by the command from microcomputer. Reset = (Sync * Tfs) + (Sync * Window) The following pages contain the block diagram and the * : Logical product output timing. +: Logical sum Syne : Synchronizing signal EFM CK o DRD Tis : Detection signal of synchronizing signal 2/S0ET. o OSC CK o- space = 588 Window : Window signal + 7ck ° INTERFACE BRAKE In the synchronous state, sync and Tfs generate REGISTER TO MICROCOMPUTER simultaneously and sync comes to the center of the window. 1/16 EFFK O 4 LOCK/DRD At this time, 1 is output to the SYCLK pin. ° oo? Frame sync status is output to SYCLK pin. sycLK tt) : The SYCLK output includes some bounce even when the Ried syne pattern is lost because of a defect an the disc. Hence, gD) there is a need for debouncing the sync status signal for it to be monitored by the system control microcomputer. 23 Debouncing is in the MS0423FP by monitoring the frame SYNC. STATES y= 08 syne status at 1/16 EFM frame clock intervals and then Lock/ outputting the result to the LOCK/ORD pin. If the monitored ORD \\ i status is locked then output is High. Eight continuous ee unlocked outputs becomes Low. BRAKE @ wrsueisu

MITSUBISHI SOUND PROCESSOR ICs M50423FP CD PLAYER DIGITAL SIGNAL PROCESSOR (3) Subcode demodulation SUBCODE DEMODULATION Among data converted from 14-bits EFM signal to 8-bit [SCOE1 | SCOE2 [SBCP|SBCO|SBCR|SBCS |SBCT|SBCRISBCV SBC} symbols, subcodes P, Q, R, S, T, U, V and W are output [0 | 0 | Highimpedance | Highimpedance _| to pins SBCP-SPCW respectively. When the subcode | 1 | 0 [| P | Q [RS | Highimpedance | synchronizing patterns So or St is detected as synchronizing | 0 | 1 [ Highimpedance | T [ U | V | W | signal of subcode data, the synchronizing signals are outot L111 {TP TatRi{s {ruil vw | to the SCOR pin. Pins SBCP-SBCW are a Three-State output system controlled by pins, SCOE1 and SCOE2 as shown in the table below. A CRC check is made for the Q channel data, and if the data is correct, a 1 is output to the CRCF pin. The EMP pin displays whether or not emphasis is present. The subcode data is not only output in parallel, but also can be obtained serially via SBCP, by inputting a clock to SCCK. Subcode output timing are shown Fig. 2.

MITSUBISHI SOUND PROCESSOR ICs CD PLAYER DIGITAL SIGNAL PROCESSOR scorn X VALID SBCP~W ' X VALID + i : ' ' ' \\ \\ EFFK ! ' 1 ! H f 43t H i oe I ° I . 4 44t ' Soa ac (Note 4) EFFK l J ! H oT 98 180) 1) AS) 3 4 SCOR j r a 1 Lo ! \\ cRCF 'X 1 4 * it EMP a H X rt vy nan a) Lit 1 St sace Ke KoXer Xs Xr Xu Xv Xw (Note 5) i EFFK ' rot Note 3. Subcode block No. in the EFM data 4. t: Oscillating frequency (VCO) typically : 1/8.6436MHz = 115.7ns.) 5. When input frequency to SCCK is more than 8ck, SBCP becomes 0. Fig. 2 Subcode output timing @ wmsusisui

MITSUBISHI SOUND PROCESSOR ICs M50423FP . CD PLAYER DIGITAL SIGNAL PROCESSOR ——_— (a) Symbol data/fiag, read/write timing t H H ' T = 1/8.4872MH: | i \\ a118ine ee ' i { \\ ‘ 1 ' ' RAS ' ' H ' ‘ i es re ee WE X 7 T y h ROBI~4 1 ' 1 ! ' ' (b) C1/C2 flag, read/write timing f \\ 1 CAS | : t t ' 1 i 1 i ' ' ' { RDBI~4 i H u ‘ Fig. 3 RAM Interface timing

MITSUBISHI SOUND PROCESSOR ICs M50423FP CD PLAYER DIGITAL SIGNAL PROCESSOR —_— (4) Subcode Q register Subcode Q-channe! data are output to SBCQ pin. The M50423FP stores the Q data in an 80-bit shift register and if CRC is OK, the system control microcomputer can access the Q data from the SBCQ pin by inputting the read-out clock to SQRCK pin. If the CRC check is OK, the M50423FP outputs the interrupt signal to the micro- : computer from SCINT, synchronaized with SCOR (Subcode syne.) signal. Timing chart CRCF SCOR SCINT ne a OOOO BObOHDOOO0 > tm LSB+— MSB LSB<-—> MSB Sbits Bbits READ DATA < 10ms SSS © mmsueisui

MITSUBISHI SOUND PROCESSOR ICs CD PLAYER DIGITAL SIGNAL PROCESSOR (5) RAM interface/CIRC decoding A 64K (4x 16K) /256K (4 x 64K) dynamic RAM is needed When correction is not possible, average interpolation or as the external memory for temporary storage to process pre-hold interpolation is perfomed. CIRC decoding (C1 decoding, C2 decoding, unscramble and Error states which are detected during decoding are output de-interleave) and output interpolation. to pins EST: and EST2. By using a 64K/256K RAM, jitter is absorbed up to +8 When an error is detected by C1 decoding, 1 is output frames (max.). to pin EST1. When an error word is judged incorrectable by Fig. 3 shows the timing for reading from and writing to C2 decoding, a “1”is output to pin EST2. the RAM. The output timings for pins EST: and EST2 are as follows: Dowing CIRC decoding, double error correction is used for both C1 and C2 decoding. Timing chart DOFK i 1 i ' 1 ' 1 1 ( t 1 1 Esti ' { l t ERROR DETECTED FRAME BY Ct DECODING wock 1 1 1 1 1 1 1 t 1 1 i 1 1 \\ 1 1 1 1 \\ 1 EST2 t ' t J H 7 i 1 ' 1 1 1 1 1 1 i ' 1 i , 1 ' 1 1 i ( \\ i 1 oo XO SOE OME} ' INTERPOLATED WORD : 1 When, DASEL3 = 0 DASEL4 = 1

MITSUBISHI SOUND PROCESSOR ICs M50423FP CD PLAYER DIGITAL SIGNAL PROCESSOR 3. Microcomputer Interface CLV servo, MUTE, and ATT system are controlled by serial commands from the microcomputer, The timing, names, and functions of each control register are as follows: Timing chart wo oXeXeXeKeKeXe Xe MLA TTT ZT © DUMMY (Don't care) x @® S/S(START/STOP) register start =1 @ BCON(BRAKECONTROL) register enable = 1 @ BRAK (BRAKE) register brake = 1 @ ATT (ATTENUATE) register -126B =1 ® MUTE register muting = 0 ® S/S timer reset register reset = 1 @ IC code M50423FP = 1 t t Mso MCK MLA t a + min: 500ns eS . @ owrcueisu

MITSUBISHI SOUND PROCESSOR ICs M50423FP CD PLAYER DIGITAL SIGNAL PROCESSOR ———$ eee Function of microcomputer Interface register S/S Controls START/STOP of the DISC MOTOR DISC MOTOR 0 by ACR (START/STOP)| disk motor STOP (OFF) START (ON) BCON Determines if BRAKE control BRAKE is controlled BRAK BRAKE OFF When ATT (ATTENUATE) | Sets attenuation (- 12dB) = 1208 When MUTE = 1 0 by ACLR S/S Resets the S/S timer which sets the a : ' time of KICK and BRAKE to 0. 3sec, S/S timer enable S/S timer disable 1 by ACLR Distinguishes the command to . 0 is code for fo [eww [ares ee Examples of system control are as follows : When the M50423FP detects that the number of rotations is less than 2/3 that of the normal play state, it output the disc rotation deterioration signal to the DRD pin. Register name Fy By using this signal in the following stop sequence, the e disc can be correctly stopped. = Els . 2| |zlz wan) Operation 3) 0/8)/ 2] B ols 2l3|8/% </5/a3/o Register name % O@(O/O/9/@/O/O/@ 2 po Jo] q 5 MUTE | [| | ft fot ti S! loly E/8 a a oe , 3/218 |z|c\\ble 8 . 0.3sec.KICK > CLV ria] [ TT [oft] Operation or B/5/8/S|<IE/sle 0.3sec.BRAKE>MOTOR OFF] [OfO]| | | [o|1] COM Operation O1O|®|O|@|O|O|@ ferake fot tat fofry fray TT Ti fofofoti for [moror OFF fol fol fy folr| = ferake TT foli ti fofofoly| 0.3sec. timer disable rLrretip (AFD: H_ checking by microcomputer) [wor ofthe Oeecemned [TOTO] TT [i {i} | (Measuring toAo (ORD: O> 1) after BRAKE stort CLV (without 0.3sec.KicK) | fi fol | | f1[1] (Stop HFD checking and) additional BRAKE time 2 x toro The following 1s example of the most simplified system MOTOR OFF [ Loti foTolojfojs] control sequence. STOP [ofofojoti] | 03sec. KICK > CLV Be The DRD signal is output to both the DRD pin and also [Base Kecmowv fT fetototofoly the LOCK/DRD pin during the braking period. eee fT CT In order to re:nitiative the microcomputer interface register PLAY | [i ToToTol7 [Oli] — execute ACLR (M50423FP clear) immediately after turning O.3sec. BRAKE>STOP] [OTOTOTOTOTOT?] the power on. * The blanks mean “Don't care"or that other commands can be used simultaneously * KICK period can be extended by repetition of start procedure. * The software developed on the M50421P/M50422P can be utilized on the M50423FP (upward compatible). However, when using this software, the following functions on the M50423FP are not available : subcode Q-register, subcode Qunterrupt signal LOCK/DRD output.

MITSUBISHI SOUND PROCESSOR ICs M50423FP CD PLAYER DIGITAL SIGNAL PROCESSOR eS 4, Digital filter 5. D-A Converter Interface The M50423FP converts the sampling frequency of audio The M50423FP has many different DAC Interface formats. data from 44.1kHz (fs) to 88.2kHz (2fs) or 176.4kHz (4fs) The desired format is selected using pins DASEL1~DASELa. by an overflow limited, FIR linear-phase digital filter. Timing signals, data and clock automatically change to Digital filter selection is done using pins DASELi~DASELa. correspond to which digital filter, fs (pass) / 2fs/ 4fs, is Table! shows the digital filter and DAC interface mode. chosen. Digital filter pass mode with no interpolation of umcorrectable If the 4fs digital filter mode is selected then the dual DAC data is designed for non-audio applications such as CD-ROM mode and 18-bits data out mode are available. or CD-1, The digital filter pass mode with interpolation is Table 1 shows the interface modes. used external precision digital filter applications. Fig. 5 (a) ~Fig. 5 (e) show the timings if interface to DAC. Fig. 4 (a) shows the characteristics of the 2fs digital filter. Fig.4 (b) shows the characteristics of the 4fs digital filter. 0 9 oo oe gat + i\\an! | a” oe eel ieee © © 4 oot | NMA IV i eee he - 1p 10k 20k 30k 40k 50k ~ 805 20k 40k 60k 80k 100k frequency (Hz) frequency (Hz) te) (o) coipalafl_| | cit af | T Tf Soh | [| [1 1 | ae a ie) 10k 20k 30k 40k 50k fe) 20k 40k 60k 80k 100k frequency (Hz) frequency (Hz) Fig. 4 (a) Frequency characteristics Fig. 4 (b) Frequency characteristics of the digital filter of the digital filter (Sampling frequency 88.2kHz:2fs) (Sampling frequency 176.4kHz:4fs)

MITSUBISHI SOUND PROCESSOR ICs M50423FP CD PLAYER DIGITAL SIGNAL PROCESSOR Table 1 DAC Interface modes poi po ooo as se ise Fin 5 @ [2 [0 Po os) SB ist] Bypass fitter | Fio. 5 () ps3 fa fo fo sts ist Fin 5) po4 [i To To fT Gs) [tse ist] Bypass filter | Fia. 5b) | pos [ if oo fT 4 fT oT ais [Msp ist Fin 5) | [ret ot tats sist] Oat DAF 8) | [po ts sist No internolation | Fie. 5 (a) —] Poa f 1 of 1 tf o fT oT 2s [ Mse ist TT Fro 5 Ge) [Lo fT 1 ft ot ts) s8 ist [Bypass filter | Fig. 5 Ce) (a) Mode 1/2/7

01 ES DOE ED OO00050000 a mE FCT ECOOOOBOB0008

sok “UPLTUTLPLTLIUTUL TALS LFLFLE ELE LALALSLSLALALELELTLULLLASLSALSLL_ pLRCK + | f t bo H H wock ~ | J LT L_ (b) Mode 3/4 oi KSB XAASKEASKERTAEROM AAA ESB KX BKENEXENT KENNA HY osck SUUUUUUUULR A Lee eee APTL 1 i | APTR __| i Fig. 5 DAC interface timing chart

MITSUBISHI SOUND PROCESSOR ICs M50423FP CD PLAYER DIGITAL SIGNAL PROCESSOR (c) Mode 5 Dot DSCK innn ul { FLFR { FLEAS LALA arma "LL (d) Mode 6 Dot L-ch) | i doz SB EINE ON IS XIX TIX IZ KIT KTON SX EXT KEK S X43 XZ XC) (R-ch) | i DSCK TUL U A a apTL i (e) Mode 8/9 Do1 EE DORED0000000000 CE LT oCD DOGO 00e0 Dsck “LOTUS Fig. 5 DAC Interface timing chart ry MITSURISHI

MITSUBISHI SOUND PROCESSOR ICs CD PLAYER DIGITAL SIGNAL PROCESSOR 6. Digital Interface output The M50423FP outputs digital interface signal conforming to EIAJ CP-340 or IEC formats. AUDIO DATA © - . a 16 The block diagram shows the digital interface and Fig. 6 BIFMSE] poTx shows the timings. Channel status clock accuracy can handle MARK ) variable pitch control and can be set using the ACRCY pin. ; woo. The clock accuracy is level Il when ACRCY pin is Low, © Wbit(EST2) and level I!l when ACRCY pin is High. ACRCY i o—,cH STATUS| 7 iG $644 b TIMIN CONTROL — SBCO~W ° 34 738 " SUBFRAME FORMAT 27 28 31 t He He M PREAMBLE |S AUXILIARY |S 's DATA (bit) sjvjulc B 1B IE} B ( ' ' és 0 VALIDITY FLAG ‘ ss _ see USER DATA S y B111 Ooo | Channel A and Top of block ; M1TTOQO0I_ | Channel A and excent top of block CHANNEL STATUS w177T0|0 1/00 1 Channel B «+ (except Channel A) PARITY bit CHANNEL CODING 1 i | }SOURCE CODING

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| BIPHASE MARK FRAME FORMAT [=[osone Tu [oane 2[ Touma. [w] ome [e[ounes[w[omme [> SUBFRAME SUBFRAME TOP OF BLOCK Fig. 6 Timing

MITSUBISHI SOUND PROCESSOR ICs. CD PLAYER DIGITAL SIGNAL PROCESSOR a 7. CLV servo control circult CLV servo control circuit operates using two signals. The first is the frequency differance beween EFM-clock and X’tal -clock. The second is the phase difference beween write- frame address and read-frame address of the external 64K or 256K RAM. Motor control signals are output to PWMi (- signal) and PWMz (+ signal). Because these singals are internally phase compensated, the CLV servo control circuit can be easily composed using current drivers on pins PWM: and PWM2. Fig. 7 shows the CLV wave form and its duty cycle when the CIRC decoding block addressing write-frame address and the read-frame address exceeds + Sframes. When this occurs the duty cycle of the CLV waveforms will be reset to 0. The disc motor can be driven by PWM waveforms directly ‘or it can be driven by an analog signal that can be generated . by integrating the PWM waveforms. By using an analog signal, it is possible to adjust the servo loop-gain by varying direct external component values. But in the case of PWM waveforms, the servo loop-gain is determined by motor torque, and the rotating moment of the disc, turntable, and disc clamper. a a PWM! 2us 227us Loew OT te to DUTY RATIO Wewme — WewMt H ra DUTY RATIO =~ Vewwa + WPWMt a) a = 8frames ~ \\ Le ra 7) Sframes Fig. 7 CLV waveform ry MITGCLIRIGHI