M485L1624FT0

M470L1624FT0 SAMSUNG | Alldatasheet

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Technical content

DDR SDRAM128MB, 256MB SODIMM Rev. 1.2 March 2004 DDR SDRAM SODIMM 200pin Unbuffered SODIMM based on 256Mb F-die 64 / 72-bit (Non ECC / ECC) Revision 1.2 March, 2004

DDR SDRAM128MB, 256MB SODIMM Rev. 1.2 March 2004

Revision History

Revision 1.0 (June, 2003) - First release Revision 1.1 (August, 2003) - Corrected typo. Revision 1.2 (March, 2004) - Corrected package dimension.

DDR SDRAM128MB, 256MB SODIMM Rev. 1.2 March 2004 SAMSUNG ELECTRONICS CO., Ltd. reserves the right to change products and specifications without notice. 200Pin Non ECC / ECC SODIMM based on 256Mb F-die(x16)

Ordering Information

Part Number Density Organization Component Composition Height M470L1624FT0-C(L)B3/A2/B0 128MB 16M x 64 16Mx16 (K4H561638F) * 4EA 1,250mil M470L3224FT0-C(L)B3/A2/B0 256MB 32M x 64 16Mx16 (K4H561638F) * 8EA 1,250mil M485L1624FT0-C(L)B3/A2/B0 128MB 16M x 72 16Mx16 (K4H561638F) * 5EA 1,250mil B3(DDR333@CL=2.5) A2(DDR266@CL=2) B0(DDR266@CL=2.5) Speed @CL2 133MHz 133MHz 100MHz Speed @CL2.5 166MHz 133MHz 133MHz CL-tRCD-tRP 2.5-3-3 2-3-3 2.5-3-3 Feature

• Power supply : Vdd: 2.5V ± 0.2V, Vddq: 2.5V ± 0.2V
• Double-data-rate architecture; two data transfers per clock cycle
• Bidirectional data strobe(DQS)
• Differential clock inputs(CK and CK)
• DLL aligns DQ and DQS transition with CK transition
• Programmable Read latency 2, 2.5 (clock)
• Programmable Burst length (2, 4, 8)
• Programmable Burst type (sequential & interleave)
• Edge aligned data output, center aligned data input
• Auto & Self refresh, 7.8us refresh interval(8K/64ms refresh)
• Serial presence detect with EEPROM
• PCB : Height 1250 (mil), single(128MB), double(256MB) sided component

DDR SDRAM128MB, 256MB SODIMM Rev. 1.2 March 2004 KEYKEY Pin Configurations (Front side/back side) Note 1. * : These pins are not used in this module. 2. Pins 71, 72, 73, 74, 77, 78, 79, 80, 83, 84 are not used on x64 module, & used on x72 module. Pin 95,122 are NC for 1Row module (M470L1624FT0, M485L1624FT0) & used for 2Row module (M470L3224FT0). Pin Front Pin Front Pin Front Pin Back Pin Back Pin Back VREF VSS DQ0 DQ1 VDD DQS0 DQ2 VSS DQ3 DQ8 VDD DQ9 DQS1 VSS DQ10 DQ11 VDD CK0 /CK0 VSS DQ16 DQ17 VDD DQS2 DQ18 VSS DQ19 DQ24 VDD DQ25 DQS3 VSS DQ26 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 DQ27 VDD CB0 CB1 VSS DQS8 CB2 VDD CB3 DU VSS CK2 /CK2 VDD CKE1 DU A12 VSS VDD A10/AP BA0 /WE /CS0 *DU(A13) VSS DQ32 DQ33 VDD DQS4 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 DQ34 VSS DQ35 DQ40 VDD DQ41 DQS5 VSS DQ42 DQ43 VDD VDD VSS VSS DQ48 DQ49 VDD DQS6 DQ50 VSS DQ51 DQ56 VDD DQ57 DQS7 VSS DQ58 DQ59 VDD SDA SCL VDDSPD VDDID VREF VSS DQ4 DQ5 VDD DM0 DQ6 VSS DQ7 DQ12 VDD DQ13 DM1 VSS DQ14 DQ15 VDD VDD VSS VSS DQ20 DQ21 VDD DM2 DQ22 VSS DQ23 DQ28 VDD DQ29 DM3 VSS DQ30 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 DQ31 VDD CB4 CB5 VSS DM8 CB6 VDD CB7 *DU/(RESET) VSS VSS VDD VDD CKE0 DU(BA2) A11 VSS VDD BA1 /RAS /CAS /CS1 DU VSS DQ36 DQ37 VDD DM4 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 DQ38 VSS DQ39 DQ44 VDD DQ45 DM5 VSS DQ46 DQ47 VDD /CK1 CK1 VSS DQ52 DQ53 VDD DM6 DQ54 VSS DQ55 DQ60 VDD DQ61 DM7 VSS DQ62 DQ63 VDD SA0 SA1 SA2 DU Pin Description Pin Name Function Pin Name Function A0 ~ A12 Address input (Multiplexed) DM0 ~ DM7, DM8(for ECC) Data - in mask BA0 ~ BA1 Bank Select Address VDD Power supply (2.5V) DQ0 ~ DQ63 Data input/output VDDQ Power Supply for DQS(2.5V) DQS0 ~ DQS8 Data Strobe input/output VSS Ground CK0,CK0 ~ CK2, CK2 Clock input VREF Power supply for reference CKE0~CKE1 Clock enable input VDDSPD Serial EEPROM Power CS0~CS1 Chip select input SDA Serial data I/O RAS Row address strobe SCL Serial clock CAS Column address strobe SA0 ~ 2 Address in EEPROM WE Write enable NC No connection CB0 ~ CB7 Check bit(Data-in/data-out)

DDR SDRAM128MB, 256MB SODIMM Rev. 1.2 March 2004 Notes: 1. DQ-to-I/O wiring is shown as recom- mended but may be changed. 2. DQ/DQS/DM/CKE/CS relationships must be maintained as shown. 3. DQ, DQS, DM/DQS resistors: 22 Ohms. DQ0 DQ1 DQ2 DQ3 LDM I/O 0 I/O 1 I/O 2 I/O 3 DQ4 DQ5 DQ6 DQ7 I/O 4 I/O 5 I/O 6 I/O 7 UDM I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ8 DM0 CSLDQSDQS0 DM1 DQS1 UDQS A0 - A12 A0-A12: DDR SDRAMs D0 - D3 BA0 - BA1 BA0-BA1: DDR SDRAMs D0 - D3 RAS RAS: SDRAMs D0 - D3 CAS CAS: SDRAMs D0 - D3 CKE0 CKE: SDRAMs D0 - D3 WE WE: SDRAMs D0 - D3 CS0 Serial PD A1 A2 SA0 SA1 SA2 SCL SDAWPVSS D0 - D3 D0 - D3 VDD/VDDQ D0 - D3 D0 - D3VREF VDDSPD SPD Clock Wiring Clock Input SDRAMs CK0/CK0 CK1/CK1 CK2/CK2

2 SDRAMs

128MB, 16M x 64 Non ECC Module (M470L1624FT0) (Populated as 1 bank of x16 DDR SDRAM Module) CK0/1/2 CK0/1/2 Card Edge D0/D2/Cap Cap/Cap/Cap Cap/Cap/Cap R=120Ω± 5% D1/D3/Cap

DDR SDRAM128MB, 256MB SODIMM Rev. 1.2 March 2004 256MB, 32M x 64 Non ECC Module (M470L3224FT0) (Populated as 2 bank of x16 DDR SDRAM Module) CS1 CS0 I/0 0 I/0 1 I/0 2 I/0 3 I/0 4 I/0 5 I/0 6 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 LDQS CS CS Serial PD A1 A2 SA0 SA1 SA2 SCL SDAWP VSS D0 - D7 VDD/VDDQ D0 - D7 D0 - D7VREF VDDSPD SPD Clock Wiring Clock Input SDRAMs CK0/CK0 CK1/CK1 CK2/CK2

4 SDRAMs

A0 - A12 A0-A12: DDR SDRAMs D0 - D7 BA0 - BA1 BA0-BA1: DDR SDRAMs D0 - D7 RAS RAS: SDRAMs D0 - D7 CAS CAS: SDRAMs D0 - D7 CKE0 CKE: SDRAMs D0 - D3 WE WE: SDRAMs D0 - D7 CKE1 CKE: SDRAMs D4 - D7 Notes: 1. DQ-to-I/O wiring is shown as recom- mended but may be changed. 2. DQ/DQS/DM/CKE/CS relationships must be maintained as shown. 3. DQ, DQS, DM/DQS resistors: 22 Ohms. Functional Block Diagram *Clock Net Wiring Card Edge D0/D2/Cap D1/D3/Cap D4/D6/Cap D5/D7/Cap R=120Ω CK0/1/2 CK0/1/2

DDR SDRAM128MB, 256MB SODIMM Rev. 1.2 March 2004 128MB, 16M x 72 ECC Module (M485L1624FT0) (Populated as 1 bank of x16 DDR SDRAM Module) A0 - A12 A0-A12: DDR SDRAMs D0 - D4 BA0 - BA1 BA0-BA1: DDR SDRAMs D0 - D4 RAS RAS: SDRAMs D0 - D4 CAS CAS: SDRAMs D0 - D4 CKE0 CKE: SDRAMs D0 - D4 WE WE: SDRAMs D0 - D4 Notes: 1. DQ-to-I/O wiring is shown as recom- mended but may be changed. 2. DQ/DQS/DM/CKE/CS relationships must be maintained as shown. 3. DQ, DQS, DM/DQS resistors: 22 Ohms. Serial PD A1 A2 SA0 SA1 SA2 SCL SDAWPVSS D0 - D4 D0 - D4 VDD/VDDQ D0 - D4 D0 - D4VREF VDDSPD SPD Clock Wiring Clock Input SDRAMs CK0/CK0 CK1/CK1 CK2/CK2

1 SDRAMs

R=120Ω± 5% D1/D3/Cap CB0 CB1 CB2 CB3 DM I/O 0 I/O 1 I/O 2 I/O 3 CB4 CB5 CB6 CB7 I/O 4 I/O 5 I/O 6 I/O 7 UDM I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 DM8 CSDQSDQS8 UDQS Functional Block Diagram

DDR SDRAM128MB, 256MB SODIMM Rev. 1.2 March 2004 Absolute Maximum Ratings Parameter Symbol Value Unit Voltage on any pin relative to Vss V IN, VOUT -0.5 ~ 3.6 V Voltage on VDD supply relative to Vss V DD -1.0 ~ 3.6 V Voltage on VDDQ supply relative to Vss V DDQ -1.0 ~ 3.6 V Storage temperature T STG -55 ~ +150 °C Power dissipation P D 1.5 * # of component W Short circuit current I OS 50 mA Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability. Note : Power & DC Operating Conditions (SSTL_2 In/Out) Notes 1. Includes ± 25mV margin for DC offset on VREF, and a combined total of ± 50mV margin for all AC noise and DC offset on VREF, bandwidth limited to 20MHz. The DRAM must accommodate DRAM current spikes on VREF and internal DRAM noise coupled TO VREF, both of which may result in VREF noise. VREF should be de-coupled with an inductance of ≤ 3nH. 2.VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF, and must track variations in the DC level of VREF 3. VID is the magnitude of the difference between the input level on CK and the input level on CK. 4. These parameters should be tested at the pin on actual components and may be checked at either the pin or the pad in simulation. The AC and DC input specifications are relative to a VREF envelop that has been bandwidth limited to 200MHZ. Recommended operating conditions(Voltage referenced to VSS=0V, TA=0 to 70°C) Parameter Symbol Min Max Unit Note Supply voltage(for device with a nominal VDD of 2.5V) V DD 2.3 2.7 5 I/O Supply voltage V DDQ 2.3 2.7 V 5 I/O Reference voltage V REF 0.49*VDDQ 0.51*VDDQ V 1 I/O Termination voltage(system) V TT VREF-0.04 V REF+0.04 V 2 Input logic high voltage V IH(DC) V REF+0.15 V DDQ+0.3 V Input logic low voltage V IL(DC) -0.3 V REF-0.15 V Input Voltage Level, CK and CK inputs V IN(DC) -0.3 V DDQ+0.3 V Input Differential Voltage, CK and CK inputs V ID(DC) 0.36 V DDQ+0.6 V 3 V-I Matching: Pullup to Pulldown Current Ratio VI(Ratio) 0.71 1.4 - 4 Input leakage current I I -2 2 uA Output leakage current I OZ -5 5 uA Output High Current(Normal strengh driver) ;VOUT = VTT + 0.84V IOH -16.8 mA Output High Current(Normal strengh driver) ;VOUT = VTT - 0.84V IOL 16.8 mA Output High Current(Half strengh driver) ;VOUT = VTT + 0.45V IOH -9 mA

DDR SDRAM128MB, 256MB SODIMM Rev. 1.2 March 2004 M470L1624FT0 (16M x 64, 128MB Module) (VDD=2.7V, T = 10°C) * Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap. Symbol B3(DDR333@CL=2.5) A2(DDR266@CL=2) B0(DDR266@CL=2.5) Unit Notes IDD0 360 320 320 mA IDD1 500 460 460 mA IDD2P 12 12 12 mA IDD2F 100 80 80 mA IDD2Q 80 72 72 mA IDD3P 140 120 120 mA IDD3N 220 180 180 mA IDD4R 800 680 680 mA IDD4W 760 620 620 mA IDD5 720 660 660 mA IDD6 Normal 12 12 12 mA Low power 6 6 6 mA Optional IDD7A 1,400 1,200 1,200 mA M470L3224FT0 (32M x 64, 256MB Module) (VDD=2.7V, T = 10°C) * Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap. Symbol B3(DDR333@CL=2.5) A2(DDR266@CL=2) B0(DDR266@CL=2.5) Unit Notes IDD0 580 500 500 mA IDD1 720 640 640 mA IDD2P 24 24 24 mA IDD2F 200 160 160 mA IDD2Q 160 144 144 mA IDD3P 280 240 240 mA IDD3N 440 360 360 mA IDD4R 1,020 860 860 mA IDD4W 980 800 800 mA IDD5 940 840 840 mA IDD6 Normal 24 24 24 mA Low power 12 12 12 mA Optional IDD7A 1,620 1,380 1,380 mA

DDR SDRAM128MB, 256MB SODIMM Rev. 1.2 March 2004 M485L1624FT0 (16M x 72, 128MB Module) (VDD=2.7V, T = 10°C) * Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap. Symbol B3(DDR333@CL=2.5) A2(DDR266@CL=2) B0(DDR266@CL=2.5) Unit Notes IDD0 810 720 720 mA IDD1 1,035 900 900 mA IDD2P 27 27 27 mA IDD2F 225 180 180 mA IDD2Q 180 162 162 mA IDD3P 315 270 270 mA IDD3N 495 405 405 mA IDD4R 1,260 1,080 1,080 mA IDD4W 1,440 1,215 1,215 mA IDD5 1,530 1,440 1,440 mA IDD6 Normal 27 27 27 mA Low power 14 14 14 mA Optional IDD7A 2,340 2,160 2,160 mA

DDR SDRAM128MB, 256MB SODIMM Rev. 1.2 March 2004 AC Operating Conditions Parameter/Condition Symbol Min Max Unit Note Input High (Logic 1) Voltage, DQ, DQS and DM signals VIH(AC) VREF + 0.31 V 3 Input Low (Logic 0) Voltage, DQ, DQS and DM signals. VIL(AC) VREF - 0.31 V 3 Input Differential Voltage, CK and CK inputs VID(AC) 0.7 VDDQ+0.6 V 1 Input Crossing Point Voltage, CK and CK inputs VIX(AC) 0.5*VDDQ-0.2 0.5*VDDQ+0.2 V 2 Note 1. VID is the magnitude of the difference between the input level on CK and the input on CK. 2. The value of VIX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the DC level of the same. 3. These parameters should be tested at the pim on actual components and may be checked at either the pin or the pad in simula- tion. the AC and DC input specificatims are refation to a Vref envelope that has been bandwidth limited 20MHz. Output Load Circuit (SSTL_2) Output Z0=50Ω CLOAD=30pF VREF =0.5*VDDQ RT=50Ω Vtt=0.5*VDDQ Input/Output Capacitance (VDD=2.5V, VDDQ=2.5V, TA= 25°C, f=1MHz) Parameter Symbol M470L1624FT0 M470L3224FT0 M485L1624FT0 Unit Min Max Min Max Min Max Input capacitance(A0 ~ A12, BA0 ~ BA1,RAS,CAS,WE ) C I N 1 4 14 54 95 74 14 5 p F Input capacitance(CKE0, CKE1) CIN2 34 38 42 50 34 38 pF Input capacitance( CS0 , CS1) C I N 3 3 43 84 25 03 43 8 p F Input capacitance( CLK0, CLK1,CLK2) CIN4 25 30 25 30 25 30 pF Input capacitance(DM0~DM7,DM8(for ECC)) CIN5 6 7 6 7 6 7 pF Data & DQS input/output capacitance(DQ0~DQ63) Cout1 6 7 6 7 6 7 pF Data input/output capacitance (CB0~CB7) Cout2 - - - - 6 7 pF

DDR SDRAM128MB, 256MB SODIMM Rev. 1.2 March 2004 AC Timming Parameters & Specifications Parameter Symbol (DDR333@CL=2.5)) (DDR266@CL=2.0) (DDR266@CL=2.5)) Unit Note Min Max Min Max Min Max Row cycle time tRC 60 65 65 ns Refresh row cycle time tRFC 72 75 75 ns Row active time tRAS 42 70K 45 120K 45 120K ns RAS to CAS d e l a y t R C D 1 82 02 0 n s Row precharge time tRP 18 20 20 ns Row active to Row active delay tRRD 12 15 15 ns Write recovery time tWR 15 15 15 ns Last data in to Read command tWTR 1 1 1 tCK Col. address to Col. address delay tCCD 1 1 1 tCK Clock cycle time CL=2.0 tCK 7.5 12 7.5 12 10 12 ns CL=2.5 6 12 7.5 12 7.5 12 ns DQS-out access time from CK/CK Data strobe edge to ouput data edge tDQSQ - 0.45 - 0.5 - 0.5 ns 12 DQS-in setup time tWPRES 0 0 0 ns 3 DQS-in hold time tWPRE 0.25 0.25 0.25 tCK DQS falling edge to CK rising-setup time tDSS 0.2 0.2 0.2 tCK DQS falling edge from CK rising-hold time tDSH 0.2 0.2 0.2 tCK DQS-in high level width tDQSH 0.35 0.35 0.35 tCK DQS-in low level width tDQSL 0.35 0.35 0.35 tCK Address and Control Input setup time(fast) tIS 0.75 0.9 0.9 ns i,5.7~9 Address and Control Input hold time(fast) tIH 0.75 0.9 0.9 ns i,5.7~9 Address and Control Input setup time(slow) tIS 0.8 1.0 1.0 ns i, 6~9 Address and Control Input hold time(slow) tIH 0.8 1.0 1.0 ns i, 6~9 Data-out high impedence time from CK/CK tHZ +0.7 +0.75 +0.75 ns 1

DDR SDRAM128MB, 256MB SODIMM Rev. 1.2 March 2004 Parameter Symbol (DDR333@CL=2.5)) (DDR266@CL=2.0) (DDR266@CL=2.5)) Unit Note Min Max Min Max Min Max Mode register set cycle time tMRD 12 15 15 ns DQ & DM setup time to DQS tDS 0.45 0.5 0.5 ns j, k DQ & DM hold time to DQS tDH 0.45 0.5 0.5 ns j, k Control & Address input pulse width tIPW 2.2 2.2 2.2 ns 8 DQ & DM input pulse width tDIPW 1.75 1.75 1.75 ns 8 Power down exit time tPDEX 6 7.5 7.5 ns Exit self refresh to non-Read command tXSNR 75 75 75 ns Exit self refresh to read command tXSRD 200 200 200 tCK Refresh interval time tREFI 7.8 7.8 7.8 us 4 Output DQS valid window tQH tHP -tQHS - tHP -tQHS - tHP -tQHS -n s 1 1 Clock half period tHP tCLmin or tCHmin - tCLmin or tCHmin - tCLmin or tCHmin - ns 10, 11 Data hold skew factor tQHS 0.55 0.75 0.75 ns 11 Active to Read with Auto precharge command tRAP 18 20 20 Autoprecharge write recovery + Precharge time tDAL (tWR/tCK) (tRP/tCK) (tWR/tCK) (tRP/tCK) (tWR/tCK) (tRP/tCK) tCK 13 System Characteristics for DDR SDRAM The following specification parameters are required in systems using DDR333 & DDR266 devices to ensure proper sys- tem performance. these characteristics are for system simulation purposes and are guaranteed by design. Table 1 : Input Slew Rate for DQ, DQS, and DM Table 2 : Input Setup & Hold Time Derating for Slew Rate Table 3 : Input/Output Setup & Hold Time Derating for Slew Rate AC CHARACTERISTICS DDR333 DDR266 PARAMETER SYMBOL MIN MAX MIN MAX Units Notes DQ/DM/DQS input slew rate measured between VIH(DC), VIL(DC) and VIL(DC), VIH(DC) DCSLEW TBD TBD TBD TBD V/ns a, m Input Slew Rate tIS tIH Units Notes

0.5 V/ns 0 0 ps i

0.4 V/ns +50 0 ps i

0.3 V/ns +100 0 ps i

Input Slew Rate tDS tDH Units Notes

0.5 V/ns 0 0 ps k

0.4 V/ns +75 +75 ps k

0.3 V/ns +150 +150 ps k

DDR SDRAM128MB, 256MB SODIMM Rev. 1.2 March 2004 Table 4 : Input/Output Setup & Hold Derating for Rise/Fall Delta Slew Rate Table 5 : Output Slew Rate Characteristice (X4, X8 Devices only) Table 6 : Output Slew Rate Characteristice (X16 Devices only) Table 7 : Output Slew Rate Matching Ratio Characteristics Delta Slew Rate tDS tDH Units Notes +/- 0.0 V/ns 0 0 ps j Slew Rate Characteristic Typical Range (V/ns) Minimum (V/ns) Maximum (V/ns) Notes Pullup Slew Rate 1.2 ~ 2.5 1.0 4.5 a,c,d,f,g,h Pulldown slew 1.2 ~ 2.5 1.0 4.5 b,c,d,f,g,h Slew Rate Characteristic Typical Range (V/ns) Minimum (V/ns) Maximum (V/ns) Notes Pullup Slew Rate 1.2 ~ 2.5 0.7 5.0 a,c,d,f,g,h Pulldown slew 1.2 ~ 2.5 0.7 5.0 b,c,d,f,g,h AC CHARACTERISTICS DDR333 DDR266 PARAMETER MIN MAX MIN MAX Notes Output Slew Rate Matching Ratio (Pullup to Pulldown) TBD TBD TBD TBD e,m

DDR SDRAM128MB, 256MB SODIMM Rev. 1.2 March 2004 Component Notes 1. tHZ and tLZ transitions occur in the same access time windows as valid data transitions. these parameters are not referenced to a specific voltage level but specify when the device output in no longer driving (HZ), or begins driving (LZ). 2. The maximum limit for this parameter is not a device limit. The device will operate with a greater value for this parameter, but sys tem performance (bus turnaround) will degrade accordingly. 3. The specific requirement is that DQS be valid (HIGH, LOW, or at some point on a valid transition) on or before this CK edge. A valid transition is defined as monotonic and meeting the input slew rate specifications of the device. when no writes were previ ously in progress on the bus, DQS will be tran sitioning from High- Z to logic LOW. If a previous write was in progress, DQS could be HIGH, LOW, or transitioning from HIGH to LOW at this time, depending on tDQSS. 4. A maximum of eight AUTO REFRESH commands can be posted to any given DDR SDRAM device. 5. For command/address input slew rate ≥ 1.0 V/ns 6. For command/address input slew rate ≥ 0.5 V/ns and < 1.0 V/ns 7. For CK & CK slew rate ≥ 1.0 V/ns 8. These parameters guarantee device timing, but they are not necessarily tested on each device. They may be guaranteed by device design or tester correlation. 9. Slew Rate is measured between VOH(ac) and VOL(ac). 10. Min (tCL, tCH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this period, less the half period jitter (tJIT(HP)) of the clock source, and less the half period jitter due to crosstalk (tJIT(crosstalk)) into the clock traces. 11. tQH = tHP - tQHS, where: tHP = minimum half clock period for any given cycle and is defined by clock high or clock low (tCH, tCL). tQHS accounts for 1) The pulse duration distortion of on-chip clock circuits; and 2) The worst case push-out of DQS on one tansition followed by the worst case pull-in of DQ on the next transition, both of which are, separately, due to data pin skew and output pattern effects, and p- channel to n-channel variation of the output drivers. 12. tDQSQ Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers for any given cycle. 13. tDAL = (tWR/tCK) + (tRP/tCK) For each of the terms above, if not already an integer, round to the next highest integer. Example: For DDR266B at CL=2.5 and tCK=7.5ns tDAL = (15 ns / 7.5 ns) + (20 ns/ 7.5ns) = (2) + (3) tDAL = 5 clocks

DDR SDRAM128MB, 256MB SODIMM Rev. 1.2 March 2004 Command Truth Table (V=Valid, X=Don′t Care, H=Logic High, L=Logic Low) COMMAND CKEn-1 CKEn CS RAS CAS WE BA0,1 A10/AP A0 ~ A9, A11, A12 Note Register Extended MRS H X L L L L OP CODE 1, 2 Register Mode Register Set H X L L L L OP CODE 1, 2 Refresh Auto Refresh H H LL LH X Self Refresh Entry L 3 Exit L H LH HH X HX XX 3 Bank Active & Row Addr. H X L L H H V Row Address Read & Column Address Auto Precharge Disable HX L H L H V L Column Address Auto Precharge Enable H 4 Write & Column Address Auto Precharge Disable HX L H L L V L Column Address Auto Precharge Enable H 4, 6 Burst Stop H X L H H L X 7 Precharge Bank Selection HX L L H L VL X All Banks X H 5 Active Power Down Entry H L HX XX XLV VV Exit L H X X X X Precharge Power Down Mode Entry H L HX XX X LH HH Exit L H HX XX LV VV DM H X X 8 No operation (NOP) : Not defined H X HX XX X LH HH 9 Note : 1. OP Code : Operand Code. A0 ~ A12 & BA0 ~ BA1 : Program keys. (@EMRS/MRS) 2. EMRS/ MRS can be issued only at all banks precharge state. A new command can be issued 2 clock cycles after EMRS or MRS. 3. Auto refresh functions are same as the CBR refresh of DRAM. The automatical precharge without row precharge command is meant by "Auto". Auto/self refresh can be issued only at all banks precharge state. 4. BA 0 ~ BA1 : Bank select addresses. If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected. If BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank B is selected. If BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank C is selected. If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected. 5. If A10/AP is "High" at row precharge, BA0 and BA1 are ignored and all banks are selected. 6. During burst write with auto precharge, new read/write command can not be issued. Another bank read/write command can be issued after the end of burst. New row active of the associated bank can be issued at t RP after the end of burst. 7. Burst stop command is valid at every burst length. 8. DM sampled at the rising and falling edges of the DQS and Data-in are masked at the both edges (Write DM latency is 0). 9. This combination is not defined for any function, which means "No Operation(NOP)" in DDR SDRAM.

DDR SDRAM128MB, 256MB SODIMM Rev. 1.2 March 2004 Physical Dimensions : 16M x64 (M470L1624FT0) Tolerances : ±.006(.15) unless otherwise specified The used device is 16Mx16 DDR SDRAM, TSOPII DDR SDRAM Part No. : K4H561638F-T*** 2.70 2.50 Units : Inches (Millimeters) Full R 2x 0.17 (4.20) 0.456 11.40 1.896 (47.40) 0.24 (6.0) 0.086 0.79 (20.00) 2.15 (63.60) (67.60) Detail Z 0.16 ± 0.0039 (4.00 ± 0.10) 0.04 ± 0.0039 (1.00 ± 0.1) 2-φ 0.07 (1.80) 1.25 (31.75) 0.16 ± 0.039 (4.00 ± 0.10) 0.096 (2.40) 0.07 (1.8)

0.150 Max

0.04 ± 0.0039 (1.00 ± 0.10)

0.157 Min

(4.00 Min) (3.80 Max) (4.00 Min)

0.024 TYP

0.018 ± 0.001 0.01 (0.25) (0.45 ± 0.03) (0.60 TYP)

0.102 Min

(2.55 Min) Detail Y 0.098 2.45 40 42 39 41 Z Y 199 200

DDR SDRAM128MB, 256MB SODIMM Rev. 1.2 March 2004 Physical Dimensions : 32M x64 (M470L3224FT0) Tolerances : ±.006(.15) unless otherwise specified The used device is 16Mx16 DDR SDRAM, TSOPII DDR SDRAM Part No. : K4H561638F-T*** 2.70 2.50 Units : Inches (Millimeters) Full R 2x 0.17 (4.20) 0.456 11.40 1.896 (47.40) 0.24 (6.0) 0.086 0.79 (20.00) 2.15 (63.60) (67.60) Detail Z 0.16 ± 0.0039 (4.00 ± 0.10) 0.04 ± 0.0039 (1.00 ± 0.1) 2-φ 0.07 (1.80) 1.25 (31.75) 0.16 ± 0.039 (4.00 ± 0.10) 0.096 (2.40) 0.07 (1.8) 0.04 ± 0.0039 (1.00 ± 0.10) (4.00 Min) (3.80 Max) (4.00 Min) 0.018 ± 0.001 0.01 (0.25) (0.45 ± 0.03) (0.60 TYP) (2.55 Min) Detail Y 0.098 2.45 40 42 39 41 Z Y 199 200

DDR SDRAM128MB, 256MB SODIMM Rev. 1.2 March 2004 Physical Dimensions : 16M x72 (M485L1624FT0) Units : Inches (Millimeters) Tolerances : ±.006(.15) unless otherwise specified The used device is 16Mx16 DDR SDRAM, TSOPII DDR SDRAM Part No. : K4H561638F-T*** 2.70 2.50 Full R 2x 0.17 (4.20) 0.456 11.40 1.896 (47.40) 0.24 (6.0) 0.086 0.79 (20.00) 2.15 (63.60) (67.60) Detail Z 0.16 ± 0.0039 (4.00 ± 0.10) 0.04 ± 0.0039 (1.00 ± 0.1) 2-φ 0.07 (1.80) 1.25 (31.75) 0.16 ± 0.039 (4.00 ± 0.10) 0.096 (2.40) 0.07 (1.8) 0.04 ± 0.0039 (1.00 ± 0.10) (4.00 Min) (3.80 Max) (4.00 Min) 0.018 ± 0.001 0.01 (0.25) (0.45 ± 0.03) (0.60 TYP) (2.55 Min) Detail Y 0.098 2.45 40 42 39 41 Z Y 199 200