M466F0804DT1-L

M466F0804DT1-L SAMSUNG | Alldatasheet

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DRAM MODULE M466F0804DT1-L REV. 0.1 Oct. 2000 M466F0804DT1-L EDO Mode 8M x 64 DRAM SODIMM Using 4Mx16, 4K Refresh 3.3V, Low power/Self-Refresh The Samsung M466F0804DT1-L is a 8Mx64bits Dynamic RAM high density memory module. The Samsung M466F0804DT1-L consists of eight CMOS 4Mx16bits DRAMs in TSOP 400mil packages and a 2K EEPROM in 8-pin TSSOP package mounted on a 144-pin glass-epoxy sub- strate. A 0.1uF decoupling capacitor is mounted on the printed circuit board for each DRAM. The M466F0804DT1-L is a Small Out-line Dual in-line Memory Module and is intended for mounting into 144 pin edge connector sockets.

• Part Identification - M466F0804DT1-L(4096 cycles/128ms, TSOP, L-ver)
• Extended Data Out Mode Operation
• New JEDEC standard proposal with EEPROM
• Serial Presense Detect with EEPROM
• CAS -before- RAS Refresh capability
• Self -refresh capability
• RAS -only and Hidden refresh capability
• LVTTL compatible inputs and outputs
• Single +3.3V ±0.3V power supply
• PCB : Height(1000mil), double sided component GENERAL DESCRIPTION FEATURES PERFORMANCE RANGE Speed t RAC t CAC t RC t HPC -L50 50ns 13ns 84ns 20ns -L60 60ns 15ns 104ns 25ns PIN CONFIGURATIONS Pin Front Pin Back Pin Front Pin Back Pin Front Pin Back V SS DQ0 DQ1 DQ2 DQ3 V CC DQ4 DQ5 DQ6 DQ7 V SS CAS0 CAS1 V CC V SS DQ8 DQ9 DQ10 DQ11 V CC DQ12 V SS DQ32 DQ33 DQ34 DQ35 V CC DQ36 DQ37 DQ38 DQ39 V SS CAS4 CAS5 V CC V SS DQ40 DQ41 DQ42 DQ43 V CC DQ44 DQ13 DQ14 DQ15 V SS RSVD RSVD RFU V CC RFU W RAS0 RAS1 OE V SS RSVD RSVD V CC DQ16 DQ17 DQ18 DQ19 V SS DQ20 DQ21 DQ45 DQ46 DQ47 V SS RSVD RSVD RFU V CC RFU RFU RFU RFU RFU V SS RSVD RSVD V CC DQ48 DQ49 DQ50 DQ51 V SS DQ52 DQ53 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 DQ22 DQ23 V CC V SS A10 V CC CAS2 CAS3 V SS DQ24 DQ25 DQ26 DQ27 V CC DQ28 DQ29 DQ30 DQ31 V SS SDA V CC 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 DQ54 DQ55 V CC A11 V SS NC NC V CC CAS6 CAS7 Vss DQ56 DQ57 DQ58 DQ59 V CC DQ60 DQ61 DQ62 DQ63 Vss SCL V CC PIN NAMES Pin Name Function A0 to Address Inputs DQ0 - DQ63 Data In/Out W Read/Write Enable OE Output Enable RAS0 , RAS1 Row Address Strobe CAS0 - CAS7 Column Address Strobe V CC Power(+3.3V) V SS Ground NC No Connection SDA Serial Address / Data I/O SCL Serial Clock RSVD Reserved Use RFU Reserved for Future Use

DRAM MODULE M466F0804DT1-L REV. 0.1 Oct. 2000 CAS4 CAS5 CAS6 CAS7 CAS0 CAS1 CAS2 CAS3 FUNCTIONAL BLOCK DIAGRAM V CC Vss 0.1uF Capacitor for each DRAM To all DRAMs RAS1 W OE A0-A11 Serial PD SDASCL Vss A1 A2A0 LCAS DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 UCAS DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 LCAS DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 UCAS DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 LCAS DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 UCAS DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 LCAS DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 UCAS DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 RAS0 U2 U6 U7U3 DQ16~31 DQ48~63 DQ0~15 DQ32~47 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 LCAS UCAS DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 LCAS UCAS DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 LCAS UCAS DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 LCAS UCAS

DRAM MODULE M466F0804DT1-L REV. 0.1 Oct. 2000 * NOTE : I CC1 , I CC3 , I CC4 and I CC6 are dependent on output loading and cycle rates. Specified values are obtained with the output open. ICC is specified as an average current. In I CC1 and I CC3 , address can be changed maximum once while RAS =V IL . In I CC4 , address can be changed maximum once within one EDO mode cycle time, tHPC . ABSOLUTE MAXIMUM RATINGS * * Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for in tended periods may affect device reliability. Item Symbol Rating Unit Voltage on any pin relative V SS Voltage on V CC supply relative to V SS Storage Temperature Power Dissipation Short Circuit Output Current V IN , V OUT V CC T stg P D IOS -0.5 to +4.6 -0.5 to +4.6 -55 to +125 V V W mA RECOMMENDED OPERATING CONDITIONS (Voltage referenced to V SS , T A = 0 to 70 °C) *1 : V CC +1.3V at pulse width ≤15ns, which is measured at V CC . *2 : -1.3V at pulse width ≤15ns, which is measured at V SS . Item Symbol Min Typ Max Unit Supply Voltage Ground Input High Voltage Input Low Voltage V CC V SS V IH V IL 3.0 2.0 -0.3 *2 3.3 3.6 V CC +0.3 *1 0.8 V V V V DC AND OPERATING CHARACTERISTICS (Recommended operating conditions unless otherwise noted) ICC1 ICC2 ICC3 ICC4 ICC5 ICC6 ICC7 ICCS I(IL) I(OL) V OH V OL Symbol Speed M466F0804DT1-L Unit Min Max ICC1 -50 -60 484 444 mA mA ICC2 Don ′t care - 8 mA ICC3 -50 -60 484 444 mA mA ICC4 -50 -60 364 324 mA mA ICC5 Don ′t care - 1.6 mA ICC6 -50 -60 484 444 mA mA ICC7 ICCS Don ′t care - 2.8 2.8 mA mA II(L) IO(L) Don ′t care -10 -10 uA uA V OH V OL Don ′t care 2.4 0.4 V V : Operating Current * ( RAS , CAS , Address cycling @t RC =min) : Standby Current ( RAS = CAS = W =V IH ) : RAS Only Refresh Current * ( CAS =V IH , RAS cycling @ tRC =min) : Extended Data Out Mode Current * ( RAS =V IL , CAS cycling : tHPC =min) : Standby Current ( RAS = CAS = W =V CC -0.2V) : CAS -Before- RAS Refresh Current * ( RAS and CAS cycling @ tRC =min) : Battery back-up current. Average power supply, Battery back-up mode. Input high voltage(V IH )=V CC -0.2V, Input low voltage(V IL )=0.2V, UCAS ,LCAS =0.2V, DQ=Don ′t care, tRC =31.25us, tRAS = tRAS min~300ns : Self Refresh Current, RAS = UCAS = LCAS =V IL , W = OE =A0~A11=V CC -0.2V or 0.2V, DQ~DQ63=V CC -0.2V or Open : Input Leakage Current (Any input 0 ≤V IN ≤Vcc+0.3V, all other pins not under test=0 V) : Output Leakage Current(Data Out is disabled, 0V ≤V OUT ≤V CC ) : Output High Voltage Level (I OH = -2mA) : Output Low Voltage Level (I OL = 2mA)

DRAM MODULE M466F0804DT1-L REV. 0.1 Oct. 2000 CAPACITANCE (T A = 25 °C, V CC =3.3V, f = 1MHz) Item Symbol Min Max Unit Input capacitance[A0-A11] Input capacitance[ W , OE ] Input capacitance[ RAS0 , RAS1 ] Input capacitance[ CAS0 - CAS7 ] Input/Output capacitance[DQ0 - 63] C IN1 C IN2 C IN3 C IN4 C DQ pF pF pF pF pF AC CHARACTERISTICS (0 °C ≤T A ≤70 °C, V CC =3.3V ±0.3V. See notes 1,2.) Test condition : V ih /V il=2.2/0.7V, V oh /V ol =2.0/0.8V, output loading CL=100pF Parameter Symbol -50 -60 Unit Note Min Max Min Max Random read or write cycle time tRC 84 104 ns Read-modify-write cycle time tRWC 128 153 ns Access time from RAS tRAC 50 60 ns 3,4,9 Access time from CAS tCAC 13 15 ns 3,4,5 Access time from column address tAA 25 30 ns 3,9 CAS to output in Low-Z tCLZ 3 3 ns 3 OE to output in Low-Z tOLZ 3 3 ns 3 Output buffer turn-off delay from CAS tCEZ 3 13 3 13 ns 3,11 Transition time(rise and fall) tT 1 50 1 50 ns 2 RAS precharge time tRP 30 40 ns RAS pulse width tRAS 50 10K 60 10K ns RAS hold time tRSH 8 10 ns CAS hold time tCSH 38 40 ns CAS pulse width tCAS 8 10K 10 10K ns RAS to CAS delay time tRCD 17 37 20 45 ns 4 RAS to column address delay time tRAD 12 25 15 30 ns 9 CAS to RAS precharge time tCRP 5 5 ns Row address set-up time tASR 0 0 ns Row address hold time tRAH 7 10 ns Column address set-up time tASC 0 0 ns 12 Column address hold time tCAH 7 10 ns 12 Column address to RAS lead time tRAL 25 30 ns Read command set-up time tRCS 0 0 ns Read command hold referenced to CAS tRCH 0 0 ns 7 Read command hold referenced to RAS tRRH 0 0 ns 7 Write command set-up time tWCS 0 0 ns 6 Write command hold time tWCH 7 10 ns 6 Write command pulse width tWP 7 10 ns Write command to RAS lead time tRWL 8 10 ns Write command to CAS lead time tCWL 7 10 ns 15 Data set-up time tDS 0 0 ns 8,18 Data hold time tDH 7 10 ns 8,18 Refresh period tREF 128 128 ms CAS to W dealy time tCWD 33 38 ns 6,14 RAS to W dealy time tRWD 70 84 ns 6

DRAM MODULE M466F0804DT1-L REV. 0.1 Oct. 2000 Test condition : V ih /V il=2.2/0.7V, V oh /V ol =2.0/0.8V, output loading CL=100pF Parameter Symbol -50 -60 Unit Note Min Max Min Max Column address to W delay time tAWD 45 53 ns 6 CAS precharge to W delay time tCPWD 47 58 ns 6 CAS setup time ( CAS -before- RAS refresh) tCSR 5 5 ns 16 CAS hold time ( CAS -before- RAS refresh) tCHR 10 10 ns 17 RAS to CAS precharge time tRPC 5 5 ns Access time from CAS precharge tCPA 28 35 ns 3 Hyper page mode cycle time tHPC 20 25 ns 10 Hyper page mode read-modify write cycle time tHPRWC 67 73 ns 10 CAS precharge time (Hyper page cycle) tCP 7 10 ns 13 RAS pulse width (Hyper page cycle) tRASP 50 200K 60 200K ns RAS hold time from CAS precharge tRHCP 30 35 ns W to RAS precharge time (C-B-R refresh) tWRP 10 10 ns W to RAS hold time (C-B-R refresh) tWRH 10 10 ns OE access time tOEA 13 15 ns 3 OE to data delay tOED 10 13 ns Output buffer turn off delay time from OE tOEZ 3 13 3 13 ns OE command hold time tOEH 5 5 ns Output data hold time tDOH 5 5 ns Output buffer turn off delay from RAS tREZ 3 13 3 15 ns 11 Output buffer turn off delay from W tWEZ 3 13 3 15 ns W to data delay tWED 15 15 ns OE to CAS hold time tOCH 5 5 ns CAS hold time to OE tCHO 5 5 ns OE precharge time tOEP 5 5 ns W pulse width(Hyper page cycle) tWPE 5 5 ns RAS pulse width (C-B-R self refresh) tRASS 100 100 us 19,20,21 RAS precharge time (C-B-R self refresh) tRPS 90 110 ns 19,20,21 CAS hold time (C-B-R self refresh) tCHS -50 -50 ns 19,20,21 AC CHARACTERISTICS (0 °C ≤T A ≤70 °C, V CC =3.3V ±0.3V. See notes 1,2.)

DRAM MODULE M466F0804DT1-L REV. 0.1 Oct. 2000 NOTES An initial pause of 200us is required after power-up followed by any 8 RAS -only or CAS -before- RAS refresh cycles before proper device operation is achieved. Input voltage levels are V ih /V il. V IH (min) and V IL (max) are ref- erence levels for measuring timing of input signals. Transi- tion times are measured between V IH (min) and V IL (max) and are assumed to be 5ns for all inputs. Measured with a load equivalent to 1 TTL loads and 100pF. Operation within the tRCD (max) limit insures that tRAC (max) can be met. tRCD (max) is specified as a reference point only. If tRCD is greater than the specified tRCD (max) limit, then access time is controlled exclusively by tCAC . Assumes that tRCD ≥tRCD (max). tWCS , tRWD , tCWD , tAWD and tCPWD are non-restrictive operat- ing parameter. They are included in the data sheet as electri- cal characteristics only. If tWCS ≥tWCS (min), the cycle is an early write cycle and the data out pin will remain high imped- ance for the duration of the cycle. If tRWD ≥tRWD (min), tCWD ≥tCWD (min), tAWD ≥tAWD (min) and tCPWD ≥tCPWD (min). The cycle is a read-modify-write cycle and the data out will contain data read from the selected cell. If neither of the above sets of conditions is satisfied, the condition of data out(at access time) is indeterminate. Either tRCH or tRRH must be satisfied for a read cycle. These parameters are referenced to the CAS leading edge in early write cycles. Operation within the tRAD (max) limit insures that tRAC (max) can be met. tRAD (max) is specified as reference point only. If tRAD is greater than the specified tRAD (max) limit access time is controlled by tAA . tASC ≥6ns, Assume tT=2.0ns If RAS goes high before CAS high going, the open circuit condition of the output is achieved by CAS high going. If CAS goes high before RAS high going , the open circuit condition of the output is achieved by RAS going. tASC is referenced to the earlier CAS falling edge and tCAH is referenced to the later CAS falling edge. tCP is specified from the last CAS rising edge in the previous cycle to the first CAS falling edge in the next cycle. tCWD is referenced to the later CAS falling edge at word read- modify-write cycle. tCWL is specified from W falling edge to the earlier CAS rising edge. tCSR is referenced to earlier CAS falling edge to the RAS fall- ing edge. tCHR is referenced to the later CAS rising from RAS falling edge. tDS , tDH is specified by the earlier CAS falling edge. If tRASS ≥100us, then RAS precharge time must use tRPS instead of tRP . For RAS -only refresh and burst CAS -before- RAS refresh mode, 4096 cycles of burst refresh must be executed within 64ms before and after self refresh, in order to meet refresh specification. For distributed CAS -before- RAS with 15.6us interval CAS - before- RAS should be executed with in 15.6us immediately before and after self refresh in order to meet refresh specifi- cation. 10. 11. 12. 13. 14. 15. 16. 17. 18. 19. 20. 21.

DRAM MODULE M466F0804DT1-L REV. 0.1 Oct. 2000 RAS V IH - V IL - CAS V IH - V IL - A V IH - V IL - W V IH - V IL - OE V IH - V IL - V OH - V OL - COLUMN ADDRESS ROW ADDRESS tRAS tRC tCRP tRP tCSH tRSHtRCD tCAS tRALtASR tRAH tASC tCAH tCRP tAA tOEA tCLZ tRAC OPEN tRCH Don ′t care Undefined tRAD tRRH DATA-OUT tREZ tRCS READ CYCLE tOEZ tCEZ tWEZ DQ tOLZ tCAC

DRAM MODULE M466F0804DT1-L REV. 0.1 Oct. 2000 tWCS NOTE : D OUT = OPEN WRITE CYCLE ( EARLY WRITE ) RAS V IH - V IL - V IH - V IL - A V IH - V IL - W V IH - V IL - OE V IH - V IL - V IH - V IL - COLUMN ADDRESS ROW ADDRESS tRAS tRC tCRP tRP tCSH tRSHtRCD tCAS tRAL tRAD tASR tRAH tASC tCAH tCRP Don ′t care Undefined tWCH tWP CAS tRWL tCWL tDS tDH DATA-INDQ

DRAM MODULE M466F0804DT1-L REV. 0.1 Oct. 2000 NOTE : D OUT = OPEN WRITE CYCLE ( OE CONTROLLED WRITE ) RAS V IH - V IL - A V IH - V IL - W V IH - V IL - OE V IH - V IL - V IH - V IL - DQ COLUMN ADDRESS ROW ADDRESS tRAS tRC tCRP tRP tCSH tRSHtRCD tCAS tRAL tRAD tASR tRAH tASC tCAH tCRP tWP Don ′t care Undefined CAS V IH - V IL - tRWL tCWL tDH tOEHtOED DATA-IN tDS

DRAM MODULE M466F0804DT1-L REV. 0.1 Oct. 2000 READ - MODIFY - WRITE CYCLE RAS V IH - V IL - CAS V IH - V IL - A V IH - V IL - W V IH - V IL - OE V IH - V IL - V I/OH - V I/OL - DQ ROW ADDR tRAS tRWC tRP tRSHtRCD tCAS tCSH tRAD tASR tRAH tASC tCAH tCRP VALID tWP Don ′t care tRWL tCWL tOEZ tOEA tOED tAWD tCWD tRWD DATA-OUT Undefined VALID DATA-IN tRAC tAA tCAC tCLZ tDS tDH COLUMN ADDRESS tOLZ

DRAM MODULE M466F0804DT1-L REV. 0.1 Oct. 2000 tDOH HYPER PAGE READ CYCLE RAS V IH - V IL - CAS V IH - V IL - A V IH - V IL - W V IH - V IL - OE V IH - V IL - COLUMN ADDRESS ROW ADDR tRASP tRP tRCD tASR tCRP Don ′t care Undefined V OH - V OL - DQ tOEP COLUMN ADDRESS tCAS tCAS tCAS tCAS tCP tCP tCP tHPC tHPC tHPC tRHCPtCSH tRAD tRAH tASC tCAH tCAH tCAH tASC tCAH tRCS tAA tRCH tASC COLUMN ADDRESS COLUMN ADDR VALID DATA-OUT tOEZ tOEA tOEP tAA tCAC tOEA tAA tCPA tCAC tCPA VALID DATA-OUT VALID DATA-OUT tOEZ tCLZ tRAC tOEA tOLZ tCAC tRRH tCHO tREZ tOEZ tCAC tOCH tCPA tCAC VALID DATA-OUT tASC tAA

DRAM MODULE M466F0804DT1-L REV. 0.1 Oct. 2000 RAS V IH - V IL - CAS V IH - V IL - A V IH - V IL - W V IH - V IL - OE V IH - V IL - COLUMN ADDRESS ROW ADDR. tRASP tRP tRCD tASR tCRP Don ′t care HYPER PAGE WRITE CYCLE ( EARLY WRITE ) Undefined V IH - V IL - DQ tRHCP tRAD tRAH tCAH tCAH tASC tCAHtASC VALID DATA-IN tDS COLUMN ADDRESS COLUMN ADDRESS tCAS tCP tCAS tCP tCAS tRSH tCSH tASC tWP tWCS tWCH tWP tWCS tWCH tWP tWCS tWCH VALID DATA-IN VALID DATA-IN tDH tDS tDH tDS tDH tCWL tCWL tCWL tRWL NOTE : D OUT = OPEN tHPC tHPC

DRAM MODULE M466F0804DT1-L REV. 0.1 Oct. 2000 Don ′t care HYPER PAGE READ-MODIFY-WRITE CYCLE Undefined RAS V IH - V IL - CAS V IH - V IL - A V IH - V IL - W V IH - V IL - OE V IH - V IL - V I/OH - V I/OL - ROW ADDR tCSH tRASP tRP tASR tRAH tRCD tCP tRAD tCAH tWP tDH COL. ADDR COL. ADDR tCAS tCAS tCRP tASC tCAH tRAL tRCS tCWL tCWD tAWD tRWD tWP tCWD tAWD tCWL tRAC tOEA tCLZ tOEZ tCPWD tOED tASC tCLZ tOEA tCAC tAA tDH tOED tRWL tCRP tDS tOEZ VALID DATA-OUT VALID DATA-IN VALID DATA-OUT VALID DATA-IN tDS DQ tRSH tOLZ tOLZ tHPRWC tCAC tAA

DRAM MODULE M466F0804DT1-L REV. 0.1 Oct. 2000 HYPER PAGE READ AND WRITE MIXED CYCLE RAS V IH - V IL - CAS V IH - V IL - A V IH - V IL - W V IH - V IL - OE V IH - V IL - COLUMN ADDRESS ROW ADDR tRASP tRP Don ′t care Undefined V I/OH - V I/OL - DQ tWEZ tCP tCP tHPC tHPC tHPC tRAD tRAH tASC tCAH tCAH tCAH tASC tCAH tRCHtRCS tRCS tRCH tASC COLUMN ADDRESS COL. ADDR VALID DATA-OUT tREZtAA tWCS VALID DATA-OUT VALID DATA-OUT VALID DATA-IN tRAC COL. ADDR tCAS tASR tCAStCAS tCAS tASC tCP tRCH tWCH tWPE tCLZ tCPA tWED tAA tWEZ tDS tDH tCAC tOEA READ( tCAC ) READ( tCPA ) WRITE READ( tAA )

DRAM MODULE M466F0804DT1-L REV. 0.1 Oct. 2000 Don ′t care RAS - ONLY REFRESH CYCLE* NOTE : W , OE , D IN = Don ′t care Undefined D OUT = OPEN RAS V IH - V IL - CAS V IH - V IL - A V IH - V IL - ROW ADDR tRC tRP tASR tCRP tRAS tRAH tRPC tCRP OPEN CAS - BEFORE - RAS REFRESH CYCLE NOTE : OE , A = Don ′t care RAS V IH - V IL - CAS V IH - V IL - tRC tRP tRAS tRPC tCP tRPC tCSR tCHR tCEZ V OH - V OL - DQ tWRP tWRH W V IH - V IL - tRP * In RAS -only refresh cycle of 64Mb A-dile & B-die, when CAS signal transits from Low to High, the valid data may be cut off.

DRAM MODULE M466F0804DT1-L REV. 0.1 Oct. 2000 HIDDEN REFRESH CYCLE ( READ ) tOEZ DATA-OUT tRP RAS V IH - V IL - CAS V IH - V IL - A V IH - V IL - W V IH - V IL - OE V IH - V IL - ROW ADDRESS tRAS tRC tCHRtRCD tRSH tRAD tASR tRAH tASC tCRP Don ′t care Undefined V OH - V OL -DQ tWRH tRRH COLUMN ADDRESS tOEA tRAS tRC tCAH tRCS tAA tRAC tCLZ tCAC tCEZ OPEN tRP tWEZ tREZ tOLZ tWRP

DRAM MODULE M466F0804DT1-L REV. 0.1 Oct. 2000 tCRP tWCS tRP RAS V IH - V IL - A V IH - V IL - W V IH - V IL - OE V IH - V IL - ROW ADDRESS tRAS tRC tRAD tASR tRAH tASC Don ′t care HIDDEN REFRESH CYCLE ( WRITE ) Undefined CAS V IH - V IL - V IH - V IL - DQ tRSHtRCD tWRH COLUMN ADDRESS tRAS tRC tCHR tCAH tWRP tDS NOTE : D OUT = OPEN tWP tWCH DATA-IN tDH tRP

DRAM MODULE M466F0804DT1-L REV. 0.1 Oct. 2000 CAS -BEFORE- RAS REFRESH COUNTER TEST CYCLE RAS V IH - V IL - CAS V IH - V IL - A V IH - V IL - COLUMN ADDRESS tRAS tRSH tCHR tRAL tCSR tCPT tRP tCAS tASC tCAH READ CYCLE V OH - V OL - DATA-OUTDQ tREZ tCLZ WRITE CYCLE V IH - V IL - DATA-INDQ tDHtDS W V IH - V IL - tWP tCWD tCWL tRWL READ-MODIFY-WRITE tAWD V IH - V IL -OE tOEA tAA tCAC tDS tDH VALID DATA-OUT V I/OH - V I/OL - DQ Don ′t care Undefined V IH - V IL - OE tOEA tOEZ OE V IH - V IL - tRCS tCLZ tOEZ tOED tWRP tWRH tRRH tRCH tRCS tCAC tAA V IH - V IL - W tWRP tWRH tWCS tWCH tCWL V IH - V IL - W tWP tRWL tWRP tWRH VALID DATA-IN NOTE : This timing diagram is applied to all devices besides 64M DRAM based modules. tCEZ tWEZ

DRAM MODULE M466F0804DT1-L REV. 0.1 Oct. 2000 OPEN CAS - BEFORE - RAS SELF REFRESH CYCLE NOTE : OE , A = Don ′t care RAS V IH - V IL - CAS V IH - V IL - tRPStRASS tRPC tCP tRPC tCSR tCEZ V OH - V OL - DQ tRP Don ′t care Undefined tCHS tWRP tWRH W V IH - V IL - OPEN TEST MODE IN CYCLE NOTE : OE , A = Don ′t care RAS V IH - V IL - CAS V IH - V IL - tRP tRC tRPC tCP tRPC tCSR tCEZ V OH - V OL - DQ tWTS tWTH W V IH - V IL - tCHR tRP tRAS

DRAM MODULE M466F0804DT1-L REV. 0.1 Oct. 2000 PACKAGE DIMENSIONS 2.66(67.60) 2.50(63.60) 2- φ 0.07 Units : Inches (millimeters) 0.024 ±0.001 0.03 TYP 0.150Max (3.81Max ) 0.04 ±0.0039 Tolerances : ±.005(.13) unless otherwise specified The used device is 4Mx16 DRAM with EDO mode, TSOP II DRAM Part No. : K4E641612D-T (1.80) 0.13(3.30) (1.00 ±0.10) 2-R 0.078 Min (2.00 Min) 0.18 (4.60) 0.083 (2.10)0.10 (2.50) 0 .2 4 ( 6 .0 ) 0.16 ±0.039 (4.00 ±0.1) 0 .7 9 ( 2 0 .0 0 ) 1 .0 1 ( 2 5 .6 5 4 ) Z Y 1.15 (3.70)

0.162 Min

(4.11 Min) 0.06 ±0.0039 (1.50 ±0.1) Detail Z ( 2 .2 5 M in ) Detail Y 0.160 ±0.0039 (4.00 ±0.1) ( Back view ) ( Front view ) 0.008 ±0.006 (0.200 ±0.150 )