M464S1724DTS-C1H

M464S1724DTS SAMSUNG | Alldatasheet

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Rev. 0.1 Sept. 2001 PC133/PC100 SODIMM The Samsung M464S1724DTS is a 16M bit x 64 Synchronous Dynamic RAM high density memory module. The Samsung M464S1724DTS consists of eight CMOS 8M x 16 bit with 4banks Synchronous DRAMs in TSOP-II 400mil package and a 2K EEPROM in 8-pin TSSOP package on a 144-pin glass-epoxy substrate. Three 0.1uF decoupling capacitors are mounted on the printed circuit board in parallel for each SDRAM. The M464S1724DTS is a Small Outline Dual In-line Memory Module and is intended for mounting into 144-pin edge connector sock- ets. Synchronous design allows precise cycle control with the use of system clock. I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable latencies allows the same device to be useful for a variety of high bandwidth, high performance memory system applications.

• Performance range
• Burst mode operation
• Auto & self refresh capability (4096 Cycles/64ms)
• LVTTL compatible inputs and outputs
• Single 3.3V ± 0.3V power supply
• MRS cycle with address key programs Latency (Access from column address) Burst length (1, 2, 4, 8 & Full page) Data scramble (Sequential & Interleave)
• All inputs are sampled at the positive going edge of the system clock
• Serial presence detect with EEPROM
• PCB : Height (1,250mil) , double sided component Part No. Max Freq. (Speed) M464S1724DTS-L7C/C7C 133MHz (7.5ns @ CL=2) M464S1724DTS-L7A/C7A 133MHz (7.5ns @ CL=3) M464S1724DTS-L1H/C1H 100MHz (10ns @ CL=2) M464S1724DTS-L1L/C1L 100MHz (10ns @ CL=3) FEATUREGENERAL DESCRIPTION M464S1724DTS SDRAM SODIMM 16Mx64 SDRAM SODIMM based on 8Mx16,4Banks,4K Refresh,3.3V Synchronous DRAMs with SPD PIN NAMES * These pins are not used in this module. ** These pins should be NC in the system which does not support SPD. Pin Name Function A0 ~ A11 Address input (Multiplexed) BA0 ~ BA1 Select bank DQ0 ~ DQ63 Data input/output CLK0 ~ CLK1 Clock input CKE0 ~ CKE1 Clock enable input CS0 ~ CS1 Chip select input RAS Row address strobe CAS Column address strobe WE Write enable DQM0 ~ 7 DQM VDD Power supply (3.3V) VSS Ground SDA Serial data I/O SCL Serial clock DU Don ′t use NC No connection PIN CONFIGURATIONS (Front side/back side) Pin Front Pin Back Pin Front Pin Back Pin Front Pin Back VSS DQ0 DQ1 DQ2 DQ3 VDD DQ4 DQ5 DQ6 DQ7 VSS DQM0 DQM1 VDD VSS DQ8 DQ9 DQ10 DQ11 VDD DQ12 DQ13 VSS DQ32 DQ33 DQ34 DQ35 VDD DQ36 DQ37 DQ38 DQ39 VSS DQM4 DQM5 VDD VSS DQ40 DQ41 DQ42 DQ43 VDD DQ44 DQ45 DQ14 DQ15 VSS NC NC CLK0 VDD RAS WE CS0 CS1 DU VSS NC NC VDD DQ16 DQ17 DQ18 DQ19 VSS DQ20 DQ46 DQ47 VSS NC NC CKE0 VDD CAS CKE1 *A12 *A13 CLK1 VSS NC NC VDD DQ48 DQ49 DQ50 DQ51 VSS DQ52 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 DQ21 DQ22 DQ23 VDD VSS A10/AP VDD DQM2 DQM3 VSS DQ24 DQ25 DQ26 DQ27 VDD DQ28 DQ29 DQ30 DQ31 VSS SDA VDD 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 DQ53 DQ54 DQ55 VDD BA0 VSS BA1 A11 VDD DQM6 DQM7 VSS DQ56 DQ57 DQ58 DQ59 VDD DQ60 DQ61 DQ62 DQ63 VSS SCL VDD * SAMSUNG ELECTRONICS CO., Ltd. reserves the right to change products and specifications without notice. Voltage Key

Rev. 0.1 Sept. 2001 PC133/PC100 SODIMM PIN CONFIGURATION DESCRIPTION Pin Name Input Function CLK System clock Active on the positive going edge to sample all inputs. CS Chip select Disables or enables device operation by masking or enabling all inputs except CLK, CKE and DQM CKE Clock enable Masks system clock to freeze operation from the next clock cycle. CKE should be enabled at least one cycle prior to new command. Disable input buffers for power down in standby. CKE should be enabled 1CLK+t SS prior to valid command. A0 ~ A11 Address Row/column addresses are multiplexed on the same pins. Row address : RA0 ~ RA11, Column address : CA0 ~ CA8 BA0 ~ BA1 Bank select address Selects bank to be activated during row address latch time. Selects bank for read/write during column address latch time. RAS Row address strobe Latches row addresses on the positive going edge of the CLK with RAS low. Enables row access & precharge. CAS Column address strobe Latches column addresses on the positive going edge of the CLK with CAS low. Enables column access. WE Write enable Enables write operation and row precharge. Latches data in starting from CAS , WE active. DQM0 ~ 7 Data input/output mask Makes data output Hi-Z, t SHZ after the clock and masks the output. Blocks data input when DQM active. (Byte masking) DQ0 ~ 63 Data input/output Data inputs/outputs are multiplexed on the same pins. VDD /VSS Power supply/ground Power and ground for the input buffers and the core logic.

Rev. 0.1 Sept. 2001 PC133/PC100 SODIMM FUNCTIONAL BLOCK DIAGRAM VDD Vss Three 0.1 uF X7R 0603 Capacitors per each SDRAM To all SDRAMs A0 ~ A11, BA0 & 1 CKE0 RAS CAS WE SDRAM U0 ~ U7 SDRAM U0 ~ U7 SDRAM U0 ~ U7 SDRAM U0 ~ U7 SDRAM U0 ~ U3 DQM4 CS0 DQM0 DQM1 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 LDQM CS UDQM DQM5 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 LDQM CS UDQM DQM6DQM2 DQM3 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 LDQM CS UDQM DQM7 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 LDQM CS UDQM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 LDQM CS UDQM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 LDQM CS UDQM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 LDQM CS UDQM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 LDQM CS UDQM CS1 CKE1 SDRAM U4 ~ U7 U0/U4 U1/U5 CLK0/1 U2/U6 U3/U7 DQn Every DQ pin of SDRAM 10Ω Use a zero ohm jumper to isolate A12 from the SDRAM pins in non-256Mbit designs.Note : Serial PD SDASCL SA1SA2SA0 WP 47KΩ

Rev. 0.1 Sept. 2001 PC133/PC100 SODIMM ABSOLUTE MAXIMUM RATINGS Parameter Symbol Value Unit Voltage on any pin relative to Vss VIN, VOUT -1.0 ~ 4.6 V Voltage on V DD supply relative to Vss VDD, VDDQ -1.0 ~ 4.6 V Storage temperature TSTG -55 ~ +150 °C Power dissipation PD 8 W Short circuit current IOS 50 mA Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability. Note : DC OPERATING CONDITIONS AND CHARACTERISTICS Recommended operating conditions (Voltage referenced to V SS = 0V, T A = 0 to 70 °C) Parameter Symbol Min Typ Max Unit Note Supply voltage VDD 3.0 3.3 3.6 V Input high voltage VIH 2.0 3.0 VDDQ +0.3 V 1 Input low voltage VIL -0.3 0 0.8 V 2 Output high voltage VOH 2.4 - - V IOH = -2mA Output low voltage VOL - - 0.4 V IOL = 2mA Input leakage current ILI -10 - 10 uA 3 CAPACITANCE (VDD = 3.3V, T A = 23 °C, f = 1MHz, V REF = 1.4V ± 200 mV) Parameter Symbol Min Max Unit Input capacitance (A 0 ~ A 11, BA0 ~ BA1) Input capacitance ( RAS , CAS , WE) Input capacitance (CKE0 ~ CKE1) Input capacitance (CLK0 ~ CLK1) Input capacitance ( CS0 ~ CS1 ) Input capacitance (DQM0 ~ DQM7) Data input/output capacitance (DQ0 ~ DQ63) CIN1 CIN2 CIN3 CIN4 CIN5 CIN6 COUT pF pF pF pF pF pF pF 1. VIH (max) = 5.6V AC.The overshoot voltage duration is ≤ 3ns. 2. VIL (min) = -2.0V AC. The undershoot voltage duration is ≤ 3ns. 3. Any input 0V ≤ VIN ≤ VDDQ . Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs. Notes :

Rev. 0.1 Sept. 2001 PC133/PC100 SODIMM DC CHARACTERISTICS (Recommended operating condition unless otherwise noted, T A = 0 to 70 °C) Parameter Sym- bol Test Condition Version Unit Note -7C -7A -1H -1L Operating current (One bank active) ICC1 Burst length = 1 tRC ≥ tRC(min) IO = 0 mA 560 520 520 520 mA 1 Precharge standby current in power-down mode ICC2P CKE ≤ VIL(max), t CC = 10ns 16 mA ICC2PS CKE & CLK ≤ VIL(max), t CC =∞ 16 Precharge standby current in non power-down mode ICC2N CKE ≥ VIH(min), CS ≥ VIH(min), t CC = 10ns Input signals are changed one time during 20ns 160 mA ICC2NS CKE ≥ VIH(min), CLK ≤ VIL(max), t CC =∞ Input signals are stable 80 Active standby current in power-down mode ICC3P CKE ≤ VIL(max), t CC = 10ns 40 mA ICC3PS CKE & CLK ≤ VIL(max), t CC =∞ 40 Active standby current in non power-down mode (One bank active) ICC3N CKE ≥ VIH(min), CS ≥ VIH(min), t CC = 10ns Input signals are changed one time during 20ns 240 mA ICC3NS CKE ≥ VIH(min), CLK ≤ VIL(max), t CC =∞ Input signals are stable 200 mA Operating current (Burst mode) ICC4 IO = 0 mA Page burst 4Banks activated tCCD = 2CLKs 680 680 640 640 mA 1 Refresh current ICC5 tRC ≥ tRC(min) 1000 920 880 880 mA 2 Self refresh current ICC6 CKE ≤ 0.2V C 16 mA L 6.4 mA 1. Measured with outputs open. 2. Refresh period is 64ms. 3. Unless otherwise noted, input swing level is CMOS(V IH/VIL=VDDQ /VSSQ) Notes :

Rev. 0.1 Sept. 2001 PC133/PC100 SODIMM 3.3V 1200 Ω 870Ω Output 50pF VOH (DC) = 2.4V, I OH = -2mA VOL (DC) = 0.4V, I OL = 2mA Vtt = 1.4V 50Ω Output 50pF Z0 = 50 Ω (Fig. 2) AC output load circuit (Fig. 1) DC output load circuit AC OPERATING TEST CONDITIONS (VDD = 3.3V ± 0.3V , TA = 0 to 70 °C) Parameter Value Unit AC input levels (Vih/Vil) 2.4/0.4 V Input timing measurement reference level 1.4 V Input rise and fall time tr/tf = 1/1 ns Output timing measurement reference level 1.4 V Output load condition See Fig. 2 OPERATING AC PARAMETER Notes : (AC operating conditions unless otherwise noted) Parameter Symbol Version Unit Note - 7C - 7A - 1H -1L Row active to row active delay tRRD(min) 15 15 20 20 ns 1 RAS to CAS delay tRCD(min) 15 20 20 20 ns 1 Row precharge time tRP(min) 15 20 20 20 ns 1 Row active time tRAS(min) 45 45 50 50 ns 1 tRAS(max) 100 us Row cycle time tRC(min) 60 65 70 70 ns 1 Last data in to row precharge tRDL(min) 2 CLK 2,5 Last data in to Active delay tDAL(min) 2 CLK + tRP - 5 Last data in to new col. address delay tCDL(min) 1 CLK 2 Last data in to burst stop tBDL(min) 1 CLK 2 Col. address to col. address delay tCCD(min) 1 CLK 3 Number of valid output data CAS latency=3 2 ea 4 CAS latency=2 1 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then rounding off to the next higher integer. 2. Minimum delay is required to complete write. 3. All parts allow every cycle column address change. 4. In case of row precharge interrupt, auto precharge and read burst stop. 5. In 100MHz and below 100MHz operating conditions, tRDL=1CLK and tDAL=1CLK + 20ns is also supported. SAMSUNG recommends tRDL=2CLK and tDAL=2CLK + tRP.

Rev. 0.1 Sept. 2001 PC133/PC100 SODIMM 1. Parameters depend on programmed CAS latency. 2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter. 3. Assumed input rise and fall time (tr & tf) = 1ns. If tr & tf is longer than 1ns, transient time compensation should be considered, i.e., [(tr + tf)/2-1]ns should be added to the parameter. Notes : AC CHARACTERISTICS (AC operating conditions unless otherwise noted) Parameter Symbol - 7C - 7A - 1H - 1L Unit Note Min Max Min Max Min Max Min Max CLK cycle time CAS latency=3 tCC 7.5 1000 7.5 1000 1000 1000 ns 1 CAS latency=2 7.5 10 10 12 CLK to valid output delay CAS latency=3 tSAC 5.4 5.4 6 6 ns 1,2 CAS latency=2 5.4 6 6 7 Output data hold time CAS latency=3 tOH 3 3 3 3 ns 2 CAS latency=2 3 3 3 3 CLK high pulse width tCH 2.5 2.5 3 3 ns 3 CLK low pulse width tCL 2.5 2.5 3 3 ns 3 Input setup time tSS 1.5 1.5 2 2 ns 3 Input hold time tSH 0.8 0.8 1 1 ns 3 CLK to output in Low-Z tSLZ 1 1 1 1 ns 2 CLK to output in Hi-Z CAS latency=3 tSHZ 5.4 5.4 6 6 ns CAS latency=2 5.4 6 6 7 REFER TO THE INDIVIDUAL COMPONENET, NOT THE WHOLE MODULE.

Rev. 0.1 Sept. 2001 PC133/PC100 SODIMM SIMPLIFIED TRUTH TABLE (V=Valid, X=Don ′t care, H=Logic high, L=Logic low) Command CKEn-1 CKEn CS RAS CAS WE DQM BA0,1 A10/AP A11, A9 ~ A0 Note Register Mode register set H X L L L L X OP code 1,2 Refresh Auto refresh H H L L L H X X Self refresh Entry L 3 Exit L H L H H H X X H X X X 3 Bank active & row addr. H X L L H H X V Row address Read & column address Auto precharge disable H X L H L H X V L Column address (A0 ~ A8) Auto precharge enable H 4,5 Write & column address Auto precharge disable H X L H L L X V L Column address (A0 ~ A8) Auto precharge enable H 4,5 Burst stop H X L H H L X X 6 Precharge Bank selection H X L L H L X V L X All banks X H Clock suspend or active power down Entry H L H X X X X XL V V V Exit L H X X X X X Precharge power down mode Entry H L H X X X X X L H H H Exit L H H X X X X L V V V DQM H V X 7 No operation command H X H X X X X X L H H H 1. OP Code : Operand code A0 ~ A 11 & BA 0 ~ BA1 : Program keys. (@ MRS) 2. MRS can be issued only at all banks precharge state. A new command can be issued after 2 clock cycles of MRS. 3. Auto refresh functions are as same as CBR refresh of DRAM. The automatical precharge without row precharge command is meant by "Auto". Auto/self refresh can be issued only at all banks precharge state. 4. BA 0 ~ BA 1 : Bank select addresses. If both BA 0 and BA 1 are "Low" at read, write, row active and precharge, bank A is selected. If both BA 0 is "Low" and BA 1 is "High" at read, write, row active and precharge, bank B is selected. If both BA 0 is "High" and BA 1 is "Low" at read, write, row active and precharge, bank C is selected. If both BA 0 and BA 1 are "High" at read, write, row active and precharge, bank D is selected. If A 10/AP is "High" at row precharge, BA 0 and BA 1 is ignored and all banks are selected. 5. During burst read or write with auto precharge, new read/write command can not be issued. Another bank read/write command can be issued after the end of burst. New row active of the associated bank can be issued at t RP after the end of burst. 6. Burst stop command is valid at every burst length. 7. DQM sampled at positive going edge of a CLK and masks the data-in at the very CLK (Write DQM latency is 0), but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2) Notes : X

Rev. 0.1 Sept. 2001 PC133/PC100 SODIMM Tolerances : ±.006(.15) unless otherwise specified The used device is 8Mx16 SDRAM, TSOP SDRAM Part No. : K4S281632D PACKAGE DIMENSIONS 2.66 2.50 Units : Inches (Millimeters) 2-R 0.078 Min (2.00 Min) 0.18 (4.60) 0.91 (23.20) 1.29 (32.80) 0.24 (6.0) 0.13 0.79 (20.00) (3.30) (63.60) (67.56) Detail Z 0.16 ± 0.0039 (4.00 ± 0.10) 0.06 ± 0.0039 (1.50 ± 0.1) 2-φ 0.07 (1.80) 1.25 (31.75) 0.16 ± 0.039 (4.00 ± 0.10) 0.083 (2.10) 0.10 (2.50) Z Y 0.15 (3.70)

0.150 Max

0.04 ± 0.0039 (1.00 ± 0.10)

0.125 Min

(3.20 Min) (3.80 Max)

0.157 Min

(4.00 Min) 1 59 61 143 2 60 62 144

0.03 TYP

0.024 ± 0.001 0.008 ±0.006 (0.200 ±0.150) (0.600 ± 0.050) (0.80 TYP )

0.100 Min

(2.540 Min) Detail Y

Rev. 0.1 Sept. 2001 PC133/PC100 SODIMM M464S1724DTS-C7C/L7C/C7A/L7A/C1H/L1H/C1L/L1L Byte # Function Described Function Supported Hex value Note -7C -7A -1H -1L -7C -7A -1H -1L 0 # of bytes written into serial memory at module manufacturer 128bytes 80h

1 Total # of bytes of SPD memory device 256bytes (2K-bit) 08h

2 Fundamental memory type SDRAM 04h

3 # of row address on this assembly 12 0Ch 1 4 # of column address on this assembly 9 09h 1 5 # of module Rows on this assembly 2 row 02h

6 Data width of this assembly 64 bits 40h

8 Voltage interface standard of this assembly LVTTL 01h

9 SDRAM cycle time @CAS latency of 3 7.5ns 7.5ns 10ns 10ns 75h 75h A0h A0h 2 10 SDRAM access time from clock @CAS latency of 3 5.4ns 5.4ns 6ns 6ns 54h 54h 60h 60h 2

11 DIMM configuraion type Non parity 00h

12 Refresh rate & type 15.625us, support self refresh 80h

13 Primary SDRAM width x16 10h

14 Error checking SDRAM width None 00h

15 Minimum clock delay for back-to-back random column address tCCD = 1CLK 01h

16 SDRAM device attributes : Burst lengths supported 1, 2, 4, 8 & full page 8Fh

17 SDRAM device attributes : # of banks on SDRAM device 4 banks 04h

18 SDRAM device attributes : CAS latency 2 & 3 2 & 3 2 & 3 2 & 3 06h 06h 06h 06h

19 SDRAM device attributes : CS latency 0 CLK 01h

20 SDRAM device attributes : Write latency 0 CLK 01h

21 SDRAM module attributes Non-buffered, non-registered

& redundant addressing 00h

22 SDRAM device attributes : General

+/- 10% voltage tolerance, Burst Read Single bit Write precharge all, auto precharge 0Eh 23 SDRAM cycle time @CAS latency of 2 7.5ns 10ns 10ns 12ns 75h A0h A0h C0h 2 24 SDRAM access time from clock @CAS latency of 2 5.4ns 6ns 6ns 7ns 54h 60h 60h 70h 2

25 SDRAM cycle time @CAS latency of 1 - - - - 00h 00h 00h 00h

26 SDRAM access time from clock @CAS latency of 1 - - - - 00h 00h 00h 00h

27 Minimum row precharge time (=t RP) 15ns 20ns 20ns 20ns 0Fh 14h 14h 14h

28 Minimum row active to row active delay (t RRD) 15ns 15ns 20ns 20ns 0Fh 0Fh 14h 14h

29 Minimum RAS to CAS delay (=t RCD) 15ns 20ns 20ns 20ns 0Fh 14h 14h 14h

30 Minimum activate precharge time (=t RAS ) 45ns 45ns 50ns 50ns 2Dh 2Dh 32h 32h

31 Module Row density 2 row of 64MB 10h

32 Command and address signal input setup time 1.5ns 1.5ns 2ns 2ns 15h 15h 20h 20h 33 Command and address signal input hold time 0.8ns 0.8ns 1ns 1ns 08h 08h 10h 10h 34 Data signal input setup time 1.5ns 1.5ns 2ns 2ns 15h 15h 20h 20h

• Organization : 8Mx64
• Composition : 8Mx16 * 8
• Used component part # : K4S281632D-TC7C/TL7C/TC75/TL75/TC1H/TL1H/TC1L/TL1L
• # of rows in module : 2 Row
• # of banks in component : 4 banks
• Feature : 1,250mil height & double sided component
• Refresh : 4K/64ms
• Contents ;

Rev. 0.1 Sept. 2001 PC133/PC100 SODIMM Byte # Function Described Function Supported Hex value Note -7C -7A -1H -1L -7C -7A -1H -1L 35 Data signal input hold time 0.8ns 0.8ns 10ns 10ns 08h 08h 10h 10h 36~61 Superset information (maybe used in future) - 00h 62 SPD data revision code Intel Rev 1.2B 12h

63 Checksum for bytes 0 ~ 62 - 66h A7h 0Eh 3Eh

64 Manufacturer JEDEC ID code Samsung CEh

72 Manufacturing location Onyang Korea 01h

73 Manufacturer part # (Memory module) M 4Dh

74 Manufacturer part # (DIMM Configuration) 4 34h

75 Manufacturer part # (Data bits) Blank 20h

78 Manufacturer part # (Mode & operating voltage) S 53h

79 Manufacturer part # (Module depth) 1 31h

81 Manufacturer part # (Refresh, #of banks in Comp. & Interface) 2 32h

82 Manufacturer part # (Composition component) 4 34h

83 Manufacturer part # (Component revision) D 44h

84 Manufacturer part # (Package type) T 54h

85 Manufacturer part # (PCB revision & type) S 53h

86 Manufacturer part # (Hyphen) " - " 2Dh

87 Manufacturer part # (Power) L / C 4Ch / 43h

88 Manufacturer part # (Minimum cycle time) 7 7 1 1 37h 37h 31h 31h

89 Manufacturer part # (Minimum cycle time) C A H L 43h 41h 48h 4Ch

90 Manufacturer part # (TBD) Blank 20h

91 Manufacturer revision code (For PCB) S 53h

93 Manufacturing date (Year) - - 3

94 Manufacturing date (Week) - - 3

95~98 Assembly serial # - - 4 99~125 Manufacturer specific data (may be used in future) Undefined -

126 System frequency for 100MHz 100MHz 64h

127 PC100 specification details Detailed PC100 Information CFh CFh CFh CDh

128+ Unused storage locations Undefined - 1. The row select address is excluded in counting the total # of addresses. 2. This value is based on the component specification. 3. These bytes are programmed by code of Date Week & Date Year with BCD format. 4. These bytes are programmed by Samsung ′s own Assembly Serial # system. All modules may have different unique serial #. Note :