M391T2953CZ0-CE7

M378T3354CZ3 SAMSUNG | Alldatasheet

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Technical content

Rev. 1.2 Aug. 2005 256MB, 512MB, 1GB Unbuffered DIMMs DDR2 SDRAM DDR2 Unbuffered SDRAM MODULE 240pin Unbuffered Module based on 512Mb C-die 64/72-bit Non-ECC/ECC * Samsung Electronics reserves the right to change products or specification without notice. INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL INFORMATION IN THIS DOCUMENT IS PROVIDED ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND. 1. For updates or additional information about Samsung products, contact your nearest Samsung office. 2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar applications where Product failure couldresult in loss of life or personal or physical harm, or any military or defense application, or any governmental procurement to which special terms or provisions may apply.

Rev. 1.2 Aug. 2005 256MB, 512MB, 1GB Unbuffered DIMMs DDR2 SDRAM DDR2 Unbuffered DIMM Ordering Information Note: “Z” of Part number(11th digit) stand for Lead-free products. Note: “3” of Part number(12th digit) stand for Dummy Pad PCB products. Part Number Density Organization Component Composition Number of Rank Height x64 Non ECC M378T3354CZ3-CE7/E6/D5/CC 256MB 32Mx64 32Mx16(K4T51163QC)*4 1 30mm M378T3354CZ0-CE7/E6/D5/CC 256MB 32Mx64 32Mx16(K4T51163QC)*4 1 30mm M378T6553CZ3-CE7/E6/D5/CC 512MB 64Mx64 64Mx8(K4T51083QC)*8 1 30mm M378T6553CZ0-CE7/E6/D5/CC 512MB 64Mx64 64Mx8(K4T51083QC)*8 1 30mm M378T2953CZ3-CE7/E6/D5/CC 1GB 128Mx64 64Mx8(K4T51083QC)*16 2 30mm M378T2953CZ0-CE7/E6/D5/CC 1GB 128Mx64 64Mx8(K4T51083QC)*16 2 30mm x72 ECC M391T6553CZ3-CE7/E6/D5/CC 512MB 64Mx72 64Mx8(K4T51083QC)*9 1 30mm M391T6553CZ0-CE7/E6/D5/CC 512MB 64Mx72 64Mx8(K4T51083QC)*9 1 30mm M391T2953CZ3-CE7/E6/D5/CC 1GB 128Mx72 64Mx8(K4T51083QC)*18 2 30mm M391T2953CZ0-CE7/E6/D5/CC 1GB 128Mx72 64Mx8(K4T51083QC)*18 2 30mm

Features

• Performance range
• JEDEC standard 1.8V ± 0.1V Power Supply
• V DDQ = 1.8V ± 0.1V
• 200 MHz f CK for 400Mb/sec/pin, 267MHz fCK for 533Mb/sec/pin, 333MHz fCK for 667Mb/sec/pin, 400MHz fCK for 800Mb/sec/pin
• 4 Banks
• Posted CAS
• Programmable CAS Latency: 3, 4, 5
• Programmable Additive Latency: 0, 1 , 2 , 3 and 4
• Write Latency(WL) = Read Latency(RL) -1
• Burst Length: 4 , 8(In terleave/nibble sequential)
• Programmable Sequential / Interleave Burst Mode
• Bi-directional Differential Data-Strobe (S ingle-ended data-strobe is an optional feature)
• Off-Chip Driver(OCD) Impedance Adjustment
• On Die Termination with selectable values(50/75/150 ohms or disable)
• PASR(Partial Array Self Refresh)
• Average Refresh Period 7.8us at lower than a T CASE 85°C, 3.9us at 85°C < TCASE < 95 °C - support High Temperature Self-Refresh rate enable feature
• Package: 60ball FBGA - 64Mx8 , 84ball FBGA - 32Mx16
• All of Lead-free products are compliant for RoHS Note: For detailed DDR2 SDRAM operation, please refer to Samsung’s Device operation & Timing diagram. E7 (DDR2-800) E6 (DDR2-667) D5 (DDR2-533) CC (DDR2-400) Unit Speed@CL3 400 400 400 400 Mbps Speed@CL4 533 533 533 400 Mbps Speed@CL5 800 667 533 -M b p s CL-tRCD-tRP 5-5-5 5-5-5 4-4-4 3-3-3 CK Address Configuration Organization Row Address Column Address Bank Address Auto Precharge 64Mx8(512Mb) based Module A0-A13 A0-A9 BA0-BA1 A10 32Mx16(512Mb) based Module A0-A12 A0-A9 BA0-BA1 A10

Rev. 1.2 Aug. 2005 256MB, 512MB, 1GB Unbuffered DIMMs DDR2 SDRAM x64 DIMM Pin Configurations (Front side/Back side) NC = No Connect, RFU = Reserved for Future Use 1. Pin196(A13) is used for x4/x8 base Unbuffered DIMM. 2. The TEST pin is reserved for bus analysis tools and is not connected on standard memory module products (DIMMs.) Pin Front Pin Back Pin Front Pin Back Pin Front Pin Back Pin Front Pin Back

1 VREF 121 VSS 31 DQ19 151 VSS 61 A4 181 VDDQ 91 VSS 211 DM5

2 VSS 122 DQ4 32 VSS 152 DQ28 62 VDDQ 182 A3 92 DQS 5 212 NC

3 DQ0 123 DQ5 33 DQ24 153 DQ29 63 A2 183 A1 93 DQS5 213 VSS

4 DQ1 124 VSS 34 DQ25 154 VSS 64 VDD 184 VDD 94 VSS 214 DQ46

5 VSS 125 DM0 35 VSS 155 DM3 KEY 95 DQ42 215 DQ47

6D Q S 0 126 NC 36 DQS 3 156 NC 65 VSS 185 CK0 96 DQ43 216 VSS

7 DQS0 127 VSS 37 DQS3 157 VSS 66 VSS 186 CK 09 7 VSS 217 DQ52

8 VSS 128 DQ6 38 VSS 158 DQ30 67 VDD 187 VDD 98 DQ48 218 DQ53

9 DQ2 129 DQ7 39 DQ26 159 DQ31 68 NC 188 A0 99 DQ49 219 VSS

10 DQ3 130 VSS 40 DQ27 160 VSS 69 VDD 189 VDD 100 VSS 220 CK2

11 VSS 131 DQ12 41 VSS 161 NC 70 A10/AP 190 BA1 101 SA2 221 CK 2

12 DQ8 132 DQ13 42 NC 162 NC 71 BA0 191 VDDQ 102 NC, TEST2 222 VSS

13 DQ9 133 VSS 43 NC 163 VSS 72 VDDQ 192 RAS 103 VSS 223 DM6

14 VSS 134 DM1 44 VSS 164 NC 73 WE 193 S 0 104 DQS 6 224 NC

15 DQS 1 135 NC 45 NC 165 NC 74 CAS 194 VDDQ 105 DQS6 225 VSS

16 DQS1 136 VSS 46 NC 166 VSS 75 VDDQ 195 ODT0 106 VSS 226 DQ54

17 VSS 137 CK1 47 VSS 167 NC 76 S 11 9 6 A131 107 DQ50 227 DQ55

18 NC 138 CK 1 48 NC 168 NC 77 ODT1 197 VDD 108 DQ51 228 VSS

19 NC 139 VSS 49 NC 169 VSS 78 VDDQ 198 VSS 109 VSS 229 DQ60

20 VSS 140 DQ14 50 VSS 170 VDDQ 79 VSS 199 DQ36 110 DQ56 230 DQ61

21 DQ10 141 DQ15 51 VDDQ 171 CKE1 80 DQ32 200 DQ37 111 DQ57 231 VSS

22 DQ11 142 VSS 52 CKE0 172 VDD 81 DQ33 201 VSS 112 VSS 232 DM7

23 VSS 143 DQ20 53 VDD 173 NC 82 VSS 202 DM4 113 DQS 7 233 NC

24 DQ16 144 DQ21 54 NC 174 NC 83 DQS 42 0 3 N C 1 1 4D Q S 72 3 4 VSS

25 DQ17 145 VSS 55 NC 175 VDDQ 84 DQS4 204 VSS 115 VSS 235 DQ62

26 VSS 146 DM2 56 VDDQ 176 A12 85 VSS 205 DQ38 116 DQ58 236 DQ63

27 DQS 2 147 NC 57 A11 177 A9 86 DQ34 206 DQ39 117 DQ59 237 VSS

28 DQS2 148 VSS 58 A7 178 VDD 87 DQ35 207 VSS 118 VSS 238 VDDSPD

29 VSS 149 DQ22 59 VDD 179 A8 88 VSS 208 DQ44 119 SDA 239 SA0

30 DQ18 150 DQ23 60 A5 180 A6 89 DQ40 209 DQ45 120 SCL 240 SA1

90 DQ41 210 VSS

Rev. 1.2 Aug. 2005 256MB, 512MB, 1GB Unbuffered DIMMs DDR2 SDRAM x72 DIMM Pin Configurations (Front side/Back side) NC = No Connect, RFU = Reserved for Future Use 1. Pin196(A13) is used for x4/x8 base Unbuffered DIMM. 2. The TEST pin is reserved for bus analysis tools and is not connected on standard memory module products (DIMMs.) Pin Front Pin Back Pin Front Pin Back Pin Front Pin Back Pin Front Pin Back

2 VSS 122 DQ4 32 VSS 152 DQ28 62 VDDQ 182 A3 92 DQS 52 1 2 N C

6D Q S 0 126 NC 36 DQS 3 156 NC 65 VSS 185 CK0 96 DQ43 216 VSS

11 VSS 131 DQ12 41 VSS 161 CB4 70 A10/AP 190 BA1 101 SA2 221 CK 2

12 DQ8 132 DQ13 42 CB0 162 CB5 71 BA0 191 VDDQ 102 NC, TEST2 222 VSS

13 DQ9 133 VSS 43 CB1 163 VSS 72 VDDQ 192 RAS 103 VSS 223 DM6

14 VSS 134 DM1 44 VSS 164 DM8 73 WE 193 S 01 0 4 D Q S 62 2 4 N C

15 DQS 1 135 NC 45 DQS 8 165 NC 74 CAS 194 VDDQ 1 0 5D Q S 62 2 5 VSS

16 DQS1 136 VSS 46 DQS8 166 VSS 75 VDDQ 195 ODT0 106 VSS 226 DQ54

17 VSS 137 CK1 47 VSS 167 CB6 76 S 1 196 A13 107 DQ50 227 DQ55

18 NC 138 CK 14 8C B 2 1 6 8 C B 77 7 O D T 1 1 9 7 VDD 1 0 8D Q 5 12 2 8 VSS

19 NC 139 VSS 49 CB3 169 VSS 78 VDDQ 198 VSS 109 VSS 229 DQ60

23 VSS 143 DQ20 53 VDD 173 NC 82 VSS 202 DM4 113 DQS 72 3 3 NC

• The VDD and VDDQ pins are tied to the single power-plane on PCB. Pin Name Description Pin Name Description A0-A13 DDR2 SDRAM address bus CK0, CK1, CK2 DDR2 SDRAM clocks (positive line of differential pair) BA0, BA1 DDR2 SDRAM bank select CK 0, CK1, CK2 DDR2 SDRAM clocks (negative line of differential pair) RAS DDR2 SDRAM row address strobe SCL I 2C serial bus clock for EEPROM CAS DDR2 SDRAM column address strobe SDA I 2C serial bus data line for EEPROM WE DDR2 SDRAM wirte enable SA0-SA2 I 2C serial address select for EEPROM S0, S1 DIMM Rank Select Lines V DD* DDR2 SDRAM core power supply CKE0,CKE1 DDR2 SDRAM clock enable lines V DDQ* DDR2 SDRAM I/O Driver power supply ODT0, ODT1 On-die termination control lines V REF DDR2 SDRAM I/O reference supply DQ0 - DQ63 DIMM memory data bus V SS Power supply return (ground) CB0 - CB7 DIMM ECC check bits V DDSPD Serial EEPROM positive power supply DQS0 - DQS8 DDR2 SDRAM data strobes NC Spare Pins(no connect) DM(0-8) DDR2 SDRAM data masks RESET Not used on UDIMM DQS0-DQS8 DDR2 SDRAM differential data strobes TEST Used by memory bus analysis tools (unused on memory DIMMs)

Rev. 1.2 Aug. 2005 256MB, 512MB, 1GB Unbuffered DIMMs DDR2 SDRAM Input/Output Functional Description Symbol Type Function CK0-CK2 CK0-CK2 Input CK and CK are differential clock inputs. All the SDRAM addr/cntl inputs are sampled on the crossing of positive edge of CK and negative edge of CK. Output (read) data is reference to the crossing of CK and CK (Both directions of crossing) CKE0-CKE1 Input Activates the SDRAM CK signal when high and deactivates the CK Signal When low. By deactivating the clocks, CKE low initiates the Powe Down mode, or the Self-Refresh mode S0-S1 Input Enables the associated SDRAM command decoder when low and disables the command decoder when high. When the command decoder is disbled, new command are ignored but previous operations continue. This signal provides for exter- nal rank selection on systems with multiple ranks RAS, CAS, WE Input RAS , CAS, and WE (ALONG WITH CS) define the command being entered. ODT0-ODT1 Input When high, termination resistance is enabled for all DQ, DQ and DM pins, assuming the function is enabled in the Extended Mode Register Set (EMRS). VREF Supply Reference voltage for SSTL 18 inputs. VDDQ Supply Power supply for the DDR II SDRAM output buffers to provide improved noise immunity. For all current DDR2 unbuffered DIMM designs, VDDQ shares the same power plane as VDD pins. BA0-BA1 Input Selects which SDRAM BANK of four is activated. A0-A13 Input During a Bank Activate command cycle, Address input defines the row address (RA0-RA13) During a Read or Write command cycle, Address input defines the colum address, In addition to the column address, AP is used to invoke autoprecharge operation at the end of the burst read or write cycle. If AP is high, autoprecharge is selected and BA0, BA1 defines the bank to be precharged. If AP is low, autoprecharge is disbled. During a precharge command cycle, AP is used in conjunction with BA0, BA1 to control which bank(s) to precharge. If AP is high, all banks will be precharged regardless of the state of BA0, BA1. If AP is low, BA0, BA1are used to define which bank to pre- charge. DQ0-DQ63 CB0-CB7 In/Out Data and Check Bit Input/Output pins. DM0-DM8 Input DM is an input mask signal for write data. Input data is masked when DM is sampled High coincident with that input data during a write access. DM is sampled on both edges of DQS. Although DM pins are input only, the DM loading matches the DQ and DQS loading. V DD,VSS Supply Power and ground for DDR2 SDRAM input buffers, and core logic. VDD and VDDQ pins are tied to V DD/VDDQ planes on these modules. DQS0-DQS8 DQS0-DQS8 In/Out Data strobe for input and output data. For Rawcards using x16 orginized DRAMs DQ0-7 connect to the LDQS pin of the DRAMs and DQ8-17 connect to the UDQS pin of the DRAM SA0-SA2 Input These signals and tied at the system planar to either V SS or VDD to configure the serial SPD EERPOM address range. SDA In/Out This bidirectional pin is used to transfer data into or out of the SPD EEPROM. A resistor must be connected from the SDA bus line to VDD to act as a pullup on the system board. SCL Input This signal is used to clock data into and out of the SPD EEPROM. A resistor may be connected from the SCL bus time to VDD to act as a pullup onthe system board. VDD SPD Supply Power supply for SPD EEPROM. This supply is separate from the V DD/VDDQ power plane. EEPROM supply is operable from 1.7V to 3.6V.

Rev. 1.2 Aug. 2005 256MB, 512MB, 1GB Unbuffered DIMMs DDR2 SDRAM DQS0 DQS0 DM0 DM CS DQS DQS DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQS1 DQS1 DM1 DM CS DQS DQS DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQS2 DQS2 DM2 DM CS DQS DQS DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQS3 DQS3 DM3 DM NU/ CS DQS DQS DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQS4 DQS4 DM4 DM CS DQS DQS DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQS5 DQS5 DM5 DM CS DQS DQS DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQS6 DQS6 DM6 DM CS DQS DQS DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQS7 DQS7 DM7 DM CS DQS DQS DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 Notes : 1. DQ,DM, DQS/DQS resistors : 22 Ohms ± 5%. 2. BAx, Ax, RAS, CAS, WE resistors : 5.1 Ohms ± 5%. Functional Block Diagram: 512MB, 64Mx64 Module(Populated as 1 rank of x8 DDR2 SDRAMs) Serial PD A1 A2 SA0 SA1 SA2 SCL SDAWP *Wire per Clock Loading Table/Wiring Diagrams * Clock Wiring Clock Input DDR2 SDRAMs *CK0/CK0 *CK1/CK1 *CK2/CK2

2 DDR2 SDRAMs

3 DDR2 SDRAMs

A0 - A13 A0-A13 : DDR2 SDRAMs D0 - D7 RAS RAS : DDR2 SDRAMs D0 - D7 CAS CAS : DDR2 SDRAMs D0 - D7 WE WE : DDR2 SDRAMs D0 - D7 CKE0 CKE : DDR2 SDRAMs D0 - D7 BA0 - BA1 BA0-BA1 : DDR2 SDRAMs D0 - D7 ODT0 ODT : DDR2 SDRAMs D0 - D7 M378T6553CZ3 / M378T6553CZ0

Rev. 1.2 Aug. 2005 256MB, 512MB, 1GB Unbuffered DIMMs DDR2 SDRAM DQS0 DQS0 DM0 DM CS DQS DQS DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQS1 DQS1 DM1 DM CS DQS DQS DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQS2 DQS2 DM2 DM CS DQS DQS DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQS3 DQS3 DM3 DM CS DQS DQS DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQS4 DQS4 DM4 DM CS DQS DQS DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQS5 DQS5 DM5 DM CS DQS DQS DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQS6 DQS6 DM6 DM CS DQS DQS DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQS7 DQS7 DM7 DM CS DQS DQS DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 Notes : 1. DQ,DM, DQS/DQS resistors : 22 Ohms ± 5%. 2. BAx, Ax, RAS, CAS, WE resistors : 5.1 Ohms ± 5%. Functional Block Diagram: 512MB, 64Mx72 ECC Module(Populated as 1 rank of x8 DDR2 SDRAMs) Serial PD A1 A2 SA0 SA1 SA2 SCL SDAWP *Wire per Clock Loading Table/Wiring Diagrams * Clock Wiring Clock Input DDR2 SDRAMs *CK0/CK0 *CK1/CK1 *CK2/CK2 A0 - A13 A0-A13 : DDR2 SDRAMs D0 - D8 RAS RAS : DDR2 SDRAMs D0 - D8 CAS CAS : DDR2 SDRAMs D0 - D8 WE WE : DDR2 SDRAMs D0 - D8 CKE0 CKE : DDR2 SDRAMs D0 - D8 BA0 - BA1 BA0-BA1 : DDR2 SDRAMs D0 - D8 ODT0 ODT : DDR2 SDRAMs D0 - D8 M391T6553CZ3 / M391T6553CZ0

Rev. 1.2 Aug. 2005 256MB, 512MB, 1GB Unbuffered DIMMs DDR2 SDRAM DQS0 DQS0 DM0 DM CS DQS DQS DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQS1 DQS1 DM1 DM CS DQS DQS DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQS2 DQS2 DM2 DM CS DQS DQS DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQS3 DQS3 DM3 DM CS DQS DQS DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQS4 DQS4 DM4 DM CS DQS DQS DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQS5 DQS5 DM5 DM CS DQS DQS DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQS6 DQS6 DM6 DM CS DQS DQS DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQS7 DQS7 DM7 DM CS DQS DQS DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 Notes : 1. DQ,DM, DQS/DQS resistors : 22 Ohms ± 5%. 2. BAx, Ax, RAS, CAS, WE resistors : 3 Ohms ± 5%. Functional Block Diagram: 1GB, 128Mx64 Module(Populated as 2 ranks of x8 DDR2 SDRAMs) Serial PD A1 A2 SA0 SA1 SA2 SCL SDAWP *Wire per Clock Loading Table/Wiring Diagrams * Clock Wiring Clock Input DDR2 SDRAMs *CK0/CK0 *CK1/CK1 *CK2/CK2

4 DDR2 SDRAMs

6 DDR2 SDRAMs

A0 - A13 A0-A13 : DDR2 SDRAMs D0 - D15 WE WE : DDR2 SDRAMs D0 - D15 CKE1 CKE : DDR2 SDRAMs D8 - D15 BA0 - BA1 BA0-BA1 : DDR2 SDRAMs D0 - D15 ODT0 ODT : DDR2 SDRAMs D0 - D7 DM CS DQS DQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DM CS DQS DQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DM CS DQS DQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 D10 DM CS DQS DQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 D11 DM CS DQS DQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 D12 DM CS DQS DQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 D13 DM CS DQS DQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 D14 DM CS DQS DQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 D15 CKE0 CKE : DDR2 SDRAMs D0 - D7 RAS RAS : DDR2 SDRAMs D0 - D15 CAS CAS : DDR2 SDRAMs D0 - D15 ODT1 ODT : DDR2 SDRAMs D8 - D15 M378T2953CZ3 / M378T2953CZ0

Rev. 1.2 Aug. 2005 256MB, 512MB, 1GB Unbuffered DIMMs DDR2 SDRAM DQS0 DQS0 DM0 DM CS DQS DQS DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQS1 DQS1 DM1 DM CS DQS DQS DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQS2 DQS2 DM2 DM CS DQS DQS DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQS3 DQS3 DM3 DM CS DQS DQS DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQS4 DQS4 DM4 DM CS DQS DQS DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQS5 DQS5 DM5 DM CS DQS DQS DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQS6 DQS6 DM6 DM CS DQS DQS DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQS7 DQS7 DM7 DM CS DQS DQS DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 Notes : 1. DQ,DM, DQS/DQS resistors : 22 Ohms ± 5%. 2. BAx, Ax, RAS, CAS, WE resistors : 3 Ohms ± 5%. Functional Block Diagram: 1GB, 128Mx72 ECC Module(Populated as 2 ranks of x8 DDR2 SDRAMs) Serial PD A1 A2 SA0 SA1 SA2 SCL SDAWP *Wire per Clock Loading Table/Wiring Diagrams * Clock Wiring Clock Input DDR2 SDRAMs *CK0/CK0 *CK1/CK1 *CK2/CK2 A0 - A13 A0-A13 : DDR2 SDRAMs D0 - D17 WE WE : DDR2 SDRAMs D0 - D17 CKE1 CKE : DDR2 SDRAMs D9 - D17 BA0 - BA1 BA0-BA1 : DDR2 SDRAMs D0 - D17 ODT0 ODT : DDR2 SDRAMs D0 - D8 DM CS DQS DQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DM CS DQS DQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 D10 DM CS DQS DQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 D11 DM CS DQS DQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 D12 DM CS DQS DQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 D13 DM CS DQS DQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 D14 DM CS DQS DQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 D15 DM CS DQS DQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 D16 CKE0 CKE : DDR2 SDRAMs D0 - D8 RAS RAS : DDR2 SDRAMs D0 - D17 CAS CAS : DDR2 SDRAMs D0 - D17 ODT1 ODT : DDR2 SDRAMs D9 - D17 DQS8 DQS8 DM8 DM CS DQS DQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DM CS DQS DQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 D17 CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7 M391T2953CZ3 / M391T2953CZ0

Rev. 1.2 Aug. 2005 256MB, 512MB, 1GB Unbuffered DIMMs DDR2 SDRAM DQS1 DQS1 DM1 CS DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 Notes : 1. DQ,DM, DQS/DQS resistors : 22 Ohms ± 5%. 4. BAx, Ax, RAS, CAS, WE resistors : 10 Ohms ± 5%. Functional Block Diagram: 256MB, 32Mx64 Module(Populated as 1 rank of x16 DDR2 SDRAMs) Serial PD A1 A2 SA0 SA1 SA2 SCL SDAWP *Wire per Clock Loading Table/Wiring Diagrams * Clock Wiring Clock Input DDR2 SDRAMs *CK0/CK0 *CK1/CK1 *CK2/CK2 NC A0 - A12 A0-A12 : DDR2 SDRAMs D0 - D3 WE WE : DDR2 SDRAMs D0 - D3 BA0 - BA1 BA0-BA1 : DDR2 SDRAMs D0 - D3 ODT0 ODT : DDR2 SDRAMs D0 - D3 CKE0 CKE : DDR2 SDRAMs D0 - D3 RAS RAS : DDR2 SDRAMs D0 - D3 CAS CAS : DDR2 SDRAMs D0 - D3 LDQS LDOS LDM DQS0 DQS0 DM0 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 UDQS UDOS UDM DQS5 DQS5 DM5 CS DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 LDQS LDOS LDM DQS4 DQS4 DM4 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 UDQS UDOS UDM DQS3 DQS3 DM3 CS DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 LDQS LDOS LDM DQS2 DQS2 DM2 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 UDQS UDOS UDM DQS7 DQS7 DM7 CS DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 LDQS LDOS LDM DQS6 DQS6 DM6 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 UDQS UDOS UDM M378T3354CZ3 / M378T3354CZ0

Rev. 1.2 Aug. 2005 256MB, 512MB, 1GB Unbuffered DIMMs DDR2 SDRAM Absolute Maximum DC Ratings Note : 1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stre ss rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this s pecification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. Storage Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, plea se refer to JESD51-2 standard. AC & DC Operating Conditions Recommended DC Operating Conditions (SSTL - 1.8) Note : There is no specific device VDD supply voltage requirement for SSTL-1.8 compliance. However under all conditions VDDQ must be less than or equal to VDD. 1. The value of VREF may be selected by the user to provide optimum noise margin in the system. Typically the value of VREF is expected to be about 0.5 x VDDQ of the transmitting device and VREF is expected to track variations in VDDQ. 2. Peak to peak AC noise on VREF may not exceed +/-2% VREF(DC). 3. VTT of transmitting device must track VREF of receiving device. 4. AC parameters are measured with VDD, VDDQ and VDDL tied together. Symbol Parameter Rating Units Notes VDD Voltage on VDD pin relative to VSS - 1.0 V ~ 2.3 V V 1 VDDQ Voltage on VDDQ pin relative to VSS - 0.5 V ~ 2.3 V V 1 VDDL Voltage on VDDL pin relative to VSS - 0.5 V ~ 2.3 V V 1 VIN, VOUT Voltage on any pin relative to VSS - 0.5 V ~ 2.3 V V 1 TSTG Storage Temperature -55 to +100 °C 1, 2 Symbol Parameter Rating Units Notes Min. Typ. Max. VDD Supply Voltage 1.7 1.8 1.9 V VDDL Supply Voltage for DLL 1.7 1.8 1.9 V 4 VDDQ Supply Voltage for Output 1.7 1.8 1.9 V 4 VREF Input Reference Voltage 0.49*V DDQ 0.50*VDDQ 0.51*VDDQ mV 1,2 VTT Termination Voltage V REF-0.04 V REF VREF+0.04 V 3

Rev. 1.2 Aug. 2005 256MB, 512MB, 1GB Unbuffered DIMMs DDR2 SDRAM Operating Temperature Condition Note : 1. Operating Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JESD51.2 standard. 2. At 85 - 95 °C operation temperature range, doubling refresh commands in frequency to a 32ms period ( tREFI=3.9 us ) is required, and to ent er to self refresh mode at this temperature range, an EMRS command is required to change internal refresh rate. Input DC Logic Level Input AC Logic Level AC Input Test Conditions Notes: 1. Input waveform timing is referenced to the input signal crossing through the V IH/IL(AC) level applied to the device under test. 2. The input signal minimum slew rate is to be maintained over the range from V REF to VIH(AC) min for rising edges and the range from V REF to VIL(AC) max for falling edges as shown in the below figure. 3. AC timings are referenced with input waveforms switching from V IL(AC) to VIH(AC) on the positive transitions and V IH(AC) to VIL(AC) on the negative transitions. Symbol Parameter Rating Units Notes TOPER Operating Temperature 0 to 95 °C 1, 2, 3 Symbol Parameter Min. Max. Units Notes VIH (DC) DC input logic high V REF + 0.125 V DDQ + 0.3 V VIL (DC) DC input logic low - 0.3 V REF - 0.125 V Symbol Parameter DDR2-400, DDR2-533 DDR2-667, DDR2-800 Units Notes Min. Max. Min. Max. VIH (AC) AC input logic high V REF + 0.250 - V REF + 0.200 V VIL (AC) AC input logic low - V REF - 0.250 V REF - 0.200 V Symbol Condition Value Units Notes VREF Input reference voltage 0.5 * V DDQ V1 VSWING(MAX) Input signal maximum peak to peak swing 1.0 V 1 SLEW Input signal minimum slew rate 1.0 V/ns 2, 3 VDDQ VIH(AC) min VIH(DC) min VREF VIL(DC) max VIL(AC) max VSS < AC Input Test Signal Waveform > VSWING(MAX) delta TRdelta TF VREF - VIL(AC) max delta TF Falling Slew = Rising Slew = VIH(AC) min - VREF delta TR

Rev. 1.2 Aug. 2005 256MB, 512MB, 1GB Unbuffered DIMMs DDR2 SDRAM IDD Specification Parameters Definition (IDD values are for full operating range of Voltage and Temperature) Symbol Proposed Conditions Units Notes IDD0 Operating one bank active-precharge current; tCK = tCK(IDD), tRC = tRC(IDD), tRAS = tRASmin(IDD); CKE is HIGH, CS\\ is HIGH between valid commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING mA IDD1 Operating one bank active-read-precharge current; IOUT = 0mA; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRC = tRC (IDD), tRAS = tRASmin(IDD), tRCD = tRCD(IDD); CKE is HIGH, CS\\ is HIGH between valid commands; Address bus inputs are SWITCHING; Data pattern is same as IDD4W mA IDD2P Precharge power-down current; All banks idle; tCK = tCK(IDD); CKE is LOW; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING mA IDD2Q Precharge quiet standby current; All banks idle; tCK = tCK(IDD); CKE is HIGH, CS\\ is HIGH; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING mA IDD2N Precharge standby current; All banks idle; tCK = tCK(IDD); CKE is HIGH, CS\\ is HIGH; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING mA IDD3P Active power-down current; All banks open; tCK = tCK(IDD); CKE is LOW; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING Fast PDN Exit MRS(12) = 0mA mA Slow PDN Exit MRS(12) = 1mA mA IDD3N Active standby current; All banks open; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP = tRP(IDD); CKE is HIGH, CS\\ is HIGH between valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING mA IDD4W Operating burst write current; All banks open, Continuous burst writes; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP = tRP(IDD); CKE is HIGH, CS\\ is HIGH between valid commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING mA IDD4R Operating burst read current; All banks open, Continuous burst reads, IOUT = 0mA; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRAS = tRAS- max(IDD), tRP = tRP(IDD); CKE is HIGH, CS\\ is HIGH between valid commands; Address bus inputs are SWITCH- ING; Data pattern is same as IDD4W mA IDD5B Burst auto refresh current; tCK = tCK(IDD); Refresh command at every tRFC(IDD) interval; CKE is HIGH, CS\\ is HIGH between valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING mA IDD6 Self refresh current; CK and CK\\ at 0V; CKE ≤ 0.2V; Other control and address bus inputs are FLOATING; Data bus inputs are FLOATING Normal mA Low Power mA IDD7 Operating bank interleave read current; All bank interleaving reads, IOUT = 0mA; BL = 4, CL = CL(IDD), AL = tRCD(IDD)-1*tCK(IDD); tCK = tCK(IDD), tRC = tRC(IDD), tRRD = tRRD(IDD), tFAW = tFAW(IDD), tRCD = 1*tCK(IDD); CKE is HIGH, CS\\ is HIGH between valid commands; Address bus inputs are STABLE during DESELECTs; Data pattern is same as IDD4R; Refer to the follow- ing page for detailed timing conditions mA

Rev. 1.2 Aug. 2005 256MB, 512MB, 1GB Unbuffered DIMMs DDR2 SDRAM M378T2953CZ3 / M378T2953CZ0 : 1GB(64Mx8 *16) Module * Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap. Symbol E7(800@CL=5) E6(667@CL=5) D5(533@CL=4) CC(400@CL=3) Unit Notes IDD0 TBD 1,000 920 920 mA IDD1 TBD 1,120 1,040 1,040 mA IDD2P TBD 128 128 128 mA IDD2Q TBD 560 480 480 mA IDD2N TBD 640 560 560 mA IDD3P-F TBD 480 480 480 mA IDD3P-S TBD 192 192 192 mA IDD3N TBD 760 680 680 mA IDD4W TBD 1,440 1,240 1,160 mA IDD4R TBD 1,480 1,280 1,160 mA IDD5B TBD 1,520 1,400 1,400 mA IDD6 TBD 128 128 128 mA IDD7 TBD 2,080 2,040 2,040 mA Operating Current Table(1-1) (TA=0oC, VDD= 1.9V) M378T6553CZ3 / M378T6553CZ0 : 512MB(64Mx8 *8) Module * Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap. Symbol E7(800@CL=5) E6(667@CL=5) D5(533@CL=4) CC(400@CL=3) Unit Notes IDD0 TBD 680 640 640 mA IDD1 TBD 800 760 760 mA IDD2P TBD 64 64 64 mA IDD2Q TBD 280 240 240 mA IDD2N TBD 320 280 280 mA IDD3P-F TBD 240 240 240 mA IDD3P-S TBD 96 96 96 mA IDD3N TBD 440 400 400 mA IDD4W TBD 1,120 960 880 mA IDD4R TBD 1,160 1,000 880 mA IDD5B TBD 1,200 1,120 1,120 mA IDD6 TBD 64 64 64 mA IDD7 TBD 1,760 1,760 1,760 mA

Rev. 1.2 Aug. 2005 256MB, 512MB, 1GB Unbuffered DIMMs DDR2 SDRAM M391T6553CZ3 / M391T6553CZ0 : 512MB(64Mx8 *9) ECC Module * Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap. Symbol E7(800@CL=5) E6(667@CL=5) D5(533@CL=4) CC(400@CL=3) Unit Notes IDD0 TBD 765 720 720 mA IDD1 TBD 900 855 855 mA IDD2P TBD 72 72 72 mA IDD2Q TBD 315 270 270 mA IDD2N TBD 360 315 315 mA IDD3P-F TBD 270 270 270 mA IDD3P-S TBD 108 108 108 mA IDD3N TBD 495 450 450 mA IDD4W TBD 1,260 1,080 990 mA IDD4R TBD 1,305 1,125 990 mA IDD5B TBD 1,350 1,260 1,260 mA IDD6 TBD 72 72 72 mA IDD7 TBD 1,980 1,980 1,980 mA Operating Current Table(1-2) (TA=0oC, VDD= 1.9V) M378T3354CZ3 / M378T3354CZ0 : 256MB(32Mx16 *4) Module * Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap. Symbol E7(800@CL=5) E6(667@CL=5) D5(533@CL=4) CC(400@CL=3) Unit Notes IDD0 TBD 400 380 380 mA IDD1 TBD 460 440 440 mA IDD2P TBD 32 32 32 mA IDD2Q TBD 140 120 120 mA IDD2N TBD 160 140 140 mA IDD3P-F TBD 120 120 120 mA IDD3P-S TBD 48 48 48 mA IDD3N TBD 220 200 200 mA IDD4W TBD 700 620 540 mA IDD4R TBD 720 640 560 mA IDD5B TBD 600 560 560 mA IDD6 TBD 32 32 32 mA IDD7 TBD 1,200 1,200 1,200 mA

Rev. 1.2 Aug. 2005 256MB, 512MB, 1GB Unbuffered DIMMs DDR2 SDRAM M391T2953CZ3 / M391T2953CZ0 : 1GB(64Mx8 *18) ECC Module * Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap. Symbol E7(800@CL=5) E6(667@CL=5) D5(533@CL=4) CC(400@CL=3) Unit Notes IDD0 TBD 1,125 1,035 1,035 mA IDD1 TBD 1,260 1,170 1,170 mA IDD2P TBD 144 144 144 mA IDD2Q TBD 630 540 540 mA IDD2N TBD 720 630 630 mA IDD3P-F TBD 540 540 540 mA IDD3P-S TBD 216 216 216 mA IDD3N TBD 855 765 765 mA IDD4W TBD 1,620 1,395 1,305 mA IDD4R TBD 1,665 1,440 1,305 mA IDD5B TBD 1,710 1,575 1,575 mA IDD6 TBD 144 144 144 mA IDD7 TBD 2,340 2,295 2,295 mA Operating Current Table(1-3) (TA=0oC, VDD= 1.9V) Input/Output Capacitance(VDD=1.8V, VDDQ=1.8V, TA=25oC) Note: DM is internally loaded to match DQ and DQS identically. Parameter Symbol Min Max Min Max Min Max Units Non-ECC M378T6553CZ3 M378T6553CZ0 M378T2953CZ3 M378T2953CZ0 M378T3354CZ3 M378T3354CZ0 Input capacitance, CK and CK CCK0 - 24 - 26 - 22 pF CCK1 - 25 - 28 - 24 CCK2 - 25 28 24 Input capacitance, CKE and CS CI1 - 42 - 42 - 34 Input capacitance, Addr, RAS, CAS, WE CI2 - 42 - 42 - 34 Input/output capacitance, DQ, DM, DQS, DQS CIO(400/533) - 6 - 10 - 6 ECC Symbol M391T6553CZ3 M391T6553CZ0 M391T2953CZ3 M391T2953CZ0 Units Input capacitance, CK and CK CCK0 - 25 - 28 pF CCK1 - 25 - 28 CCK2 25 28 Input capacitance, CKE and CS CI1 - 44 - 44 Input capacitance, Addr, RAS, CAS, WE CI2 - 44 - 44 Input/output capacitance, DQ, DM, DQS, DQS CIO(400/533) - 6 - 10

Rev. 1.2 Aug. 2005 256MB, 512MB, 1GB Unbuffered DIMMs DDR2 SDRAM (0 °C < TOPER < 95 °C; VDDQ = 1.8V + 0.1V; VDD = 1.8V + 0.1V) Refresh Parameters by Device Density Speed Bins and CL, tRCD, tRP, tRC and tRAS for Corresponding Bin Timing Parameters by Speed Grade (Refer to notes for informations related to this table at the bottom) Parameter Symbol 256Mb 512Mb 1Gb 2Gb 4Gb Units Refresh to active/Refresh command time tRFC 75 105 127.5 195 327.5 ns Average periodic refresh interval tREFI Speed DDR2-800(E7) DDR2-667(E6) DDR2-533(D5) DDR2-400(CC) UnitsBin(CL - tRCD - tRP) 5 - 5 - 5 5 - 5 - 5 4 - 4 - 4 3 - 3 - 3 Parameter min max min max min max min max tCK, CL=3 5 8 5 8 5 8 5 8 ns tCK, CL=4 3.75 8 3.75 8 3.75 8 5 8 ns tCK, CL=5 2.5 8 3 8 3.75 8 - - ns tRCD 12.5 - 15 - 15 - 15 - ns tRP 12.5 - 15 - 15 - 15 - ns tRC 51.5 - 54 - 55 - 55 - ns tRAS 39 70000 39 70000 40 70000 40 70000 ns Parameter Symbol DDR2-800 DDR2-667 DDR2-533 DDR2-400 Units Note min max min max min max min max DQ output access time from CK/CK tAC - 400 400 -450 +450 -500 +500 -600 +600 ps DQS output access time from CK/CK tDQSCK - 350 350 -400 +400 -450 +450 -500 +500 ps CK half period tHP min(tCL,t CH) x min(tCL, tCH) x min(tCL, tCH) x min(tCL, tCH) x ps Clock cycle time, CL=x tCK 2500 8000 3000 8000 3750 8000 5000 8000 ps DQ and DM input hold time tDH(base) 125 x 175 x 225 x2 7 5 x ps DQ and DM input setup time tDS(base) 50 x 100 x 100 x1 5 0 x ps Control & Address input pulse width for each input tIPW 0.6 x 0.6 x 0.6 x0 . 6 x tCK DQ and DM input pulse width for each input tDIPW 0.35 x 0.35 x 0.35 x0 . 3 5 x tCK Data-out high-impedance time from CK/CK tHZ x tAC max x tAC max x tAC max x tAC max ps DQS low-impedance time from CK/CK tLZ(DQS) tAC min tAC max tAC min tAC max tAC min tAC max tAC min tAC max ps DQ low-impedance time from CK/CK tLZ(DQ) 2* tAC min tAC max 2*tAC min tAC max 2* tACmin tAC max 2* tACmin tAC max ps DQS-DQ skew for DQS and associated DQ signals tDQSQ x 200 x 240 x3 0 0x3 5 0 ps DQ hold skew factor tQHS x 300 x 340 x4 0 0x4 5 0 ps DQ/DQS output hold time from DQS tQH tHP - tQHS x tHP - tQHS x tHP - tQHS x tHP - tQHS x ps First DQS latching transition to associated clock edge DQS input high pulse width tDQSH 0.35 x 0.35 x 0.35 x 0.35 x tCK DQS input low pulse width tDQSL 0.35 x 0.35 x 0.35 x 0.35 x tCK

Rev. 1.2 Aug. 2005 256MB, 512MB, 1GB Unbuffered DIMMs DDR2 SDRAM Parameter Symbol DDR2-800 DDR2-667 DDR2-533 DDR2-400 Units Note min max min max min max min max DQS falling edge to CK setup time tDSS 0.2 x 0.2 x 0.2 x 0.2 x tCK DQS falling edge hold time from CK tDSH 0.2 x 0.2 x 0.2 x 0.2 x tCK Mode register set command cycle time tMRD 2 x 2 x 2 x 2 x tCK Write preamble tWPRE 0.35 x 0.35 x 0.35 x 0.35 x tCK Address and control input hold time tIH(base) 250 x 275 x3 7 5 x 475 x ps Address and control input setup time tIS(base) 175 x 200 x2 5 0 x 350 x ps Active to active command period for 1KB page size products tRRD 7.5 x 7.5 x7 . 5 x 7.5 x ns Active to active command period for 2KB page size products tRRD 10 x 10 x1 0 x 10 x ns Four Activate Window for 1KB page size products tFAW 35 37.5 37.5 37.5 ns Four Activate Window for 2KB page size products tFAW 45 50 50 50 ns CAS to CAS command delay tCCD 2 x 2 2 2 tCK Write recovery time tWR 15 x 15 x1 5 x 15 x ns Auto precharge write recovery + precharge time tDAL WR+tRP x WR+tRP x WR+tRP x WR+tRP x tCK Internal write to read command delay tWTR 7.5 7.5 x7 . 5 x1 0 x ns Internal read to precharge command delay tRTP 7.5 7.5 7.5 7.5 ns Exit self refresh to a non-read command tXSNR tRFC + 10 tRFC + 10 tRFC + 10 tRFC + 10 ns Exit self refresh to a read command tXSRD 200 x2 0 0 200 200 tCK Exit precharge power down to any non-read command tXP 2 x 2 x 2 x 2 x tCK Exit active power down to read command tXARD 2 x 2 x 2 x 2 x tCK Exit active power down to read command (slow exit, lower power) tXARDS 8 - AL 7 - AL 6 - AL 6 - AL tCK CKE minimum pulse width (high and low pulse width) tCKE 3 3 33 tCK ODT turn-on delay tAOND 2 2 2 2 2 2 2 2 tCK ODT turn-on tAON tAC(min) tAC(max) + 0.7 tAC(min) tAC(max) +0.7 tAC(min) tAC(max) +1 tAC(min) tAC(max) +1 ns ODT turn-on(Power-Down mode) tAONPD tAC(min)+ 2tCK + tAC(max) tAC(min)+ 2tCK+tA C(max)+1 tAC(min)+ 2tCK+tA C(max)+ tAC(min)+ 2tCK+tAC (max)+1 ns ODT turn-off tAOF tAC(min) tAC(max) + 0.6 tAC(min) tAC(max) + 0.6 tAC(min) tAC(max)+ 0.6 tAC(min) tAC(max)+ 0.6 ns ODT turn-off (Power-Down mode) tAOFPD tAC(min)+ 2.5tCK + tAC(max) tAC(min)+ 2.5tCK+ tAC(max) tAC(min)+ 2.5tCK+ tAC(max) tAC(min)+ 2.5tCK+ tAC(max) ns ODT to power down entry latency tANPD 3 3 3 3 tCK ODT power down exit latency tAXPD 8 8 8 8 tCK OCD drive mode output delay tOIT 0 12 0 12 0 12 0 12 ns Minimum time clocks remains ON after CKE asynchronously drops LOW tDelay tIS+tCK +tIH tIS+tCK +tIH tIS+tCK +tIH tIS+tCK +tIH ns

Rev. 1.2 Aug. 2005 256MB, 512MB, 1GB Unbuffered DIMMs DDR2 SDRAM Physical Dimensions: 64Mbx8 based 64Mx64/x72 Module(1 Rank) 131.35 Units : Millimeters 133.35 10.00 1.270 ± 0.10 2.7 SPD N/A (for x72) 128.95 (2) 2.50 (2X)4.00 30.00 2.30 17.80 (for x64) ECC The used device is 64M x8 DDR2 SDRAM, FBGA. DDR2 SDRAM Part NO : K4T51083QC M378T6553CZ3 / M378T6553CZ0 A B 63.00 55.00 2.50 1.00 0.20 2.50±0.20 Detail B 5.00 Detail A 4.00 1.50±0.10 0.80±0.054.00 3.80 3.00 4.00 M391T6553CZ3 / M391T6553CZ0

Rev. 1.2 Aug. 2005 256MB, 512MB, 1GB Unbuffered DIMMs DDR2 SDRAM 2.50 Physical Dimensions: 64Mbx8 based 128Mx64/x72 Module(2 Ranks) 131.35 Units : Millimeters 133.35 10.00 1.270 ± 0.10 4.00 128.95 (2) 2.50 (2X)4.00 2.30 17.80 N/A (for x64) (for x72) ECC The used device is 64M x8 DDR2 SDRAM, FBGA. DDR2 SDRAM Part NO : K4T51083QC SPD M378T2953CZ3 / M378T2953CZ0 1.00 0.20 2.50±0.20 Detail B 5.00 Detail A 4.00 1.50±0.10 0.80±0.054.00 3.80 3.00 4.00 A B 63.00 55.00 30.00 N/A (for x72) (for x64) ECC M391T2953CZ3 / M391T2953CZ0

Rev. 1.2 Aug. 2005 256MB, 512MB, 1GB Unbuffered DIMMs DDR2 SDRAM Physical Dimensions: 32Mbx16 based 32Mx64 Module(1 Rank) 131.35 Units : Millimeters 133.35 10.00 128.95 (2) 2.50 (2X)4.00 30.00 2.30 17.80 SPD 1.270 ± 0.10 2.7 The used device is 32M x16 DDR2 SDRAM, FBGA. DDR2 SDRAM Part NO : K4T51163QC M378T3354CZ3 / M378T3354CZ0 2.50 1.00 0.20 2.50±0.20 Detail B 5.00 Detail A 4.00 1.50±0.10 0.80±0.054.00 3.80 3.00 4.00 A B 63.00 55.00

Rev. 1.2 Aug. 2005 256MB, 512MB, 1GB Unbuffered DIMMs DDR2 SDRAM

Revision History

Revision 1.0 (Feb. 2005) - Initial Release Revision 1.1 (Mar. 2005) - Changed the IDD0/IDD3N/IDD3P current values. Revision 1.2 (Aug. 2005) - Revised the IDD Current Values.