M38000E2-XXXFS

M38022M4 MITSUBISHI | Alldatasheet

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ADVANCED AND EVER ADVANCING MITSUBISHI ELECTRIC MITSUBISHI 8-BIT SINGLE-CHIP MICROCOMPUTER

740 FAMILY / 38000 SERIES

User’s Manual MITSUBISHI ELECTRIC

keep safety first in your circuit designs ! l Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non-flammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials l These materials are intended as a reference to assist our customers in the selection of the Mitsubishi semiconductor product best suited to the customer’s application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Mitsubishi Electric Corporation or a third party. l Mitsubishi Electric Corporation assumes no responsibility for any damage, or infringement of any third-party’s rights, originating in the use of any product data, diagrams, charts or circuit application examples contained in these materials. l All information contained in these materials, including product data, diagrams and charts, represent information on products at the time of publication of these materials, and are subject to change by Mitsubishi Electric Corporation without notice due to product improvements or other reasons. It is therefore recommended that customers contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for the latest product information before purchasing a product listed herein. l Mitsubishi Electric Corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. l The prior written approval of Mitsubishi Electric Corporation is necessary to reprint or reproduce in whole or in part these materials. l If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. l Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for further details on these materials or the products contained therein.

This user’s manual describes Mitsubishi’s CMOS 8- bit microcomputers 3802 Group. After reading this manual, the user should have a through knowledge of the functions and features of the 3802 Group, and should be able to fully utilize the product. The manual starts with specifications and ends with application examples. For details of software, refer to the “SERIES MELPS 740 <SOFTWARE> USER’S MANUAL.” For details of development support tools, refer to the “DEVELOPMENT SUPPORT TOOLS FOR MICRO- COMPUTERS” data book.

BEFORE USING THIS USER’S MANUAL This user’s manual consists of the following three chapters. Refer to the chapter appropriate to your conditions, such as hardware design or software development. Chapter 3 also includes necessary information for systems development. Be sure to refer to this chapter. 1. Organization l CHAPTER 1 HARDWARE This chapter describes features of the microcomputer and operation of each peripheral function. l CHAPTER 2 APPLICATION This chapter describes usage and application examples of peripheral functions, based mainly on setting examples of related registers. l CHAPTER 3 APPENDIX This chapter includes necessary information for systems development using the microcomputer, electric characteristics, a list of registers, the masking confirmation (mask ROM version), and mark specifications which are to be submitted when ordering. 2. Structure of register The figure of each register structure describes its functions, contents at reset, and attributes as follows : 0 0 : Single-chip mode Note 2. Bit attributes••••••The attributes of control register bits are classified into 3 bytes : read-only, write-only and read and write. In the figure, these attributes are represented as follows : : Bit in which nothing is arranged 0 1 : Name Function At resetRWB 0 5 b0b1b2b3b4b5b6b7 Contents immediately after reset release Bit attributes (Note 1) Processor mode bits Stack page selection bit Nothing arranged for these bits. These are write disabled bits. When these bits are read out, the contents are “0.” Fix this bit to “0.” Main clock (XIN-XOUT ) stop bit Internal system clock selection bit 1 0 : 1 1 : Not available b1 b0 0 : 0 page1 : 1 page 0 : Operating 1 : Stopped 0 : XIN-XOUT selected 1 : XCIN-XCOUT selected : Bit that is not used for control of the corresponding function Note 1. Contents immediately after reset release Undefined••••••Undefined or reset release

• •••••Contents determined by option at reset release [ (Note 2) CPU mode register (CPUM) [Address : 3B16] Bits

LIST OF GROUPS HAVING THE SIMILAR FUNCTIONS Prescaler : 3 Timer : 4 <8-bit> Prescaler : 3 Timer : 4 <8-bit> Prescaler : 3 Timer : 4 <8-bit> Function Group Pin (Package type) Timer A-D converter D-A converter Clock generating circuit Serial I/O Remarks One Time PROM EPROM RAM Mask ROM Memory type ]24K 512 384 32K8K 16K 32K 16K (Note 1) (Note 1) 16K (Note 1) 32K (Note 1) 384 384 640 (Note 1) 24K 384 384 640 16K (Note 1) 32K (Note 1) 32K (Note 1) 32K 1024 PWM output 512 16K 16K 16K 3800 group 64 pin

• 64P4B
• 64P6N-A
• 64P6D-A 1 circuit UART or Clock synchronous 5 1 3802 group 64 pin
• 64P4B
• 64P6N-A 8-bit 5 8-channel 8-bit 5 2-channel UART or Clock synchronous 5 1 Clock synchronous 5 1 1 circuit 1 circuit UART or Clock synchronous 5 1 Clock synchronous 5 1 3806 group 3807 group 80 pin
• 80P6N-A 2 circuit 8-bit 5 13-channel 8-bit 5 4-channel UART or Clock synchronous 5 1 Clock synchronous 5 1 Timer : 3 <8-bit> Timer X/Y : 2 Timer A/B : 2 <16-bit> 80 pin
• 80P6N-A
• 80P6S-A
• 80P6D-A 12K (Note 1) 16K (Note 1) 24K (Note 3) 24K 32K (Note 3) 48K (Note 3) 1024512384 384 1024 24K (Note 2) 48K (Note 3) 8-bit 5 8-channel 8-bit 5 2-channel As of September 1995 Real time port output Analog comparator Watchdog timer 48K (Note 2) Notes 1: Extended operating temperature version available 2: High-speed version available 3: Extended operating temperature version and High-speed version available ] . ROM expansion 3802 group, one of the CMOS 8-bit microcomputer 38000 series presented in this user’s manual is provided with standard functions. The basic functions of the 3800, 3802, 3806 and 3807 groups having the same functions are shown below. For the detailed functions of each group, refer to the related data book and user’s manual. List of groups having the same functions

i Table of contents

3802 GROUP USER'S MANUAL

CHAPTER 1. HARDWARE

ii 3802 GROUP USER'S MANUAL Table of contents CHAPTER 2. APPLICATION CHAPTER 3. APPENDIX

3.1.12 Timing requirements and Switching characteristics

3802 GROUP USER’S MANUAL i

ii 3802 GROUP USER’S MANUAL List of figures CHAPTER 2 APPLICATION Fig. 2.3.19 Setting of related registers at a transmitting side Fig. 2.3.20 Setting of related registers at a receiving side

3802 GROUP USER’S MANUAL iii

Fig. 2.3.21 Control procedure at a transmitting side Fig. 2.3.31 Connection diagram [Cyclic transmission or reception of block data between microcomputers]..2-43 Fig. 2.3.32 Fig. 2.3.33 Setting of related registers [Cyclic transmission or reception of block data between microcomputers]..2-44 Fig. 2.3.38

iv 3802 GROUP USER’S MANUAL List of figures CHAPTER 3 APPENDIX Fig. 3.2.3 Standard characteristic example of CMOS output port at P-channel drive(1) . 3-18 Fig. 3.2.4 Standard characteristic example of CMOS output port at P-channel drive(2) . 3-18 Fig. 3.2.5 Standard characteristic example of CMOS output port at N-channel drive(1) . 3-19 Fig. 3.2.6 Standard characteristic example of CMOS output port at N-channel drive(2) . 3-19 Fig. 3.4.3 Wiring for the V

3802 GROUP USER’S MANUAL v

ii 3802 GROUP USER’S MANUAL List of tables Table 3.1.21 Timing requirements in memory expansion mode and microprocessor mode Table 3.1.22 Switching characteristics in memory expansion mode and microprocessor mode Table 3.5.1 Function of CNTR

DESCRIPTION

FEATURES

APPLICATIONS

3802 GROUP USER’S MANUAL1-2

PIN CONFIGURATION (TOP VIEW) Package type : 64P6N-A 64-pin plastic-molded QFP The 3802 group is the 8-bit microcomputer based on the 740 fam- ily core technology. The 3802 group is designed for controlling systems that require analog signal processing and include two serial I/O functions, A-D converters, and D-A converters. The various microcomputers in the 3802 group include variations of internal memory size and packaging. For details, refer to the section on part numbering. For details on availability of microcomputers in the 3802 group, re- fer to the section on group expansion. (at 8 MHz oscillation frequency)

• Memory size (connect to external ceramic resonator or quartz-crystal oscillator) (Extended operating temperature version : 4.0 to 5.5 V)
• Memory expansion possible (Extended operating temperature version : –40 to 85°C)

Office automation, VCRs, tuners, musical instruments, cameras, air conditioners, etc. Fig. 1 Pin configuration of M38022M4-XXXFP DESCRIPTION/FEATURES/APPLICATIONS/PIN CONFIGURATION P41/INT0 P00/AD0 P03/AD3 P04/AD4 P05/AD5 P06/AD6 P07/AD7 P11/AD9 P12/AD10 P13/AD11 P14/AD12 P15/AD13 P16/AD14 P17/AD15 P62/AN2 P61/AN1 P60/AN0 P57/INT3 M38022M4-XXXFP P56/PWM P55/CNTR 1 P54/CNTR 0 P52/SCLK2 P51/SOUT2 P50/SIN2 P47/SRDY1 P45/TXD P44/RXD P43/INT2 P63 /AN3 P64/AN4 P65/AN5 AV SS VREF VCC P30/DA1 P31/DA2 P32/ONW P33/RESET OUT P34/f P35/SYNC P36/WR P37/RD P42/INT1 CNV SS XIN XOUT VSS P27/DB7 P26/DB6 P25/DB5 P24/DB4 P23/DB3 P22/DB2 P21/DB1 P20/DB0 RESET P53/SRDY2 P46/SCLK1 P10/AD8 P01/AD1 P02/AD2 P40/INT4P67/AN7 P66/AN6

PIN CONFIGURATION (TOP VIEW) Package type : 64P4B 64-pin shrink plastic-molded DIP P64/AN4 P66/AN6 P67/AN7 AV SS VREF VCC P63/AN3 P65/AN5 P62/AN2 P61/AN1 P60/AN0 P57/INT3 P56/PWM P55/CNTR 1 P54/CNTR 0 P53/SRDY2 P52/SCLK2 P51/SOUT2 P50/SIN2 P47/SRDY1 P46/SCLK1 P43/INT2 P44/RXD P45/TXD CNV SS P41/INT0 P40/INT4 XIN XOUT VSS P42/INT1 RESET P24/DB4 P23/DB3 P22/DB2 P20/DB0 P21/DB1 P25/DB5 P27/DB7 P26/DB6 P33/RESET OUT P34/f P35/SYNC P37/RD P36/WR P32/ONW P30/DA1 P31/DA2 P00/AD0 P01/AD1 P02/AD2 P03/AD3 P04/AD4 P05/AD5 P06/AD6 P07/AD7 P10/AD8 P11/AD9 P12/AD10 P13/AD11 P14/AD12 P17/AD15 P16/AD14 P15/AD13 M38022M4-XXXSP PIN CONFIGURATION Fig.2 Pin configuration of M38022M4-XXXSP

3802 GROUP USER’S MANUAL1-4

FUNCTIONAL BLOCK DIAGRAM (Package : 64P4B) FUNCTIONAL BLOCK FUNCTIONAL BLOCK Fig. 3 Functional block diagram CNTR 1CNTR 0 VREF AV SS RAM ROM CPU A X Y S PC H PC L PS VSS RESET VCC 1 26 CNV SS P0(8) 49 50 5152 5354 55 56 P1(8) 41 43 45 4742 44 46 48 P2(8) 33 35 37 3936 38 40 P3(8) 57 59 61 6358 60 62 64 P4(8) 20 22 24 2821 23 25 29 P5(8) 12 14 16 1813 15 17 19 P6(8) 46 1059 113 342 XIN XOUT D-A (8) D-A (8) A-D (8) Reset input Clock generating circuit Clock input Clock output Prescaler 12 (8) Timer 1 (8) Timer 2 (8) I/O port P4 I/O port P0I/O port P1I/O port P2I/O port P3I/O port P5I/O port P6 7 8 SI/O1 (8) INT0 INT2 INT4 Prescaler X (8) Timer X (8) Prescaler Y (8) Timer Y (8) converter 2 converter 1 SI/O2 (8)PWM (8) INT3 converter

• Apply voltage of 3.0 V–5.5 V to VCC , and 0 V to VSS . (Extended operating temperature version : 4.0 V to 5.5 V)
• This pin controls the operation mode of the chip.
• Normally connected to VSS .
• If this pin is connected to VCC , the internal ROM is inhibited and external memory is accessed.
• Reference voltage input pin for A-D and D-A converters
• GND input pin for A-D and D-A converters
• Connect to VSS .
• Reset input pin for active “L”
• Input and output signals for the clock generating circuit.
• Connect a ceramic resonator or quartz-crystal oscillator between the X IN and XOUT pins to set the oscillation frequency.
• If an external clock is used, connect the clock source to the XIN pin and leave the XOUT pin open.
• The clock is used as the oscillating source of system clock.
• 8 bit CMOS I/O port
• I/O direction register allows each pin to be individually programmed as either input or output.
• At reset this port is set to input mode.
• In modes other than single-chip, these pins are used as address, data, and control bus I/O pins.
• CMOS compatible input level
• CMOS 3-state output structure
• 8-bit CMOS I/O port with the same function as port P0
• CMOS compatible input level
• CMOS 3-state output structure
• 8-bit CMOS I/O port with the same function as port P0
• CMOS compatible input level
• CMOS 3-state output structure
• 8-bit CMOS I/O port with the same function as port P0
• CMOS compatible input level
• CMOS 3-state output structure Function except a port function
• D–A conversion output pins
• External interrupt input pin
• Serial I/O1 I/O pins
• Serial I/O2 I/O pins
• Timer X and Timer Y I/O pins
• PWM output pin
• External interrupt input pin
• A-D conversion input pins Name Power source CNV SS Analog reference voltage Analog power source Reset input Clock input Clock output I/O port P0 I/O port P1 I/O port P2 I/O port P3 I/O port P4 I/O port P5 I/O port P6 PIN DESCRIPTION

Table 1. Pin description

3802 GROUP USER’S MANUAL1-6

M3802 2 M 4 - XXX SPProduct Package type ROM number ROM/PROM size : 4096 bytes : 8192 bytes : 12288 bytes : 16384 bytes : 20480 bytes : 24576 bytes : 28672 bytes : 32768 bytes The first 128 bytes and the last 2 bytes of ROM are reserved areas ; they cannot be used. Memory type : Mask ROM version : EPROM or One Time PROM version RAM size : 192 bytes : 256 bytes : 384 bytes : 512 bytes : 640 bytes : 768 bytes : 896 bytes : 1024 bytes Normally, using hyphen. When electrical characteristic, or division of quality identification code using alphanumeric character – : standard D : Extended operating temperature version SP : 64P4B package FP : 64P6N-A package SS : 64S1B-E package FS : 64D0 package Omitted in some types. M E Fig.4 Part numbering PART NUMBERING

Table 2. List of supported products

3802 GROUP USER’S MANUAL

Currently supported products are listed below. Table 3. List of supported products (Extended operating temperature version)

1-93802 GROUP USER’S MANUAL HARDWARE FUNCTIONAL DESCRIPTION FUNCTIONAL DESCRIPTION Central Processing Unit (CPU) The 3802 group uses the standard 740 family instruction set. Refer to the table of 740 family addressing modes and machine instruc- tions or the SERIES 740 <Software> User´s Manual for details on the instruction set. Machine-resident 740 family instructions are as follows: The FST and SLW instructions cannot be used. The MUL, DIV, WIT and STP instruction can be used. The central processing unit (CPU) has the six registers. Accumulator (A) The accumulator is an 8-bit register. Data operations such as data transfer, etc., are executed mainly through the accumulator. Index register X (X), Index register Y (Y) Both index register X and index register Y are 8-bit registers. In the index addressing modes, the value of the OPERAND is added to the contents of register X or register Y and specifies the real address. When the T flag in the processor status register is set to “1”, the value contained in index register X becomes the address for the sec- ond OPERAND. Stack pointer (S) The stack pointer is an 8-bit register used during sub-routine calls and interrupts. The stack is used to store the current address data and processor status when branching to subroutines or interrupt rou- tines. The lower eight bits of the stack address are determined by the con- tents of the stack pointer. The upper eight bits of the stack address are determined by the Stack Page Selection Bit. If the Stack Page Selection Bit is “0”, then the RAM in the zero page is used as the stack area. If the Stack Page Selection Bit is “1”, then RAM in page 1 is used as the stack area. The Stack Page Selection Bit is located in the SFR area in the zero page. Note that the initial value of the Stack Page Selection Bit var- ies with each microcomputer type. Also some microcomputer types have no Stack Page Selection Bit and the upper eight bits of the stack address are fixed. The operations of pushing register contents onto the stack and popping them from the stack are shown in Fig.7. Program counter (PC) The program counter is a 16-bit counter consisting of two 8-bit registers PC H and PCL. It is used to indicate the address of the next instruction to be executed. Fig. 7. 740 Family CPU register structure b7 b0 X b7 b0 S b7 b0 Y b7 b0 PC L Processor Status Register (PS) Carry Flag b7 b0 b7 b0 A b15 PC H Zero Flag Interrupt Disable Flag Decimal Mode Flag Break Flag Index X Mode Flag Overflow Flag Negative Flag Program Counter Stack Pointer Index Register Y Index Register X Accumulator CZIDBTVN

1-10 3802 GROUP USER’S MANUAL HARDWARE FUNCTIONAL DESCRIPTION Execute JSR On-going Routine M (S) (PC H ) (S) (S – 1) M (S) (PC L) Execute RTS (PCL) M (S) (S) (S – 1) (S) (S + 1) (S) (S + 1) (PCH ) M (S) Subroutine Restore Return Address Store Return Address on Stack (Note 2) M (S) (PS) Execute RTI (PS) M (S) (S) (S – 1) (S) (S + 1) Interrupt Service Routine Restore Contents of Processor Status Register M (S) (PC H ) (S) (S – 1) M (S) (PC L) (S) (S – 1) (PCL) M (S) (S) (S + 1) (S) (S + 1) (PCH ) M (S) Restore Return Address I Flag “0” to “1” Fetch the Jump Vector Store Return Address on Stack (Note 2) Store Contents of Processor Status Register on Stack Interrupt request (Note 1) Note 1 : The condition to enable the interrupt Interrupt enable bit is “1” Interrupt disable flag is “0” 2 : When an interrupt occurs, the address of the next instruction to be executed is stored in the stack area. When a subroutine is called, the address one before the next instruction to be executed is stored in the stack area. Accumulator Processor status register Push instruction to stack PHA PHP Pop instruction from stack PLA PLP Fig. 8. Register push and pop at interrupt generation and subroutine call Table. 4. Push and pop instructions of accumulator or processor status register

1-113802 GROUP USER’S MANUAL HARDWARE FUNCTIONAL DESCRIPTION Processor status register (PS) The processor status register is an 8-bit register consisting of flags which indicate the status of the processor after an arithmetic opera- tion. Branch operations can be performed by testing the Carry (C) flag, Zero (Z) flag, Overflow (V) flag, or the Negative (N) flag. In deci- mal mode, the Z, V, N flags are not valid. After reset, the Interrupt disable (I) flag is set to “1”, but all other flags are undefined. Since the Index X mode (T) and Decimal mode (D) flags directly affect arithmetic operations, they should be initialized in the beginning of a program. (1) Carry flag (C) The C flag contains a carry or borrow generated by the arithmetic logic unit (ALU) immediately after an arithmetic operation. It can also be changed by a shift or rotate instruction. (2) Zero flag (Z) The Z flag is set if the result of an immediate arithmetic operation or a data transfer is “0”, and cleared if the result is anything other than “0”. (3) Interrupt disable flag (I) The I flag disables all interrupts except for the interrupt generated by the BRK instruction. Interrupts are disabled when the I flag is “1”. When an interrupt occurs, this flag is automatically set to “1” to prevent other interrupts from interfering until the current interrupt is serviced. (4) Decimal mode flag (D) The D flag determines whether additions and subtractions are executed in binary or decimal. Binary arithmetic is executed when this flag is “0”; decimal arithmetic is executed when it is “1”. Decimal correction is automatic in decimal mode. Only the ADC and SBC instructions can be used for decimal arithmetic. (5) Break flag (B) The B flag is used to indicate that the current interrupt was generated by the BRK instruction. The BRK flag in the processor status register is always “0”. When the BRK instruction is used to generate an interrupt, the processor status register is pushed onto the stack with the break flag set to “1”. The saved processor status is the only place where the break flag is ever set. (6) Index X mode flag (T) When the T flag is “0”, arithmetic operations are performed between accumulator and memory, e.g. the results of an operation between two memory locations is stored in the accumulator. When the T flag is “1”, direct arithmetic operations and direct data transfers are enabled between memory locations, i.e. between memory and memory, memory and I/O, and I/O and I/O. In this case, the result of an arithmetic operation performed on data in memory location 1 and memory location 2 is stored in memory location 1. The address of memory location 1 is specified by index register X, and the address of memory location 2 is specified by normal addressing modes. (7) Overflow flag (V) The V flag is used during the addition or subtraction of one byte of signed data. It is set if the result exceeds +127 to -128. When the BIT instruction is executed, bit 6 of the memory location operated on by the BIT instruction is stored in the overflow flag. (8) Negative flag (N) The N flag is set if the result of an arithmetic operation or data transfer is negative. When the BIT instruction is executed, bit 7 of the memory location operated on by the BIT instruction is stored in the negative flag. Table. 5. Set and clear instructions of each bit of processor status register Set instruction Clear instruction C flag Z flag I flag D flag B flag T flag V flag N flag SEC CLC SEI CLI SED CLD SET CLT CLV _ _

1-12 3802 GROUP USER’S MANUAL HARDWARE FUNCTIONAL DESCRIPTION CPU Mode Register The CPU mode register is allocated at address 003B16. The CPU mode register contains the stack page selection bit. Fig. 9. Structure of CPU mode register CPU mode register (CPUM : address 003B16) b7 b0 Stack page selection bit 0 : 0 page 1 : 1 page Not used (return “0” when read) Processor mode bits b1 b0 0 0 : Single-chip mode 0 1 : Memory expansion mode 1 0 : Microprocessor mode 1 1 : Not available

Special function register (SFR) area The Special Function Register area in the zero page contains con- trol registers such as I/O ports and timers. RAM RAM is used for data storage and for stack area of subroutine calls and interrupts. ROM The first 128 bytes and the last 2 bytes of ROM are reserved for device testing and the rest is user area for storing programs. Interrupt vector area The interrupt vector area contains reset and interrupt vectors. Zero page The 256 bytes from addresses 000016 to 00FF16 are called the zero page area. The internal RAM and the special function regis- ters (SFR) are allocated to this area. The zero page addressing mode can be used to specify memory and register addresses in the zero page area. Access to this area with only 2 bytes is possible in the zero page addressing mode. Special page The 256 bytes from addresses FF0016 to FFFF16 are called the special page area. The special page addressing mode can be used to specify memory addresses in the special page area. Ac- cess to this area with only 2 bytes is possible in the special page addressing mode. Fig. 10 Memory map diagram 010016 000016 004016 044016 FF0016 FFDC 16 FFFE 16 FFFF 16 192 256 384 512 640 768 896 1024 XXXX 00FF16 013F16 01BF 16 023F16 02BF 16 033F16 03BF 16 043F16 4096 8192 12288 16384 20480 24576 28672 32768 F000 E00016 D000 16 C000 16 B00016 A00016 900016 800016 F08016 E08016 D080 16 C080 16 B08016 A08016 908016 808016 YYYY 16 ZZZZ 16 RAM ROM Reserved area SFR area Not used Interrupt vector area ROM area Reserved ROM area (128 bytes) Zero page Special page RAM area RAM capacity (bytes) Address XXXX 16 ROM capacity (bytes) Address YYYY 16 Reserved ROM area Address ZZZZ 16 FUNCTIONAL DESCRIPTION

3802 GROUP USER’S MANUAL1-14

Fig. 11 Memory map of special function register (SFR) 002016 002116 002216 002316 002416 002516 002616 002716 002816 002916 002A16 002B16 002C 16 002D 16 002E16 002F16 003016 003116 003216 003316 003416 003516 003616 003716 003816 003916 003A16 003B16 003C 16 003D 16 003E16 003F16 000016 000116 000216 000316 000416 000516 000616 000716 000816 000916 000A16 000B16 000C 16 000D 16 000E16 000F16 001016 001116 001216 001316 001416 001516 001616 001716 001816 001916 001A16 001B16 001C 16 001D 16 001E16 001F16 Serial I/O2 register (SIO2) Port P0 (P0) Port P0 direction register (P0D) Port P1 (P1) Port P1 direction register (P1D) Port P2 (P2) Port P2 direction register (P2D) Port P3 (P3) Port P3 direction register (P3D) Port P4 (P4) Port P4 direction register (P4D) Port P5 (P5) Port P5 direction register (P5D) Port P6 (P6) Port P6 direction register (P6D) Transmit/Receive buffer register (TB/RB) Serial I/O1 status register (SIO1STS) Serial I/O1 control register (SIO1CON) UART control register (UARTCON) Baud rate generator (BRG) Serial I/O2 control register (SIO2CON) Interrupt control register 2(ICON2) A-D conversion register (AD) Prescaler Y (PREY) Timer Y (TY) AD/DA control register (ADCON) D-A1 conversion register (DA1) D-A2 conversion register (DA2) Interrupt edge selection register (INTEDGE) CPU mode register (CPUM) Interrupt request register 1(IREQ1) Interrupt request register 2(IREQ2) Interrupt control register 1(ICON1) Prescaler 12 (PRE12) Timer 2 (T2) Prescaler X (PREX) Timer X (TX) Timer 1 (T1) Timer XY mode register (TM) PWM control register (PWMCON) PMW prescaler (PREPWM) PWM register (PWM) FUNCTIONAL DESCRIPTION

Table 6. list of I/O port functions tion I/O ports, refer to the applicable sections. 2: Make sure that the input level at each pin is either 0 V or VCC during execution of the STP instruction. When an input level is at an intermediate potential, a current will flow from VCC to VSS through the input-stage gate. which determine the input/output direction of each individual pin. can be set to be input port or output port. output latch is written to and the pin remains floating.

3802 GROUP USER’S MANUAL1-16

Fig. 12 Port block diagram (single-chip mode) (1) (1) Ports P0, P1, P2, P32–P37 Direction register Data bus Port latch (2) Ports P30, P31 (3) Ports P40–P43, P57 Direction register Data bus Port latch Serial I/O1 input Serial I/O1 enable bit Receive enable bit (4) Port P44 (5) Port P45 (6) Port P46 Direction register Data bus Port latch Serial I/O1 ready output Serial I/O1 enable bit SRDY1 output enable bit Serial I/O1 mode selection bit (7) Port P47 (8) Port P50 Serial I/O2 input Direction register Data bus Port latch D–A conversion output DA 1 output enable bit (P30) DA 2 output enable bit (P31) Direction register Data bus Port latch Interrupt input Direction register Data bus Port latch Serial I/O1 output Serial I/O1 enable bit Transmit enable bit P45/TXD P-channel output disable bit Direction register Data bus Port latch Serial I/O1 clock output Serial I/O1 mode selection bit Serial I/O1 enable bit Serial I/O1 enable bit Serial I/O1 synchronous clock selection bit Serial I/O1 external clock input Direction register Data bus Port latch FUNCTIONL DESCRIPTION

Fig. 13 Port block diagram (single-chip mode) (2) (14) Port P6(13) Port P56 (12) Ports P54, 55 (9) Port P51 (10) Port P52 (11) Port P53 Serial I/O2 transmit end signal Serial I/O2 port selection bit P51/SOUT2 P-channel output disable bit Direction register Data bus Port latch Serial I/O2 output Serial I/O2 external clock input Serial I/O2 synchronous clock selection bit Serial I/O2 port selection bit Direction register Data bus Port latch Serial I/O2 clock output Direction register Data bus Port latch Serial I/O2 ready output SRDY2 output enable bit Direction register Data bus Port latch Pulse output mode Timer output CNTR 0, CNTR1 Interrupt input Direction register Data bus Port latch PWM output PWM output enable bit A-D conversion input Direction register Data bus Port latch Analog input pin selection bit FUNCTIONAL DESCRIPTION

3802 GROUP USER’S MANUAL1-18

Interrupt enable bits can be set or cleared by software. received according to priority. table into the program counter. (1) Disable the external interrupt which is selected. (2) Change the active edge selection. (3) Clear the interrupt request bit which is selected to “0”. (4) Enable the external interrupt which is selected. Table 7. Interrupt vector addresses and priority Note 1: Vector addresses contain interrupt jump destination addresses. 2: Reset function in the same way as an interrupt with the highest priority.

Fig. 14 Interrupt control Fig. 15 Structure of interrupt-related registers FUNCTIONAL DESCRIPTION b7 b0 b7 b0 b7 b0 b7 b0 b7 b0 Interrupt edge selection register INT0 active edge selection bit INT1 active edge selection bit Not used (returns “0” when read) INT 2 active edge selection bit INT3 active edge selection bit INT4 active edge selection bit Not used (returns “0” when read) (INTEDGE : address 003A16) Interrupt request register 1 INT0 interrupt request bit INT1 interrupt request bit Serial I/O1 receive interrupt request bit Serial I/O1 transmit interrupt request bit Timer X interrupt request bit Timer Y interrupt request bit Timer 1 interrupt request bit Timer 2 interrupt request bit Interrupt control register 1 INT0 interrupt enable bit INT1 interrupt enable bit Serial I/O1 receive interrupt enable bit Serial I/O1 transmit interrupt enable bit Timer X interrupt enable bit Timer Y interrupt enable bit Timer 1 interrupt enable bit Timer 2 interrupt enable bit 0 : No interrupt request issued 1 : Interrupt request issued (IREQ1 : address 003C 16) (ICON1 : address 003E16) Interrupt request register 2 CNTR 0 interrupt request bit CNTR 1 interrupt request bit Serial I/O2 interrupt request bit INT2 interrupt request bit INT3 interrupt request bit INT4 interrupt request bit AD converter interrupt request bit Not used (returns “0” when read) (IREQ2 : address 003D 16) Interrupt control register 2 CNTR 0 interrupt enable bit CNTR 1 interrupt enable bit Serial I/O2 interrupt enable bit INT 2 interrupt enable bit INT3 interrupt enable bit INT4 interrupt enable bit AD converter interrupt enable bit Not used (returns “0” when read) (Do not write “1” to this bit) 0 : Interrupts disabled 1 : Interrupts enabled (ICON2 : address 003F 16) 0 : Falling edge active 1 : Rising edge active Interrupt disable flag (I) Interrupt request Interrupt request bit Interrupt enable bit BRK instruction Reset

3802 GROUP USER’S MANUAL1-20

0: Count start 1: Count stop Timer XY mode register (TM : address 0023 16) Timer Y operating mode bit 0 0: Timer mode 0 1: Pulse output mode 1 0: Event counter mode 1 1: Pulse width measurement mode CNTR 1 active edge switch bit 0: Interrupt at falling edge Count at rising edge in event counter mode 1: Interrupt at rising edge Count at falling edge in event counter mode CNTR 0 active edge switch bit 0: Interrupt at falling edge Count at rising edge in event counter mode 1: Interrupt at rising edge Count at falling edge in event counter mode Timer X operating mode bit 0 0: Timer mode 0 1: Pulse output mode 1 0: Event counter mode 1 1: Pulse width measurement mode b1b0 b4b5 Timer Y count stop bit 0: Count start 1: Count stop Timers The 3802 group has four timers: timer X, timer Y, timer 1, and timer All timers are count down. When the timer reaches “00 16”, an un- derflow occurs at the next count pulse and the corresponding timer latch is reloaded into the timer and the count is continued. When a timer underflows, the interrupt request bit corresponding to that timer is set to “1”. The division ratio of each timer or prescaler is given by 1/(n + 1), where n is the value in the corresponding timer or prescaler latch. Timer 1 and Timer 2 The count source of prescaler 12 is the oscillation frequency di- vided by 16. The output of prescaler 12 is counted by timer 1 and timer 2, and a timer underflow sets the interrupt request bit. Timer X and Timer Y Timer X and Timer Y can each be selected in one of four operating modes by setting the timer XY mode register. Timer Mode The timer counts f(X IN)/16 in timer mode. Pulse Output Mode Timer X (or timer Y) counts f(XIN)/16. Whenever the contents of the timer reach “0016”, the signal output from the CNTR0 (or CNTR 1) pin is inverted. If the CNTR0 (or CNTR1) active edge switch bit is “0”, output begins at “ H”. If it is “1”, output starts at “L”. When using a timer in this mode, set the corresponding port P5 4 ( or port P55) direction register to out- put mode. Event Counter Mode Operation in event counter mode is the same as in timer mode, except the timer counts signals input through the CNTR 0 or CNTR 1 pin. Pulse Width Measurement Mode If the CNTR0 (or CNTR1) active edge selection bit is “0”, the timer counts at the oscillation frequency divided by 16 while the CNTR0 (or CNTR1) pin is at “H”. If the CNTR0 (or CNTR1) active edge switch bit is “1”, the count continues during the time that the CNTR 0 (or CNTR1) pin is at “L”. In all of these modes, the count can be stopped by setting the timer X (timer Y) count stop bit to “1”. Every time a timer underflows, the corresponding interrupt request bit is set. Fig. 16 Structure of timer XY register FUNCTIONAL DESCRIPTION

Fig. 17 Block diagram of timer X, timer Y, timer 1, and timer 2 Timer X latch (8) Timer X (8) Prescaler X latch (8) Prescaler X (8) Oscillator Divider f(XIN) 1/16 CNTR 0 active edge switch bit P54/CNTR 0 pin Port P54 direction register “0” “1” Eventcounter mode Timer X count stop bit CNTR 0 active edge switch bit Port P54 latch Pulse output mode Pulse width measurement mode Timer mode Pulse output mode “1” “0” Timer X latch write pulse Pulse output mode To timer X interrupt request bit To CNTR 0 interrupt request bit Data bus Timer Y latch (8) Timer Y (8) Prescaler Y latch (8) Prescaler Y (8) CNTR 1 active edge switch bit P55/CNTR 1 pin Port P55 direction register “0” “1” Eventcounter mode Timer Y count stop bit CNTR 1 active edge switch bit Port P5 latch Pulse output mode Pulse width measurement mode Timer mode Pulse output mode “1” “0” Timer Y latch write pulse Pulse output mode To timer Y interrupt request bit To CNTR 1 interrupt request bit Data bus Q Q R Toggle flip- flop T Q Q R Toggle flip- flop T Timer 2 latch (8) Timer 1 latch (8)Prescaler 12 latch (8) Prescaler 12 (8) Timer 2 (8)Timer 1 (8) Data bus To timer 2 interrupt request bit To timer 1 interrupt request bit FUNCTIONAL DESCRIPTION

3802 GROUP USER’S MANUAL1-22

Serial I/O1 can be used as either clock synchronous or asynchro- nous (UART) serial I/O. A dedicated timer is also provided for baud rate generation. Clock synchronous serial I/O mode Clock synchronous serial I/O1 mode can be selected by setting the mode selection bit of the serial I/O1 control register to “1”. For clock synchronous serial I/O1, the transmitter and the receiver must use the same clock. If an internal clock is used, transfer is started by a write signal to the TB/RB (address 0018 16). Fig. 18 Block diagram of clock synchronous serial I/O1 Fig. 19 Operation of clock synchronous serial I/O1 function FUNCTIONAL DESCRIPTION 1/4XIN F/F P46/SCLK1 Serial I/O1 status register Serial I/O1 control register P47/SRDY1 P44/RXD P45/TXD f(XIN) Receive buffer Address 001816 Receive shift register Receive buffer full flag (RBF) Receive interrupt request (RI) Clock control circuitShift clock Serial I/O1 synchronous clock selection bit Frequency division ratio 1/(n+1) Baud rate generator Address 001C16 BRG count source selection bit Clock control circuitFalling-edge detector Transmit buffer Data bus Address 001816 Shift clock Transmit shift completion flag (TSC) Transmit buffer empty flag (TBE) Transmit interrupt request (TI) Transmit interrupt source selection bit Address 001916 Data bus Address 001A16 Transmit shift register D 7 D 7 D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 0 D 1 D 2 D 3 D 4 D 5 D 6 RBF = 1 TSC = 1TBE = 0 TBE = 1 TSC = 0 Transfer shift clock (1/2 to 1/2048 of the internal clock, or an external clock) Serial output TxD Serial input RxD Write pulse to receive/transmit buffer (address 0018 16) Overrun error (OE) detection Notes 1 : The transmit interrupt (TI) can be selected to occur either when the transmit buffer has emptied (TBE=1) or after the transmit shift operation has ended (TSC=1), by setting the transmit interrupt source selection bit (TIC) of the serial I/O1 control register. 2 : If data is written to the transmit buffer when TSC=0, the transmit clock is generated continuously and serial data is output continuously from the TxD pin. 3 : The receive interrupt (RI) is set when the receive buffer full flag (RBF) becomes “1” . Receive enable signal SRDY1

Asynchronous serial I/O (UART) mode Clock asynchronous serial I/O mode (UART) can be selected by clearing the serial I/O mode selection bit of the serial I/O control register to “0”. Eight serial data transfer formats can be selected, and the transfer formats used by a transmitter and receiver must be identical. The transmit and receive shift registers each have a buffer, but the two buffers have the same address in memory. Since the shift reg- ister cannot be written to or read from directly, transmit data is written to the transmit buffer, and receive data is read from the re- ceive buffer. The transmit buffer can also hold the next data to be transmitted, and the receive buffer can hold a character while the next charac- ter is being received. Fig. 20 Block diagram of UART serial I/O FUNCTIONAL DESCRIPTION f(XIN) OE PE FE Data bus Receive buffer Address 001816 Receive shift register Receive buffer full flag (RBF) Receive interrupt request (RI) Baud rate generator Frequency division ratio 1/(n+1) Address 001C16 ST/SP/PA generator Transmit buffer Data bus Transmit shift register Address 001816 Transmit shift completion flag (TSC) Transmit buffer empty flag (TBE) Transmit interrupt request (TI) Address 001916 STdetector SP detector UART control register Address 001B16 Character length selection bit Address 001A16 BRG count source selection bit Transmit interrupt source selection bit Serial I/O1 synchronous clock selection bit Clock control circuit Character length selection bit 7 bits 8 bits Serial I/O1 control register P46/SCLK1 Serial I/O1 status register P44/RXD P45/TXD

3802 GROUP USER’S MANUAL1-24

Fig. 21 Operation of UART serial I/O function Serial I/O1 control register (SIO1CON) 001A16 The serial I/O control register consists of eight control bits for the serial I/O function. UART control register (UARTCON) 001B16 The UART control register consists of four control bits (bits 0 to 3) which are valid when asynchronous serial I/O is selected and set the data format of an data transfer. One bit in this register (bit 4) is always valid and sets the output structure of the P4 5/TX D pin. Serial I/O1 status register (SIO1STS) 001916 The read-only serial I/O1 status register consists of seven flags (bits 0 to 6) which indicate the operating status of the serial I/O function and various errors. Three of the flags (bits 4 to 6) are valid only in UART mode. The receive buffer full flag (bit 1) is cleared to “0” when the receive buffer is read. If there is an error, it is detected at the same time that data is transferred from the receive shift register to the receive buffer, and the receive buffer full flag is set. A write to the serial I/O status reg- ister clears all the error flags OE, PE, FE, and SE (bit 3 to bit 6, re- spectively). Writing “0” to the serial I/O enable bit SIOE (bit 7 of the Serial I/O Control Register) also clears all the status flags, in- cluding the error flags. All bits of the serial I/O1 status register are initialized to “0” at re- set, but if the transmit enable bit (bit 4) of the serial I/O control reg- ister has been set to “1”, the transmit shift completion flag (bit 2) and the transmit buffer empty flag (bit 0) become “1”. Transmit buffer/Receive buffer register (TB/ RB) 001816 The transmit buffer and the receive buffer are located at the same address. The transmit buffer is write-only and the receive buffer is read-only. If a character bit length is 7 bits, the MSB of data stored in the receive buffer is “0”. Baud rate generator (BRG) 001C16 The baud rate generator determines the baud rate for serial trans- fer. The baud rate generator divides the frequency of the count source by 1/(n + 1), where n is the value written to the baud rate genera- tor. FUNCTIONAL DESCRIPTION TSC=0 TBE=1 RBF=0 TBE=0 TBE=0 RBF=1 RBF=1 STD 0 D 1 SP D 0 D 1ST SP TBE=1 TSC=1 STD 0 D 1 SP D 0 D 1ST SP Transmit or receive clock Transmit buffer write signal Generated at 2nd bit in 2-stop-bit mode 1 start bit 7 or 8 data bit 1 or 0 parity bit 1 or 2 stop bit (s) 1: Error flag detection occurs at the same time that the RBF flag becomes "1" (at 1st stop bit, during reception). 2: The transmit interrupt (TI) can be selected to occur when either the TBE or TSC flag becomes "1", depending on the setting of the transmit interrupt source selection bit (TIC) of the serial I/O control register. 3: The receive interrupt (RI) is set when the RBF flag becomes "1". 4: After data is written to the transmit buffer when TSC=1, 0.5 to 1.5 cycles of the data shift cycle is necessary until changing to TSC=0. Notes Serial output TXD Serial input RXD Receive buffer read signal

Transmit buffer empty flag (TBE) 0: Buffer full 1: Buffer empty Receive buffer full flag (RBF) 0: Buffer empty 1: Buffer full Transmit shift completion flag (TSC) 0: Transmit shift in progress 1: Transmit shift completed Overrun error flag (OE) 0: No error 1: Overrun error Parity error flag (PE) 0: No error 1: Parity error Framing error flag (FE) 0: No error 1: Framing error Summing error flag (SE) 0: (OE) U (PE) U (FE)=0 1: (OE) U (PE) U (FE)=1 Not used (returns "1" when read) Serial I/O1 status register (SIO1STS : address 0019 16) Serial I/O1 control register (SIO1CON : address 001A16) b0 b0 BRG count source selection bit (CSS) 0: f(XIN) 1: f(XIN)/4 Serial I/O1 synchronous clock selection bit (SCS) 0: BRG output divided by 4 when clock synchronous serial I/O is selected, BRG output divided by 16 when UART is selected. 1: External clock input when clock synchronous serial I/O is selected, external clock input divided by 16 when UART is selected. S RDY1 output enable bit (SRDY) 0: P47 pin operates as ordinaly I/O pin 1: P47 pin operates as SRDY1 output pin Transmit interrupt source selection bit (TIC) 0: Interrupt when transmit buffer has emptied 1: Interrupt when transmit shift operation is completed Transmit enable bit (TE) 0: Transmit disabled 1: Transmit enabled Receive enable bit (RE) 0: Receive disabled 1: Receive enabled Serial I/O1 mode selection bit (SIOM) 0: Asynchronous serial I/O (UART) 1: Clock synchronous serial I/O Serial I/O enable bit (SIOE) 0: Serial I/O disabled (pins P4 4 to P47 operate as ordinary I/O pins) 1: Serial I/O enabled (pins P4 4 to P47 operate as serial I/O pins) b7 UART control register (UARTCON : address 001B16) Character length selection bit (CHAS) 0: 8 bits 1: 7 bits Parity enable bit (PARE) 0: Parity checking disabled 1: Parity checking enabled Parity selection bit (PARS) 0: Even parity 1: Odd parity Stop bit length selection bit (STPS) 0: 1 stop bit 1: 2 stop bits 5/TXD P-channel output disable bit (POFF) 0: CMOS output (in output mode) 1: N-channel open drain output (in output mode) Not used (return "1" when read) Fig. 22 Structure of serial I/O control registers FUNCTIONAL DESCRIPTION

3802 GROUP USER’S MANUAL1-26

The serial I/O2 function can be used only for clock synchronous serial I/O. For clock synchronous serial I/O the transmitter and the receiver must use the same clock. If the internal clock is used, transfer is started by a write signal to the serial I/O2 register. Serial I/O2 control register (SIO2CON) 001D16 The serial I/O2 control register contains seven bits which control various serial I/O functions. Fig. 23 Structure of serial I/O2 control register Fig. 24 Block diagram of serial I/O2 function FUNCTIONAL DESCRIPTION XIN "1" "0" "0" "1" "0" "1" SRDY2 SCLK2 "0" "1" Data bus Serial I/O2 interrupt request Serial I/O2 port selection bit Serial I/O counter 2 (3) Serial I/O shift register 2 (8) Synchronization circuit Serial I/O2 port selection bit Serial I/O2 synchronous clock selection bit SRDY2 output enable bit External clock Internal synchronous clock selection bits Divider P53 latch P53/SRDY2 P52/SCLK2 P51/SOUT2 P50/SIN2 P52 latch P51 latch Serial I/O2 control register (SIO2CON : address 001D16) Internal synchronous clock selection bits 0 0 0: f(XIN)/8 0 0 1: f(XIN)/16 0 1 0: f(XIN)/32 0 1 1: f(XIN)/64 1 1 0: f(XIN)/128 1 1 1: f(XIN)/256 Serial I/O2 port selection bit (SM23) 0: I/O port 1: S OUT2 ,SCLK2 output pin SRDY2 output enable bit (SM24) 0: I/O port 1: SRDY2 output pin Transfer direction selection bit (SM25) 0: LSB first 1: MSB first Serial I/O2 synchronous clock selection bit (SM2 0: External clock 1: Internal clock 1/SOUT2 P-channel output disable bit 0: CMOS output (in output mode) 1: N-channel open-drain output (in output mode) b2 b1 b0

Fig. 25 Timing of serial I/O2 function FUNCTIONAL DESCRIPTION D 7D 0 D 1 D 2 D 3 D 4 D 5 D 6 Transfer clock (Note 1) Serial I/O2 output SOUT2 Serial I/O2 input SIN2 Receive enable signal SRDY2 Serial I/O2 register write signal (Note 2) Serial I/O2 interrupt request bit set 1: When the internal clock is selected as the transfer clock, the divide ratio can be selected by setting bits 0 to 2 of the serial I/O2 control register. 2: When the internal clock is selected as the transfer clock, the SOUT2 pin goes to high impedance after transfer completion. Notes

3802 GROUP USER’S MANUAL1-28

“0” “1” PWM prescaler pre-latch PWM register pre-latch PWM prescaler latch PWM register latch Transfer control circuit PWM register X IN Port P56 latch PWM enable bit Port P56 PWM prescaler PULSE WIDTH MODULATION (PWM) The 3802 group has a PWM function with an 8-bit resolution, based on a signal that is the clock input XIN or that clock input di- vided by 2. Data Setting The PWM output pin also functions as port P56. Set the PWM pe- riod by the PWM prescaler, and set the period during which the output pulse is an “H” by the PWM register. If the value in the PWM prescaler is n and the value in the PWM register is m (where n = 0 to 255 and m = 0 to 255) : PWM period = 255 5 (n+1)/f(X IN) = 51 5 (n+1) µs (when XIN = 5 MHz) Output pulse “H” period = PWM period 5 m/255 = 0.2 5 (n+1) 5 m µ s (when XIN = 5 MHz) PWM Operation When bit 0 (PWM enable bit) of the PWM control register is set to “1”, operation starts by initializing the PWM output circuit, and pulses are output starting at an “H”. If the PWM register or PWM prescaler is updated during PWM output, the pulses will change in the cycle after the one in which the change was made. Fig. 26 Timing of PWM cycle Fig. 27 Block diagram of PWM function 51 5 m 5 (n+1) 255 ms PWM output m: Contents of PWM register n : Contents of PWM prescaler T : PWM cycle (when XIN = 5 MHz) FUNCTIONAL DESCRIPTION

B T C T2= PWM output PWM register write signal PWM prescaler write signal (Changes from “A” to “B” during “H” period) (Changes from “T” to “T2” during PWM period) When the contents of the PWM register or PWM prescaler have changed, the PWM output will change from the next period after the change. T T T2 Fig. 28 Structure of PWM control register Fig. 29 PWM output timing when PWM register or PWM prescaler is changed PWM control register (PWMCON : address 002B16) PWM function enable bit Count source selection bit Not used (return “0” when read) b7 b0 0: PWM disabled 1: PWM enabled 0: f(XIN) 1: f(XIN)/2 FUNCTIONAL DESCRIPTION

3802 GROUP USER’S MANUAL1-30

The functional blocks of the A-D converter are described below. [A-D conversion register] The A-D conversion register is a read-only register that stores the result of an A-D conversion. When reading this register during an A-D conversion, the previous conversion result is read. [AD/DA control register] The AD/DA control register controls the A-D conversion process. Bits 0 to 2 select a specific analog input pin. Bit 3 signals the completion of an A-D conversion. The value of this bit remains at “0” during an A-D conversion, and changes to “1” when an A-D conversion ends. Writing “0” to this bit starts the A-D conversion. Bits 6 and 7 are used to control the output of the D-A converter. [Comparison voltage generator] The comparison voltage generator divides the voltage between AV SS and VREF into 256, and outputs the divided voltages. [Channel selector] The channel selector selects one of the ports P60/AN0 to P67/AN7, and inputs the voltage to the comparator. Fig.30 Structure of AD/DA control register Fig. 31 Block diagram of A-D converter [Comparator and Control circuit] The comparator and control circuit compares an analog input volt- age with the comparison voltage, then stores the result in the A-D conversion register. When an A-D conversion is complete, the control circuit sets the AD conversion completion bit and the AD interrupt request bit to “1”. Note that the comparator is constructed linked to a capacitor, so set f(X IN) to 500 kHz or more during an A-D conversion. AD/DA control register (ADCON : address 003416) Analog input pin selection bits 0 0 0: P60/AN0 0 0 1: P61/AN1 0 1 0: P62/AN2 0 1 1: P63/AN3 1 0 0: P64/AN4 1 0 1: P65/AN5 1 1 0: P66/AN6 1 1 1: P67/AN7 AD conversion completion bit 0: Conversion in progress 1: Conversion completed Not used (return "0" When read) DA 1 output enable bit 0: DA1 output disabled 1: DA1 output enabled DA 2 output enable bit 0: DA2 output disabled 1: DA2 output enabled b7 b0 b2 b1 b0 Channel selector A-D control circuit A-D conversion register Resistor ladder VREF AV SS Comparator A-D interrupt request b7 b0 P60/AN0 P61/AN1 P62/AN2 P63/AN3 P64/AN4 P65/AN5 P66/AN6 P67/AN7 Data bus (Address 003516) AD/DA control register (Address 003416) FUNCTIONAL DESCRIPTION

The 3802 group has two internal D-A converters (DA1 and DA2) with 8-bit resolutions. The D-A converter is performed by setting the value in the D-A conversion register. The result of D-A converter is output from the DA 1 or DA2 pin by setting the DA output enable bit to “1”. When using the D-A converter, the corresponding port direction register bit (P3 0/DA1 or P31/DA2) should be set to “0” (input sta- tus). The output analog voltage V is determined by the value n (base 10) in the D-A conversion register as follows: V = V REF 5 n/256 (n = 0 to 255) Where VREF is the reference voltage. At reset, the D-A conversion registers are cleared to “0016”, the DA output enable bits are cleared to “0”, and the P30/DA1 and P31/ DA 2 pins are set to input (high impedance). The D-A output is not buffered, so connect an external buffer when driving a low-impedance load. Set V CC to 3.0 V or more when using the D-A converter. Fig. 32 Block diagram of D-A converter Fig. 33 Equivalent connection circuit of D-A converter P30/DA1 D-A1 conversion register (8) R-2R resistor ladder DA 1 output enable bit P31/DA2 D-A2 conversion register (8) R-2R resistor ladder DA 2 output enable bit Data bus FUNCTIONAL DESCRIPTION AV SS VREF "0" "1" MSB "0" "1" R R R R R R R 2R 2R LSB P30/DA1 D-A1 conversion register DA 1 output enable bit

3802 GROUP USER’S MANUAL1-32

Note. 5 : Undefined ] : The initial values of CM1 are determined by the level at the CNV SS pin. The contents of all other registers and RAM are undefined after a reset, so they must be initialized by software. Register contents (000116) · · · Prescaler X Port P0 direction register Port P1 direction register Port P2 direction register Port P3 direction register Port P4 direction register Port P5 direction register Port P6 direction register Serial I/O1 status register Serial I/O1 control register Timer X UART control register Serial I/O2 control register Prescaler 12 Timer 1 Timer XY mode register (1) (2) (3) (4) (5) (6) (7) (8) (9) (10) (11) (12) (13) (14) (15) (16) (17) (18) (19) (20) (21) (22) (23) (24) (25) (26) (27) (28) (29) (30) (31) (0003 16) · · · (000516) · · · (000716) · · · (000916) · · · (000B16) · · · (000D16) · · · (001916) · · · (001A16) · · · (001B16) · · · (001D16) · · · (002016) · · · (002116) · · · (002216) · · · (002316) · · · (002416) · · · (002516) · · · (002616) · · · (002716) · · · (002B16) · · · (003416) · · · (003616) · · · (003716) · · · (003A16) · · · (003B16) · · · (003C16) · · · (003D16) · · · (003E16) · · · Address Timer 2 Prescaler Y Timer Y PWM control register AD/DA control register D-A1 conversion register D-A2 conversion register Interrupt edge selection register CPU mode register Interrupt request register 1 Interrupt request register 2 Interrupt control register 1 Interrupt control register 2 Processor status register Program counter 0016 0016 0016 0016 0016 0016 0016 FF16 FF16 FF16 FF16 0016 FF16 0116 0016 0016 0016 111000 0 0 0016 0016 0016 Contents of address FFFC16 55555 1 55(PS) (PCH ) (PCL) Contents of address FFFD16 0016 0016 0016 (003F16) · · · 100000 0 0 FF16 000010 0 0 0016 000000 0 ] Reset Circuit To reset the microcomputer, the RESET pin should be held at an “L” level for 2 µs or more. Then the RESET pin is returned to an “H” level (the power source voltage should be between 4.0 V and 5.5 V), reset is released. Internal operation begin until after 8 to 13 X IN clock cycles are completed. After the reset is completed, the pro- gram starts from the address contained in address FFFD 16 (high- order byte) and address FFFC16 (low-order byte). Make sure that the reset input voltage is less than 0.6 V for VCC of

3.0 V (Extended operating temperature version : the reset input

voltage is less than 0.8 V for V CC of 4.0 V). Fig. 35 Internal status of microcomputer after reset Fig. 34 Example of reset circuit FUNCTIONAL DESCRIPTION 4.0V 0.8V VCC RESET Power source voltage Reset input voltage VSS M51953AL 3 0.1 m F 3802 group

Fig. 36 Timing of reset FUNCTIONAL DESCRIPTION RESET Data f Address SYNC XIN: 8 to 13 clock cycles XIN ? ? ?? ? FFFC FFFD AD H , ADL 1: f(XIN) and f(f) are in the relationship: f(XIN)=2 • f(f). 2: A question mark (?) indicates an undefined status that depends on the previous status. Reset address from the vector table Notes RESET OUT (internal reset)

3802 GROUP USER’S MANUAL1-34

An oscillation circuit can be formed by connecting a resonator be- tween XIN and XOUT . To supply a clock signal externally, input it to the XIN pin and make the XOUT pin open. Oscillation control Stop Mode If the STP instruction is executed, the internal clock φ stops at an “H”. Timer 1 is set to “01 16” and prescaler 12 is set to “FF16”. Oscillator restarts when an external interrupt is received, but the internal clock φ remains at an “H” until timer 1 underflow. This allows time for the clock circuit oscillation to stabilize. If oscillator is restarted by a reset, no wait time is generated, so keep the RESET pin at an “L” level until oscillation has stabilized. Wait Mode If the WIT instruction is executed, the internal clock φ stops at an “H” level, but the oscillator itself does not stop. The internal clock restarts if a reset occurs or when an interrupt is received. Since the oscillator does not stop, normal operation can be started immediately after the clock is restarted. To ensure that interrupts will be received to release the STP or WIT state, interrupt enable bits must be set to “1” before the STP or WIT instruction is executed. When the STP status is released, prescaler 12 and timer 1 will start counting and reset will not be released until timer 1 underflows, so set the timer 1 interrupt enable bit to “0” before the STP instruction is executed. Fig. 39 Block diagram of clock generating circuit Fig. 38 External clock input circuit Fig. 37 Ceramic resonator circuit FUNCTIONAL DESCRIPTION C OUT XIN X OUT C IN X IN XOUT Open External oscillation circuit Vss Vcc X OUTXIN R SQ STP instruction WIT instruction R S Q R SQ Reset STP instruction Timer 1 ONW control Prescaler 121/2 f output Internal clock f Rd Rf ONW pin Single-chip mode Reset Interrupt request Interrupt disable flag (I) FF16 0116 Reset or STP instruction

ports P0 to P3 lose their I/O port functions and become bus pins. Outputs low-order byte of address. Outputs high-order byte of address. (including instruction codes). (except that the port latch cannot be read). Table 8. Functions of ports in memory expansion mode and The shaded areas are external memory areas. : YYYY 16 is the start address of internal ROM.

3802 GROUP USER’S MANUAL1-36

Bus control with memory expansion The 3802 group has a built-in ONW function to facilitate access to external memory and I/O devices in memory expansion mode or microprocessor mode. If an “L” level signal is input to the ONW pin when the CPU is in a read or write state, the corresponding read or write cycle is ex- tended by one cycle of φ. During this extended period, the RD or WR signal remains at “L”. This extension period is valid only for writing to and reading from addresses 0000 16 to 000716 and 044016 to FFFF16 in microprocessor mode, 044016 to YYYY16 in memory expansion mode, and only read and write cycles are ex- tended. Fig. 42 ONW function timing FUNCTIONAL DESCRIPTION f Read cycle Write cycleDummy cycle Write cycle Read cycle Dummy cycle AD 15 to AD0 Period during which ONW input signal is received During this period, the ONW signal must be fixed at either “H” or “L”. At all other times, the input level of the ONW signal has no affect on operations. The bus cycles is not extended for an address in the area 0008 16 to 043F16, regardless of whether the ONW signal is received. ] : ]]] ONW WR RD

The contents of the processor status register (PS) after a reset are undefined, except for the interrupt disable flag (I) which is “1”. Af- ter a reset, initialize flags which affect program execution. In particular, it is essential to initialize the index X mode (T) and the decimal mode (D) flags because of their effect on calculations. Interrupts The contents of the interrupt request bits do not change immedi- ately after they have been written. After writing to an interrupt re- quest register, execute at least one instruction before executing a BBC or BBS instruction. Decimal Calculations To calculate in decimal notation, set the decimal mode flag (D) to “1”, then execute an ADC or SBC instruction. Only the ADC and SBC instructions yield proper decimal results. After executing an ADC or SBC instruction, execute at least one instruction before executing a SEC, CLC, or CLD instruction. In decimal mode, the values of the negative (N), overflow (V), and zero (Z) flags are invalid. The carry flag can be used to indicate whether a carry or borrow has occurred. Initialize the carry flag before each calculation. Clear the carry flag before an ADC and set the flag before an SBC. Timers If a value n (between 0 and 255) is written to a timer latch, the fre- quency division ratio is 1/(n + 1). Multiplication and Division Instructions The index X mode (T) and the decimal mode (D) flags do not af- fect the MUL and DIV instruction. The execution of these instructions does not change the contents of the processor status register. Ports The contents of the port direction registers cannot be read. The following cannot be used:

• The data transfer instruction (LDA, etc.)
• The operation instruction when the index X mode flag (T) is “1”
• The addressing mode which uses the value of a direction regis- ter as an index
• The bit-test instruction (BBC or BBS, etc.) to a direction register
• The read-modify-write instruction (ROR, CLB, or SEB, etc.) to a direction register Use instructions such as LDM and STA, etc., to set the port direc- tion registers. Serial I/O In clock synchronous serial I/O, if the receive side is using an ex- ternal clock and it is to output the S RDY1 signal, set the transmit enable bit, the receive enable bit, and the SRDY1 output enable bit to “1”. Serial I/O1 continues to output the final bit from the T XD pin after transmission is completed. The SOUT2 pin from serial I/O2 goes to high impedance after transmission is completed. A-D Converter The comparator uses internal capacitors whose charge will be lost if the clock frequency is too low. Make sure that f(X IN) is at least 500 kHz during an A-D conver- sion. (If the ONW pin has been set to “L”, the A-D conversion will take twice as long to match the longer bus cycle, and so f(X IN) must be at least 1 MHz.) Do not execute the STP or WIT instruction during an A-D conver- sion. D-A Converter The accuracy of the D-A converter becomes poor rapidly under the V CC = 3.0 V or less condition. Instruction Execution Time The instruction execution time is obtained by multiplying the fre- quency of the internal clock φ by the number of cycles needed to execute an instruction. The number of cycles required to execute an instruction is shown in the list of machine instructions. The frequency of the internal clock φ is half of the X IN frequency. When the ONW function is used in modes other than single-chip mode, the frequency of the internal clock φ may be one fourth the X IN frequency. Memory Expansion Mode The memory expansion mode is not available in the following mi- crocomputers.
• M38024M6-XXXSP
• M38024M6-XXXFP Memory Expansion Mode and Microproces- sor Mode Execute the LDM or STA instruction for writing to port P3 (address 000616) in memory expansion mode and microprocessor mode. Set areas which can be read out and write to port P3 (address 0006 16) in a memory, using the read-modify-write instruction (SEB, CLB). NOTE ON PROGRAMMING

3802 GROUP USER’S MANUAL1-38

1. Mask ROM Order Confirmation Form
2. Data to be written to ROM, in EPROM form (three identical

Figure 35 is recommended to verify programming. expose to 150 °C exceeding 100 hours. Table 9. Programming adapter

interrupt enable bit and an interrupt disable flag. Table 10. Interrupt sources, vector addresses and interrupt priority Note: Reset functions in the same way as an interrupt with the highest priority.

FUNCTIONAL DESCRIPTION SUPPLEMENT Timing After Interrupt The interrupt processing routine begins with the machine cycle following the completion of the in- struction that is currently in execution. Figure 44 shows a timing chart after an interrupt occurs, and Figure 45 shows the time up to execu- tion of the interrupt processing routine. Fig. 44 Timing chart after an interrupt occurs Fig. 45 Time up to execution of the interrupt processing routine Generation of interrupt request Main routine Interrupt processing routine 7 to 23 cycles (At performing 8.0 MHz, 1.75 µs to 5.75 µs) 2 cycles 5 cycles Start of interrupt processing 0 to 16 cycles Waiting time for post-processing of pipeline Stack push and Vector fetch [ : at execution of DIV instruction (16 cycles) : CPU operation code fetch cycle : Vector address of each interrupt : Jump destination address of each interrupt : “00 16” or “0116” SYNC BL, BH AL, AH SPS Data bus Not used PC H PC L PS A L AH Address bus S, SPS S-2 , SPSS-1, SPSPC B L BH AL, AH SYNC RD WR

nal operations are performed as follows.

1. After the start of A-D conversion, A-D conversion
2. The highest-order bit of A-D conversion register
3. As a result of comparison, when Vref < VIN, the

value converts into a digital value. Table 11. Change of A-D conversion register during A-D conversion

FUNCTIONAL DESCRIPTION SUPPLEMENT Figures 46 shows A-D conversion equivalent cir- cuit, and Figure 47 shows A-D conversion timing chart. Fig. 46 A-D conversion equivalent circuit Fig. 47 A-D conversion timing chart Write signal for AD/DA control register AD conversion completion bit Sampling clock 50 cycles VSSVCC AV SSVCC AN 0 AN 1 AN 2 AN 3 AN 4 AN 5 AN 6 AN 7 VREF AV SS AD/DA control register Build-in D-A converter Vref Reference clock A-D conversion register A-D conversion interrupt request Chopper amplifier Sampling clock VIN C b1b2 b0 about 2 kΩ

2.1 I/O port

2.2 Timer

2.3 Serial I/O

2.4 PWM

2.5 A-D converter

2.6 Processor mode

2.7 Reset

2-2 3802 GROUP USER’S MANUAL

2.1.1 Memory map of I/O port

Port P0 (P0) Port P0 direction register (P0D) Port P1 (P1) Port P1 direction register (P1D) Port P2 (P2) Port P2 direction register (P2D) Port P3 (P3) Port P3 direction register (P3D) Port P4 (P4) Port P4 direction register (P4D) Port P5 (P5) Port P5 direction register (P5D) Port P6 (P6) Port P6 direction register (P6D) Fig. 2.1.1 Memory map of I/O port related registers

2-33802 GROUP USER’S MANUAL

2.1.2 Related registers

Fig. 2.1.2 Structure of Port Pi (i = 0, 1, 2, 3, 4, 5, 6) Port Pi b7 b6 b5 b4 b3 b2 b1 b0 B Function At resetRW Name Port Pi0 Port Pi1 Port Pi2 Port Pi3 Port Pi4 Port Pi5 Port Pi6 Port Pi7 In output mode Write Read l Port latch In input mode Write : Port latch Read : Value of pins l [Address : 00 16, 0216, 0416, 0616, 0816, 0A16, 0C16] Fig. 2.1.3 Structure of Port Pi direction register (i = 0, 1, 2, 3, 4, 5, 6) Port Pi direction register b7 b6 b5 b4 b3 b2 b1 b0 B Function At resetRW Name Port Pi direction register 0 Port Pi direction register (PiD) (i = 0, 1, 2, 3, 4, 5, 6) [Address : 0116, 0316, 0516, 0716, 0916, 0B16, 0D16] 0 : Port Pi0 input mode 1 : Port Pi0 output mode 0 : Port Pi1 input mode 1 : Port Pi1 output mode 0 : Port Pi2 input mode 1 : Port Pi2 output mode 0 : Port Pi3 input mode 1 : Port Pi3 output mode 0 : Port Pi4 input mode 1 : Port Pi4 output mode 0 : Port Pi5 input mode 1 : Port Pi5 output mode 0 : Port Pi6 input mode 1 : Port Pi6 output mode 0 : Port Pi7 input mode 1 : Port Pi7 output mode

2-4 3802 GROUP USER’S MANUAL

2.1.3 Handling of unused pins

Table 2.1.1 Handling of unused pins (in single-chip mode) Name of Pins/Ports

• Set to the input mode and connect to VCC or VSS through a resistor of 1 k to 10 k .
• Set to the output mode and open at “L” or “H.” Connect to V SS (GND) or open. Connect to VSS (GND). Open (only when using external clock). Handling P0, P1, P2, P3, P4, P5, P6 V REF AV SS X OUT Name of Pins/Ports Handling Table 2.1.2 Handling of unused pins (in memory expansion mode and microprocessor mode) Open
• Set to the input mode and connect to VCC or VSS through a resistor of 1 k to 10 k .
• Set to the output mode and open at “L” or “H.” Connect to V SS (GND) or open. Connect to VCC through a resistor of 1 k to 10 k . Open Open Open Connect to V SS (GND). Open (only when using external clock). P3 0, P31 P4, P5, P6 V REF ____ ONW RESET OUT SYNC AV SS X OUT

2-53802 GROUP USER’S MANUAL APPLICATION

2.2.1 Memory map of timer

Fig. 2.2.1 Memory map of timer related registers 003C 16 002016 002116 002216 002316 002416 002516 002616 002716 003D 16 003E16 003F16 Prescaler 12 (PRE12) Timer 1 (T1) Timer 2 (T2) Timer XY mode register (TM) Prescaler X (PREX) Timer X (TX) Prescaler Y (PREY) Timer Y (TY) Interrupt request register 1 (IREQ1) Interrupt request register 2 (IREQ2) Interrupt control register 1 (ICON1) Interrupt control register 2 (ICON2)

2-6 3802 GROUP USER’S MANUAL

2.2.2 Related registers

Fig. 2.2.2 Structure of Prescaler 12, Prescaler X, Prescaler Y Fig. 2.2.3 Structure of Timer 1 Prescaler 12, Prescaler X, Prescaler Y b7 b6 b5 b4 b3 b2 b1 b0 B Function At resetRW Prescaler 12 (PRE12), Prescaler X (PREX), Prescaler Y (PREY) [Address : 2016, 2416, 2616] The count value of each prescaler is set. The value set in this register is written to both the prescaler and the prescaler latch at the same time. When the prescaler is read out, the value (count value) of the prescaler is read out. l l l b7 b6 b5 b4 b3 b2 b1 b0 B Function At resetRW Timer 1 (T1) [Address : 2116] The count value of the Timer 1 is set. The value set in this register is written to both the Timer 1 and the Timer 1 latch at the same time. When the Timer 1 is read out, the value (count value) of the Timer 1 is read out. l l l Timer 1

2-73802 GROUP USER’S MANUAL APPLICATION Fig. 2.2.4 Structure of Timer 2, Timer X, Timer Y Timer 2, Timer X, Timer Y b7 b6 b5 b4 b3 b2 b1 b0 B Function At resetRW Timer 2 (T2), Timer X (TX), Timer Y (TY) [Address : 2216, 2516, 2716] The count value of each timer is set. The value set in this register is written to both the Timer and the Timer latch at the same time. When the Timer is read out, the value (count value) of the Timer is read out. l l l

2-8 3802 GROUP USER’S MANUAL Fig. 2.2.5 Structure of Timer XY mode register /LiteDiagLines /LiteDiagLines/LiteDiagLines Function Timer XY mode register b7 b6 b5 b4 b3 b2 b1 b0 B At resetR W Timer XY mode register (TM) Name Timer X operating mode bit CNTR 0 active edge switch bit Timer Y operating mode bit CNTR 1 active edge switch bit 0 0 : Timer mode 0 1 : Pulse output mode 1 0 : Event counter mode 1 1 : Pulse width measurement mode 0 0 : Timer mode 0 1 : Pulse output mode 1 0 : Event counter mode 1 1 : Pulse width measurement mode It depends on the operating mode of the Timer X (refer to Table 2.2.1). It depends on the operating mode of the Timer Y (refer to Table 2.2.1). b5 b4 Timer X count stop bit [Address : 2316] b1 b0 Timer Y count stop bit 0 : Count start 1 : Count stop 0 : Count start 1 : Count stop Operating mode of Timer X/Timer Y Timer mode Pulse output mode Event counter mode Pulse width measurement mode Table. 2.2.1 Function of CNTR0/CNTR 1 edge switch bit Function of CNTR0/CNTR 1 edge switch bit (bits 2 and 6) “0” “1” “0” “1” “0” “1” “0” “1”

• Generation of CNTR 0/CNTR 1 interrupt request : Falling edge (No effect on timer count)
• Generation of CNTR 0/CNTR 1 interrupt request : Rising edge (No effect on timer count)
• Start of pulse output : From “H” level
• Generation of CNTR 0/CNTR 1 interrupt request : Falling edge
• Start of pulse output : From “L” level
• Generation of CNTR 0/CNTR 1 interrupt request : Rising edge
• Timer X/Timer Y : Count of rising edge
• Generation of CNTR 0/CNTR 1 interrupt request : Falling edge
• Timer X/Timer Y : Count of falling edge
• Generation of CNTR 0/CNTR 1 interrupt request : Rising edge
• Timer X/Timer Y : Measurement of “H” level width
• Generation of CNTR 0/CNTR 1 interrupt request : Falling edge
• Timer X/Timer Y : Measurement of “L” level width
• Generation of CNTR 0/CNTR 1 interrupt request : Rising edge

2-93802 GROUP USER’S MANUAL APPLICATION Fig. 2.2.7 Structure of Interrupt request register 2 Fig. 2.2.6 Structure of Interrupt request register 1 Interrupt request register 2 b7 b6 b5 b4 b3 b2 b1 b0 B Function At resetRW Interrupt request reigster 2 (IREQ2) [Address : 3D16] Name CNTR 0 interrupt request bit CNTR 1 interrupt request bit Serial I/O2 interrupt request bit 0 : No interrupt request 1 : Interrupt request 0 : No interrupt request 1 : Interrupt request 0 : No interrupt request 1 : Interrupt request 0 : No interrupt request 1 : Interrupt request INT2 interrupt request bit 0 : No interrupt request 1 : Interrupt request Nothing is allocated for this bit. This is a write disabled bit. When this bit is read out, the value is “0.” AD conversion interrupt request bit INT 4 interrupt request bit 0 : No interrupt request 1 : Interrupt request “0” is set by software, but not “1.”[ 4 00 : No interrupt request 1 : Interrupt request INT3 interrupt request bit [ 0 5 Interrupt request register 1 b7 b6 b5 b4 b3 b2 b1 b0 B Function At resetRW Interrupt request reigster 1 (IREQ1) [Address : 3C16] Name “0” is set by software, but not “1.”[ /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines Timer Y interrupt request bit /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines Timer X interrupt request bit Timer 1 interrupt request bit0 : No interrupt request 1 : Interrupt request /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines Timer 2 interrupt request bit 0 : No interrupt request 1 : Interrupt request 0 : No interrupt request 1 : Interrupt request 0 : No interrupt request 1 : Interrupt request 0 : No interrupt request 1 : Interrupt request 0 : No interrupt request 1 : Interrupt request 0 : No interrupt request 1 : Interrupt request 0 : No interrupt request 1 : Interrupt request INT0 interrupt request bit INT1 interrupt request bit Serial I/O1 receive interrupt request bit Serial I/O1 transmit interrupt request bit

2-10 3802 GROUP USER’S MANUAL Fig. 2.2.8 Structure of Interrupt control register 1 Fig. 2.2.9 Structure of Interrupt control register 2 Interrupt control register 2 b7 b6 b5 b4 b3 b2 b1 b0 B Function At resetRW Interrupt control reigster 2 (ICON2) [Address : 3F16] Name CNTR 0 interrupt enable bit CNTR 1 interrupt enable bit Serial I/O2 interrupt enable bit 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabledINT2 interrupt enable bit 0 : Interrupt disabled 1 : Interrupt enabled Fix this bit to “0.” AD conversion interrupt enable bit INT4 interrupt enable bit 0 : Interrupt disabled 1 : Interrupt enabled 4 00 : Interrupt disabled 1 : Interrupt enabled INT 3 interrupt enable bit /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines Timer Y interrupt enable bit/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines Interrupt control register 1 b7 b6 b5 b4 b3 b2 b1 b0 B Function At resetRW Interrupt control register 1 (ICON1) [Address : 3E16] Name INT0 interrupt enable bit INT1 interrupt enable bit 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines Timer X interrupt enable bit Timer 1 interrupt enable bit0 : Interrupt disabled 1 : Interrupt enabled /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines Timer 2 interrupt enable bit 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled Serial I/O1 transmit interrupt enable bit Serial I/O1 receive interrupt enable bit

2-113802 GROUP USER’S MANUAL APPLICATION

2.2.3 Timer application examples

(1) Basic functions and uses [Function 1] Control of Event interval (Timer X, Timer Y, Timer 1, Timer 2) The Timer count stop bit is set to “0” after setting a count value to a timer. Then a timer interrupt request occurs after a certain period. [Use] • Generation of an output signal timing

• Generation of a waiting time [Function 2] Control of Cyclic operation (Timer X, Timer Y, Timer 1, Timer 2) The value of a timer latch is automatically written to a corresponding timer every time a timer underflows, and each cyclic timer interrupt request occurs. [Use] • Generation of cyclic interrupts
• Clock function (measurement of 250m second) Application example 1
• Control of a main routine cycle [Function 3] Output of Rectangular waveform (Timer X, Timer Y) The output level of the CNTR pin is inverted every time a timer underflows (Pulse output mode). [Use] • A piezoelectric buzzer output Application example 2
• Generation of the remote-control carrier waveforms [Function 4] Count of External pulse (Timer X, Timer Y) External pulses input to the CNTR pin are selected as a timer count source (Event counter mode). [Use] • Measurement of frequency Application example 3
• Division of external pulses.
• Generation of interrupts in a cycle based on an external pulse. (count of a reel pulse) [Function 5] Measurement of External pulse width (Timer X, Timer Y) The “H” or “L” level width of external pulses input to CNTR pin is measured (Pulse width measurement mode). [Use] • Measurement of external pulse frequency (Measurement of pulse width of FG pulse ] gener- ated by motor) Application example 4
• Measurement of external pulse duty (when the frequency is fixed) ] FG pulse : Pulse used for detecting the motor speed to control the motor speed.

2-12 3802 GROUP USER’S MANUAL (2) Timer application example 1 : Clock function (measurement of 250 ms) Outline : The input clock is divided by a timer so that the clock counts up every 250 ms. Specifications :• The clock f(XIN) = 4.19 MHz (222 Hz) is divided by a timer.

• The clock is counted at intervals of 250 ms by the Timer X interrupt. Figure 2.2.10 shows a connection of timers and a setting of division ratios, Figures 2.2.11 show a setting of related registers, and Figure 2.2.12 shows a control procedure. Fig. 2.2.10 Connection of timers and setting of division ratios [Clock function] Timer X interrupt request bit 1/16 0 or 11/2561/256f(XIN) =

4.19 MHz

0 : No interrupt request 1 : Interrupt request The clock is divided by 4 by software. 1 second

2-133802 GROUP USER’S MANUAL 255PREX Prescaler X (Address : 2416) 255TX Timer X (Address:2516) Set “division ratio – 1” Timer X interrupt enable bit : Interrupt enabled ICON1 Interrupt control register 1 (Address : 3E16) Timer X interrupt request bit (becomes “1” every 250 ms) IREQ1 Interrupt request register 1 (Address : 3C16) Timer X operating mode bits : Timer mode TM Timer XY mode register (Address : 2316) 001 Timer X count stop bit : Count stop Set to “0” at starting to count. b7 b0 b7 b0 b7 b0 b7 b0 b7 b0 Fig. 2.2.11 Setting of related registers [Clock function]

2-14 3802 GROUP USER’S MANUAL APPLICATION Control procedure : Figure 2.2.12 shows a control procedure. RESET Initialization SEI TM ICON1 PREX TX TM CLI (Address : 2316) (Address : 3E16), bit4 (Address : 2416) (Address : 2516) (Address : 2316), bit3 XXXX 1X 002 256 – 1 256 – 1 All interrupts : Disabled l l l l l l l X : This bit is not used in this application. Set it to “0” or “1.” It’s value can be disregarded. Timer X interrupt processing routine CLT (Note 2) CLD (Note 3) Push register to stack RTI Y N Clock stop? Clock count up (1/4 second-year) Pop registers Check if the clock has already been set. Count up the clock. Pop registers which is pushed to stack Main processing PREX TX IREQ1 .... (Address : 2416) (Address : 2516) (Address : 3C16), bit4 256 – 1 256 – 1 [Processing for completion of setting clock] (Note 1) Note 1: This processing is performed only at completing to set the clock. When restarting the clock from zero second after completing to set the clock, re-set timers. l l l l l Note 2: When using the Index X mode flag (T). Note 3: When using the Decimal mode flag (D). Push the register used in the interrupt processing routine into the stack. Timer X : Timer mode Timer X interrupt : Enabled Set “division ratio – 1” to the Prescaler X and Timer X. Timer X count : Operating Interrupts : Enabled Fig. 2.2.12 Control procedure [Clock function]

2-153802 GROUP USER’S MANUAL (3) Timer application example 2 : Piezoelectric buzzer output Outline : The rectangular waveform output function of a timer is applied for a piezoelectric buzzer output. Specifications :• The rectangular waveform resulting from dividing clock f(XIN) = 4.19 MHz into about 2 kHz (2048 Hz) is output from the P54/CNTR 0 pin.

• The level of the P54/CNTR 0 pin fixes to “H” while a piezoelectric buzzer output is stopped. Figure 2.2.13 shows an example of a peripheral circuit, and Figure 2.2.14 shows a connection of the timer and setting of the division ratio. Fig. 2.2.13 Example of a peripheral circuit Fig. 2.2.14 Connection of the timer and setting of the division ratio [Piezoelectric buzzer output] 244 µs 244 µs 3802 group PiPiPi.... P54/CNTR 0 Set a division ratio so that the underflow output cycle of the Timer X becomes this value. The “H” level is output while a piezoelectric buzzer output is stopped. CNTR 0 output 1/16 1/2f(XIN) = 4.19 MHz Fixed Timer X Fixed 1/64 CNTR 01 Prescaler X

2-16 3802 GROUP USER’S MANUAL APPLICATION Fig. 2.2.15 Setting of related registers [Piezoelectric buzzer output] Control procedure : Figure 2.2.16 shows a control procedure. Fig. 2.2.16 Control procedure [Piezoelectric buzzer output] (Address : 0A16), bit4 (Address : 0B16) (Address : 3E16), bit4 (Address : 2316) (Address : 2516) (Address : 2416) Initialization P5D ICON1 TM TX PREX .... XXXX 10012 64 – 1 1 – 1 A piezoelectric buzzer is requested? RESET Y N Main processing TM (Address : 2316), bit3 0 Timer X interrupts : Disabled During stopping outputting a piezoelectric buzzerDuring outputting a piezoelectric buzzer Output unit l l l TM (Address : 2316), bit3 1 TX (Address : 2516) 64 –1 X : This bit is not used in this application. Set it to “0” or “1.” It’s value can be disregarded. l l The piezoelectric buzzer request occured in the main processing is processed in the output unit. XXX 1XXXX 2 Set “division ratio – 1” to the Prescaler X and Timer X. The CNTR 0 output is stopped at this point (stop outputting a piezoelectric buzzer). 63TX Timer X (Address : 2516) Set “division ratio – 1” 010 CNTR 0 active edge switch bit : Output from the “H” level Timer X count stop bit : Count Stop Set to “0” at starting to count. Timer X operating mode bits : Pulse output mode TM Timer XY mode register (Address : 2316) b7 b0 b7 b0 PREX Prescaler X (Address : 2416) b7 b0

2-173802 GROUP USER’S MANUAL (4) Timer application example 3 : Measurement of frequency Outline : The following two values are compared for judging if the frequency is within a certain range.

• A value counted a pulse which is input to P55/CNTR 1 pin by a timer.
• A referance value Specifications :• The pulse is input to the P55/CNTR 1 pin and counted by the Timer Y.
• A count value is read out at the interval of about 2 ms (Timer 1 interrupt interval : 244 µ s 5 8). When the count value is 28 to 40, it is regarded the input pulse as a valid.
• Because the timer is a down-counter, the count value is compared with 227 to 215 . ] 227 to 215 = 255 (initialized value of counter) – 28 to 40 (the number of valid value). Figure 2.2.17 shows a method for judging if input pulse exists, and Figure 2.2.18 shows a setting of related registers. Input pulse 71.4 µ s or more (14 kHz or less) 71.4 µ s (14 kHz) 50 µ s (20 kHz) 50 µ s or less (20 kHz or more) Invalid Valid Invalid 2 ms 71.4 µ s = 28 counts 2 ms 50 µ s = 40 counts Fig 2.2.17 A method for judging if input pulse exists

2-18 3802 GROUP USER’S MANUAL APPLICATION Fig. 2.2.18 Setting of related registers [Measurement of frequency] 0PREY Prescaler Y (Address : 2616) Set “division ratio – 1” 255TY Timer Y (Address : 2716) Set “255” to this register immediately before counting pulse. (After a certain time, this value is decreased by the number of input pulses) Timer Y interrupt enable bit : Interrupt disabled ICON1 Interrupt control register 1 (Address : 3E16) Judgment of Timer Y interrupt request bit (When this bit is set to “1” at reading out the count value of the Timer Y (address : 27 16), 256 pulses or more are input (at setting 255 to the Timer Y ).) IREQ1 Interrupt request register 1 (Address : 3C16) CNTR 1 active edge switch bit : Count at falling edge Timer Y count stop bit : Count stop Set to “0” at starting to count. Timer Y operating mode bit : Event counter mode TM Timer XY mode register (Address : 2316) b7 b0 Prescaler 12 (Address : 2016) b7 b0 63PRE12 7T1 Timer 1 (Address : 2116) b7 b0 b7 b0 b7 b0 b7 b0 Timer 1 interrupt enable bit : Interrupt enabled b7 b0

2-193802 GROUP USER’S MANUAL Control procedure : Figure 2.2.19 shows a control procedure. Fig. 2.2.19 Control procedure [Measurement of frequency] Timer 1 interrupt processing routine RESET IREQ1 (Address : 3C16), bit5? Initialization SEI TM PRE12 PREY TY ICON1 TM CLI .... (Address : 2316) (Address : 2016) (Address : 2116) (Address : 2616) (Address : 2716) (Address : 3E16), bit6 (Address : 2316), bit7 1110XXXX 2 64–1 8–1 1–1 256–1 (A) TY (Address : 2716) TY IREQ1 (Address : 2716) (Address : 3C16), bit5 256 – 1 Fpulse 0 Fpulse 1 Processing for a result of judgment RTI Out of range In range Compare the count value read with the reference value. Store the comparison result in flag Fpulse. l l CLT (Note 1) CLD (Note 2) Push register to stack Note 1: When using the Index X mode flag (T). Note 2: When using the Decimal mode flag (D). l Push the register used in the interrupt processing routine into the stack. Pop registers Xl :This bit is not used in this application. Set it to “0” or “1.” It’s value can be disregarded. l l Read the count value. Store the count value in the accumulator (A). l l Initialize the count value. Set the Timer Y interrupt request bit to “0.” l When the count value is 256 or more, the processing is performed as out of range. l l l l All interrupts : Disabled Timer Y : Event counter mode (Count at falling edge of pulse input from CNTR1 pin) Set the division ratio so that the Timer 1 interrupt occurs every 2 ms. Timer 1 interrupt : Enabled l l Timer Y count : Start Interrupts : Enabled < <214 (A) 228? Pop registers which is pushed to stack.l

2-20 3802 GROUP USER’S MANUAL APPLICATION (5) Timer application example 4 : Measurement of pulse width of FG pulse generated by motor Outline : The “H” level width of a pulse input to the P54/CNTR 0 pin is counted by Timer X. An underflow is detected by Timer X interrupt and an end of the input pulse “H” level is detected by CNTR 0 interrupt. Specifications : • The “H” level width of a FG pulse input to the P54/CNTR 0 pin is counted by Timer X. (Example : When the clock frequency is 4.19 MHz, the count source would be 3.8 µ s that is obtained by dividing the clock frequency by 16. Measurement can be made up to 250 ms in the range of FFFF to 000016.) Figure 2.2.20 shows a connection of the timer and a setting of the division ration, and Figure 2.2.21 shows a setting of related registers. Fig. 2.2.20 Connection of the timer and setting of the division ratio [Measurement of pulse width] Timer X interrupt request bit 1/16 0 or 11/2561/256 Fixed Prescaler X Timer X 250 ms 0 : No interrupt request 1 : Interrupt request f(XIN) = 4.19 MHz

2-213802 GROUP USER’S MANUAL Fig. 2.2.21 Setting of related registers [Measurement of pulse width] CNTR 0 active edge switch bit : Count “H” level width Timer X operating mode bits : Pulse width measurement mode Timer X count stop bit : Count stop Set to “0” at starting to count. TM Timer XY mode register (Address : 2316) b7 b0 255PREX Prescaler X (Address : 2416) Set “division ratio – 1” 255TX Timer X (Address : 2516) Timer X interrupt enable bit : Interrupt enabled ICON1 Interrupt control register 1 (Address : 3E16) b7 b0 b7 b0 b7 b0 CNTR 0 interrupt enable bit : Interrupt enabled ICON2 Interrupt control register 2 (Address : 3F16) CNTR 0 interrupt request bit (This bit is set to “1” at completion of inputting “H” level si gnal.) IREQ2 Interrupt request register 2 (Address : 3D16) b7 b0 b7 b0 Timer X interrupt request bit (This bit is set to “1” at underflow of Timer X.) IREQ1 Interrupt request register (Address : 3C16) b7 b0

2-22 3802 GROUP USER’S MANUAL APPLICATION Figure 2.2.22 shows a control procedure. (Address : 2316) (Address : 2416) (Address : 2516) (Address : 3E16), bit4 (Address : 3C16), bit4 (Address : 3F16), bit0 (Address : 3D16), bit0 (Address : 2316), bit3 All interrupts : Disabledl XXXX 10112 256–1 256–1 RESET Initialization CNTR 0 interrupt processing routine CLT (Note 1) CLD (Note 2) Push register to stack RTI Pop registers Timer X interrupt processing routine Processing for error RTI Error occursl l l l l A count value is read out and stored to RAM. Set the division ratio so that the Timer X interrupt occurs every 250 ms. l l SEI TM PREX TX ICON1 IREQ1 ICON2 IREQ2 TM CLI .... .... .... X : This bit is not used in this application. Set it to “0” or “1.” It’s value can be disregarded. PREX(A) Result of pulse width measurement low–order 8-bit (A) Result of pulse width measurement high–order 8-bit PREX (Address : 24 16) TX (Address : 2516) Inversion of (A) TX 256– 1 Inversion of (A) 256 – 1 Push the register used in the interrupt processing routine into the stack. Pop registers which is pushed to stack. Timer X : Pulse width measurement mode (Count “H” level width of pulse input from CNTR0 pin.) Set the division ratio so that the Timer X interrupt occurs every 250 ms. l Note 1:When using the Index X mode flag (T). Note 2: When using the Decimal mode flag (D). CNTR 0 interrupt : Enabled l Timer X interrupt : Enabled l l Timer X count : Operating Interrupts : Enabled l Fig. 2.2.22 Control procedure [Measurement of pulse width]

2-233802 GROUP USER’S MANUAL APPLICATION

2.3.1 Memory map of serial I/O

Fig. 2.3.1 Memory map of serial I/O related registers 001F16 001816 001916 001A16 001B16 001C 16 001D 16 Transm it/Receive buffer register (TB/RB ) Serial I/O1 status register (SIO1STS) Serial I/O1 control register (SIO1CON) UART control register (UART CO N) Baud rate generator (BRG) Serial I/O2 control register (SIO2CO N) Serial I/O2 register (SIO2 ) 003F16 003A16 003C 16 003D 16 003E16 Interrupt edge select ion register (INT EDGE) Interrupt request register 1 (IREQ 1) Interrupt request register 2 (IREQ 2) Interrupt control register 2 (ICO N2) Interrupt control register 1 (ICO N1)

2-24 3802 GROUP USER’S MANUAL APPLICATION

2.3.2 Related registers

Transmit/Receive buffer register b7 b6 b5 b4 b3 b2 b1 b0 B Function At resetRW Transmit/Receive buffer register (TB/RB) [Address : 1816] A transmission data is written to or a receive data is read out from this buffer register.

• At writing : a data is written to the Transmit buffer register.
• At reading : a content of the Receive buffer register is read out. 5 ? Note: A content of the transmit buffer register cannot be read out. A data cannot be written to the receive buffer register. Fig. 2.3.2 Structure of Transmit/Receive buffer register b7 b6 b5 b4 b3 b2 b1 b0 B Function At resetRW Serial I/O1 status register (SIO1STS) [Address : 1916] Name Transmit buffer empty flag (TBE) 0 : (OE) (PE) (FE) = 0 1 : (OE) (PE) (FE) = 1 Overrun error flag (OE) 0 : Buffer full 1 : Buffer empty Nothing is allocated for this bit. It is a write disabled bit. When this bit is read out, the value is “0.” Receive buffer full flag (RBF) Transmit shift register shift completion flag (TSC) Parity error flag (PE) Framing error flag (FE) Summing error flag (SE) 0 : Buffer empty 1 : Buffer full 0 : Transmit shift in progress 1 : Transmit shift completed 0 : No error 1 : Overrun error 0 : No error 1 : Parity error 0 : No error 1 : Framing error Serial I/O1 status register Fig. 2.3.3 Structure of Serial I/O1 status register

2-253802 GROUP USER’S MANUAL APPLICATION Fig. 2.3.4 Structure of Serial I/O1 control register Fig. 2.3.5 Structure of UART control register Serial I/O1 synchronous clock selection bit (SCS) SRDY1 output enable bit (SRDY) Transmit interrupt source selection bit (TIC) Serial I/O1 control register b7 b6 b5 b4 b3 b2 b1 b0 B Function At resetRW 0 : f(XIN) 1 : f(XIN)/4 0 Serial I/O1 control register (SIO1CON) [Address : 1A16] Name BRG count source selection bit (CSS) Serial I/O1 enable bit (SIOE) 0 : I/O port (P47) 1 : SRDY1 output pin Transmit enable bit (TE) Receive enable bit (RE) Serial I/O1 mode selection bit (SIOM) 0 : Transmit buffer empty 1 : Transmit shift operating completion 0 : Transmit disabled 1 : Transmit enabled 0 : Receive disabled 1 : Receive enabled 0 : UART 1 : Clock synchronous serial I/O 0 : Serial I/O1 disabled (P44–P47 : I/O port) 1 : Serial I/O1 enabled (P44–P47 : Serial I/O function pin) At selecting clock synchronous serial I/O 0 : BRG output divided by 4 1 : External clock input At selecting UART 0 : BRG output divided by 16 1 : External clock input divided by 16 In output mode 0 : CMOS output 1 : N-channel open-drain output UART control register b7 b6 b5 b4 b3 b2 b1 b0 B Function At resetRW UART control register (UARTCON) [Address : 1B16] Name 0 : 8 bits 1 : 7 bits 0 : Parity checking disabled 1 : Parity checking enabled 0 : 1 stop bit 1 : 2 stop bits 0 : Even parity 1 : Odd parity Character length selection bit (CHAS) Parity enable bit (PARE) Stop bit length selection bit (STPS) Parity selection bit (PARS) P45/TxD P-channel output disable bit (POFF) Nothing is allocated for these bits. These are write disabled bits. When these bits are read out, the values are “1.”

2-26 3802 GROUP USER’S MANUAL APPLICATION A count value of Baud rate generator is set. Function Baud rate generator (BRG) [Address : 1C16] Baud rate generator b7 b6 b5 b4 b3 b2 b1 b0 B At resetRW Fig. 2.3.6 Structure of Baud rate generator Fig. 2.3.7 Structure of Serial I/O2 control register Serial I/O2 control register (SIO2CON) [Address : 1D16] Serial I/O2 control register b7 b6 b5 b4 b3 b2 b1 b0 B Function At resetRW Name SRDY2 output enable bit Internal synchronous clock selection bits 0 : I/O port (P51, P52) 1 : SOUT2 , SCLK2 output pin 0 : I/O port (P53) 1 : SRDY2 output pin 0 : LSB first 1 : MSB first 0 : External clock 1 : Internal clock 0 0 0 : f(XIN)/8 0 0 1 : f(XIN)/16 0 1 0 : f(XIN)/32 0 1 1 : f(XIN)/64 1 1 0 : f(XIN)/128 1 1 1 : f(XIN)/256 Transfer direction selection bit Serial I/O2 port selection bit Serial I/O2 synchronous clock selection bit P51/SOUT2 P-channel output disable bit b2 b1 b0 0 : CMOS output 1 : N-channel open-drain output In output mode

2-273802 GROUP USER’S MANUAL APPLICATION Fig. 2.3.9 Structure of Interrupt edge selection register Fig. 2.3.8 Structure of Serial I/O2 register Serial I/O2 register b7 b6 b5 b4 b3 b2 b1 b0 Function Serial I/O2 register (SIO2) [Address : 1F16] A shift register for serial transmission and reception. At transmitting : Set a transmission data. At receiving : Store a reception data. B At resetRW l l WR Interrupt edge selection register b7 b6 b5 b4 b3 b2 b1 b0 B Function At reset Interrupt edge selection register (INTEDGE) [Address : 3A16] Name 0 : Falling edge active 1 : Rising edge active 0 : Falling edge active 1 : Rising edge active 0 : Falling edge active 1 : Rising edge active 0 : Falling edge active 1 : Rising edge active 0 : Falling edge active 1 : Rising edge active INT0 interrupt edge selection bit INT1 interrupt edge selection bit INT2 interrupt edge selection bit INT3 interrupt edge selection bit INT4 interrupt edge selection bit Nothing is allocated for this bit. This is a write disabled bit.When this bit is read out, the value is “0.” Nothing is allocated for these bits. These are write disabled bits. When these bits are read out, the values are “0.”

2-28 3802 GROUP USER’S MANUAL APPLICATION Serial I/O1 receive interrupt request bit Interrupt request register 1 b7 b6 b5 b4 b3 b2 b1 b0 B Function At resetRW Interrupt request reigster 1 (IREQ1) [Address : 3C16] Name INT0 interrupt request bit INT1 interrupt request bit 0 : No interrupt request 1 : Interrupt request 0 : No interrupt request 1 : Interrupt request 0 : No interrupt request 1 : Interrupt request 0 : No interrupt request 1 : Interrupt request Serial I/O1 transmit interrupt request bit Timer Y interrupt request bit Timer 1 interrupt request bit0 : No interrupt request 1 : Interrupt request Timer 2 interrupt request bit 0 : No interrupt request 1 : Interrupt request 0 : No interrupt request 1 : Interrupt request 0 : No interrupt request 1 : Interrupt request [ “0” is set by software, but not “1.” Timer X interrupt request bit Fig. 2.3.10 Structure of Interrupt request register 1 Fig. 2.3.11 Structure of Interrupt request register 2 Interrupt request register 2 b7 b6 b5 b4 b3 b2 b1 b0 B Function At resetRW Interrupt request reigster 2 (IREQ2) [Address : 3D16] Name CNTR 0 interrupt request bit CNTR 1 interrupt request bit Serial I/O2 interrupt request bit 0 : No interrupt request 1 : Interrupt request 0 : No interrupt request 1 : Interrupt request 0 : No interrupt request 1 : Interrupt request 0 : No interrupt request 1 : Interrupt requestINT2 interrupt request bit 0 : No interrupt request 1 : Interrupt request Nothing is allocated for this bit. This is a write disabled bit. When this bit is read out, the value is “0.” AD conversion interrupt request bit INT 4 interrupt request bit 0 : No interrupt request 1 : Interrupt request [ “0” is set by software, but not “1.” 4 00 : No interrupt request 1 : Interrupt request INT3 interrupt request bit [ 0 5

2-293802 GROUP USER’S MANUAL APPLICATION Fig. 2.3.12 Structure of Interrupt control register 1 Fig. 2.3.13 Structure of Interrupt control register 2 Timer Y interrupt enable bit Interrupt control register 1 b7 b6 b5 b4 b3 b2 b1 b0 B Function At resetRW Interrupt control register 1 (ICON1) [Address : 3E16] Name INT0 interrupt enable bit INT1 interrupt enable bit 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled Timer X interrupt enable bit Timer 1 interrupt enable bit0 : Interrupt disabled 1 : Interrupt enabled Timer 2 interrupt enable bit 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled Serial I/O1 transmit interrupt enable bit Serial I/O1 receive interrupt enable bit Interrupt control register 2 b7 b6 b5 b4 b3 b2 b1 b0 B Function At resetRW Interrupt control reigster 2 (ICON2) [Address : 3F16] Name CNTR 0 interrupt enable bit CNTR 1 interrupt enable bit Serial I/O2 interrupt enable bit 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled INT2 interrupt enable bit 0 : Interrupt disabled 1 : Interrupt enabled Fix this bit to “0.” AD conversion interrupt enable bit INT4 interrupt enable bit 0 : Interrupt disabled 1 : Interrupt enabled 4 00 : Interrupt disabled 1 : Interrupt enabled INT 3 interrupt enable bit

2-30 3802 GROUP USER’S MANUAL APPLICATION

2.3.3 Serial I/O connection examples

(1) Control of peripheral IC equipped with CS pin There are connection examples using a clock synchronous serial I/O mode. Figure 2.3.14 shows connection examples of a peripheral IC equipped with the CS pin. Fig. 2.3.14 Serial I/O connection examples (1) Port SCLK TXD R XD Port CS CLK IN OUT CS CLK IN OUT (4) Connecting ICs 3802 group Peripheral IC 1 Peripheral IC 2 Port SCLK TXD CS CLK IN OUT (2) Transmission and reception 3802 group Peripheral IC (E PROM etc.) (3) Transmission and reception (Pins R XD and TXD are connected) (Pins IN and OUT in peripheral IC are connected) CS CLK IN OUT 3802 group Peripheral IC (E PROM etc.) [ 2 “Port” is an output port controlled by software. Use SOUT and SIN instead of TXD and RXD in the serial I/O2. Notes1: Port SCLK TXD CS CLK DATA (1) Only transmission (using the R XD pin as an I/O port) 3802 group Peripheral IC (OSD controller etc.) [ 1 [ 1: Select an N-channel open-drain output control of TXD pin. 2: Use such OUT pin of peripheral IC as an N-channel open- drain output in high impedance during receiving data. Port SCLK TXD R XD R XD

2-313802 GROUP USER’S MANUAL APPLICATION (2) Connection with microcomputer Figure 2.3.15 shows connection examples of the other microcomputers. Fig. 2.3.15 Serial I/O connection examples (2) (4) Using UART SCLK TXD R XD CLK IN OUT (2) Selecting an external clock 3802 group Microcomputer (3) Using the SRDY siganl output function (Selecting an external clock) SRDY SCLK TXD R XD RDY CLK IN OUT 3802 group Microcomputer CLK IN OUT (1) Selecting an internal clock 3802 group Microcomputer [ : UART can not be used in the serial I/O2 Note: Use SOUT and SIN instead of TXD and RXD in the serial I/O2. R XD TXD SCLK TXD R XD R XD TXD 3802 group Microcomputer

2-32 3802 GROUP USER’S MANUAL APPLICATION

2.3.4 Setting of serial I/O transfer data format

A clock synchronous or clock asynchronous (UART) is selected as a data format of the serial I/O1. The serial I/O2 operates in a clock synchronous. Figure 2.3.16 shows a setting of serial I/O transfer data format. Fig. 2.3.16 Setting of Serial I/O transfer data format 1ST-8DATA-1SP ST LSB Serial I/O1 UART Clock synchronous Serial I/O 1ST-7DATA-1SP ST LSB 1ST-8DATA-1PAR-1SP ST LSB 1ST-7DATA-1PAR-1SP ST LSB 1ST-8DATA-2SP ST LSB 1ST-7DATA-2SP ST LSB 1ST-8DATA-1PAR-2SP ST LSB 1ST-7DATA-1PAR-2SP ST LSB MSB SP MSB SP MSB PAR SP MSB PAR SP MSB 2SP MSB 2SP MSB PAR 2SP MSB PAR 2SP LSB first Serial I/O2 Clock synchronous Serial I/O LSB first MSB first ST : Start bit SP : Stop bit PAR : Parity bit

2-333802 GROUP USER’S MANUAL APPLICATION

2.3.5 Serial I/O application examples

(1) Communication using a clock synchronous serial I/O (transmit/receive) Outline : 2-byte data is transmitted and received through the clock synchronous serial I/O. The SRDY signal is used for communication control. Fig. 2.3.17 Connection diagram [Communication using a clock synchronous serial I/O] Specifications : • The Serial I/O1 is used (clock synchronous serial I/O is selected)

• Synchronous clock frequency : 125 kHz (f(XIN) = 4 MHz is divided by 32)
• The S RDY1 (receivable signal) is used.
• The receiving side outputs the S RDY1 signal at intervals of 2 ms (generated by timer), and 2-byte data is transferred from the transmitting side to the receiving side. Fig. 2.3.18 Timing chart [Communication using a clock synchronous serial I/O]
• • • •D 0 D 4D 2D 1 D 6D 5 D 7D 3 D 0 D 4D 2D 1 D 6D 5 D 7D 3 D 0 D 1
• • • •
• • • • TXD SCLK1 SRDY1 2 ms P41/INT0 SCLK1 TXD 3802 group SRDY1 SCLK R XD 3802 group Transmitting side Receiving side

2-34 3802 GROUP USER’S MANUAL APPLICATION Fig. 2.3.19 Setting of related registers at a transmitting side [Communication using a clock synchronous serial I/O] Serial I/O1 status register (Address : 1916) SIO1STS Transmit buffer empty flag

• Check to be transferred data from the Transmit buffer register to Transmit shift register.
• Writable the next transmission data to the Transmit buffer register at being set to “1.” Transmitting side Transmit shift register shift completion flag Check a completion of transmitting 1-byte data with this flag “1” : Transmit shift completed b7 b0 Interrupt edge selection register (Address : 3A16) INTEDGE INT0 active edge selection bit : Select INT0 falling edge b7 b0 Baud rate generator (Address : 1C16) BRG Set “division ratio – 1”7 b7 b0 Serial I/O1 control register (Address : 1A16) SIO1CON BRG counter source selection bit : f(XIN) Serial I/O1 synchronous clock selection bit : BRG/4 Transmit enable bit : Transmit enabled Receive enable bit : Receive disabled Serial I/O1 mode selection bit : Clock synchronous serial I/O Serial I/O1 enable bit : Serial I/O1 enabled b7 b0 00011 1

2-353802 GROUP USER’S MANUAL APPLICATION Fig. 2.3.20 Setting of related registers at a receiving side [Communication using a clock synchronous serial I/O] b7 b0 b7 b0 Receiving side Serial I/O1 control register (Address : 1A16) SIO1CON Serial I/O1 synchronous clock selection bit : External clock SRDY1 output enable bit : Use the SRDY1 output Transmit enable bit : Transmit enabled Set this bit to “1,” using SRDY1 output. Receive enable bit : Receive enabled Sirial I/O1 mode selection bit : Clock synchronous serial I/O Serial I/O1 enable bit : Serial I/O1 enabled Serial I/O1 status register (Address : 1916) SIO1STS Receive buffer full flag Check a completion of receiving 1-byte data with this flag. “1” : At completing to receive “0” : At reading out a receive buffer111111

2-36 3802 GROUP USER’S MANUAL APPLICATION Control procedure : Figure 2.3.21 shows a control procedure at a transmitting side, and Figure 2.3.22 shows a control procedure at a receiving side. Fig. 2.3.21 Control procedure at a transmitting side [Communication using a clock synchronous serial I/O] RESET Initialization (Address : 1A16) (Address : 1C16) (Address : 3A16), bit0 SIO1CON BRG INTEDGE 8—1 TB/RB (Address : 1816) The first byte of a transmission data

• Write a transmission data The Transmit buffer empty flag is set to “0” by this writing.
• Detect INT 0 falling edgeIREQ1 (Address:3C16), bit0?
• Check to be transfered data from the Transmit buffer register to the Transmit shift register. (Transmit buffer empty flag) SIO1STS (Address : 19 16), bit0? TB/RB (Address : 1816) • Write a transmission data The transmit buffer empty flag is set to “0” by this writing. The second byte of a transmission data
• Check to be transfered data from the Transmit buffer register to the Transmit shift register. (Transmit buffer empty flag) SIO1STS (Address : 19 16), bit0?
• Check a shift completion of the Transmit shift register (Transmit shift register shift completion flag) SIO1STS (Address : 1916), bit2? IREQ1 (Address : 3C16), bit0 0 X : This bit is not used in this application. Set it to “0” or “1.” It’s value can be disregarded. l 1101XX 002

2-373802 GROUP USER’S MANUAL APPLICATION Fig. 2.3.22 Control procedure at a receiving side [Communication using a clock synchronous serial I/O] Pass 2 ms? RESET Initialization SIO1CON (Address : 1A16) 1111X 11X 2 TB/RB (Address : 1816) Dummy data • SRDY1 output SRDY1 signal is output by writing data to the TB/RB. Using the SRDY1 , the transmit enabled bit (bit4) of the SIO1CON is set to “1.”

• An interval of 2 ms is generated by a timer. Y N
• Check a completion of receiving (Receive buffer full flag) SIO1STS (Address : 1916), bit1? Read out reception data from TB/RB (Address : 1816)
• Receive the first byte data. A Receive buffer full flag is set to “0” by reading data.
• Check a completion of receiving (Receive buffer full flag) SIO1STS (Address : 1916), bit1? Read out reception data from TB/RB (Address : 1816)
• Receive the second byte data. A Receive buffer full flag is set to “0” by reading data. X : This bit is not used in this application. Set it to “0” or “1.” It’s value can be disregarded. l

2-38 3802 GROUP USER’S MANUAL APPLICATION (2) Output of serial data (control of a peripheral IC) Outline : 4-byte data is transmitted and received through the clock synchronous serial I/O. The CS signal is output to a peripheral IC through the port P53. Fig. 2.3.23 Connection diagram [Output of serial data] P53 SCLK1 TXD CS Peripheral IC3802 group (1) Example for using Serial I/O1 (2) Example for using Serial I/O2 DATA CS CLK P53 SCLK2 SOUT2 Peripheral IC3802 group DATA CS CLKCLK DATA CS CLK DATA Specifications : • The Serial I/O is used. (clock synchronous serial I/O is selected)

• Synchronous clock frequency : 125 kHz (f(XIN) = 4 MHz is divided by 32)
• Transfer direction : LSB first
• The Serial I/O interrupt is not used. ___
• The Port P53 is connected to the CS pin (“L” active) of the peripheral IC for a transmission control (the output level of the port P53 is controlled by software). Figre 2.3.24 shows an output timing chart of serial data. Fig. 2.3.24 Timing chart [Output of serial data] CS DO 0 DO 1 DO 2 DO 3 CLK DATA Note: The SOUT2 pin is in high impedance after completing to transfer data, using the serial I/O2

2-393802 GROUP USER’S MANUAL APPLICATION Figure 2.3.25 shows a setting of serial I/O1 related registers, and Figure 2.3.26 shows a setting of serial I/O1 transmission data. Fig. 2.3.26 Setting of serial I/O1 transmission data [Output of serial data] Fig. 2.3.25 Setting of serial I/O1 related registers [Output of serial data] Serial I/O1 synchronous clock selection bit : BRG/4 SRDY1 output enable bit : Not use the SRDY1 signal output function Serial I/O1 transmit interrupt enable bit : Interrupt disabled ICON1 Interrupt control register 1 (Address : 3E16) Serial I/O1 transmit interrupt request bit Using this bit, check the completion of transmitting 1-byte base data. “1” : Transmit shift completion IREQ1 Interrupt request register 1 (Address : 3C16) 001SIO1CON Serial I/O1 control register (Address : 1A16) 0011 BRG count source selection bit : f(XIN) Transmit interrupt source selection bit : Transmit shift operating completion Transmit enable bit : Transmit enabled Receive enable bit : Receive disabled b7 b0 b7 b0 b7 b0 Serial I/O1 mode selection bit : Clock synchronous serial I/O Serial I/O1 enable bit : Serial I/O1 enabled P45/TXD P-channel output disable bit : CMOS output UARTCON UART control register (Address : 1B16) b7 b0

7 Set “division ratio – 1”BRG

Baud rate generator (Address : 1C16) b7 b0 Set a transmission data. Check that transmission of the previous data is completed before writing data (bit 3 of the Interrupt re quest register 1 is set to “1”). TB/RB Transmit/Receive buffer register (Address : 1816) b7 b0

Control procedure : When the registers are set as shown in Fig. 2.3.25, the Serial I/O1 can transmit 1-byte data simply by writing data to the Transmit buffer register. Thus, after setting the CS signal to “L,” write the transmission data to the Receive buffer register on a 1-byte base, and return the CS signal to “H” when the desired number of bytes have been transmitted. Figure 2.3.27 shows a control procedure of serial I/O1. P5 (Address : 0A16), bit3 0 N Y IREQ1 (Address : 3C16), bit3? Complete to transmit data? Initialization SIO1CON UARTCON BRG ICON1 P5D .... .... (Address : 1A16) (Address : 1B16), bit4 (Address : 1C16) (Address : 3E16), bit3 (Address : 0A16), bit3 (Address : 0B16) 110110002 XXXX 1XXX 2 IREQ1 (Address : 3C16), bit3 0 TB/RB (Address : 1816) P5 (Address : 0A16), bit3 1 a transmission data X : This bit is not used in this application. Set it to “0” or “1.” It’s value can be disregarded. Set the Serial I/O1. Set the CS signal output level to “L.” Set the Serial I/O1 transmit interrupt request bit to “0.” Write a transmission data. (start to transmit 1-byte data) Check the completion of transmitting 1- byte data. Use any of RAM area as a counter for counting the number of transmitted bytes. Check that transmission of the target number of bytes has been completed. Return the CS signal output level to “H” when transmission of the target number of bytes is completed. l l l l l l l l l l Serial I/O1 transmit interrupt : Disabled Set the CS signal output port. (“H” level output) RESET l 8–1 Fig. 2.3.27 Control procedure of serial I/O1 [Output of serial data]

2-413802 GROUP USER’S MANUAL Figure 2.3.28 shows a setting of serial I/O2 related registers, and Figure 2.3.29 shows a setting of serial I/O2 transmission data. Serial I/O2 port selection bit : Use the Serial I/O2 SRDY2 output enable bit : Not use the SRDY2 signal output function Serial I/O2 interrupt enable bit : Interrupt disabled ICON2 Interrupt control register 2 (Address : 3F16) Serial I/O2 interrupt request bit Using this bit, check the completion of transmitting 1-byte base data. “1” : Transmit completion IREQ2 Interrupt request register 2 (Address : 3D16) 010SIO2CON Serial I/O2 control register (Address : 1D16) 0011 Internal synchronous clock selection bits : f(XIN)/32 Transfer direction selection bit : LSB first Serial I/O2 synchronous clock selection bit : Internal clock P51/SOUT2 P-channel output disable bit : CMOS output b7 b0 b7 b0 b7 b0 Fig. 2.3.28 Setting of serial I/O2 related registers [Output of serial data] Fig. 2.3.29 Setting of serial I/O2 transmission data [Output of serial data] Set a transmission data. Check that transmission of the previous data is completed before writing data (bit 2 of the Interrupt re quest register 2 is set to “1”). SIO2 Serial I/O2 register (Address : 1F16) b7 b0

Control procedure : When the registers are set as shown in Fig. 2.3.28, the Serial I/O2 can transmit 1-byte data simply by writing data to the Serial I/O2 register. Thus, after setting the CS signal to “L,” write the transmission data to the Serial I/O1 register on a 1-byte base, and return the CS signal to “H” when the desired number of bytes have been transmitted. Figure 2.3.30 shows a control procedure of serial I/O2. Fig. 2.3.30 Control procedure of serial I/O2 [Output of serial data] Complete to transmit data? Set the Serial I/O2 control register. Serial I/O2 interrupt : Disabled Set the CS signal output port. (“H” level output) Set the CS signal output level to “L.” Set the Serial I/O2 interrupt request bit to “0.” Write a transmission data. (start to transmit 1-byte data) Check the completion of transmitting 1- byte data. Use any of RAM area as a counter for counting the number of transmitted bytes. Check that transmission of the target number of bytes has been completed. Return the CS signal output level to “H” when transmission of the target number of bytes is completed. RESET P5 (Address : 0A 16), bit3 0 N Y IREQ2 (Address : 3D16), bit2? IREQ2 (Address : 3D16), bit2 0 SIO2 (Address : 1F16) P5 (Address : 0A16), bit3 1 a transmission data l l l l l l l l l X : This bit is not used in this application. Set it to “0” or “1.” It’s value can be disregarded. l Initialization SIO2CON ICON2 P5D (Address : 1D16) (Address : 3F16), bit2 (Address : 0A16), bit3 (Address : 0B16) 010010102 XXXX 1XXX 2 l

2-433802 GROUP USER’S MANUAL (3) Cyclic transmission or reception of block data (data of a specified number of bytes) between microcomputers [without using an automatic transfer] Outline : When a clock synchronous serial I/O is used for communication, synchronization of the clock and the data between the transmitting and receiving sides may be lost because of noise included in the synchronizing clock. Thus, it is necessary to be corrected constantly. This “heading adjustment” is carried out by using the interval between blocks in this example. Fig. 2.3.31 Connection diagram [Cyclic transmission or reception of block data between microcomputers] SCLK Master unit SCLK Slave unit Note: Use SOUT and SIN instead of TXD and RXD in the serial I/O2. TXD R XD TXD R XD Specifications :• The serial I/O1 is used (clock synchronous serial I/O is selected).

• Synchronous clock frequency : 131 kHz (f(XIN) = 4.19 MHz is divided by 32)
• Byte cycle: 488 µs
• Number of bytes for transmission or reception : 8 byte/block
• Block transfer cycle : 16 ms
• Block transfer period : 3.5 ms
• Interval between blocks : 12.5 ms
• Heading adjustive time : 8 ms Limitations of the specifications 1. Reading of the reception data and setting of the next transmission data must be completed within the time obtained from “byte cycle – time for transferring 1-byte data” (in this example, the time taken from generating of the Serial I/O1 receive interrupt request to generating of the next synchronizing clock is 431 µ s). 2. “Heading adjustive time < interval between blocks” must be satisfied.

The communication is performed according to the timing shown below. In the slave unit, when a synchronizing clock is not input within a certain time (heading adjustive time), the next clock input is processed as the beginning (heading) of a block. When a clock is input again after one block (8 byte) is received, the clock is ignored. Figure 2.3.33 shows a setting of related registers. Fig. 2.3.32 Timing chart [Cyclic transmission or reception of block data between microcomputers] D 0 Byte cycle Block transfer period Block transfer cycle D 1 D 2 D 7 D 0 Interval between blocks Processing for heading adjustment Heading adjustive time Fig. 2.3.33 Setting of related registers [Cyclic transmission or reception of block data between microcomputers] Master unit Transmit enabled SIO1CON Serial I/O1 control register (Address : 1A16) Synchronous clock : BRG/4 Transmit interrupt source : Transmit shift operating completion Receive enabled Clock synchronous serial I/O 011110 01 Serial I/O1 enabled BRG count source : f(XIN) Not use the SRDY1 output Not be effected by external clock Transmit enabled SIO1CON Serial I/O1 control register (Address : 1A16) Not use the serial I/O1 transmit interrupt Receive enabled Clock synchronous serial I/O 111 1 Slave unit Serial I/O1 enabled Synchronous clock : External clock Not use the SRDY1 output UARTCON UART control register (Address : 1B16) P45/TXD pin : CMOS output Both of units b7 b0 7BRG b7 b0 Baud rate generator (Address : 1C16) Set “division ratio – 1” b7 b0 b7 b0

2-453802 GROUP USER’S MANUAL Control procedure : Control in the master unit After a setting of the related registers is completed as shown in Figure 2.3.33, in the master unit transmission or reception of 1-byte data is started simply by writing transmission data to the Transmit buffer register. To perform the communication in the timing shown in Figure 2.3.32, therefore, take the timing into account and write transmission data. Read out the reception data when the Serial I/O1 transmit interrupt request bit is set to “1,” or before the next transmission data is written to the Transmit buffer register. A processing example in the master unit using timer interrupts is shown below. Interrupt processing routine executed every 488 µ s Write a transmission data Read a reception data NWithin a block transfer period? Y YComplete to transfer a block? N RTI Write the first transmission data (first byte) in a block Count a block interval counter NStart a block transfer? Y Generate a certain block interval by using a timer or other functions. Check the block interval counter and determine to start of a block transfer. l l CLT (Note 1) CLD (Note 2) Push register to stack Note 1: When using the Index X mode flag (T). Note 2: When using the Decimal mode flag (D). Push the register used in the interrupt processing routine into the stack. l Pop registers Pop registers which is pushed to stack. l Fig. 2.3.34 Control in the master unit À

\` Control in the slave unit After a setting of the related registers is completed as shown in Figure 2.3.33, the slave unit becomes the state which is received a synchronizing clock at all times, and the Serial I/O1 receive interrupt request bit is set to “1” every time an 8-bit synchronous clock is received. By the serial I/O1 receive interrupt processing routine, the data to be transmitted next is written to the Transmit buffer register after received data is read out. However, if no serial I/O1 receive interrupt occurs for more than a certain time (head adjustive time), the following processing will be performed. 1. The first 1 byte data of the transmission data in the block is written into the Transmit buffer register. 2. The data to be received next is processed as the first 1 byte of the received data in the block. Figure 2.3.35 shows the control in the slave unit using a serial I/O1 receive interrupt and any timer interrupt (for head adjustive). Fig. 2.3.35 Control in the slave unit Write a transmission data Read a reception data NWithin a block transfer period? Y Y A received byte counter ≥ 8? N RTI Write any data (FF16) A received byte counter +1 Heading adjustive counter Initialized value (Note 3) Serial I/O1 receive interrupt processing routine Timer interrupt processing routine Heading adjustive counter – 1 NHeading adjustive counter = 0? Y RTI Write the first transmission data (first byte) in a block A received byte counter0 Check the received byte counter to judge if a block has been transfered. In this example, set the value which is equal to the heading adjustive time divided by the timer interrupt cycle as the initialized value of the heading adjustive counter. For example: When the heading adjustive time is 8 ms and the timer interrupt cycle is 1 ms, set 8 as the initialized value. l CLT (Note 1) CLD (Note 2) Push register to stack Push the register used in the interrupt processing routine into the stack. l CLT (Note 1) CLD (Note 2) Push register to stack Push the register used in the interrupt processing routine into the stack. l Pop registers Pop registers which is pushed to stack. l Pop registers Pop registers which is pushed to stack. l Notes 1: When using the Index X mode flag (T). 2: When using the Decimal mode flag (D).

2-473802 GROUP USER’S MANUAL (4) Communication (transmit/receive) using an asynchronous serial I/O (UART) Point : 2-byte data is transmitted and received through an asynchronous serial I/O. The port P40 is used for communication control. Fig. 2.3.36 Connection diagram [Communication using UART] Transmitting side P40 3802 group P40 3802 group Receiving side TXD XDR Specifications : • The Serial I/O1 is used (UART is selected).

• Transfer bit rate : 9600 bps (f(XIN) = 4.9152 MHz is divided by 512)
• Communication control using port P40 (The output level of the port P40 is controlled by softoware.)
• 2-byte data is transferred from the transmitting side to the receiving side at inter- vals of 10 ms (generated by timer). Fig. 2.3.37 Timing chart [Communication using UART] P40 TXD 10 ms D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7ST SP(2) D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7ST SP(2) D 0ST

Notes 1: Equation of transfer bit rate m: when bit 0 of the Serial I/O1 control register (Address : 1A16) is set to “0,” a value of m is 1. when bit 0 of the Serial I/O1 control register (Address : 1A 16) is set to “1,” a value of m is 4. 2: A BRG count source is selected by bit 0 of the Serial I/O1 control register (Address : 1A16). Table 2.3.1 shows setting examples of Baud rate generator (BRG) values and transfer bit rate values, Figure 2.3.38 shows a setting of related registers at a transmitting side, and Figure 2.3.39 shows a setting of related registers at a receiving side. Table 2.3.1 Setting examples of Baud rate generator values and transfer bit rate values BRG setting valueActual time (bps)BRG setting value at f(XIN) = 4.9152 MHZ 600 1200 2400 4800 9600 19200 38400 76800 31250 62500 600.96 1201.92 2403.85 4807.69 9615.38 20833.33 41666.67 83333.33 31250.00 62500.00 207(CF 16) 103(6716) 51(3316) 25(1916) 12(0C16) 5(0516) 2(0216) 5(0516) 15(0F16) 7(0716) 600.00 1200.00 2400.00 4800.00 9600.00 19200.00 38400.00 76800.00 191(BF 16) 95(5F16) 47(2F16) 23(1716) 11(0B16) 5(0516) 2(0216) 5(0516) 600.00 1200.00 2400.00 4800.00 9600.00 19200.00 38400.00 76800.00 127(7F 16) 63(3F16) 31(1F16) 15(0F16) 7(0716) 3(0316) 1(0116) 3(0316) at f(XIN) = 8 MHZat f(XIN) = 7.3728 MHZTransfer bit rate (bps) (Note 1) BRG count source (Note 2) Actual time (bps) Actual time (bps)BRG setting value f(XIN)/4 f(XIN)/4 f(XIN)/4 f(XIN)/4 f(XIN)/4 f(XIN)/4 f(XIN)/4 f(XIN) f(XIN) f(XIN) Transfer bit rate (bps) = (BRG setting value + 1) 5 16 5 m f(XIN)

2-493802 GROUP USER’S MANUAL Fig. 2.3.38 Setting of related registers at a transmitting side [Communication using UART] Serial I/O1 status register (Address : 1916) SIO1STS Transmitting side Baud rate generator (Address : 1C16) BRG 7 SIO1CON 100 1 01 0 UART control register (Address : 1B16) UARTCON 001 0 f(XIN) Transfer bit rate 16 m b7 b0 Serial I/O1 control register (Address : 1A16) b7 b0 b7 b0 b7 b0 Set when bit 0 of the Serial I/O1 control register (Address : 1A16) is set to “0,” a value of m is 1. when bit 0 of the Serial I/O1 control register (Address : 1A16) is set to “1,” a value of m is 4. BRG count source selection bit : f(XIN)/4 Serial I/O1 synchronous clock selection bit : BRG/16 Transmit enable bit : Transmit enabled Receive enable bit : Receive disabled Serial I/O1 mode selection bit : Asynchronous serial I/O(UART) Serial I/O1 enable bit : Serial I/O1 enabled SRDY1 output enable bit : Not use SRDY1 out Character length selection bit : 8 bits Parity enable bit : Parity checking disabled P45/TXD P-channel output disable bit : CMOS output Stop bit length selection bit : 2 stop bits Transmit buffer empty flag

• Check to be transferred data from the Transmit buffer register to the Transmit shift register.
• Writable the next transmission data to the Transmit buffer register at being set to “1.” Transmit shift register shift completion flag Check a completion of transmitting 1-byte data with this flag. “1” : Transmit shift completed

Serial I/O1 status register (Address : 1916) SIO1STS BRG 7 Serial I/O1 control register (Address : 1A16) SIO1CON 10 0 10 1 0 UARTCON 010 b7 b0 Receive buffer full flag Check a completion of receiving 1-byte data with this flag. “1” : at completing to receive “0” : at reading out a content of the Receive buffer register Overrun error flag “1” : when data are ready to be transferred to the Receive shift register in the state of storing data into the Receive buffer register. Parity error flag “1” : when parity error occurs at enabled parity. Framing error flag “1” : when data can not be received at the timing of setting a stop bit. Summing error flag “1” : when even one of the following errors occurs.

• Overrun error
• Parity error
• Framing error b7 b0 UART control register (Address : 1B16) b7 b0 Character length selection bit : 8 bits Parity enable bit : Parity checking disabled Stop bit length selection bit : 2 stop bits Baud rate generator (Address : 1C16) b7 b0 f(XIN) Transfer bit rate 16 m 1–Set when bit 0 of the Serial I/O1 control register (Address : 1A16) is set to “0,” a value of m is 1. when bit 0 of the Serial I/O1 control register (Address : 1A 16) is set to “1,” a value of m is 4. BRG count source selection bit : f(XIN)/4 Serial I/O1 synchronous clock selection bit : BRG/16 Transmit enable bit : Transmit disabled Receive enable bit : Receive enabled Serial I/O1 mode selection bit : Asynchronous serial I/O(UART) Serial I/O1 enable bit : Serial I/O1 enabled SRDY1 output enable bit : Not use SRDY1 out Fig. 2.3.39 Setting of related registers at a receiving side [Communication using UART]

2-513802 GROUP USER’S MANUAL Control procedure : Figure 2.3.40 shows a control procedure at a transmitting side, and Figure 2.3.41 shows a control procedure at a receiving side. Fig. 2.3.40 Control procedure at a transmitting side [Communication using UART] SIO1STS (Address : 1916), bit0? RESET

• End of communication (Address : 1A16) (Address : 1B16) (Address : 1C16) (Address : 0816), bit0 (Address : 0916) P4 (Address : 0816), bit0 1 Pass 10 ms? Y N TB/RB (Address : 1816) The second byte of a transmission data SIO1STS (Address : 1916), bit2? Initialization SIO1CON UARTCON BRG P4D 1001X 001 000010002 8– 1 TB/RB (Address : 1816) The first byte of a transmission data P4 (Address : 0816), bit0 0 X : This bit is not used in this application. Set it to “0” or “1.” It’s value can be disregarded.
• Set port P40 for a communication control.
• An interval of 10 ms is generated by a timer.
• Start of communication.
• Write a transmission data The Transmit buffer empty flag is set to “0” by this writing.
• Write a transmission data The Transmit buffer empty flag is set to “0” by this writing.
• Check to be transferred data from the Transmit buffer register to the Transmit shift register. (Transmit buffer empty flag)
• Check to be transferred data from the Transmit buffer register to the Transmit shift register. (Transmit buffer empty flag)
• Check a shift completion of the Transmit shift register. (Transmit shift register shift completion flag) SIO1STS (Address : 19 16), bit0? XXXXXXX 12 l

Fig. 2.3.41 Control procedure at a receiving side [Communication using UART] (Address : 1A16) (Address : 1B16) (Address : 1C16) (Address : 0916) RESET

• Check a completion of receiving. (Receive buffer full flag) SIO1STS (Address : 19 16), bit1? Read out a reception data from RB (Address : 1816) SIO1STS (Address : 1916), bit6? Initialization SIO1CON UARTCON BRG P4D 1010X 0012 000010002 8–1 XXXXXXX 02 SIO1STS (Address : 1916), bit1?
• Check an error flag. SIO1STS (Address : 1916), bit6? P4 (Address : 0816), bit0? SIO1CON (Address : 1A16) SIO1CON (Address : 1A16) 0000X 0012 1010X 0012 Processing for error Read out a reception data from RB (Address : 1816)
• Receive the first 1 byte data A Receive buffer full flag is set to “0” by reading data.
• Check a completion of receiving. (Receive buffer full flag)
• Receive the second byte data A Receive buffer full flag is set to “0” by reading data.
• Check an error flag.
• Countermeasure for a bit slippage X : This bit is not used in this application. Set it to “0” or “1.” It’s value can be disregarded. l

2-533802 GROUP USER’S MANUAL APPLICATION

2.4.1 Memory map of PWM

Fig. 2.4.1 Memory map of PWM related registers 002B16 002C 16 002D 16 PWM control register (PWMCON) PWM prescaler (PREPWM) PWM register (PWM)

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2.4.2 Related registers

PWM control register (PWMCON) [Address:2B16] FunctionName Nothing is arranged for these bits. These are write disabled bits. When these bits are read out, the contents are "0". PWM function enable bit 0 : PWM disabled 1 : PWM enabled Count source selection bit0 : f(XIN) 1 : f(XIN)/2 Fig. 2.4.2 Structure of PWM control register PWM prescaler b7 b6 b5 b4 b3 b2 b1 b0 B Function At resetRW PWM prescaler (PREPWM) [Address : 2C16] PWM cycle is set. The values set in this register is written to both the PWM prescaler pre-latch and the PWM prescaler latch at the same time. When data is written during outputting PWM, the pulses corresponding to the changed contents are output starting with the next cycle. When this register is read out, the content of the PWM prescaler latch is read out. l l l l Fig. 2.4.3 Structure of PWM prescaler

2-553802 GROUP USER’S MANUAL APPLICATION PWM register (PWM) [Address : 2D16] Function “H” level output period of PWM is set. The values set in this register is written both the PWM register pre-latch and the PWM register latch at the same time. When data is written during outputting PWM, the pulses corresponding to the changed contents are output starting with the next cycle. When this register is read out, the content of the PWM register latch is read out. l l l l Fig. 2.4.4 Structure of PWM register

2-56 3802 GROUP USER’S MANUAL Specifications :• Motor is controlled by using the 8-bit-resolution PWM output function.

• Clock f(XIN) = 5.0 MHz
• “T,” PWM cycle : 102 µ s
• “t,” “H” level width of output pulse : 40 µ s (Fixed speed) ] A motor speed can be changed by changing the “H” level width of output pluse.

2.4.3 PWM output circuit application example

(1) Control of motor Outline : The rotation speed of the motor is controlled by using PWM (pulse width modulation) output. a setting of the related registers. Fig. 2.4.5 Connection diagram Fig. 2.4.6 PWM output timing PWM output t = 40 µ s T = 102 µ s P56/PWM 3802 group D-A converter Motor driver M

2-573802 GROUP USER’S MANUAL APPLICATION Fig. 2.4.7 Setting of related registers [About PWM output] 1. Set the PWM function enable bit to “1” : The P56/PWM pin is used as the PWM pin. “H” level pulse is output first. 2. Set the PWM function enable bit to “0” : The P56/PWM pin is used as the port P56. Thus, when fixing the output level, make sure the following.

• First, write an output value to bit 6 of the Port P5 register.
• Then write “X 1XXXXXX 2” to the Port P5 direction register. (X : This bit is not used in this application. Set it to “0” or “1.” It’s value can be disregarded.) 3. After data is set to the PWM prescaler and the PWM register, the PWM waveforms corresponding to new data will be output from the next repetitive cycle. PWM function enable bit : PWM enabled (Note) PWMCON PWM control register (Address : 2B16) 255 5 (n + 1) Set “T”, PWM cycle n = 1PREPWM PWM prescaler (Address : 2C16) Note :The PWM output function is given priority even when the corresponding bit to P56 pin of Port P5 direction register is set to “0” (input mode). b7 b0 Count source selection bit : f(XIN) b7 b0 n [Equation] T = Set “t”, “H” level width of PWM m = 100PWM PWM register (Address : 2D16) b7 b0 m [Equation] t = f(XIN) T 5 m 255 Fig. 2.4.8 PWM output PWM output Change PWM output data From the next repetitive cycle, output modified data

2-58 3802 GROUP USER’S MANUAL Control procedure :By setting the related registers as shown to Figure 2.4.7, PWM waveforms are output to the externalunit. This PWM output is integrated through the low pass filter and converted into DC signals for control of the motor. Figure 2.4.9 shows control procedure. Fig. 2.4.9 Control procedure P5 (Address : 0A16), bit6 P5D (Address : 0B16) PREPWM (Address : 2C16) PWM (Address : 2D16) PWMCON (Address : 2B16)

• Output “L” level from P56/PWM pin.0 X 1XXXXXX 2 100 00000001
• Set the PWM cycle
• Set the “H” level width of PWM
• Select the PWM count source, and enable the PWM output.
• X : This bit is not used in this application. Set it to “0” or “1.” It’s value can be disregarded.

2-593802 GROUP USER’S MANUAL APPLICATION

2.5.1 Memory map of A-D conversion

Fig. 2.5.1 Memory map of A-D conversion related registers 003F16 003416 003516 003D 16 Interrupt request register 2 (IREQ2) Interrupt control register 2 (ICON2) AD/DA control register (ADCON) A-D conversion register (AD)

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2.5.2 Related registers

When these bits are read out, the values are “0.” Nothing is allocated for these bits. These are write disabled bits. AD/DA control register b7 b6 b5 b4 b3 b2 b1 b0 B Function At resetRWName Analog input pin selection bits AD/DA control register (ADCON) [Address : 3416] 0 0 0 : P60/AN0 0 0 1 : P61/AN1 0 1 0 : P62/AN2 0 1 1 : P63/AN3 1 0 0 : P64/AN4 1 0 1 : P65/AN5 1 1 0 : P66/AN6 1 1 1 : P67/AN7 b2 b1 b0 10 : Conversion in progress 1 : Conversion completed AD conversion completion bit3 00 : DA1 output disable 1 : DA1 output enable DA 1 output enable bit6 0 54 0 : DA2 output disabled 1 : DA2 output enabled DA 2 output enable bit 5 0 5 Fig. 2.5.3 Structure of A-D conversion register A-D conversion register b7 b6 b5 b4 b3 b2 b1 b0 B Function At resetRW A-D conversion register (AD) [Address : 3516] The read-only register which A-D conversion results are stored.50 Fig. 2.5.2 Structure of AD/DA control register

2-613802 GROUP USER’S MANUAL APPLICATION Fig. 2.5.4 Structure of Interrupt request register 2 Fig. 2.5.5 Structure of Interrupt control register 2 Interrupt request register 2 b7 b6 b5 b4 b3 b2 b1 b0 B Function At resetRW Interrupt request reigster 2 (IREQ2) [Address : 3D16] Name CNTR 0 interrupt request bit CNTR 1 interrupt request bit Serial I/O2 interrupt request bit 0 : No interrupt request 1 : Interrupt request 0 : No interrupt request 1 : Interrupt request 0 : No interrupt request 1 : Interrupt request 0 : No interrupt request 1 : Interrupt request INT2 interrupt request bit 0 : No interrupt request 1 : Interrupt request Nothing is allocated for this bit. This is a write disabled bit. When this bit is read out, the value is “0.” AD conversion interrupt request bit INT4 interrupt request bit 0 : No interrupt request 1 : Interrupt request [ “0” is set by software, but not “1.” 4 00 : No interrupt request 1 : Interrupt request INT3 interrupt request bit [ 0 5 /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines Interrupt control register 2 b7 b6 b5 b4 b3 b2 b1 b0 B Function At resetRW Interrupt control reigster 2 (ICON2) [Address : 3F16] Name CNTR 0 interrupt enable bit CNTR 1 interrupt enable bit Serial I/O2 interrupt enable bit 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled INT2 interrupt enable bit 0 : Interrupt disabled 1 : Interrupt enabled Fix this bit to “0.” AD conversion interrupt enable bit INT4 interrupt enable bit 0 : Interrupt disabled 1 : Interrupt enabled 4 00 : Interrupt disabled 1 : Interrupt enabled INT 3 interrupt enable bit

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2.5.3 A-D conversion application example

Conversion of Analog input voltage Outline : The analog input voltage input from the sensor is converted into digital values. Fig. 2.5.6 Connection diagram [Conversion of Analog input voltage] Specifications :• The analog input voltage input from the sensor is converted into digital values.

• The P60/AN0 pin is used as an analog input pin. Fig. 2.5.7 Setting of related registers [Conversion of Analog input voltage] P60/AN0 3802 group Sensor /LiteDiagLines/LiteDiagLines /LiteDiagLines 0 Analog input pin selection bits : Select the P60/AN0 pin ADCON AD/DA control register (Address : 3416) 000 AD conversion completion bit : Conversion in progress Store a result of A-D conversion (Note) AD A-D conversion register (Address : 3516) (read-only) Note: Read out a result of A-D conversion after bit 3 of the AD/DA control register (ADCON) is set to “1.” b7 b0 b7 b0

2-633802 GROUP USER’S MANUAL APPLICATION Control procedure : By setting the related registers as shown in Figure 2.5.7, the analog input voltage input from the sensor are converted into digital values. Fig. 2.5.8 Control procedure [Conversion of Analog input voltage] Read out AD (Address : 3516) ADCON (Address : 3416), bit0 – bit2 ADCON (Address : 3416), bit3 0ADCON (Address : 3416), bit3?

• Select the P60/AN0 pin as an analog input pin.
• Start A-D conversion.
• Check the completion of A-D conversion.
• Read out the conversion result. 0002

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2.6.1 Memory map of processor mode

Fig. 2.6.1 Memory map of processor mode related register

2.6.2 Related register

Fig. 2.6.2 Structure of CPU mode register 003B16 CPU mode register (CPUM) Nothing is allocated for these bits. These are write disabled bits. When these bits are read out, the values are “0.” CPU mode register (CPUM) [Adress : 3B16] CPU mode register b7 b6 b5 b4 b3 b2 b1 b0 Function At resetRW B Name Processor mode bits 00 : Single-chip mode 01 : Memory expansion mode 10 : Microprocessor mode 11 : Not available Stack page selection bit 0 : 0 page 1 : 1 page [ An initial value of bit 1 is determined by a level of the CNV SS pin. 0 5 0 5 0 5 0 5

2-653802 GROUP USER’S MANUAL

2.6.3 Processor mode application examples

____ (1) Application example of memory expansion in the case where the ONW (One-Wait) function is not used Outline : The external memory is accessed in the microprocessor mode. At f(X IN) = 8 MHz, an available RAM is given by the following : ___

• OE access time : ta (OE) ≤ 50 ns
• Setup time for writing data : tsu (D) ≤ 65 ns For example, the M5M5256BP-10 whose address access is 100 ns is available. Figure 2.6.3 shows an expansion example of a 32K byte ROM and a 32K byte RAM. Fig. 2.6.3 Expansion example of ROM and RAM 3802 group CNV SS ONW AD 15 8P 4 8P 5 8P 6 AD 14 AD 0 DB 0 DB 7 RD WR M5M27C256AK-10 M5M5256BP-10 CE A0–A14 D 0–D 7 OE A0–A14 DQ 1–DQ 8 OE W 8MHz VCC = 5.0V± 10 % 000016 800016 044016 004016 000816 FFFF 16 External RAM area (M5M5256BP) SFR area Internal RAM area External RAM area (M5M5256BP) External ROM area (M5M27C256AK) Memory map 74F04 S 2P 3 0, P31 EPROM SRAM

2-66 3802 GROUP USER’S MANUAL Fig. 2.6.4 Read-cycle (OE access, SRAM) Fig. 2.6.5 Read-cycle (OE access, EPROM) Output enabled access time of M5M5256BP Data bus setup time before RD of 3802 td(AH – RD) RD pulse width of 3802 RD delay time after outputting address of 3802 50 ns (max) 65 ns (min) Address (low-order)A0–A7 (Port P0) Address (high-order)A8–A14 (Port P1) /,/,/,/,/,/,/, /,/,/,/,/,/,/, DataDQ 1–DQ 8 (Port P2) S (A15) WR “H” level 125 ns - 10 ns (min)125 ns - 35 ns (min) OE (RD of 3802) td(AH – RD) tWL (RD) ta(OE) tsu(DB – RD) :tWL (RD) :ta(OE) tsu(DB – RD) :RD delay time after outputting address of 3802 :Output enabled access time of M5M27C256AK :Data bus setup time before RD of 3802 50 ns (max) 65 ns (min) Address (low-order)A0–A7 (Port P0) Address (high-order)A8–A14 (Port P1) /,/,/,/,/,/,/, (Port P2) WR H level CE 5.8 ns (max) tPHL 125 ns - 10ns (min)125 ns - 35 ns (min) OE (RD of 3802) td(AH – RD) tWL (RD) ta(OE) tsu(DB – RD) :RD pulse width of 3802 ta(OE) td(AH – RD) tWL (RD) tsu(DB – RD) tPHL Output delay time of 74F04

2-673802 GROUP USER’S MANUAL Fig. 2.6.6 Write-cycle (W control, SRAM) td(AH – WR) W (WR of 3802) 65 ns (max) 35 ns (min) Address (low-order) Address (high-order) /,/,/,/,/,/,/, /,/,/,/,/,/,/, DataDQ 1–DQ 8 (Port P2) S (A15) OE (RD of 3802) “ H ” level 125 ns - 10 ns (min)125 ns - 35 ns (min) td(AH – WR) tWL (WR) td(WR – DB) tsu(D) :WR delay time after outputting address of 3802 :WR pulse width of 3802tWL (WR) :Data bus delay time after WR of 3802td(WR – DB) :Data setup time of M5M5256BPtsu(D) A0–A7 (Port P0) A8–A14 (Port P1)

2-68 3802 GROUP USER’S MANUAL (2) Application example of memory expansion in the case where the ONW (One-Wait) function is used ____ Outline : ONW function is used when the external memory access is slow. ____ If “L” level signal is input to the P32/ONW pin while the CPU is in the read or write status, the read or write cycle corresponding to 1 cycle of is extended. In the extended period, the RD or WR signal is kept at the “L” level. The ONW function operates only when data is read from or written into addresses 000016 to 000716 and addresses 044016 to FFFF16 . ____ Figure 2.6.7 shows an application example of the ONW function. ____ Fig. 2.6.7 Application example of the ONW function 3802 group CNV SS AD 15 8 P5 8 P6 ONW AD 14 AD 0 DB 0 DB 7 RD WR M5M27C 256AK-10 M5M5256BP-10 CE A0–A14 D 0–D 7 OE A0–A14 DQ 1–DQ 8 OE W 8MH z VCC = 5.0V±10 % External RAM area (M5M5256BP) SFR area Internal RAM area External RAM area (M5M5256BP) External ROM area (M5M27C256AK) 000016 800016 044016 004016 000816 FFFF 16 Memory map 74F04 S – 15 8 P4

2 P30, P31

2-693802 GROUP USER’S MANUAL

2.7.1 Connection example of reset IC

Figure 2.7.2 shows the system example which switch to the RAM backup mode by detecting a drop of the system power source voltage with the INT interrupt. Fig. 2.7.1 Example of Poweron reset circuit Fig. 2.7.2 RAM back-up system System power source voltage M62009L, M62009P, M62009FP VCC 1 RESET INT GND CdV1 VCC 2 3802 group VCC INT RESET

40 VSS

400.1 µ F Power source GND Delay capacity Output VSS VCC

3.1 Electrical characteristics

3.2 Standard characteristics

3.3 Notes on use

3.4 Countermeasures against noise

3.5 List of registers

3.6 Mask ROM ordering method

3.7 Mark specification form

3.8 Package outline

3.9 List of instruction codes

3.10 Machine instructions

3.11 SFR memory map

3.12 Pin configuration

3802 GROUP USER'S MANUAL3-2

3.1.1 ABSOLUTE MAXIMUM RATINGS

Input voltage P00–P0 7, P10–P1 7, P20–P2 7, P30–P3 7, P40–P4 7, P50–P5 7, P60–P6 7, VREF Input voltage RESET, XIN Input voltage CNVSS Output voltage P00–P0 7, P10–P1 7, P20–P2 7, P30–P3 7, P40–P4 7, P50–P5 7, P60–P6 7, XOUT Power dissipation Operating temperature Storage temperature VCC VI VI VI VO Pd Topr Tstg Symbol Parameter Conditions Ratings –0.3 to 7.0 –0.3 to VCC +0.3 –0.3 to VCC +0.3 –0.3 to 13 –0.3 to VCC +0.3 1000 (Note) –20 to 85 –40 to 125 V V V V V mW Unit Ta = 25 °C All voltages are based on VSS . Output transistors are cut off. Table 3.1.2 RECOMMENDED OPERATING CONDITIONS (Vcc = 3.0 to 5.5 V, Ta = –20 to 85°C, unless otherwise noted) Note 1: 5.5 5.5 VCC VCC VCC VCC VCC

0.2 VCC

0.16 VCC

–80 –80 –40 –40 –10

6 VCC –16

Power source voltage (f(XIN) < 2 MHz) (Note 1) Power source voltage (f(XIN) = 8 MHz) (Note 1) Power source voltage Analog reference voltage (when A-D converter is used) Analog reference voltage (when D-A converter is used) Analog power source voltage Analog input voltage AN 0–AN 7 “H” input voltage P0 0–P0 7, P10–P1 7, P20–P2 7, P30–P3 7, P40–P4 7, P50–P5 7, P60–P6 7 “H” input voltage RESET, X IN, CNVSS “L” input voltage P0 0–P0 7, P10–P1 7, P20–P2 7, P30–P3 7, P40–P4 7, P50–P5 7, P60–P6 7 “L” input voltage RESET, CNV SS “L” input voltage X IN “H” total peak output currentP00–P07, P10–P17, P20–P27, P30–P37 (Note 2) “H” total peak output current P40–P4 7,P50–P5 7, P60–P6 7 (Note 2) “L” total peak output currentP00–P07, P10–P17, P20–P27, P30–P37 (Note 2) “L” total peak output current P40–P4 7,P50–P5 7, P60–P6 7 (Note 2) “H” total average output currentP00–P07, P10–P17, P20–P27, P30–P37 (Note 2) “H” total average output current P40–P4 7,P50–P5 7, P60–P6 7 (Note 2) “L” total average output currentP00–P07, P10–P17, P20–P27, P30–P37 (Note 2) “L” total average output current P40–P4 7,P50–P5 7, P60–P6 7 (Note 2) “H” peak output current P0 0–P0 7, P10–P1 7, P20–P2 7, P30–P3 7, P40–P4 7, P50–P5 7, P60–P67 (Note 3) “L” peak output current P0 0–P0 7, P10–P1 7, P20–P2 7, P30–P3 7, P40–P4 7, P50–P5 7, P60–P67 (Note 3) “H” average output current P00–P0 7, P10–P1 7, P20–P2 7, P30–P3 7, P40–P4 7, P50–P5 7, P60–P67 (Note 4) “L” average output current P00–P0 7, P10–P1 7, P20–P2 7, P30–P3 7, P40–P4 7, P50–P5 7, P60–P67 (Note 4) Internal clock oscillation frequency (VCC = 4.0 to 5.5 V) Internal clock oscillation frequency (VCC = 3.0 to 4.0 V) VCC VSS VREF AVSS VIA VIH VIH VIL VIL VIL ΣIOH(peak) ΣIOH(peak) ΣIOL(peak) ΣIOL(peak) ΣIOH(avg) ΣIOH(avg) ΣIOL(avg) ΣIOL(avg) IOH(peak) IOL(peak) IOH(avg) IOL(avg) f(XIN) Symbol Parameter Limits Min. V V V V V V V V V V mA mA mA mA mA mA mA mA mA mA mA mA MHz Unit 3.0 4.0 2.0 3.0 AV SS

0.8 VCC

5.0 5.0 Typ. Max. Note: 300 mW in case of the flat package. 3.1Electrical characteristics Table 3.1.1 Absolute maximum ratings

3.1.2 Recommended operating conditions

The total output current is the sum of all the currents flowing through all the applicable ports. The total average current is an average value measured over 100 ms. The total peak current is the peak value of all the currents. 2:The peak output current is the peak current flowing in each port. 3:The average output current IOL(avg), IOH(avg) in an average value measured over 100 ms.

3802 GROUP USER'S MANUAL 3-3

stopped, output transistors isolated. Note 1:P4 5 is measured when the P45/TX D P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”. P51 is measured when the P51/SOUT2 P-channel output disable bit of the serial I/O2 control register (bit 7 of address 001D16) is “0”. 2:With output transistors isolated and A-D converter having completed conversion, and not including current flowing through VREF pin. 2.0 1.0 5.0 5.0 –5.0 –5.0 5.5 2.0 “H” output voltage P00–P0 7, P10–P1 7, P20–P2 7, P30–P3 7, P40–P4 7, P50–P5 7, P60–P6 7 (Note 1) “L” output voltage P00–P0 7, P10–P1 7, P20–P2 7, P30–P3 7, P40–P4 7,P50–P57, P60–P6 7 Hysteresis CNTR 0, CNTR1, INT0–INT4 Hysteresis R X D, SCLK1 , SIN2, SCLK2 Hysteresis RESET “H” input current P00–P0 7, P10–P1 7, P20–P2 7, P30–P3 7, P40–P4 7, P50–P5 7, P60–P6 7 “H” input current RESET, CNVSS “H” input current XIN “L” input current P00–P0 7, P10–P1 7, P20–P2 7, P30–P3 7, P40–P4 7, P50–P5 7, P60–P6 7, RESET, CNVSS “L” input current RESET, CNVSS “L” input current XIN RAM hold voltage Symbol Parameter Limits Min. V Unit VCC –2.0 VCC –1.0 0.4 0.5 0.5 6.4 0.8 1.5 0.2 0.1 Typ. Max. IOH = –10 mA VCC = 4.0 to 5.5 V IOH = –1.0 mA VCC = 3.0 to 5.5 V IOL = 10 mA VCC = 4.0 to 5.5 V IOL = 1.0 mA VCC = 3.0 to 5.5 V VI = VCC VI = VCC VI = VCC VI = VSS VI = VSS VI = VSS When clock stopped f(XIN) = 8 MHz, VCC = 5 V f(XIN) = 5 MHz, VCC = 5 V f(XIN) = 2 MHz, VCC = 3 V Ta = 25 °C (Note 2) Ta = 85 °C (Note 2) 2.0 Test conditions VT+ – VT– VT+ – VT– VT+ – VT– IIH IIH IIH IIL IIL IIL VRAM VOH VOL ICC V V V V µ A µ A µ A µ A µ A µ A V mA µ A Power source current When WIT instruction is executed with f(Xin) = 8MHz,VCC =5V When WIT instruction is executed with f(Xin) = 5MHz,VCC =5V When WIT instruction is executed with f(Xin) = 2MHz,V CC =3V ±2.5 200 5.0 Limits Min. Bits LSB tC (φ) kΩ µ A µ A Typ. Max. 150 0.5 Note: When D-A conversion registers (addresses 003616 and 003716) contain “0016”. Resolution Absolute accuracy (excluding quantization error) Conversion time Ladder resistor Reference power source input current (Note) A-D port input current t CONV R LADDER IVREF II(AD) Symbol Parameter Unit VREF = 5.0 V 50 Table 3.1.3 ELECTRICAL CHARACTERISTICS (VCC = 3.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted) Test conditions Table 3.1.4 A–D CONVERTER CHARACTERISTICS (VCC = 3.0 to 5.5 V, VSS = AVSS = 0 V, VREF = 2.0 V to VCC , Ta = –20 to 85 °C, unless otherwise noted)

3.1.3 Electrical characteristics

3.1.4 A-D converter characteristics

3802 GROUP USER'S MANUAL3-4

Note: Using one D-A converter, with the value in the D-A conversion register of the other D-A converter being “0016”, and excluding cur- rents flowing through the A-D resistance ladder. 1.0 2.5 3.2 Resolution Absolute accuracy VCC = 4.0 to 5.5 V VCC = 3.0 to 4.0 V Setting time Output resistor Reference power source input current (Note) tsu R O IVREF Symbol Parameter Limits Min. Bits µs kΩ mA Unit Typ. Max.Test conditions 2.5 Table 3.1.5 D-A CONVERTER CHARACTERISTICS (VCC = 3.0 to 5.5 V, VSS = AVSS = 0 V, VREF = 3.0 V to VCC , Ta = –20 to 85 °C, unless otherwise noted)

3.1.5 D-A CONVERTER CHARACTERISTICS

3802 GROUP USER'S MANUAL 3-5

Note: When f(XIN) = 8 MHz and bit 6 of address 001A16 is “1”. Divide this value by four when f(XIN) = 8 MHz and bit 6 of address 001A16 is “0”. Reset input “L” pulse width External clock input cycle time External clock input “H” pulse width External clock input “L” pulse width CNTR 0, CNTR1 input cycle time CNTR 0, CNTR1 input “H” pulse width INT0 to INT4 input “H” pulse width CNTR 0, CNTR1 input “L” pulse width INT0 to INT4 input “L” pulse width Serial I/O1 clock input cycle time (Note) Serial I/O2 clock input cycle time Serial I/O1 clock input “H” pulse width (Note) Serial I/O2 clock input “H” pulse width Serial I/O1 clock input “L” pulse width (Note) Serial I/O2 clock input “L” pulse width Serial I/O1 input set up time Serial I/O2 input set up time Serial I/O1 input hold time Serial I/O2 input hold time tw(RESET) tc(XIN) twH(X IN) twL(XIN) tc(CNTR) twH(CNTR) twH(INT) twL(CNTR) twL(INT) tc(SCLK1 ) tc(SCLK2 ) twH(S CLK1 ) twH(S CLK2 ) twL(SCLK1 ) twL(SCLK2 ) tsu(RXD–S CLK1 ) tsu(SIN2–S CLK2 ) th(SCLK1 –R X D) th(SCLK2 –SIN2) Symbol Parameter Limits Min. µs ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit Table 3.1.6 TIMING REQUIREMENTS (1) (VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted) 125 200 800 1000 370 400 370 400 220 200 100 200 Typ. Max. Reset input “L” pulse width External clock input cycle time External clock input “H” pulse width External clock input “L” pulse width CNTR 0, CNTR1 input cycle time CNTR 0, CNTR1 input “H” pulse width INT0 to INT4 input “H” pulse width CNTR 0, CNTR1 input “L” pulse width INT0 to INT4 input “L” pulse width Serial I/O1 clock input cycle time (Note) Serial I/O2 clock input cycle time Serial I/O1 clock input “H” pulse width (Note) Serial I/O2 clock input “H” pulse width Serial I/O1 clock input “L” pulse width (Note) Serial I/O2 clock input “L” pulse width Serial I/O1 input set up time Serial I/O2 input set up time Serial I/O1 input hold time Serial I/O2 input hold time tw(RESET) tc(XIN) twH(X IN) twL(XIN) tc(CNTR) twH(CNTR) twH(INT) twL(CNTR) twL(INT) tc(SCLK1 ) tc(SCLK2 ) twH(S CLK1 ) twH(S CLK2 ) twL(SCLK1 ) twL(SCLK2 ) tsu(RX D–S CLK1 ) tsu(SIN2–SCLK2 ) th(SCLK1 –R X D) th(SCLK2 –S IN2) Symbol Parameter Limits Min. µ s ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit Table 3.1.7 TIMING REQUIREMENTS (2) (VCC = 3.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted) 500/ (3 VCC –8) 200/ (3 VCC –8) 200/ (3 VCC –8) 500 230 230 230 230 2000 2000 950 950 950 950 400 400 200 300 Typ. Max. Note: When f(XIN) = 2 MHz and bit 6 of address 001A16 is “1”. Divide this value by four when f(XIN) = 2 MHz and bit 6 of address 001A16 is “0”.

3.1.6 Timing requirements and Switching characteristics

3802 GROUP USER'S MANUAL3-6

Serial I/O1 clock output “H” pulse width Serial I/O2 clock output “H” pulse width Serial I/O1 clock output “L” pulse width Serial I/O2 clock output “L” pulse width Serial I/O1 output delay time (Note 1) Serial I/O2 output delay time (Note 2) Serial I/O1 output valid time (Note 1) Serial I/O2 output valid time (Note 2) Serial I/O1 clock output rising time Serial I/O1 clock output falling time Serial I/O2 clock output rising time Serial I/O2 clock output falling time CMOS output rising time (Note 3) CMOS output falling time (Note 3) 140 200 Symbol Parameter Limits Min. ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit Table 3.1.8 SWITCHING CHARACTERISTICS (1) (VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted) tc(SCLK1 )/2–30 tc(SCLK2 )/2–160 tc(SCLK1 )/2–30 tc(SCLK2 )/2–160 –30 Typ. Max. twH(S CLK1 ) twH(S CLK2 ) twL(SCLK1 ) twL(SCLK2 ) td(SCLK1 –TXD) td(SCLK2 –S OUT2 ) tv(SCLK1 –TX D) tv(SCLK2 –SOUT2 ) tr(SCLK1 ) tf(SCLK1 ) tr(SCLK2 ) tf(SCLK2 ) tr(CMOS) tf(CMOS) Test conditions Fig. 3.1.1 Note1: When the P45/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”. 2: When the P51/SOUT2 P-channel output disable bit of the serial I/O2 control register (bit 7 of address 001D16) is “0”. 3: XOUT pin is excluded. Table 3.1.9 SWITCHING CHARACTERISTICS (2) (VCC = 3.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted) Serial I/O1 clock output “H” pulse width Serial I/O2 clock output “H” pulse width Serial I/O1 clock output “L” pulse width Serial I/O2 clock output “L” pulse width Serial I/O1 output delay time (Note 1) Serial I/O2 output delay time (Note 2) Serial I/O1 output valid time (Note 1) Serial I/O2 output valid time (Note 2) Serial I/O1 clock output rising time Serial I/O1 clock output falling time Serial I/O2 clock output rising time Serial I/O2 clock output falling time CMOS output rising time (Note 3) CMOS output falling time (Note 3) 350 400 Symbol Parameter Limits Min. ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit tc(SCLK1 )/2–50 tc(SCLK2 )/2–240 tc(SCLK1 )/2–50 tc(SCLK2 )/2–240 –30 Typ. Max. twH(S CLK1 ) twH(S CLK2 ) twL(SCLK1 ) twL(SCLK2 ) td(SCLK1 –TXD) td(SCLK2 –S OUT2 ) tv(SCLK1 –TX D) tv(SCLK2 –SOUT2 ) tr(SCLK1 ) tf(SCLK1 ) tr(SCLK2 ) tf(SCLK2 ) tr(CMOS) tf(CMOS) Test conditions Fig. 3.1.1 Note1: When the P45/TX D P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”. 2: When the P51/SOUT2 P-channel output disable bit of the serial I/O2 control register (bit 7 of address 001D16) is “0”. 3: XOUT pin is excluded.

3802 GROUP USER'S MANUAL 3-7

Note 1:The RESET OUT output goes “H” in sync with the rise of the φ clock that is anywhere between about 8 cycle and 13 cycles after the RESET input goes “H”. Before φ ONW input set up time After φ ONW input hold time Before φ data bus set up time After φ data bus hold time Before RD ONW input set up time Before WR ONW input set up time After RD ONW input hold time After WR ONW input hold time Before RD data bus set up time After RD data bus hold time tsu(ONW– φ) th(φ–ONW) tsu(DB–φ) th(φ–DB) tsu(ONW–RD) tsu(ONW–WR) th(RD–ONW) th(WR–ONW) tsu(DB–RD) th(RD–DB) Symbol Parameter Limits Min. ns ns ns ns ns ns ns ns Unit –20 –20 –20 –20 Typ. Max. φ clock cycle time φ clock “H” pulse width φ clock “L” pulse width After φ AD15–AD 8 delay time After φ AD15–AD 8 valid time After φ AD 7–AD 0 delay time After φ AD7–AD 0 valid time SYNC delay time SYNC valid time RD and WR delay time RD and WR valid time After φ data bus delay time After φ data bus valid time RD pulse width, WR pulse width RD pulse width, WR pulse width (When one-wait is valid) After AD 15–AD 8 RD delay time After AD15–AD 8 WR delay time After AD7–AD 0 RD delay time After AD7–AD 0 WR delay time After RD AD15–AD 8 valid time After WR AD15–AD 8 valid time After RD AD7–AD 0 valid time After WR AD7–AD 0 valid time After WR data bus delay time After WR data bus valid time RESET OUT output delay time (Note 1) RESET OUT output valid time (Note 1) 200 200 Symbol Parameter Limits Min. ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit tc(XIN)–10 tc(XIN)–10 t c(XIN)–10 3tc(XIN)–10 tc(XIN)–35 tc(XIN)–40 c(XIN) tc(XIN)–15 tc(XIN)–20 Typ. Max. t c(φ) twH(φ) twL(φ) td(φ–AH) tv(φ–AH) td(φ–AL) tv(φ–AL) td(φ–SYNC) tv(φ–SYNC) td(φ–WR) tv(φ–WR) td(φ–DB) tv(φ–DB) twL(RD) twL(WR) td(AH–RD) td(AH–WR) td(AL–RD) td(AL–WR) tv(RD–AH) tv(WR–AH) tv(RD–AL) tv(WR–AL) td(WR–DB) tv(WR–DB) td(RESET–RESET OUT ) tv(φ–RESET) Test conditions Fig. 3.1.1 Table 3.1.10 TIMING REQUIREMENTS 1 IN MEMORY EXPANSION MODE AND MICROPROCESSOR MODE (1) (VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted) Table 3.1.11 SWITCHING CHARATERISTICS 1 IN MEMORY EXPANSION MODE AND MICROPROCESSOR MODE (1) (VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)

3802 GROUP USER'S MANUAL3-8

Before φ ONW input set up time After φ ONW input hold time Before φ data bus set up time After φ data bus hold time Before RD ONW input set up time Before WR ONW input set up time After RD ONW input hold time After WR ONW input hold time Before RD data bus set up time After RD data bus hold time tsu(ONW– φ) th(φ–ONW) tsu(DB–φ) th(φ–DB) tsu(ONW–RD) tsu(ONW–WR) th(RD–ONW) th(WR–ONW) tsu(DB–RD) th(RD–DB) Symbol Parameter Limits Min. ns ns ns ns Unit –20 –20 180 –20 –20 185 Typ. Max. φ clock cycle time φ clock “H” pulse width φ clock “L” pulse width After φ AD15–AD 8 delay time After φ AD15–AD 8 valid time After φ AD 7–AD 0 delay time After φ AD7–AD 0 valid time SYNC delay time SYNC valid time RD and WR delay time RD and WR valid time After φ data bus delay time After φ data bus valid time RD pulse width, WR pulse width RD pulse width, WR pulse width (when one-wait is valid) After AD 15–AD 8 RD delay time After AD15–AD 8 WR delay time After AD7–AD 0 RD delay time After AD7–AD 0 WR delay time After RD AD15–AD 8 valid time After WR AD15–AD 8 valid time After RD AD7–AD 0 valid time After WR AD7–AD 0 valid time After WR data bus delay time After WR data bus valid time RESET OUT output delay time (Note 1) RESET OUT output valid time (Note 1) Symbol Parameter Limits Min. ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit tc(XIN)–20 tc(XIN)–20 t c(XIN)–20 3tc(XIN)–20 tc(XIN)–145 tc(XIN)–145 c(XIN) Typ. Max. t c(φ) twH(φ) twL(φ) td(φ–AH) tv(φ–AH) td(φ–AL) tv(φ–AL) td(φ–SYNC) tv(φ–SYNC) td(φ–WR) tv(φ–WR) td(φ–DB) tv(φ–DB) twL(RD) twL(WR) td(AH–RD) td(AH–WR) td(AL–RD) td(AL–WR) tv(RD–AH) tv(WR–AH) tv(RD–AL) tv(WR–AL) td(WR–DB) tv(WR–DB) td(RESET–RESET OUT ) tv(φ–RESET) Test conditions Fig. 3.1.1 Note1: The RESET OUT output goes “H” in sync with the fall of the φ clock that is anywhere between about 8 cycle and 13 cycles after the RESET input goes “H”. Table 3.1.12 TIMING REQUIREMENTS IN MEMORY EXPANSION MODE AND MICROPROCESSOR MODE (2) (VCC = 3.0 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted) Table 3.1.13 SWITCHING CHARACTERISTICS 2 IN MEMORY EXPANSION MODE AND MICROPROCESSOR MODE (2) (VCC = 3.0 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted) ns ns ns ns ns 150 150 200 195 300 300

3802 GROUP USER'S MANUAL 3-9

Input voltage P00–P0 7, P10–P1 7, P20–P2 7, P30–P3 7, P40–P4 7, P50–P5 7, P60–P6 7, VREF Input voltage RESET, XIN Input voltage CNVSS Output voltage P00–P0 7, P10–P1 7, P20–P2 7, P30–P3 7, P40–P4 7, P50–P5 7, P60–P6 7, XOUT Power dissipation Operating temperature Storage temperature VCC VI VI VI VO Pd Topr Tstg Symbol Parameter Conditions Ratings –0.3 to 7.0 –0.3 to VCC +0.3 –0.3 to VCC +0.3 –0.3 to 13 –0.3 to VCC +0.3 1000 (Note) –40 to 85 –65 to 150 V V V V V mW Unit Ta = 25 °C All voltage are based on VSS . Output transistors are cut off. Note 1:The total output current is the sum of all the currents flowing through all the applicable ports. The total average current is an aver- age value measured over 100 ms. The total peak current is the peak value of all the currents. 2:The peak output current is the peak current flowing in each port. 3:The average output current IOL(avg), IOH(avg) in an average value measured over 100 ms. 5.5 VCC VCC VCC VCC VCC –80 –80 –40 –40 –10 Power source voltage (f(X IN) ≤ 2 MHz) Power source voltage Analog reference voltage (when A-D converter is used) Analog reference voltage (when D-A converter is used) Analog power source voltage Analog input voltage AN 0–AN 7 “H” input voltage P0 0–P0 7, P10–P1 7, P20–P2 7, P30–P3 7, P40–P4 7, P50–P5 7, P60–P6 7 “H” input voltage RESET, X IN, CNVSS “L” input voltage P0 0–P0 7, P10–P1 7, P20–P2 7, P30–P3 7, P40–P4 7, P50–P5 7, P60–P6 7 “L” input voltage RESET, CNV SS “L” input voltage X IN “H” total peak output currentP00–P07, P10–P17, P20–P27, P30–P37 (Note 1) “H” total peak output current P40–P4 7,P50–P5 7, P60–P6 7 (Note 1) “L” total peak output currentP00–P07, P10–P17, P20–P27, P30–P37 (Note 1) “L” total peak output current P40–P4 7,P50–P5 7, P60–P6 7 (Note 1) “H” total average output currentP00–P07, P10–P17, P20–P27, P30–P37 (Note 1) “H” total average output current P40–P4 7,P50–P5 7, P60–P6 7 (Note 1) “L” total average output currentP00–P07, P10–P17, P20–P27, P30–P37 (Note 1) “L” total average output current P40–P4 7,P50–P5 7, P60–P6 7 (Note 1) “H” peak output current P0 0–P0 7, P10–P1 7, P20–P2 7, P30–P3 7, P40–P4 7, P50–P5 7, P60–P6 7 (Note 2) “L” peak output current P0 0–P0 7, P10–P1 7, P20–P2 7, P30–P3 7, P40–P4 7, P50–P5 7, P60–P6 7 (Note 2) “H” average output current P00–P0 7, P10–P1 7, P20–P2 7, P30–P3 7, P40–P4 7, P50–P5 7, P60–P6 7 (Note 3) “L” average output current P00–P0 7, P10–P1 7, P20–P2 7, P30–P3 7, P40–P4 7, P50–P5 7, P60–P6 7 (Note 3) Internal clock oscillation frequency (VCC = 4.0 to 5.5 V) VCC VSS VREF AVSS VIA VIH VIH VIL VIL VIL ΣIOH(peak) ΣIOH(peak) ΣIOL(peak) ΣIOL(peak) ΣIOH(avg) ΣIOH(avg) ΣIOL(avg) ΣIOL(avg) IOH(peak) IOL(peak) IOH(avg) IOL(avg) f(XIN) Symbol Parameter Limits Min. V V V V V V V V V V mA mA mA mA mA mA mA mA mA mA mA mA MHz Unit 4.0 2.0 4.0 AVSS 5.0 Typ. Max. Table 3.1.14 Absolute maximum ratings (Extended operating temperature version) Table 3.1.15 Recommended operating conditions (Extended operating temperature version) (VCC = 4.0 to 5.5 V, Ta = –40 to 85 °C, unless otherwise noted)

3.1.7 Absolute maximum ratings (Extended operating temperature version)

Note: 300mW in case of the flat package

3.1.8 Recommended operatinmg conditions (Extended operating temperature version)

3802 GROUP USER'S MANUAL3-10

stopped, output transistors isolated. Note 1:P4 5 is measured when the P45/TX D P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”. P51 is measured when the P51/SOUT2 P-channel output disable bit of the serial I/O2 control register (bit 7 of address 001D16) is “0”. 2:With output transistors isolated and A-D converter having completed conversion, and not including current flowing through VREF pin. 2.0 5.0 5.0 –5.0 5.5 “H” output voltage P00–P0 7, P10–P1 7, P20–P27, P30–P3 7, P40–P4 7, P50–P57, P60–P6 7 (Note 1) “L” output voltage P00–P0 7, P10–P1 7, P20–P27, P30–P3 7, P40–P4 7,P50–P5 7, P60–P6 7 Hysteresis CNTR 0, CNTR1, INT0–INT4 Hysteresis R XD, SCLK1 , SIN2, SCLK2 Hysteresis RESET “H” input current P00–P0 7, P10–P1 7, P20–P27, P30–P3 7, P40–P4 7, P50–P57, P60–P6 7 “H” input currentRESET , CNVSS “H” input current XIN “L” input current P00–P0 7, P10–P1 7, P20–P27, P30–P3 7, P40–P4 7, P50–P57, P60–P6 7, RESET , CNVSS “L” input current XIN RAM hold voltage Symbol Parameter Limits Min. Unit VCC –2.0 0.4 0.5 0.5 6.4 1.5 0.1 Typ. Max. IOH = –10 mA IOL = 10 mA VI = VCC VI = VCC VI = VCC VI = VSS VI = VSS When clock stopped f(XIN) = 8 MHz f(XIN) = 5 MHz When WIT instruction is executed with f(XIN) = 8 MHz When WIT instruction is executed with f(XIN) = 5 MHz Ta = 25 °C (Note 2) Ta = 85 °C (Note 2) 2.0 Test conditions Note: When D-A conversion registers (addresses 003616 and 003716) contain “0016”. ±2.5 200 5.0 Resolution Absolute accuracy (excluding quantization error) Conversion time Ladder resistor Reference power source input current (Note) A-D port input current t CONV R LADDER IVREF II(AD) Symbol Parameter Limits Min. Bits LSB tC (φ) kΩ µA µA Unit Typ. Max. VREF = 5.0 V Test conditions ± 1 150 0.5 Table 3.1.17 A-D CONVERTER CHARACTERISTICS (Extended operating temperature version) (VCC = 4.0 to 5.5 V, VSS = AVSS = 0 V, VREF = 2.0 V to VCC , Ta = –40 to 85 °C, unless otherwise noted) VT+ – VT– VT+ – VT– VT+ – VT– IIH IIH IIH IIL IIL VRAM VOH VOL V V V V V µA µA µA µA µA V Power source current mA Table 3.1.16 Electrical characteristics (Extended operating temperature version) (VCC = 4.0 to 5.5 V, VSS = 0 V , Ta = –40 to 85 °C, unless otherwise noted) ICC µA

3.1.9 Electrical characteristics (Extended operating temperature version)

3.1.10 A-D converter characteristics (Extended operating temperature version)

3802 GROUP USER'S MANUAL 3-11

Note: Using one D-A converter, with the value in the D-A conversion register of the other D-A converter being “0016”, and excluding cur- rents flowing through the A-D resistance ladder. 1.0 3.2 Resolution Absolute accuracy Setting time Output resistor Reference power source input current (Note) t su RO IVREF Symbol Parameter Limits Min. Bits µs kΩ mA Unit Typ. Max.Test conditions 2.5 Table 3.1.18 D-A CONVERTER CHARACTERISTICS (Extended operating temperature version) (VCC = 4.0 to 5.5 V, VSS = AVSS = 0 V, VREF = 4.0 V to VCC , Ta = –40 to 85 °C, unless otherwise noted)

3.1.11 D-A converter characteristics (Extended operating temperature version)

3802 GROUP USER'S MANUAL3-12

Note: When f(XIN) = 8 MHz and bit 6 of address 001A16 is “1”. Divide this value by four when f(XIN) = 8 MHz and bit 6 of address 001A16 is “0”. Reset input “L” pulse width External clock input cycle time External clock input “H” pulse width External clock input “L” pulse width CNTR 0, CNTR1 input cycle time CNTR 0, CNTR1 input “H” pulse width INT0 to INT4 input “H” pulse width CNTR 0, CNTR1 input “L” pulse width INT0 to INT4 input “L” pulse width Serial I/O1 clock input cycle time (Note) Serial I/O2 clock input cycle time Serial I/O1 clock input “H” pulse width (Note) Serial I/O2 clock input “H” pulse width Serial I/O1 clock input “L” pulse width (Note) Serial I/O2 clock input “L” pulse width Serial I/O1 input set up time Serial I/O2 input set up time Serial I/O1 input hold time Serial I/O2 input hold time tw(RESET) tc(XIN) twH(X IN) twL(XIN) tc(CNTR) twH(CNTR) twH(INT) twL(CNTR) twL(INT) tc(SCLK1 ) tc(SCLK2 ) twH(S CLK1 ) twH(S CLK2 ) twL(SCLK1 ) twL(SCLK2 ) tsu(RX D–S CLK1 ) tsu(SIN2–SCLK2 ) th(SCLK1 –R X D) th(SCLK2 –SIN2) Symbol Parameter Limits Min. µs ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit 125 200 800 1000 370 400 370 400 220 200 100 200 Typ. Max. Table 3.1.20 Switching characteristics (Extended operating temperature version) (VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –40 to 85 °C, unless otherwise noted) Table 3.1.19 Timing requirements (Extended operating temperature version) (VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –40 to 85 °C, unless otherwise noted) Serial I/O1 clock output “H” pulse width Serial I/O2 clock output “H” pulse width Serial I/O1 clock output “L” pulse width Serial I/O2 clock output “L” pulse width Serial I/O1 output delay time (Note 1) Serial I/O2 output delay time (Note 2) Serial I/O1 output valid time (Note 1) Serial I/O2 output valid time (Note 2) Serial I/O1 clock output rising time Serial I/O1 clock output falling time Serial I/O2 clock output rising time Serial I/O2 clock output falling time CMOS output rising time (Note 3) CMOS output falling time (Note 3) 140 200 Symbol Parameter Limits Min. ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit tc(SCLK1 )/2–30 tc(SCLK2 )/2–160 tc(SCLK1 )/2–30 tc(SCLK2 )/2–160 –30 Typ. Max. twH(S CLK1 ) twH(S CLK2 ) twL(SCLK1 ) twL(SCLK2 ) td(SCLK1 –TX D) td(SCLK2 –S OUT2 ) tv(SCLK1 –TXD) tv(SCLK2 –S OUT2 ) tr(SCLK1 ) tf(SCLK1 ) tr(SCLK2 ) tf(SCLK2 ) tr(CMOS) tf(CMOS) Test conditions Fig. 3.1.1 Note1: When the P45/TX D P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”. 2: When the P51/SOUT2 P-channel output disable bit of the serial I/O2 control register (bit 7 of address 001D16) is “0”. 3: XOUT pin excluded.

3.1.12 Timing requirements and Switching characteristics (Extended operating temperature version)

3802 GROUP USER'S MANUAL 3-13

Note 1:The RESET OUT output goes “H” in sync with the rise of the φ clock that is anywhere between about 8 cycle and 13 cycles after the RESET input goes “H”. Table 3.1.21 Timing requirements in memory expansion mode and microprocessor mode (Extended operating temperature version) (VCC = 4.0 to 5.5 V , VSS = 0 V, Ta = –40 to 85 °C, unless otherwise noted) Before φ ONW input set up time After φ ONW input hold time Before φ data bus set up time After φ data bus hold time Before RD ONW input set up time Before WR ONW input set up time After RD ONW input hold time After WR ONW input hold time Before RD data bus set up time After RD data bus hold time tsu(ONW– φ) th(φ–ONW) tsu(DB–φ) th(φ–DB) tsu(ONW–RD) tsu(ONW–WR) th(RD–ONW) th(WR–ONW) tsu(DB–RD) th(RD–DB) Symbol Parameter Limits Min. ns ns ns ns ns ns ns ns Unit –20 –20 –20 –20 Typ. Max. φ clock cycle time φ clock “H” pulse width φ clock “L” pulse width After φ AD15–AD 8 delay time After φ AD15–AD 8 valid time After φ AD7–AD 0 delay time After φ AD7–AD 0 valid time SYNC delay time SYNC valid time RD and WR delay time RD and WR valid time After φ data bus delay time After φ data bus valid time RD pulse width, WR pulse width RD pulse width, WR pulse width (when one wait is valid) Symbol Parameter Min. ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit tc(XIN)–10 tc(XIN)–10 25 tc(XIN) Typ. Max. t c(φ) twH(φ) twL(φ) td(φ–AH) tv(φ–AH) td(φ–AL) tv(φ–AL) td(φ–SYNC) tv(φ–SYNC) td(φ–WR) tv(φ–WR) td(φ–DB) tv(φ–DB) twL(RD) twL(WR) td(AH–RD) td(AH–WR) td(AL–RD) td(AL–WR) tv(RD–AH) tv(WR–AH) tv(RD–AL) tv(WR–AL) td(WR–DB) tv(WR–DB) td(RESET–RESET OUT ) tv(φ–RESET) Test conditions Fig. 3.1.1 Table 3.1.22 Switching characteristics in memory expansion mode and microprocessor mode (Extended operating temperature version) Fig. 3.1.1 Circuit for measuring output switching characteristics (VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –40 to 85 °C, unless otherwise noted) After AD15–AD 8 RD delay time After AD15–AD 8 WR delay time After AD7–AD 0 RD delay time After AD7–AD 0 WR delay time After RD AD15–AD 8 valid time After WR AD15–AD 8 valid time After RD AD7–AD 0 valid time After WR AD7–AD 0 valid time After WR data bus delay time After WR data bus valid time RESET OUT output delay time RESET OUT output valid time (Note 1) tc(XIN)–10 3tc(XIN)–10 tc(XIN)–35 tc(XIN)–40 tc(XIN)–15 tc(XIN)–20 15 65 200 200 ns ns ns ns ns ns ns ns nsMeasurement output pin 100pF CMOS output Limits

3802 GROUP USER'S MANUAL3-14

3.1.13 Timing diagram

tWL(INT) tWH(INT) tWL(X IN) tWH(X IN) tC(XIN) XIN tW(RESET) RESET tf tr tWL(CNTR) tWH(CNTR) tC(CNTR) td(SCLK1 -TXD),td(SCLK2-SOUT2 ) tv(SCLK1 -TXD), tv(SCLK2-SOUT2 ) tC(SCLK1 ), tC(SCLK2 ) tWL(S CLK1 ), tWL(S CLK2 ) tWH(S CLK1 ), tWH(S CLK2 ) th(SCLK1-R XD), th(SCLK2-SIN2) tsu(RXD -SCLK1 ), tsu(SIN2-SCLK2 ) TXD SOUT2 R XD SIN2 SCLK1 SCLK2 INT0–INT4 CNTR 0, CNTR1 Fig. 3.1.2 Timing diagram (in single-chip mode)

3802 GROUP USER'S MANUAL 3-15

Timing Diagram in Memory Expansion Mode and Microprocessor Mode (1) Timing Diagram in Microprocessor Mode tWL( f)tWH( f) tC(f) f td(f-AH) td(f-AL) td(f-SYNC) tv(f-AH) tv(f-AL) tv(f-SYNC) td(f-WR) tv(f-WR) tSU(ONW- f) th(f-ONW) tSU(DB- f) th(f-DB) td(f-DB) tv(f-DB) td(RESET- RESET OUT ) AD 15–AD 8 AD 7–AD 0 SYNC RD,WR ONW DB 0–DB 7 DB 0–DB 7 RESET f RESET OUT tv(f- RESETOUT )

0.5 VCC

(At CPU reading) (At CPU writing) Fig. 3.1.3 Timing diagram (in memory expansion mode and microprocessor mode) (1)

3802 GROUP USER'S MANUAL3-16

Timing Diagram in Memory Expansion Mode and Microprocessor Mode (2)

0.5 VCCRD,WR

0.5 VCCAD 15–AD 8

td(AH-WR) tv(WR-AH)

0.5 VCCAD 7–AD 0

td(AL-WR) tv(WR-AL)

0.2 VCCDB 0–DB 7

0.5 VCCRD

tSU(DB-RD) th(RD-DB)

0.5 VCCDB 0–DB 7

0.5 VCCWR

td(WR-DB) tv(WR-DB) th(WR-ONW) ONW tsu(ONW-WR) tv(RD-AH)td(AH-RD) td(AL-RD) tv(RD-AL) th(RD-ONW)tsu(ONW-RD) tWL(RD) tWL(WR) (At CPU reading) (At CPU writing) tWL(RD) tWL(WR) Fig. 3.1.4 Timing diagram (in memory expansion mode and microprocessor mode) (2)

3-173802 GROUP USER’S MANUAL

3.2.1 Power source current characteristic examples

Fig. 3.2.1 Power source current characteristic example [Measuring condition : 25 °C, A-D conversion stopped] Fig. 3.2.2 Power source current characteristic example (in wait mode) [Measuring condition : 25 °C, A-D conversion stopped] Vcc = 5.5V, Ta = 25 Vcc = 4.0V, Ta = 25 84321 567 Frequency f(XIN) (MHz) Power source current (mA) Rectangular waveform Vcc = 5.5V, Ta = 25 Vcc = 4.0V, Ta = 25 84321 567 Frequency f(XIN) (MHz) Power source current (mA) Rectangular waveform

3-18 3802 GROUP USER’S MANUAL

3.2.2 Port standard characteristic examples

Fig. 3.2.3 Standard characteristic example of CMOS output port at P-channel drive (1) Fig. 3.2.4 Standard characteristic example of CMOS output port at P-channel drive (2) VOH (V) IOH (mA) 0.5 –10 –15 –20 –25 –30 –35 –40 –45 –50 –10 –15 –20 –25 –30 –35 –40 –45 –50 Vcc = 5.0V Ta = 90 5.5 V cc = 5.5V Ta = 90 Vcc = 3.0V Ta = 90 VOH (V) IOH (mA) 0.5 Vcc = 5.0V Ta = 25 5.5 Vcc = 3.0V Ta = 25 Vcc = 5.5V Ta = 25 [Port 60 IOH –V OH characteristic (P-channel drive)] (Pins with same characteristic : P0, P1, P2, P3, P4, P5, P6) [Port 60 IOH –VOH characteristic (P-channel drive)] (Pins with same characteristic : P0, P1, P2, P3, P4, P5, P6)

3-193802 GROUP USER’S MANUAL Fig. 3.2.5 Standard characteristic example of CMOS output port at N-channel drive (1) VOL (V) IOL (mA) 0.5 V cc = 3.0V Ta = 90 V cc = 5.5V Ta = 90 V cc = 5.0V Ta = 90 Fig. 3.2.6 Standard characteristic example of CMOS output port at N-channel drive (2) VOL (V) IOL (mA) 0.5 V cc = 5.0V Ta = 25 V cc = 5.5V Ta = 25 V cc = 3.0V Ta = 25 [Port 60 IOL –V OL characteristic (N-channel drive)] (Pins with same characteristic : P0, P1, P2, P3, P4, P5, P6) [Port 60 IOL –V OL characteristic (N-channel drive)] (Pins with same characteristic : P0, P1, P2, P3, P4, P5, P6)

3-20 3802 GROUP USER’S MANUAL

3.2.3 A-D conversion standard characteristics

Figure 3.2.7 shows the A-D conversion standard characteristics. The lower-side line on the graph indicates the absolute precision error. It represents the deviation from the ideal value. For example, the conversion of output code from 127 to 128 occurs ideally at the point of AN = 2550 mV, but the measured value is –5 mV. Accordingly, the measured point of conversion is repre- sented as “2550 – 5 = 2545 mV.” The upper-side line on the graph indicates the width of input voltages equivalent to output codes. For example, the measured width of the input voltage for output code 170 is 23 mV, so the differential nonlinear error is represented as “23 – 20 = 3 mV” (0.15 LSB). Fig. 3.2.7 A-D conversion standard characteristics M38027E8SS A-D CONVERTER STEP WIDTH MEASUREMENT Measured when a power source voltage is stable in the single-chip mode

3-213802 GROUP USER’S MANUAL

3.2.4 D-A conversion standard characteristics

Figure 3.2.8 shows the D-A conversion standard characteristics. The lower-side line on the graph indicates the absolute precision error. In this case, it represents the difference between the ideal analog output value for an input code and the measured value. The upper-side line on the graph indicates the change width of output analog value to a one-bit change of input code. Fig. 3.2.8 D-A conversion standard characteristics Measured when a power source voltage is stable in the single-chip mode M38027E8SS D-A CONVERTER STEP WIDTH MEASUREMENT

3802 GROUP USER’S MANUAL3-22

(1) Sequence for switching an external interrupt detection edge Clear an interrupt enable bit to “0” (interrupt disabled) Switch the detection edge Clear an interrupt request bit to “0” (no interrupt requ- est issued) Set the interrupt enable bit to “1” ( interrupt enabled )

3.3.1 Notes on interrupts

When the external interrupt detection edge must be switched, make sure the following sequence. Reason The interrupt circuit recognizes the switching of the detection edge as the change of external input signals. This may cause an unnecessary interrupt. (2) Bit 7 of the interrupt control register 2 Fix the bit 7 of the interrupt control register 2 (Address:003F 16) to “0”. Figure 3.3.1 shows the structure of the interrupt control register 2. Fig. 3.3.1 Structure of interrupt control register 2

3.3.2 Notes on the serial I/O1

(1) Stop of data transmission As for the serial I/O1 that can be used as either a clock synchronous or an asynchronous (UART) serial I/O, clear the transmit enable bit to “0” (transmit disabled), and clear the serial I/O enable bit to “0” (serial I/O1 disabled)in the following cases : l when stopping data transmission during transmitting data in the clock synchronous serial I/O mode l when stopping data transmission during transmitting data in the UART mode l when stopping only data transmission during transmitting and receiving data in the UART mode Reason Since transmission is not stopped and the transmission circuit is not initialized even if the serial I/O1 enable bit is cleared to “0” (serial I/O1 disabled), the internal transmission is running (in this case, since pins TxD, RxD, S and SRDY1 function as I/O ports, the transmission data is not output). When data is written to the transmit buffer register in this state, the data is transferred to the transmit shift register and start to be shifted. When the serial I/O1 enable bit is set to “1” at this time, the data during internally shifting is output to the TxD pin and ti may cause an operation failure to a microcomputer. (2) Stop of data reception As for the serial I/O1 that can be used as either a clock synchronous or an asynchronous (UART) serial I/O, clear the receive enable bit to “0” (receive disabled), or clear the serial I/O enable bit to “0” (serial I/O disabled) in the following case : l when stopping data reception during receiving data in the clock synchronous serial I/O mode Clear the receive enable bit to “0” (receive disabled) in the following cases : l when stopping data reception during receiving data in the UART mode l when stopping only data reception during transmitting and receiving data in the UART mode b7 b0 Interrupt control register 2 Address 003F16 Interrupt enable bits Not used Fix this bit to “0”

3802 GROUP USER’S MANUAL 3-23

(3) Stop of data transmission and reception in a clock synchronous serial I/O mode As for the serial I/O1 that can be used as either a clock synchronous or an asynchronous (UART) serial I/O, clear both the transmit enable bit and receive enable bit to “0” (transmit and receive disabled) at the same time in the following case: l when stopping data transmission and reception during transmitting and receiving data in the clock synchronous mode (when data is transmitted and received in the clock synchronous serial I/O mode, any one of data transmission and reception cannot be stopped.) Reason In the clock synchronous serial I/O mode, the same clock is used for transmission and reception. If any one of transmission and reception is disabled, a bit error occurs because transmission and reception cannot be synchronized. In this mode, the clock circuit of the transmission circuit also operates for data reception. Accordingly, the transmission circuit does not stop by clearing only the transmit enable bit to “0” (transmit disabled). Also, the transmission circuit is not initialized by clearing the serial I/O1 enable bit to “0” (serial I/O1 disabled) (refer to (1)). (4) The SRDY pin on a receiving side_____ When signals are output from the SRDY pin on the reception side by using an external clock in the clock_____ synchronous serial I/O mode, set all of the receive enable bit, the SRDY output enable bit, and the transmit enable bit to “1” (transmit enabled). (5) Stop of data reception in a clock synchronous serial I/O mode Set the serial I/O1 control register again after the transmission and the reception circuits are reset by clearing both the transmit enable bit and the receive enable bit to “0.” Clear both the transmit enable bit (TE) and the receive enable bit (RE) to “0” Set the bits 0 to 3 and bit 6 of the serial I/O1 control register Set both the transmit enable bit (TE) and the receive enable bit (RE) to “1” Can be set with the LDM instruction at the same time (6) Control of data transmission using the transmit shift completion flag The transmit shift completion flag changes from “1” to “0” with a delay of 0.5 to 1.5 shift clocks. When checking the transmit shift completion flag after writing a data to the transmit buffer register for controlling a data transmission, note this delay. (7) Control of data transmission using an external clock When an external clock is used as the synchronous clock for data transmission, set the transmit enable bit to “1” at “H” level of the S CLK input signal. Also, write data to the transmit buffer register at “H” level of the SCLK input signal.

3.3.3 Notes on the A-D converter

(1) Input of signals from signal source with high impedance to an analog input pin Make the signal source impedance for analog input low, or equip an analog input pin with an external capacitor of 0.01 µF to 1 µF. Further, maek sure to check the operation of application products on the user side. Reason The A-D converter builds in the capacitor for analog voltage comparison. Accordingly, when signals from signal source with high impedance are input to an analog input pin, a charge and discharge noise generates. This may cause the A-D conversion precision to be worse.

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(2) AVSS pin Connect a power source for the A-D converter, AVSS pin to the VSS line of the analog circuit. (3) A clock frequency during an A-D conversion The comparator consists of a capacity coupling, and a charge of the capacity will be lost if the clock frequency is too low. Thus, make sure the following during an A-D conversion. l f(X IN) is 500 kHz or more . (When the ONW pin is "L", f(XIN) is 1 MHz or more.) l Do not execute the STP instruction and WIT instruction.

3.3.4 Notes on the RESET pin

When a rising time of the reset signal is long, connect a ceramic capacitor or others across the RESET pin and the VSS pin. And use a 1000 pF or more capacitor for high frequency use. When connecting the capacitor, make sure the following : l Make the length of the wiring which is connected to a capacitor the shortest possible. l Make sure to check the operation of application products on the user side. Reason If the several nanosecond or several ten nanosecond impulse noise enters the RESET pin, a microcomputer may malfunction.

3.3.5 Notes on input and output pins

(1) Fix of a port input level in stand-by state Fix input levels of an input and an I/O port for getting effect of low-power dissipation in stand-by state, especially for the I/O ports of the N-channel open-drain. Pull-up (connect the port to V CC ) or pull-down (connect the port to VSS ) these ports through a resistor. When determining a resistance value, make sure the following: l External circuit l Variation of output levels during the ordinary operation * stand-by state : the stop mode by executing the STP instruction the wait mode by executing the WIT instruction Reason Even when setting as an output port with its direction register, in the following state : the transistor becomes the OFF state, which causes the ports to be the high-impedance state. Make sure that the level becomes “undefined” depending on external circuits. Accordingly, the potential which is input to the input buffer in a microcomputer is unstable in the state that input levels of an input and an I/O port are “undefined.” This may cause power source current. (2) Modify of the content of I/O port latch When the content of the port latch of an I/O port is modified with the bit managing instruction*, the value of the unspecified bit may be changed. Reason The bit managing instruction is read-modify-write instruction for reading and writing data by a byte unit. Accordingly, when this instruction is executed on one bit of the port latch of an I/O port, the following is executed to all bits of the port latch. l As for a bit which is set as an input port : The pin state is read in the CPU, and is written to this bit after bit managing. l As for a bit which is set as an output port : The bit value is read in the CPU, and is written to this bit after bit managing.

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Make sure the following : l Even when a port which is set as an output port is changed for an input port, its port latch holds the output data. l Even when a bit of a port latch which is set as an input port is not speccified with a bit managing instruction, its value may be changed in case where content of the pin differs from a content of the port latch. * bit managing instructions : SEB and CLB instruction (3) The AVSS pin when not using the A-D converter When not using the A-D converter, handle a power source pin for the A-D converter, AVSS pin as follows : l l l l l AV SS : Connect to the VSS pin Reason If the AVSS pin is opened, the microcomputer may malfunction by effect of noise or others.

3.3.6 Notes on memory expansion mode and microprocessor mode

(1) Writing data to the port latch of port P3 In the memory expansion or the microprocessor mode, ports P30 and P31 can be used as the output port. Use the LDM or STA instruction for writing data to the port latch (address 000616) of port P3. When using a read-modify-write instruction (the SEB or the CLB instruction), allocate the read and the write enabled memory at address 000616. Reason In the memory expansion or microprocessor mode, address 000616 is allocated in the external area. Accordingly, Data is read from the external memory. Data is written to both the port latch of the port P3 and the external memory. Accordingly, when executing a read-modify-write instruction for address 000616, external memory data is read and modified, and the result is written in both the port latch of the port P3 and the external memory. If the read enabled memory is not allocated at address 0006 16, the read data is undefined. The undefined data is modified and written to the port latch of the port P3. The port latch data of port P3 becomes “undefined.” (2) Overlap of an internal memory and an external memory When the internal and the external memory are overlapped in the memory expansion mode, the internal memory is valid in this overlapped area. When the CPU writes or reads to this area, the following is performed : When reading data Only the data in the internal memory is read into the CPU and the data in the external memory is not read into the CPU. However, as the read signal and address are still valid, the external memory data of the corresponding address is output to the external data bus. When writing data Data is written in both the internal and the external memory.

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3.3.7 Notes on built-in PROM

(1) Programming adapter To write or read data into/from the internal PROM, use the dedicated programming adapter and general-purpose PROM programmer as shown in Table 3.3.1. Table 3.3.1 Programming adapter Microcomputer M38027E8SS M38027E8SP (one-time blank) M38027E8DSP (one-time blank) M38027E8FS M38027E8FP (one-time blank) M38027E8DFP (one-time blank) Programming adapter PCA4738S-64A PCA4738L-64A PCA4738F-64A (2) Write and read In PROM mode, operation is the same as that of the M5M27C256AK and the M5M27C101, but programming conditions of PROM programmer are not set automatically because there are no internal device ID codes. Accurately set the following conditions for data write/read. Take care not to apply 21 V to Vpp pin (is also used as the CNV SS pin), or the product may be permanently damaged. l Programming voltage : 12.5 V l Setting of programming adapter switch : refer to table 3.3.2 l Setting of PROM programmer address : refer to table 3.3.3 Table 3.3.2 Setting of programming adapter switch SW 1 CMOS SW 2 CMOS SW 3 OFF Programming adapter PCA4738S-64A PCA4738L-64A PCA4738F-64A

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Table 3.3.3 Setting of PROM programmer address PROM programmer completion address Address : 7FFD16 (Note 1) Address : 7FFD16 (Note 2) PROM programmer start address Address : 408016 (Note 1) Address : 008016 (Note 2) Note1 : Addresses C08016 to FFFD16 in the internal PROM correspond to addresses 408016 to 7FFD16 in the ROM programmer. 2 : Addresses 808016 to FFFD16 in the internal PROM correspond to addresses 008016 to 7FFD16 in the ROM programmer. (3) Erasing Contents of the windowed EPROM are erased through an ultraviolet light source of the wavelength 2537- Angstrom . At least 15 W-sec/cm are required to erase EPROM contents. Microcomputer M38022E4SS M38022E4SP M38022E4FS M38022E4FP M38022E4DSP M38022E4DFP M38027E8SS M38027E8SP M38027E8FS M38027E8FP M38027E8DSP M38027E8DFP

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3.4 Countermeasures against noise

Countermeasures against noise are described below. The following countermeasures are effective against noise in theory, however, it is necessary not only to take measures as follows but to evaluate before actual use.

3.4.1 Shortest wiring length

The wiring on a printed circuit board can be as an antenna which feeds noise into the microcomputer. The shorter the total wiring length (by mm unit), the less the possibility of noise insertion into a microcomputer. (1) Wiring for the RESET pin Make the length of wiring which is connected to the RESET pin as short as possible. Especially, connect a capacitor across the RESET pin and the V SS pin with the shortest possible wiring (within 20mm). Reason The reset works to initialize a microcomputer. The width of a pulse input into the RESET pin is determined by the timing necessary conditions. If noise having a shorter pulse width than the standard is input to the RESET pin, the reset is released before the internal state of the microcomputer is completely initialized. This may cause a program runaway. Fig. 3.4.1 Wiring for the RESET pin (2) Wiring for clock input/output pins l Make the length of wiring which is connected to clock I/O pins as short as possible. l Make the length of wiring (within 20mm) across the grounding lead of a capacitor which is connected to an oscillatorand the V SS pin of a microcomputer as short as possible. l Separate the VSS pattern only for oscillation from other VSS patterns. Reason A microcomputer's operation synchronizes with a clock generated by the oscillator (circuit). If noise enters clock I/O pins, clock waveforms may be deformed. This may cause a malfunction or program runaway. Also, if a potential difference is caused by the noise between the V SS level of a microcomputer and the VSS level of an oscillator, the correct clock will not be input in the microcomputer. RESETReset circuit Noise VSSVSS Reset circuit VSS RESET VSS 3802 group 3802 groupN.G. O.K.

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Fig. 3.4.2 Wiring for clock I/O pins (3) Wiring for the VPP pin of the One Time PROM version and the EPROM version (In this microcomputer the VPP pin is also used as the CNVSS pin) Connect an approximately 5 kΩ resistor to the VPP pin the shortest possible in series and also to the VSS pin. When not connecting the resistor, make the length of wiring between the VPP pin and the VSS pin the shortest possible. Note:Even when a circuit which inclued an approximately 5 kΩ resistor is used in the Mask ROM version, the maicrocomputer operates correctly. Reason The VPP pin of the One Time PROM and the EPROM version is the power source input pin for the built-in PROM. When programming in the built-in PROM, the impedance of the V PP pin is low to allow the electric current for wiring flow into the PROM. Be- cause of this, noise can enter easily. If noise enters the V PP pin, abnormal in struction codes or data are read from the built-in PROM, which may cause a program runaway.

3.4.2 Connection of a bypass capacitor across the

Connect an approximately 0.1 µF bypass capacitor across the VSS line and the VCC line as follows: l Connect a bypass capacitor across the VSS pin and the VCC pin at equal length . l Connect a bypass capacitor across the VSS pin and the VCC pin with the shortest possible wiring. l Use lines with a larger diameter than other signal lines for VSS line and VCC line. Fig. 3.4.3 Wiring for the VPP pin of the One Time PROM and the EPROM version Fig. 3.4.4 Bypass capacitor across the VSS line and the VCC line VSS VCC VSSVCC Chip XIN XOUT VSS An example of VSS patterns on the underside of a printed circuit board Oscillator wiring pattern example Separate the V SS line for oscillation from other VSS lines Noise XIN XOUT VSS XIN XOUT VSS N.G. O.K. CNV SS /VPP Approximately 5kΩ 3802 group VSS Make it the shortest possible

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3.4.3 Wiring to analog input pins

l Connect an approximately 100 Ω to 1 kΩ resistor to an analog signal line which is connected to an analog input pin in series. Besides, connect the resistor to the microcomputer as close as possible. l Connect an approximately 1000 pF capacitor across the V SS pin and the analog input pin. Besides, connect the capacitor to the VSS pin as close as possible. Also, connect the capacitor across the analog input pin and the V SS pin at equal length. Reason Signals which is input in an analog input pin (such as an A-D converter input pin) are usually output signals from sensor. The sensor which detects a change of event is installed far from the printed circuit board with a microcomputer, the wiring to an analog input pin is longer necessarily. This long wiring functions as an antenna which feeds noise into the microcomputer, which causes noise to an analog input pin. 3.4.4. Consideration for oscillator Take care to prevent an oscillator that generates clocks for a microcomputer operation from being affected by other signals. (1) Keeping an oscillator away from large current signal lines Install a microcomputer (and especially an oscillator) as far as possible from signal lines where a current larger than the tolerance of current value flows. Reason In the system using a microcomputer, there are signal lines for controlling motors, LEDs, and thermal heads or others. When a large current flows through those signal lines, strong noise occurs because of mutual inductance. (2) Keeping an oscillator away from signal lines where potential levels change frequently Install an oscillator and a connecting pattern of an osillator away from signal lines where potential levels change frequently. Also, do not cross such signal lines over the clock lines or the signal lines which are sensitive to noise. Reason Signal lines where potential levels change frequently (such as the CNTR pin line) may affect other lines at signal rising or falling edge. If such lines cross over a clock line, clock waveforms may be deformed, which causes a microcomputer failure or a program runaway. Fig.3.4.6 Wiring for a large current signal line Fig.3.4.7 Wiring to a signal line where potential levels change frequently XIN XOUT VSS M Microcomputer Mutual inductance Large current GND XIN XOUT VSS CNTRDo not cross Fig.3.4.5 Analog signal line and a resistor and a capacitor N.G. O.K. VSS Analog input pin Microcomputer(Note) Thermistor Noise Note:The resistor is for dividing resistance with a thermister.

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3.4.5 Setup for I/O ports

Setup I/O ports using hardware and software as follows: <Hardware> l Connect a resistor of 100 Ω or more to an I/O port inseries. <Software> l As for an input port, read data several times by a program for checking whether input levels are equal or not. l As for an output port, since the output data may reverse because of noise, rewrite data to its port latch at fixed periods. l Rewirte data to direction registers and pull-up control registers (only the product having it) at fixed periods. Fig. 3.4.8 Setup for I/O ports When a direction register is set for input port again at fixed periods, a several-nanosecond short pulse may be output from this port. If this is undesirable, connect a capacitor to this port to remove the noise pulse.

3.4.6 Providing of watchdog timer function by

If a microcomputer runs away because of noise or others, it can be detected by a software watchdog timer and the microcomputer can be reset to normal operation. This is equal to or more effective than program runaway detection by a hardware watchdog timer. The following shows an example of a watchdog timer provided by software. In the following example, to reset a microcomputer to normal operation, the main routine detects errors of the interrupt processing routine and the interrupt processing routine detects errors of the main routine. This example assumes that interrupt processing is repeated multiple times in a single main routine processing. <The main routine> l Assigns a single byte of RAM to a software watchdog timer (SWDT) and writes the initial value N in the SWDT once at each execution of the main routine. The initial value N should satisfy the following condition: Fig. 3.4.9 Watchdog timer by software N+1 ≥ (Counts of interrupt processing executed in each main routine) As the main routine execution cycle may change because of an interrupt processing or others, the initial value N should have a margin. l Watches the operation of the interrupt processing routine by comparing the SWDT contents with counts of interrupt processing count after the initial value N has been set. l Detects that the interrupt processing routine has failed and determines to branch to the program initialization routine for recovery processing in the following cases: If the SWDT contents do not change after interrupt processing Direction register Port latch Data bus I/O port pins Noise Noise N.G. O.K. Main routine (SWDT) ← N CLI Main processing (SWDT) Interrupt processing routine errors Interrupt processing routine (SWDT) ← (SWDT)—1 Interrupt processing (SWDT) Main routine errors ≤0 RTI Return =N? ≤0?

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<The interrupt processing routine> l Decrements the SWDT contents by 1 at each interrupt processing. l Determins that the main routine operates normally when the SWDT contents are reset to the initial value N at almost fixed cycles (at the fixed interrupt processing count). l Detects that the main routine has failed and determines to branch to the program initialization routine for recovery processing in the following case: When the contents of the SWDT reach 0 or less by continuative decrement without initializing to the initial value N .

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Fig. 3.5.2 Structure of Port Pi direction register (i = 0, 1, 2, 3, 4, 5, 6) Fig. 3.5.1 Structure of Port Pi (i = 0, 1, 2, 3, 4, 5, 6) Port Pi direction register b7 b6 b5 b4 b3 b2 b1 b0 B Function At resetRW Name Port Pi direction register 0 Port Pi direction register (PiD) (i = 0, 1, 2, 3, 4, 5, 6) [Address : 0116, 0316, 0516, 0716, 0916, 0B16, 0D16] 0 : Port Pi0 input mode 1 : Port Pi0 output mode 0 : Port Pi1 input mode 1 : Port Pi1 output mode 0 : Port Pi2 input mode 1 : Port Pi2 output mode 0 : Port Pi3 input mode 1 : Port Pi3 output mode 0 : Port Pi4 input mode 1 : Port Pi4 output mode 0 : Port Pi5 input mode 1 : Port Pi5 output mode 0 : Port Pi6 input mode 1 : Port Pi6 output mode 0 : Port Pi7 input mode 1 : Port Pi7 output mode Port Pi b7 b6 b5 b4 b3 b2 b1 b0 B Function At resetRW Name Port Pi0 Port Pi1 Port Pi2 Port Pi3 Port Pi4 Port Pi5 Port Pi6 Port Pi7 In output mode Write Read l Port latch In input mode Write : Port latch Read : Value of pins l [Address : 00 16, 0216, 0416, 0616, 0816, 0A16, 0C16]

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Fig. 3.5.3 Structure of Transmit/Receive buffer register Transmit/Receive buffer register b7 b6 b5 b4 b3 b2 b1 b0 B Function At resetRW Transmit/Receive buffer register (TB/RB) [Address : 1816] A transmission data is written to or a receive data is read out from this buffer register.

• At writing : a data is written to the Transmit buffer register.
• At reading : a content of the Receive buffer register is read out. 5 ? Fig. 3.5.4 Structure of Serial I/O1 status register b7 b6 b5 b4 b3 b2 b1 b0 B Function At resetRW Serial I/O1 status register (SIO1STS) [Address : 1916] Name Transmit buffer empty flag (TBE) 0 : (OE) (PE) (FE) = 0 1 : (OE) (PE) (FE) = 1 Overrun error flag (OE) 0 : Buffer full 1 : Buffer empty Nothing is allocated for this bit. It is a write disabled bit. When this bit is read out, the value is “0.” Receive buffer full flag (RBF) Transmit shift register shift completion flag (TSC) Parity error flag (PE) Framing error flag (FE) Summing error flag (SE) 0 : Buffer empty 1 : Buffer full 0 : Transmit shift in progress 1 : Transmit shift completed 0 : No error 1 : Overrun error 0 : No error 1 : Parity error 0 : No error 1 : Framing error Serial I/O1 status register

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Fig. 3.5.5 Structure of Serial I/O1 control register Serial I/O1 synchronous clock selection bit (SCS) SRDY1 output enable bit (SRDY) Transmit interrupt source selection bit (TIC) Serial I/O1 control register b7 b6 b5 b4 b3 b2 b1 b0 B Function At resetRW 0 : f(XIN) 1 : f(XIN)/4 0 Serial I/O1 control register (SIO1CON) [Address : 1A16] Name BRG count source selection bit (CSS) Serial I/O1 enable bit (SIOE) 0 : I/O port (P47) 1 : SRDY1 output pin Transmit enable bit (TE) Receive enable bit (RE) Serial I/O1 mode selection bit (SIOM) 0 : Transmit buffer empty 1 : Transmit shift operating completion 0 : Transmit disabled 1 : Transmit enabled 0 : Receive disabled 1 : Receive enabled 0 : UART 1 : Clock synchronous serial I/O 0 : Serial I/O1 disabled (P44–P47 : I/O port) 1 : Serial I/O1 enabled (P44–P47 : Serial I/O function pin) At selecting clock synchronous serial I/O 0 : BRG output divided by 4 1 : External clock input At selecting UART 0 : BRG output divided by 16 1 : External clock input divided by 16 Fig. 3.5.6 Structure of UART control register In output mode 0 : CMOS output 1 : N-channel open-drain output UART control register b7 b6 b5 b4 b3 b2 b1 b0 B Function At resetRW UART control register (UARTCON) [Address : 1B16] Name 0 : 8 bits 1 : 7 bits 0 : Parity checking disabled 1 : Parity checking enabled 0 : 1 stop bit 1 : 2 stop bits 0 : Even parity 1 : Odd parity Character length selection bit (CHAS) Parity enable bit (PARE) Stop bit length selection bit (STPS) Parity selection bit (PARS) P45/TxD P-channel output disable bit (POFF) Nothing is allocated for these bits. These are write disabled bits. When these bits are read out, the values are “1.”

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Fig. 3.5.7 Structure of Baud rate generator A count value of Baud rate generator is set. Function Baud rate generator (BRG) [Address : 1C16] Baud rate generator b7 b6 b5 b4 b3 b2 b1 b0 B At resetRW Fig. 3.5.8 Structure of Serial I/O2 control register Serial I/O2 control register (SIO2CON) [Address : 1D16] Serial I/O2 control register b7 b6 b5 b4 b3 b2 b1 b0 B Function At resetRW Name SRDY2 output enable bit Internal synchronous clock selection bits 0 : I/O port (P51, P52) 1 : SOUT2 , SCLK2 output pin 0 : I/O port (P53) 1 : SRDY2 output pin 0 : LSB first 1 : MSB first 0 : External clock 1 : Internal clock 0 0 0 : f(XIN)/8 0 0 1 : f(XIN)/16 0 1 0 : f(XIN)/32 0 1 1 : f(XIN)/64 1 1 0 : f(XIN)/128 1 1 1 : f(XIN)/256 Transfer direction selection bit Serial I/O2 port selection bit Serial I/O2 synchronous clock selection bit P51/SOUT2 P-channel output disable bit b2 b1 b0 0 : CMOS output 1 : N-channel open-drain output In output mode

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Fig. 3.5.9 Structure of Serial I/O2 register Serial I/O2 register b7 b6 b5 b4 b3 b2 b1 b0 Function Serial I/O2 register (SIO2) [Address : 1F16] A shift register for serial transmission and reception. At transmitting : Set a transmission data. At receiving : Store a reception data. B At resetRW l l Fig. 3.5.10 Structure of Prescaler 12, Prescaler X, Prescaler Y Prescaler 12, Prescaler X, Prescaler Y b7 b6 b5 b4 b3 b2 b1 b0 B Function At resetRW Prescaler 12 (PRE12), Prescaler X (PREX), Prescaler Y (PREY) [Address : 2016, 2416, 2616] The count value of each prescaler is set. The value set in this register is written to both the prescaler and the prescaler latch at the same time. When the prescaler is read out, the value (count value) of the prescaler is read out. l l l

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Fig. 3.5.11 Structure of Timer 1 b7 b6 b5 b4 b3 b2 b1 b0 B Function At resetRW Timer 1 (T1) [Address : 2116] The count value of the Timer 1 is set. The value set in this register is written to both the Timer 1 and the Timer 1 latch at the same time. When the Timer 1 is read out, the value (count value) of the Timer 1 is read out. l l l Timer 1 Fig. 3.5.12 Structure of Timer 2, Timer X, Timer Y Timer 2, Timer X, Timer Y b7 b6 b5 b4 b3 b2 b1 b0 B Function At resetRW Timer 2 (T2), Timer X (TX), Timer Y (TY) [Address : 2216, 2516, 2716] The count value of each timer is set. The value set in this register is written to both the Timer and the Timer latch at the same time. When the Timer is read out, the value (count value) of the Timer is read out. l l l

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Pulse width measurement mode Table. 3.5.1 Function of CNTR0/CNTR 1 edge switch bit Fig. 3.5.13 Structure of Timer XY mode register Function of CNTR0/CNTR 1 edge switch bit (bits 2 and 6) “0” “1” “0” “1” “0” “1” “0” “1”

• Generation of CNTR 0/CNTR 1 interrupt request : Falling edge (No effect on timer count)
• Generation of CNTR 0/CNTR 1 interrupt request : Rising edge (No effect on timer count)
• Start of pulse output : From “H” level
• Generation of CNTR 0/CNTR 1 interrupt request : Falling edge
• Start of pulse output : From “L” level
• Generation of CNTR 0/CNTR 1 interrupt request : Rising edge
• Timer X/Timer Y : Count of rising edge
• Generation of CNTR 0/CNTR 1 interrupt request : Falling edge
• Timer X/Timer Y : Count of falling edge
• Generation of CNTR 0/CNTR 1 interrupt request : Rising edge
• Timer X/Timer Y : Measurement of “H” level width
• Generation of CNTR 0/CNTR 1 interrupt request : Falling edge
• Timer X/Timer Y : Measurement of “L” level width
• Generation of CNTR 0/CNTR 1 interrupt request : Rising edge /LiteDiagLines /LiteDiagLines/LiteDiagLines Function Timer XY mode register b7 b6 b5 b4 b3 b2 b1 b0 B At resetR W Timer XY mode register (TM) Name Timer X operating mode CNTR 0 active edge switch bit Timer Y operating mode CNTR 1 active edge switch bit 0 0 : Timer mode 0 1 : Pulse output mode 1 0 : Event counter mode 1 1 : Pulse width measurement mode 0 0 : Timer mode 0 1 : Pulse output mode 1 0 : Event counter mode 1 1 : Pulse width measurement mode It depends on the operating mode of the Timer X (refer to Table 3.5.1). It depends on the operating mode of the Timer Y (refer to Table 3.5.1 ). b5 b4 Timer X count stop bit [Address : 2316] b1 b0 Timer Y count stop bit 0 : Count start 1 : Count stop 0 : Count start 1 : Count stop

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Fig. 3.5.14 Structure of PWM control register Fig. 3.5.15 Structure of PWM prescaler PWM control register b7 b6 b5 b4 b3 b2 b1 b0 B At resetRW PWM control register (PWMCON) [Address:2B16] FunctionName Nothing is arranged for these bits. These are write disabled bits. When these bits are read out, the contents are "0". PWM function enable bit 0 : PWM disabled 1 : PWM enabled Count source selection bit0 : f(XIN) 1 : f(XIN)/2 PWM prescaler b7 b6 b5 b4 b3 b2 b1 b0 B Function At resetRW PWM prescaler (PREPWM) [Address : 2C16] PWM cycle is set. The values set in this register is written to both the PWM prescaler pre-latch and the PWM prescaler latch at the same time. When data is written during outputting PWM, the pulses corresponding to the changed contents are output starting with the next cycle. When this register is read out, the content of the PWM prescaler latch is read out. l l l l

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Fig. 3.5.16 Structure of PWM register PWM register b7 b6 b5 b4 b3 b2 b1 b0 b At resetRW PWM register (PWM) [Address : 2D16] Function “H” level output period of PWM is set. The values set in this register is written both the PWM register pre-latch and the PWM register latch at the same time. When data is written during outputting PWM, the pulses corresponding to the changed contents are output starting with the next cycle. When this register is read out, the content of the PWM register latch is read out. l l l l

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Fig. 3.5.18 Structure of A-D conversion register Fig. 3.5.17 Structure of AD/DA control register A-D conversion register b7 b6 b5 b4 b3 b2 b1 b0 B Function At resetRW A-D conversion register (AD) [Address : 3516] The read-only register which A-D conversion results are stored.50 AD/DA control register b7 b6 b5 b4 b3 b2 b1 b0 B Function At resetRWName Analog input pin selection bits AD/DA control register (ADCON) [Address : 3416] 0 0 0 : P60/AN0 0 0 1 : P61/AN1 0 1 0 : P62/AN2 0 1 1 : P63/AN3 1 0 0 : P64/AN4 1 0 1 : P65/AN5 1 1 0 : P66/AN6 1 1 1 : P67/AN7 b2 b1 b0 00 : DA1 output disable 1 : DA1 output enable DA 1 output enable bit6 0 5Nothing is allocated for these bits. These are write disabled bits.4 When these bits are read out, the values are “0.” 0 : DA2 output disabled 1 : DA2 output enabled DA 2 output enable bit 5 0 5 AD conversion completion bit0 : Conversion in progress 1 : Conversion completed

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Fig. 3.5.19 Structure of D-A 1 conversion, D-A 2 conversion register Fig. 3.5.20 Structure of Interrupt edge selection register D-A1 conversion register, D-A2 conversion register b7 b6 b5 b4 b3 b2 b1 b0 B Function At resetRW D-A1 conversion register (DA1), D-A2 conversion register (DA2) [Address : 3616, 3716] An output value of each D-A converter is set. WR Interrupt edge selection register b7 b6 b5 b4 b3 b2 b1 b0 B Function At reset Interrupt edge selection register (INTEDGE) [Address : 3A16] Name 0 : Falling edge active 1 : Rising edge active 0 : Falling edge active 1 : Rising edge active 0 : Falling edge active 1 : Rising edge active 0 : Falling edge active 1 : Rising edge active 0 : Falling edge active 1 : Rising edge active INT0 interrupt edge selection bit INT1 interrupt edge selection bit INT2 interrupt edge selection bit INT3 interrupt edge selection bit INT4 interrupt edge selection bit Nothing is allocated for this bit. This is a write disabled bit.When this bit is read out, the value is “0.” Nothing is allocated for these bits. These are write disabled bits. When these bits are read out, the values are “0.”

3802 GROUP USER’S MANUAL3-44

Fig. 3.5.21 Structure of CPU mode register Nothing is allocated for these bits. These are write disabled bits. When these bits are read out, the values are “0.” CPU mode register (CPUM) [Adress : 3B16] CPU mode register b7 b6 b5 b4 b3 b2 b1 b0 Function At resetRW B Name Processor mode bits 00 : Single-chip mode 01 : Memory expansion mode 10 : Microprocessor mode 11 : Not available Stack page selection bit 0 : 0 page 1 : 1 page [ An initial value of bit 1 is determined by a level of the CNV SS pin. 0 5 0 5 0 5 0 5

3802 GROUP USER’S MANUAL 3-45

Fig. 3.5.22 Structure of Interrupt request register 1 Fig. 3.5.23 Structure of Interrupt request register 2 Interrupt request register 2 b7 b6 b5 b4 b3 b2 b1 b0 B Function At resetRW Interrupt request reigster 2 (IREQ2) [Address : 3D16] Name CNTR 0 interrupt request bit CNTR 1 interrupt request bit Serial I/O2 interrupt request bit 0 : No interrupt request 1 : Interrupt request 0 : No interrupt request 1 : Interrupt request 0 : No interrupt request 1 : Interrupt request 0 : No interrupt request 1 : Interrupt request INT2 interrupt request bit 0 : No interrupt request 1 : Interrupt request Nothing is allocated for this bit. This is a write disabled bit. When this bit is read out, the value is “0.” AD conversion interrupt request bit INT 4 interrupt request bit 0 : No interrupt request 1 : Interrupt request [ “0” is set by software, but not “1.” 4 00 : No interrupt request 1 : Interrupt request INT3 interrupt request bit [ 0 5 Timer X interrupt request bit Serial I/O1 receive interrupt request bit Interrupt request register 1 b7 b6 b5 b4 b3 b2 b1 b0 B Function At resetRW Interrupt request reigster 1 (IREQ1) [Address : 3C16] Name INT0 interrupt request bit INT1 interrupt request bit 0 : No interrupt request 1 : Interrupt request 0 : No interrupt request 1 : Interrupt request 0 : No interrupt request 1 : Interrupt request 0 : No interrupt request 1 : Interrupt request Serial I/O1 transmit interrupt request bit Timer Y interrupt request bit Timer 1 interrupt request bit0 : No interrupt request 1 : Interrupt request Timer 2 interrupt request bit 0 : No interrupt request 1 : Interrupt request 0 : No interrupt request 1 : Interrupt request 0 : No interrupt request 1 : Interrupt request [ “0” is set by software, but not “1.”

3802 GROUP USER’S MANUAL3-46

Fig. 3.5.24 Structure of Interrupt control register 1 Fig. 3.5.25 Structure of Interrupt control register 2 Interrupt control register 2 b7 b6 b5 b4 b3 b2 b1 b0 B Function At resetRW Interrupt control reigster 2 (ICON2) [Address : 3F16] Name CNTR 0 interrupt enable bit CNTR 1 interrupt enable bit Serial I/O2 interrupt enable bit 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabledINT2 interrupt enable bit 0 : Interrupt disabled 1 : Interrupt enabled Fix this bit to “0.” AD conversion interrupt enable bit INT4 interrupt enable bit 0 : Interrupt disabled 1 : Interrupt enabled 4 00 : Interrupt disabled 1 : Interrupt enabled INT 3 interrupt enable bit Timer Y interrupt enable bit Interrupt control register 1 b7 b6 b5 b4 b3 b2 b1 b0 B Function At resetRW Interrupt control register 1 (ICON1) [Address : 3E16] Name INT0 interrupt enable bit INT1 interrupt enable bit 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled Timer X interrupt enable bit Timer 1 interrupt enable bit0 : Interrupt disabled 1 : Interrupt enabled Timer 2 interrupt enable bit 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled Serial I/O1 transmit interrupt enable bit Serial I/O1 receive interrupt enable bit

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3.4 List of instruction codes

3.9 List of instruction codes

D 7 – D4 D 3 – D0 Hexadecimal notation 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 A B C D E F 0000 BRK BPL JSR ABS BMI RTI BVC RTS BVS BRA BCC LDY IMM BCS CPY IMM BNE CPX IMM BEQ 0001 ORA IND, X ORA IND, Y AND IND, X AND IND, Y EOR IND, X EOR IND, Y ADC IND, X ADC IND, Y STA IND, X STA IND, Y LDA IND, X LDA IND, Y CMP IND, X CMP IND, Y SBC IND, X ZP, X SBC IND, Y 0010 JSR ZP, IND CLT JSR SP SET STP MUL ZP, X RRF ZP LDX IMM JMP ZP, IND 0011 BBS 0, A BBC 0, A BBS 1, A BBC 1, A BBS 2, A BBC 2, A BBS 3, A BBC 3, A BBS 4, A BBC 4, A BBS 5, A BBC 5, A BBS 6, A BBC 6, A BBS 7, A BBC 7, A 0100 BIT ZP COM ZP TST ZP STY ZP STY ZP, X LDY ZP LDY ZP, X CPY ZP CPX ZP 0101 ORA ZP ORA ZP, X AND ZP AND ZP, X EOR ZP EOR ZP, X ADC ZP ADC ZP, X STA ZP STA ZP, X LDA ZP LDA ZP, X CMP ZP CMP ZP, X SBC ZP SBC ZP, X 0110 ASL ZP ASL ZP, X ROL ZP ROL ZP, X LSR ZP LSR ZP, X ROR ZP ROR ZP, X STX ZP STX ZP, Y LDX ZP LDX ZP, Y DEC ZP DEC ZP, X INC ZP INC ZP, X 0111 BBS 0, ZP BBC 0, ZP BBS 1, ZP BBC 1, ZP BBS 2, ZP BBC 2, ZP BBS 3, ZP BBC 3, ZP BBS 4, ZP BBC 4, ZP BBS 5, ZP BBC 5, ZP BBS 6, ZP BBC 6, ZP BBS 7, ZP BBC 7, ZP 1000 PHP CLC PLP SEC PHA CLI PLA SEI DEY TYA TAY CLV INY CLD INX SED 1001 ORA IMM ORA ABS, Y AND IMM AND ABS, Y EOR IMM EOR ABS, Y ADC IMM ADC ABS, Y STA ABS, Y LDA IMM LDA ABS, Y CMP IMM CMP ABS, Y SBC IMM SBC ABS, Y 1010 A ASL A DEC A ROL A INC A LSR A ROR A TXA TXS TAX TSX DEX NOP 1011 B SEB 0, A CLB 0, A SEB 1, A CLB 1, A SEB 2, A CLB 2, A SEB 3, A CLB 3, A SEB 4, A CLB 4, A SEB 5, A CLB 5, A SEB 6, A CLB 6, A SEB 7, A CLB 7, A 1100 C BIT ABS LDM ZP JMP ABS JMP IND STY ABS LDY ABS LDY ABS, X CPY ABS CPX ABS 1101 D ORA ABS ORA ABS, X AND ABS AND ABS, X EOR ABS EOR ABS, X ADC ABS ADC ABS, X STA ABS STA ABS, X LDA ABS LDA ABS, X CMP ABS CMP ABS, X SBC ABS SBC ABS, X 1110 E ASL ABS ASL ABS, X ROL ABS ROL ABS, X LSR ABS LSR ABS, X ROR ABS ROR ABS, X STX ABS LDX ABS LDX ABS, Y DEC ABS DEC ABS, X INC ABS INC ABS, X 1111 F SEB 0, ZP CLB 0, ZP SEB 1, ZP CLB 1, ZP SEB 2, ZP CLB 2, ZP SEB 3, ZP CLB 3, ZP SEB 4, ZP CLB 4, ZP SEB 5, ZP CLB 5, ZP SEB 6, ZP CLB 6, ZP SEB 7, ZP CLB 7, ZP WIT DIV

Symbol Function Details IMP IMM A BIT, A ZP BIT, ZP OP n # OP n # OP n # OP n # OP n #OP n # APPENDIX 3-66 3802 GROUP USER'S MANUAL Adds the carry, accumulator and memory con- tents. The results are entered into the accumulator. Adds the contents of the memory in the ad- dress indicated by index register X, the contents of the memory specified by the ad- dressing mode and the carry. The results are entered into the memory at the address indi- cated by index register X. “AND’s” the accumulator and memory con- tents. The results are entered into the accumulator. “AND’s” the contents of the memory of the ad- dress indicated by index register X and the contents of the memory specified by the ad- dressing mode. The results are entered into the memory at the address indicated by index register X. Shifts the contents of accumulator or contents of memory one bit to the left. The low order bit of the accumulator or memory is cleared and the high order bit is shifted into the carry flag. Branches when the contents of the bit speci- fied in the accumulator or memory is “0”. Branches when the contents of the bit speci- fied in the accumulator or memory is “1”. Branches when the contents of carry flag is “0”. Branches when the contents of carry flag is “1”. Branches when the contents of zero flag is “1”. “AND’s” the contents of accumulator and memory. The results are not entered any- where. Branches when the contents of negative flag is “1”. Branches when the contents of zero flag is “0”. Branches when the contents of negative flag is “0”. Jumps to address specified by adding offset to the program counter. Executes a software interrupt. ADC (Note 1) (Note 5) AND (Note 1) ASL BBC (Note 4) BBS (Note 4) BCC (Note 4) BCS (Note 4) BEQ (Note 4) BIT BMI (Note 4) BNE (Note 4) BPL (Note 4) BRA BRK 7 0 C ← ← 0 29 2 2 0A 2 1 03+2i 17+2i 07+2i 06 5 2 25 3 2 65 3 269 2 2 13+2i When T = 0 A ← A + M + C When T = 1 M(X) ← M(X) + M + C When T = 0 A ← A M When T = 1 M(X) ← M(X) M Ab or Mb = 0? Ab or Mb = 1? C = 0? C = 1? Z = 1? A M N = 1? Z = 0? N = 0? PC ← PC ± offset B ← 1 M(S) ← PC H S ← S – 1 M(S) ← PCL S ← S – 1 M(S) ← PS S ← S – 1 PC L ← ADL PC H ← ADH V V V 2

ZP, X ZP, Y ABS ABS, X ABS, Y IND ZP, IND IND, X IND, Y REL SP 7 6 5 4 3 2 1 0 Processor status register NVTBD I ZCOP n # OP n # OP n # OP n # OP n # OP n # OP n # OP n # OP n # OP n # OP n # 3-673802 GROUP USER’S MANUAL APPENDIX N N N M V M Z Z Z Z C C

Symbol Function Details IMP IMM A BIT, A ZP BIT, ZP OP n # OP n # OP n # OP n # OP n #OP n # APPENDIX 3-68 3802 GROUP USER'S MANUAL Branches when the contents of overflow flag is “0”. Branches when the contents of overflow flag is “1”. Clears the contents of the bit specified in the accumulator or memory to “0”. Clears the contents of the carry flag to “0”. Clears the contents of decimal mode flag to “0”. Clears the contents of interrupt disable flag to “0”. Clears the contents of index X mode flag to “0”. Clears the contents of overflow flag to “0”. Compares the contents of accumulator and memory. Compares the contents of the memory speci- fied by the addressing mode with the contents of the address indicated by index register X. Forms a one’s complement of the contents of memory, and stores it into memory. Compares the contents of index register X and memory. Compares the contents of index register Y and memory. Decrements the contents of the accumulator or memory by 1. Decrements the contents of index register X by 1. Decrements the contents of index register Y by 1. Divides the 16-bit data that is the contents of M (zz + x + 1) for high byte and the contents of M (zz + x) for low byte by the accumulator. Stores the quotient in the accumulator and the 1’s complement of the remainder on the stack. “Exclusive-ORs” the contents of accumulator and memory. The results are stored in the ac- cumulator. “Exclusive-ORs” the contents of the memory specified by the addressing mode and the contents of the memory at the address indi- cated by index register X. The results are stored into the memory at the address indi- cated by index register X. Connects oscillator output to the X OUT pin. Increments the contents of accumulator or memory by 1. Increments the contents of index register X by Increments the contents of index register Y by BVC (Note 4) BVS (Note 4) CLB CLC CLD CLI CLT CLV CMP (Note 3) COM CPX CPY DEC DEX DEY DIV EOR (Note 1) FST INC INX INY V = 0? V = 1? Ab or Mb ← 0 C ← 0 D ← 0 I ← 0 T ← 0 V ← 0 When T = 0 A – M When T = 1 M(X) – M M ← M X – M Y – M A ← A – 1 or M ← M – 1 X ← X – 1 Y ← Y – 1 A ← (M(zz + X + 1), M(zz + X)) / A M(S) ← 1’s complememt of Remainder S ← S – 1 When T = 0 A ← A V– M When T = 1 M(X) ← M(X) V– M A ← A + 1 or M ← M + 1 X ← X + 1 Y ← Y + 1 CA 1B+2i 1F+2i 21 52

ZP, X ZP, Y ABS ABS, X ABS, Y IND ZP, IND IND, X IND, Y REL SP 7 6 5 4 3 2 1 0 Processor status register NVTBD I ZCOP n # OP n # OP n # OP n # OP n # OP n # OP n # OP n # OP n # OP n # OP n # 3-693802 GROUP USER’S MANUAL APPENDIX N N N N N N N N N N N DD DE FE Z Z Z Z Z Z Z Z Z Z Z C C C

Symbol Function Details IMP IMM A BIT, A ZP BIT, ZP OP n # OP n # OP n # OP n # OP n #OP n # APPENDIX 3-70 3802 GROUP USER'S MANUAL Jumps to the specified address. After storing contents of program counter in stack, and jumps to the specified address. Load accumulator with contents of memory. Load memory indicated by index register X with contents of memory specified by the ad- dressing mode. Load memory with immediate value. Load index register X with contents of memory. Load index register Y with contents of memory. Shift the contents of accumulator or memory to the right by one bit. The low order bit of accumulator or memory is stored in carry, 7th bit is cleared. Multiplies the accumulator with the contents of memory specified by the zero page X address- ing mode and stores the high byte of the result on the stack and the low byte in the accumula- tor. No operation. “Logical OR’s” the contents of memory and ac- cumulator. The result is stored in the accumulator. “Logical OR’s” the contents of memory indi- cated by index register X and contents of memory specified by the addressing mode. The result is stored in the memory specified by index register X. JMP JSR LDA (Note 2) LDM LDX LDY LSR MUL (Note 5) NOP ORA (Note 1) If addressing mode is ABS PC L ← ADL PC H ← ADH If addressing mode is IND PC L ← M (ADH , ADL) PC H ← M (ADH, ADL + 1) If addressing mode is ZP, IND PC L ← M(00, ADL) PC H ← M(00, ADL + 1) M(S) ← PCH S ← S – 1 M(S) ← PCL S ← S – 1 After executing the above, if addressing mode is ABS, PC L ← ADL PC H ← ADH if addressing mode is SP, PC L ← ADL PC H ← FF If addressing mode is ZP, IND, PC L ← M(00, ADL) PC H ← M(00, ADL + 1) When T = 0 A ← M When T = 1 M(X) ← M M ← nn X ← M Y ← M M(S) · A ← A 5 M(zz + X) S ← S – 1 PC ← PC + 1 When T = 0 A ← A V M When T = 1 M(X) ← M(X) V M 4A 2 1 EA 2 1 7 0 0→ → C

ZP, X ZP, Y ABS ABS, X ABS, Y IND ZP, IND IND, X IND, Y REL SP 7 6 5 4 3 2 1 0 Processor status register NVTBD I ZCOP n # OP n # OP n # OP n # OP n # OP n # OP n # OP n # OP n # OP n # OP n # 3-713802 GROUP USER’S MANUAL APPENDIX N N N N Z Z Z Z Z C B6 4 2 BD BC BE

53 B 2

Symbol Function Details IMP IMM A BIT, A ZP BIT, ZP OP n # OP n # OP n # OP n # OP n #OP n # APPENDIX 3-72 3802 GROUP USER'S MANUAL Saves the contents of the accumulator in memory at the address indicated by the stack pointer and decrements the contents of stack pointer by 1. Saves the contents of the processor status register in memory at the address indicated by the stack pointer and decrements the contents of the stack pointer by 1. Increments the contents of the stack pointer by 1 and restores the accumulator from the memory at the address indicated by the stack pointer. Increments the contents of stack pointer by 1 and restores the processor status register from the memory at the address indicated by the stack pointer. Shifts the contents of the memory or accumu- lator to the left by one bit. The high order bit is shifted into the carry flag and the carry flag is shifted into the low order bit. Shifts the contents of the memory or accumu- lator to the right by one bit. The low order bit is shifted into the carry flag and the carry flag is shifted into the high order bit. Rotates the contents of memory to the right by 4 bits. Returns from an interrupt routine to the main routine. Returns from a subroutine to the main routine. Subtracts the contents of memory and complement of carry flag from the contents of accumulator. The results are stored into the accumulator. Subtracts contents of complement of carry flag and contents of the memory indicated by the addressing mode from the memory at the ad- dress indicated by index register X. The results are stored into the memory of the ad- dress indicated by index register X. Sets the specified bit in the accumulator or memory to “1”. Sets the contents of the carry flag to “1”. Sets the contents of the decimal mode flag to “1”. Sets the contents of the interrupt disable flag to “1”. Sets the contents of the index X mode flag to “1”. Disconnects the oscillator output from the X OUT pin. PHA PHP PLA PLP ROL ROR RRF RTI RTS SBC (Note 1) (Note 5) SEB SEC SED SEI SET SLW M(S) ← A S ← S – 1 M(S) ← PS S ← S – 1 S ← S + 1 A ← M(S) S ← S + 1 PS ← M(S) S ← S + 1 PS ← M(S) S ← S + 1 PC L ← M(S) S ← S + 1 PC H ← M(S) S ← S + 1 PC L ← M(S) S ← S + 1 PC H ← M(S) When T = 0 A ← A – M – C When T = 1 M(X) ← M(X) – M – C Ab or Mb ← 1 C ← 1 D ← 1 I ← 1 T ← 1 7 0 ← ← C ← 7 0 → → 0B+2i 0F+2i 21 52 7 0 C → →

ZP, X ZP, Y ABS ABS, X ABS, Y IND ZP, IND IND, X IND, Y REL SP 7 6 5 4 3 2 1 0 Processor status register NVTBD I ZCOP n # OP n # OP n # OP n # OP n # OP n # OP n # OP n # OP n # OP n # OP n # 3-733802 GROUP USER’S MANUAL APPENDIX N N N N V Z Z Z Z C C C FD 3F 95 3 E 16 2F 16 2 (Value saved in stack) (Value saved in stack)

Symbol Function Details IMP IMM A BIT, A ZP BIT, ZP OP n # OP n # OP n # OP n # OP n #OP n # APPENDIX 3-74 3802 GROUP USER'S MANUAL Stores the contents of accumulator in memory. Stops the oscillator. Stores the contents of index register X in memory. Stores the contents of index register Y in memory. Transfers the contents of the accumulator to index register X. Transfers the contents of the accumulator to index register Y. Tests whether the contents of memory are “0” or not. Transfers the contents of the stack pointer to index register X. Transfers the contents of index register X to the accumulator. Transfers the contents of index register X to the stack pointer. Transfers the contents of index register Y to the accumulator. Stops the internal clock. STA STP STX STY TAX TAY TST TSX TXA TXS TYA WIT M ← A M ← X M ← Y X ← A Y ← A M = 0? X ← S A ← X S ← X A ← Y AA BA Notes 1 : The number of cycles “n” is increased by 3 when T is 1. 2 : The number of cycles “n” is increased by 2 when T is 1. 3 : The number of cycles “n” is increased by 1 when T is 1. 4 : The number of cycles “n” is increased by 2 when branching has occurred. 5 : N, V, and Z flags are invalid in decimal operation mode.

ZP, X ZP, Y ABS ABS, X ABS, Y IND ZP, IND IND, X IND, Y REL SP 7 6 5 4 3 2 1 0 Processor status register NVTBD I ZCOP n # OP n # OP n # OP n # OP n # OP n # OP n # OP n # OP n # OP n # OP n # 3-753802 GROUP USER’S MANUAL APPENDIX N N N N N N Z Z Z Z Z Z 96 5 2

9 D 63 9 9 63 8 1 72 9 1 72

Symbol Contents Symbol Contents Addition Subtraction Logical OR Logical AND Logical exclusive OR Negation Shows direction of data flow Index register X Index register Y Stack pointer Program counter Processor status register 8 high-order bits of program counter 8 low-order bits of program counter 8 high-order bits of address 8 low-order bits of address FF in Hexadecimal notation Immediate value Memory specified by address designation of any ad- dressing mode Memory of address indicated by contents of index register X Memory of address indicated by contents of stack pointer Contents of memory at address indicated by AD H and AD L, in ADH is 8 high-order bits and ADL is 8 low-or- der bits. Contents of address indicated by zero page AD L 1 bit of accumulator 1 bit of memory Opcode Number of cycles Number of bytes Implied addressing mode Immediate addressing mode Accumulator or Accumulator addressing mode Accumulator bit relative addressing mode Zero page addressing mode Zero page bit relative addressing mode Zero page X addressing mode Zero page Y addressing mode Absolute addressing mode Absolute X addressing mode Absolute Y addressing mode Indirect absolute addressing mode Zero page indirect absolute addressing mode Indirect X addressing mode Indirect Y addressing mode Relative addressing mode Special page addressing mode Carry flag Zero flag Interrupt disable flag Decimal mode flag Break flag X-modified arithmetic mode flag Overflow flag Negative flag IMP IMM A BIT, A ZP BIT, ZP ZP, X ZP, Y ABS ABS, X ABS, Y IND ZP, IND IND, X IND, Y REL SP C Z I D B T V N V X Y S PC PS PC H PC L AD H AD L FF nn M M(X) M(S) M(AD H , ADL) M(00, ADL) Ab Mb OP n V

3-76 3802 GROUP USER’S MANUAL 001F16 Serial I/O2 register (SIO2) Port P0 (P0) Port P0 direction register (P0D) Port P1 (P1) Port P1 direction register (P1D) Port P2 (P2) Port P2 direction register (P2D) Port P3 (P3) Port P3 direction register (P3D) Port P4 (P4) Port P4 direction register (P4D) Port P5 (P5) Port P5 direction register (P5D) Port P6 (P6) Port P6 direction register (P6D) Transmit/Receive buffer register (TB/RB) Serial I/O1 status register (SIO1STS) Serial I/O1 control register (SIO1CON) UART control register (UARTCON) Baud rate generator (BRG) Serial I/O2 control register (SIO2CON) Interrupt control register 2(ICON2) A-D conversion register (AD) Prescaler Y (PREY) Timer Y (TY) AD/DA control register (ADCON) D-A1 conversion register (DA1) D-A2 conversion register (DA2) Interrupt edge selection register (INTEDGE) CPU mode register (CPUM) Interrupt request register 1(IREQ1) Interrupt request register 2(IREQ2) Interrupt control register 1(ICON1) Prescaler 12 (PRE12) Timer 2 (T2) Prescaler X (PREX) Timer X (TX) Timer 1 (T1) Timer XY mode register (TM) PWM control register (PWMCON) PWM prescaler (PREPWM) PWM register (PWM)

3-773802 GROUP USER’S MANUAL PIN CONFIGURATION (TOP VIEW) Package type : 64P6N-A 64-pin plastic-molded QFP P41/INT0 P00/AD0 P03/AD3 P04/AD4 P05/AD5 P06/AD6 P07/AD7 P11/AD9 P12/AD10 P13/AD11 P14/AD12 P15/AD13 P16/AD14 P17/AD15 P62/AN2 P61/AN1 P60/AN0 P57/INT3 M38022M4-XXXFP P56/PWM P55/CNTR 1 P54/CNTR 0 P52/SCLK2 P51/SOUT2 P50/SIN2 P47/SRDY1 P45/TXD P44/RXD P43/INT2 P63 /AN3 P64/AN4 P65/AN5 AV SS VREF VCC P30/DA1 P31/DA2 P32/ONW P33/RESET OUT P34/f P35/SYNC P36/WR P37/RD P42/INT1 CNV SS XIN XOUT VSS P27/DB7 P26/DB6 P25/DB5 P24/DB4 P23/DB3 P22/DB2 P21/DB1 P20/DB0 RESET P53/SRDY2 P46/SCLK1 P10/AD8 P01/AD1 P02/AD2 P40/INT4P67/AN7 P66/AN6

3-78 3802 GROUP USER’S MANUAL PIN CONFIGURATION (TOP VIEW) P64/AN4 P66/AN6 P67/AN7 AV SS VREF VCC P63/AN3 P65/AN5 P62/AN2 P61/AN1 P60/AN0 P57/INT3 P56/PWM P55/CNTR 1 P54/CNTR 0 P53/SRDY2 P52/SCLK2 P51/SOUT2 P50/SIN2 P47/SRDY1 P46/SCLK1 P43/INT2 P44/RXD P45/TXD CNV SS P41/INT0 P40/INT4 XIN XOUT VSS P42/INT1 RESET P24/DB4 P23/DB3 P22/DB2 P20/DB0 P21/DB1 P25/DB5 P27/DB7 P26/DB6 P33/RESET OUT P34/f P35/SYNC P37/RD P36/WR P32/ONW P30/DA1 P31/DA2 P00/AD0 P01/AD1 P02/AD2 P03/AD3 P04/AD4 P05/AD5 P06/AD6 P07/AD7 P10/AD8 P11/AD9 P12/AD10 P13/AD11 P14/AD12 P17/AD15 P16/AD14 P15/AD13 M38022M4-XXXSP Package type : 64P4B 64-pin shrink plastic-molded DIP

USER’S MANUAL 3802Group Mar. First Edition 1996 Editioned by Committee of editing of Mitsubishi Semiconductor USER’S MANUAL Published by Mitsubishi Electric Corp., Semiconductor Marketing Division This book, or parts thereof, may not be reproduced in any form without permission of Mitsubishi Electric Corporation. ©1996 MITSUBISHI ELECTRIC CORPORATION

MITSUBISHI ELECTRIC CORPORATION HEAD OFFICE: MITSUBISHI DENKI BLDG., MARUNOUCHI, TOKYO 100. TELEX: J24532 CABLE: MELCO TOKYO User’s Manual

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H-EE417-A KI-9603 Printed in Japan (ROD) © 1996 MITSUBISHI ELECTRIC CORPORATION New publication, effective Mar. 1996. Specifications subject to change without notice.

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REVISION DESCRIPTION LIST 3802 GROUP USER’S MANUAL (1/1) Revision Description