M37920S4CGP

M37920S4CGP MITSUBISHI | Alldatasheet

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Technical content

Notice: This is not a final specification. Some parametric limits are subject to change. 16-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS

DESCRIPTION

The M37920S4CGP is a single-chip microcomputers designed with high-performance CMOS silicon gate technology. These are housed in 100-pin plastic molded QFP. This microcomputer supports the

7900 Series instruction set, which are enhanced and expanded in-

struction set and are upper-compatible with the 7700/7751 Series in- struction set. The CPU of this microcomputer is a 16-bit parallel processor that can also be switched to perform 8-bit parallel processing. Also, the bus interface unit of this microcomputer enhance the memory access ef- ficiency to execute instructions fast. This microcomputer include the 4-channel DMA controller and the DRAM controller with enhanced fast page mode. Therefore, this microcomputer are suitable for of- fice, business, and industrial equipment controller that require fast processing of large data. DISTINCTIVE FEATURES <Microcomputer mode>

• Memory
• Instruction execution time
• DRAM controller
• Real-time output .... 4 bits × 2 channels, or 6 bits × 1 channel + 2 bits × 1 channel
• 12-bit watchdog timer APPLICATION Telecommunications equipment such as copiers, printers, typewrit- ers, facsimiles, optical disk drives, HDD, mobile radio communica- tion equipment, ISDN terminals Control devices for office automation equipment such as personal computers Outline 100P6S-A M37920S4CGP PIN CONFIGURATION (TOP VIEW) ↔ D0 P66/DMAREQ 3 ↔ P65/TA4IN/DMAREQ 2 ↔ P64/TA4OUT /DMAACK 2 ↔ P60/TA1OUT /DMAACK 0 ↔ P57/TA2IN/RTP13 ↔ P56/TA2OUT /RTP12 ↔ P55/RTP11 ↔ P54/RTP10 ↔ P53/RTP03 ↔ P52/RTP02 ↔ P51/TA0IN/RTP01 ↔ P50/TA0OUT /RTP00 ↔ P96/WRH/UCAS ↔ P95/WRL/LCAS ↔ P94/CAS/W ↔ P93/CS3/RAS3 ↔ P92/CS2/RAS2 ↔ P91/CS1/RAS1 ↔ CS 0 ↔ P44/HLDA ↔ P43/HOLD ↔ P42/TC ↔ P41/φ1 ↔ P40/ALE ↔ P33/BHW ← BLW ← RD ← 100 P63/TA3IN/DMAREQ 1 ↔ P62/TA3OUT /DMAACK 1 ↔ P61/TA1IN/DMAREQ 0 ↔ ↔ P30/RDY ← BYTE ← NMI ← RESET ← MD0 VSS ← XIN → XOUT VCC ↔ P27/D15 ↔ P26/D14 ↔ P25/D13 ↔ P24/D12 ↔ P23/D11 ↔ P22/D10 ↔ P21/D9 ↔ P20/D8 ↔ D7 ↔ D4 ↔ D3 ↔ D2 ↔ D1 ← MD1 VSS → A23 → A22/MA11 → A21 → A20/MA10 → A19 → A18/MA9 → A17 → A16/MA8 → A15/MA7 → A14/MA6 → A13/MA5 → A12/MA4 → A11/MA3 → A10/MA2 → A9/MA1 → A8/MA0 → A7 → A6 → A5 → A4 → A3 → A2 → A1 ↔ D6 ↔ D5A0 ← P86/CLK0 ↔ P85/RXD 0 ↔ P84/TXD 0 ↔ P83/CTS0/RTS0 ↔ P82/CTS0/CLK1 ↔ P81/RXD 1 ↔ VCC AV CC VREF AV SS VSS P73/AN3/ADTRG /INT4 ↔ P72/AN2/INT3 ↔ P71/AN1 ↔ P70/AN0 ↔ P122/INT2/TB2IN ↔ P121/INT1/TB1IN ↔ P120/INT0/TB0IN ↔ P80/TXD 1 ↔ M37920S4CGP

Notice: This is not a final specification. Some parametric limits are subject to change. M37920S4CGP 16-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS BLOCK DIAGRAM Data bank Register DT (8) Program Counter PC (16) Incrementer/Decrementer (24) Program Bank Register PG (8) Input Buffer Register IB (16) Direct Page Register DPR0 (16) Stack Pointer S (16) Index Register Y (16) Index Register X (16) Arithmetic Logic Unit (16) Accumulator B (16) Accumulator A (16) Instruction register (8) Central Processing Unit (CPU) Incrementer (24) Program Address Register PA (24) Data Address Register DA (24) Bus Interface Unit (BIU) RESET MD1 Reference voltage input VREF (0 V) AV SS AVccVcc External data bus width select input BYTE Clock Generating Circuit Clock input XIN XOUT Data Buffer DQ0 (8) Instruction Queue Buffer Q0 (8) Data Bus (Odd) Address Bus A-D converter (10) Watchdog timer Timer TB1 (16) Timer TB2 (16) Timer TB0 (16) Timer TA1 (16) Timer TA2 (16) Timer TA3 (16) Timer TA4 (16) Timer TA0 (16) Input/Output port P8 Input/Output port P7 Input/Output port P4 Input/Output port P6 Input/Output port P5 Data busInput/Output port P2 Input/Output port P3 MD0 (0 V) Vss Processor Status Register PS (11) NMI Data Bus (Even) Data Buffer DQ1 (8) Data Buffer DQ2 (8) Data Buffer DQ3 (8) Instruction Queue Buffer Q1 (8) Instruction Queue Buffer Q2 (8) Instruction Queue Buffer Q3 (8) Instruction Queue Buffer Q4 (8) Instruction Queue Buffer Q5 (8) Instruction Queue Buffer Q6 (8) Instruction Queue Buffer Q7 (8) Instruction Queue Buffer Q8 (8) Instruction Queue Buffer Q9 (8) Direct Page Register DPR1 (16) Direct Page Register DPR2 (16) Direct Page Register DPR3 (16) Clock output Reset input UART1(9) UART0(9) RAM 2048 bytes DRAM controoler DMA0(16) DMA1(16) DMA2(16) DMA3(16) P12(3) Data I/O circuitP2(8)P3(2) Input/Output port P9 Input/Output port P12 RD Read output BLW Write output(0 V)(5 V) Address output circuit Address bus

Notice: This is not a final specification. Some parametric limits are subject to change. 16-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS ROM RAM P2, P5 P6, P8 P12 TA0–TA4 TB0–TB2 UART0 and UART1 Memory expansion Operating temperature range Device structure Package Number of basic machine instructions Instruction execution time External clock input frequency f(X IN) Memory size Programmable input/output ports Multi-functional timers Serial I/O A-D converter Watchdog timer DMA controller DRAM controller Chip-select wait control Real-time output Interrupts Clock generating circuit Power supply voltage Power dissipation Ports’ input/output characteristics FUNCTIONS (Microcomputer mode) FunctionsParameter Input/Output withstand voltage Output current 203 50 ns (the fastest instruction at f(XIN) = 20 MHz) 20 MHz (Max.) External 2048 bytes 8-bit 5 2 2-bit 5 1 5-bit 5 1 7-bit 5 2 4-bit 5 1 6-bit 5 1 3-bit 5 1 16-bit 5 5 16-bit 5 3 (UART or Clock synchronous serial I/O) 5 2 10-bit successive approximation method 5 1 (4 channels) 12-bit 5 1 4 channels Maximum transfer rate 20 Mbytes/sec. (at f(XIN) = 20 MHz, 0 wait, 1-bus cycle transfer) 10 Mbytes/sec. (at f(XIN) = 20 MHz, 0 wait, 2-bus cycles transfer) 1 channel Supports fast page access mode. Incorporates 8-bit refresh timer. Supports CAS before RAS refresh method or self refresh method. Chip select area 5 4 (CS 0–CS 3). A wait number and bus width can be set for each chip select area. 4 bits 5 2 channels; or 6 bits 5 1 channel + 2 bits 5 1 channel 6 external types, 17 internal types. Each interrupt except NMI can be set to a priority level within the range of 0–7 by software. Built-in (externally connected to a ceramic resonator or quartz crystal resonator).

5 V±10 %

135 mW (at f(X IN) = 20 MHz, typ.) 5 V 5 mA Up to 16 Mbytes. Note that bank FF 16 is a reserved area. –20 to 85 °C CMOS high-performance silicon gate process 100-pin plastic molded QFP

Notice: This is not a final specification. Some parametric limits are subject to change. M37920S4CGP 16-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS Vcc, Vss MD0 MD1 RESET X IN XOUT BYTE AVcc, AVss VREF A0–A7 A8–A15/ MA 0–MA 7 A16–A23/ MA 8–MA 11 D0–D 7 P20/D8– P27/D15 P30/RDY , RD, BLW, 3/BHW P40/ALE, P41/φ1, P42/TC, P43/HOLD, P44/HLDA P50–P5 7 P60–P6 6 Power supply input MD0 MD1 Reset input Clock input Clock output External data bus width select input Analog power supply input Reference voltage input Low-order address Middle-order address/ DRAM address High-order address/ DRAM address Low-order data I/O port P2/ High-order data Memory control signal I/O I/O port P4 I/O port P5 I/O port P6 Input Input Input Input Output Input Input Output Output Output I/O I/O Input Output Output Output Output Output I/O Input Output I/O I/O Apply 5 V±10 % to Vcc, and 0 V to Vss. This pin controls the processor mode. Connect this pin to V CC . Connect this pin to Vss. The microcomputer is reset when “L” level is applies to this pin. These are input and output pins of the internal clock generating circuit. Connect a ceramic or quartz- crystal resonator between the X IN and XOUT pins. When an external clock is used, the clock source should be connected to the XIN pin, and the XOUT pin should be left open. This pin determines whether the external data bus has an 8-bit width or 16-bit width for the memory expansion mode or microprocessor mode. The width is 16 bits when “L” signal is input, and 8 bits when “H” signal is input. Power supply input pin for the A-D converter. Connect AVcc to Vcc, and AVss to Vss externally. This is the reference voltage input pin for the A-D converter. The low-order 8 bits of address (A 0–A7) are output. The middle-order 8 bits of address (A8–A15) are input/output. While DRAM space is accessed, multiplexed address (MA0–MA 7) is output. The high-order 8 bits of address (A16–A23) are output. While DRAM space is ac- cessed, multiplexed address (MA8–MA 11) is output. The low-order 8 bits of data (D0–D 7) are input/output. n When 8-bit external data bus is used (BYTE = “H” level) Port P2 is an 8-bit I/O port. n When 16-bit external data bus is used (BYTE = “L” level) The high-order 8 bits (D8–D15) are input/output. While the input level at pin RDY is “L”, the microcomputer is placed in the ready state. While pin RD is at “L” level, the microcomputer reads out data and instruc- tion codes. Also, pin RDY can function as a programmable I/O port pin (P3 0) by software. n When 8-bit external data bus is used (BYTE = “H” level) While pin BLW is at “L” level, the microcomputer writes data. n When 16-bit external data bus is used (BYTE = “L” level) While pin BLW is at “L” level, the microcomputer writes data into an even- numbered address. While pin BHW is at “L” level, the microcomputer writes data into an odd- numbered address. Signal ALE is used to latch an address. φ 1 has the same period as internal clock φ. Pin P42 functions as a programmable I/O port pin. While the input level at pin HOLD is at “L” level, the microcomputer is placed in the hold state. Signal HLDA is used to inform the external that the microcomputer enters the hold state. By software, pin ALE, clock φ 1 output pin, and pins HOLD, HLDA function as programmable I/O port pins (P40, P41, P43, P44). Pin P42 also functions as pin TC. Port P5 is an 8-bit I/O port. These pins also function as I/O pins for timers A0, A2, and pulse output pins for the real-time output. Port P6 is a 7-bit I/O port. These pins also function as I/O pins for timers A1, A3, A4, input pins for DMA requests, and output pins for DMA acknowledge signals. PIN DESCRIPTION (Microcomputer mode) FunctionsInput/ OutputNamePin

Notice: This is not a final specification. Some parametric limits are subject to change. 16-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS I/O I/O Output I/O I/O Input FunctionsInput/ OutputNamePin P70–P7 3 P80–P8 6 CS 0 P91–P9 6 P120–P122 NMI Port P7 is a 4-bit I/O port. P72 and P73 also function as input pins for INT3 and INT4. According to the software setting, these pins also function as input pins for the A-D converter. Port P8 is a 7-bit I/O port. These pins also function as I/O pins for UART0, UART1. This is an output pin for CS Port P9 is a 6-bit I/O port. According to the software setting, P91–P93 also funtion as chip select output pins. While DRAM space is selected, P94–P96 function as output pins for DRAM control signals. Port P12 is a 3-bit I/O port. These pins also functions as input pins for INT0, INT1, INT2. According to software setting, these pins also function as input pins for timers B0–B2. This pin is for a non-maskable interrupt. I/O port P7 I/O port P8 Chip-select output I/O port P9 I/O port P12 Non-maskable interrupt

Notice: This is not a final specification. Some parametric limits are subject to change. M37920S4CGP 16-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS Fig. 1 Memory map INT4 A-D conversion Reserved area (Note 1) Reserved area (Note 1) Reserved area (Note 1) Address matching detect DMA0 DMA1 DMA2 DMA3 UART1 transmit UART1 receive UART0 transmit UART0 receive Timer B2 Timer B1 Timer B0 Interrupt vector table Timer A4 Timer A3 Timer A2 Timer A1 Timer A0 Watchdog timer BRK instruction (Note 2) Zero divide INT3 INT2 INT1 INT0 NMI RESET DBC (Note 2) 00000016 Bank 016 FFFFFF 16 FE0000 16 00FFFF 16 01000016 01FFFF 16 Bank FE16 00000016 00080016 0000FF16 00FFFE 16 00FFC0 16 Internal RAM 2048 bytes Peripheral devices control registers 000FFF 16 00100016 FEFFFF 16 FF000016 00FFFF 16 00FFC0 16 Bank 116 Bank FF Notes 1: Do not write to this address. 2: These are interrupts used only for debugging. Do not use these interrupts. BASIC FUNCTION BLOCKS The M37920S4CGP is the same functions as the M37920F8CGP except for the following. Therefore, refer to the datasheet of the M37920F8CGP .

• The M37920S4CGP does not include the internal flash memory.
• The M37920S4CGP operates only in the microprocessor mode.
• The M37920S4CGP does not have the flash memory control regis- ter (address 9E 16).
• Some of programmable I/O ports of the M37920S4CGP differ from those of the M37920FGCGP. MEMORY Figure 1 shows the memory map.

Notice: This is not a final specification. Some parametric limits are subject to change. 16-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS Fig. 2 Location of peripheral devices’ control registers (1) 00000016 00000116 00000216 00000316 00000416 00000516 00000616 00000716 00000816 00000916 00000A16 00000B16 00000C 16 00000D 16 00000E16 00000F16 00001016 00001116 00001216 00001316 00001416 00001516 00001616 00001716 00001816 00001916 00001A16 00001B16 00001C 16 00001D 16 00001E16 00001F16 00002016 00002116 00002216 00002316 00002416 00002516 00002616 00002716 00002816 00002916 00002A16 00002B16 00002C 16 00002D 16 00002E16 00002F16 00003016 00003116 00003216 00003316 00003416 00003516 00003616 00003716 00003816 00003916 00003A16 00003B16 00003C 16 00003D 16 00003E16 00003F16 Port P2 register Port P3 register [Port P1 direction register] (Note 2) [Port P0 direction register] (Note 2) [Port P1 register] (Note 2) [Port P0 register] (Note 2) Port P2 direction register Port P3 direction register Port P4 register Port P5 register Port P4 direction register Port P5 direction register Port P6 register Port P7 register Port P6 direction register Port P7 direction register Port P8 register Port P8 direction register [Port P10 register] (Note 2) [Port P11 register] (Note 2) [Port P10 direction register] (Note 2) [Port P11 direction register] (Note 2) A-D control register 0 A-D control register 1 A-D register 1 A-D register 2 A-D register 3 UART0 transmit/receive mode register UART0 baud rate register (BRG0) UART0 transmit buffer register UART0 transmit/receive control register 1 UART0 receive buffer register UART1 transmit/receive mode register UART1 baud rate register (BRG1) UART1 transmit buffer register UART1 transmit/receive control register 0 UART1 transmit/receive control register 1 UART1 receive buffer register Address (Hexadecimal notation) 000040 00004116 00004216 00004316 00004416 00004516 00004616 00004716 00004816 00004916 00004A16 00004B16 00004C 16 00004D 16 00004E16 00004F16 00005016 00005116 00005216 00005316 00005416 00005516 00005616 00005716 00005816 00005916 00005A16 00005B16 00005C 16 00005D 16 00005E16 00005F16 00006016 00006116 00006216 00006316 00006416 00006516 00006616 00006716 00006816 00006916 00006A16 00006B16 00006C 16 00006D 16 00006E16 00006F16 00007016 00007116 00007216 00007316 00007416 00007516 00007616 00007716 00007816 00007916 00007A16 00007B16 00007C 16 00007D 16 00007E16 00007F16 Address (Hexadecimal notation) Count start register One-shot start register Timer A clock division select register Timer A0 register Timer A1 register Timer A2 register Timer A3 register Timer A4 register Timer B0 register Timer B1 register Timer B2 register Timer A1 mode register Timer A0 mode register Timer A2 mode register Timer A3 mode register Timer A4 mode register Timer B0 mode register Timer B1 mode register Timer B2 mode register Processor mode register 1 Watchdog timer register Particular function select register 0 Particular function select register 1 Debug control register 0 INT 3 interrupt control register UART0 transmit interrupt control register UART1 receive interrupt control register Timer A0 interrupt control register Timer A1 interrupt control register Timer A3 interrupt control register Timer A4 interrupt control register Timer B0 interrupt control register Timer B2 interrupt control register INT 1 interrupt control register Watchdog timer frequency select register Debug control register 1 INT4 interrupt control register UART1 transmit interrupt control register Timer A2 interrupt control register Timer B1 interrupt control register INT 2 interrupt control register Address comparison register 0 Address comparison register 1 Particular function select register 2 Reserved area (Note 1) Notes 1: Do not read/write to this address. 2: These registers are used in the bus fixation of the power saving function. For details, refer to the section on the power saving function of the M37920F8CGP datasheet. UART0 transmit/receive control register 0 Up-down register Processor mode register 0 A-D conversion interrupt control register UART0 receive interrupt control register INT0 interrupt control register Port P9 register Port P9 direction register Port P12 register Port P12 direction register A-D register 0 Reserved area (Note 1) Reserved area (Note 1)

Notice: This is not a final specification. Some parametric limits are subject to change. M37920S4CGP 16-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS Fig. 3 Location of peripheral devices’ control registers (2) 0000C0 16 0000C1 16 0000C2 16 0000C3 16 0000C4 16 0000C5 16 0000C6 16 0000C7 16 0000C8 16 0000C9 16 0000CA 16 0000CB 16 0000CC 16 0000CD 16 0000CE 16 0000CF 16 0000D0 16 0000D1 16 0000D2 16 0000D3 16 0000D4 16 0000D5 16 0000D6 16 0000D7 16 0000D8 16 0000D9 16 0000DA 16 0000DB 16 0000DC 16 0000DD 16 0000DE 16 0000DF 16 0000E016 0000E116 0000E216 0000E316 0000E416 0000E516 0000E616 0000E716 0000E816 0000E916 0000EA 16 0000EB 16 0000EC 16 0000ED 16 0000EE 16 0000EF 16 0000F016 0000F116 0000F216 0000F316 0000F416 0000F516 0000F616 0000F716 0000F816 0000F916 0000FA 16 0000FB 16 0000FC 16 0000FD 16 0000FE 16 0000FF16 0000A016 0000A116 0000A216 0000A316 0000A416 0000A516 0000A616 0000A716 0000A816 0000A916 0000AA 16 0000AB 16 0000AC 16 0000AD 16 0000AE 16 0000AF 16 0000B016 0000B116 0000B216 0000B316 0000B416 0000B516 0000B616 0000B716 0000B816 0000B916 0000BA 16 0000BB 16 0000BC 16 0000BD 16 0000BE 16 0000BF 16 Real-time output control register Pulse output data register 0 Pulse output data register 1 Reserved area (Note 1) CTS/RTS separate select register 000080 00008116 00008216 00008316 00008416 00008516 00008616 00008716 00008816 00008916 00008A16 00008B16 00008C 16 00008D 16 00008E16 00008F16 00009016 00009116 00009216 00009316 00009416 00009516 00009616 00009716 00009816 00009916 00009A16 00009B16 00009C 16 00009D 16 00009E16 00009F16 Address (Hexadecimal notation) CS 0 control register L CS 0 control register H CS 1 control register L CS 1 control register H CS 2 control register L CS 2 control register H CS 3 control register L CS 3 control register H Area CS 0 start address register Area CS 1 start address register Area CS 2 start address register Area CS 3 start address register Reserved area (Note 1) Reserved area (Note 1) Reserved area (Note 1) Note 1: Do not read/write to this address. Reserved area (Note 1) Reserved area (Note 1) Reserved area (Note 1) Reserved area (Note 1) Address (Hexadecimal notation) DRAM control register Refresh timer DMAC control register L DMAC control register H DMA0 interruput control register DMA1 interruput control register DMA2 interruput control register DMA3 interruput control register Source address register 0 L Source address register 0 M Source address register 0 H Destination address register 0 L Destination address register 0 M Destination address register 0 H Transfer counter register 0 L Transfer counter register 0 M Transfer counter register 0 H DMA0 mode register L DMA0 mode register H DMA0 control register Source address register 1 L Source address register 1 M Source address register 1 H Destination address register 1 L Destination address register 1 M Destination address register 1 H Transfer counter register 1 L Transfer counter register 1 M Transfer counter register 1 H DMA1 mode register L DMA1 mode register H DMA1 control register Source address register 2 L Source address register 2 M Source address register 2 H Destination address register 2 L Destination address register 2 M Destination address register 2 H Transfer counter register 2 L Transfer counter register 2 M Transfer counter register 2 H DMA 2 mode register L DMA 2 mode register H DMA 2 control register Source address register 3 L Source address register 3 M Source address register 3 H Destination address register 3 L Destination address register 3 M Destination address register 3 H Transfer counter register 3 L Transfer counter register 3 M Transfer counter register 3 H DMA 3 mode register L DMA 3 mode register H DMA 3 control register

Notice: This is not a final specification. Some parametric limits are subject to change. Table 1. Relationship between pins MD0, MD1 and processor mode

Notice: This is not a final specification. Some parametric limits are subject to change. M37920S4CGP 16-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS Fig. 4 Processor mode register 0’s bit configuration 76543210 Processor mode register 0 Processor mode bits 0 0 : Do not select. 0 1 : Do not select. 1 0 : Microprocessor mode 1 1 : Do not select. Interrupt priority detection time select bits 0 0 : 7 cycles of φ 0 1 : 4 cycles of φ 1 0 : 2 cycles of φ 1 1 : Do not select. Software reset bit By a write of “1” to this bit, the microcomputer will be reset, and then, restarted. External bus wait number select bits 0 0 : 0 wait 0 1 : 1 wait 1 0 : 2 wait 1 1 : ALE expansion wait Clock φ 1 output select bit 0 : φ1 output is disabled. (P41 functions as a programmable I/O port pin.) 1 : φ1 output is enabled. (P41 functions as the clock φ1 output pin.) Address 5E16

Notice: This is not a final specification. Some parametric limits are subject to change. 16-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS Fig. 5 Processor mode register 1’s bit configuration 76543210 Processor mode register 1 Fix this bit to “0”. RDY input select bit 0 : RDY input is disabled. (P30 functions as a programmable I/O port pin.) 1 : RDY input is enabled. (P30 functions as pin RDY.) ALE output select bit 0 : ALE output is disabled. (P40 functions as a programmable I/O port pin.) 1 : ALE output is enabled. (P40 functions as pin ALE.) Direct page register switch bit 0 : Only DPR0 is used. 1 : DPR0 to DPR3 are used. Recovery cycle insert select bit 0 : No recovery cycle is inserted at access to the external area. 1 : Recovery cycle is inserted at access to the external area. Address HOLD input, HLDA output select bit 0 : HOLD input and HLDA output are disabled. (P40 and P44 function as programmable I/O port pins.) 1 : HOLD input and HLDA output are enabled. (P43 and P44 function as pins HOLD and HLDA, respectively.) “0” at read. 000

Notice: This is not a final specification. Some parametric limits are subject to change. M37920S4CGP 16-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS Fig. 6 Microcomputer internal status just after reset (1) (0416)··· Address Port P0 direction register 00 16 (0516)···Port P1 direction register (0816)···Port P2 direction register (0916)···Port P3 direction register (1516)···Port P9 direction register 0016 (0C 16)···Port P4 direction register (0D 16)···Port P5 direction register 00 16 (1016)···Port P6 direction register (1116)···Port P7 direction register (1416)···Port P8 direction register (5616)···Timer A0 mode register 00 16 (5716)···Timer A1 mode register 00 16 (5816)···Timer A2 mode register 00 16 (5916)···Timer A3 mode register 00 16 (5A16)···Timer A4 mode register 00 16 (1816)···Port P10 direction register 00 16 (1916)···Port P11 direction register 00 16 Notes 1: The contents of the other registers and RAM are undefined at reset and must be initialized by software. 2: The status just after reset depends on the voltage level applied to pin MD0. 3: At power-on reset, these bits are clear to “0”. At hardware or software reset, on the other hand, these bits retain the state just before reset. 00000 ???(1E16)···A-D control register 0 0000 001(1F16)···A-D control register 1 100 000(3416)···UART 0 Transmit/Receive control register 0 100 000(3C 16)···UART 1 Transmit/Receive control register 0 00000 010(3516)···UART 0 Transmit/Receive control register 1 00000 010(3D 16)···UART 1 Transmit/Receive control register 1 00 000(4216)···One-shot start register 00(4516)···Timer A clock division select register (1C 16)···Port P12 direction register (3016)···UART 0 Transmit/Receive mode register 0016 (3816)···UART 1 Transmit/Receive mode register 0016 00000 000(4416)···Up-down register (4016)···Count start register 00 16 00?0 000(5B16)···Timer B0 mode register 00?0 000(5C 16)···Timer B1 mode register 00?0 000(5D 16)···Timer B2 mode register 1000(Note 2) 0 (Note 2) 0(5E16)···Processor mode register 0 (5F16)···Processor mode register 1 (6016)··· Address Watchdog timer (Note 3) 0 0 000 0000 FFF 16 (6116)···Watchdog timer frequency select register (6216)···Particular function select register 0 (6316)···Particular function select register 1 (6616)···Debug control register 0 (6716)···Debug control register 1 INT2 interrupt control register Processor status register PS 0016 0016 Program bank register PG Contents at address FFFF16Program counter PCH Contents at address FFFE16Program counter PCL 000016 (6E16)···INT3 interrupt control register (6F16)···INT4 interrupt control register 0000 ?000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 (72 16)···UART 0 receive interrupt control register (7316)···UART 1 transmit interrupt control register (7416)···UART 1 receive interrupt control register (7716)···Timer A2 interrupt control register (7816)···Timer A3 interrupt control register (7916)···Timer A4 interrupt control register (7A16)···Timer B0 interrupt control register 000 000 (7C 16)···Timer B2 interrupt control register 000 (7E16)···INT1 interrupt control register (7016)···A-D conversion interrupt control register (7116)···UART 0 transmit interrupt control register (7516)···Timer A0 interrupt control register (7616)···Timer A1 interrupt control register 000 000 (7D 16)···INT0 interrupt control register (7B16)···Timer B1 interrupt control register Direct page registers DPR0 to DPR3 (7F16)··· 000 1??000??000 Data bank register DT 0016 (Note 2)000 0 (Note 3) 0000 00 000 0000 000 0000 0000 000 0000 000 FFF 16Stack pointer 000 (Note 3)(Note 3)

Notice: This is not a final specification. Some parametric limits are subject to change. 16-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS Fig. 7 Microcomputer internal registers’ status just after reset (2) (8016)··· Address CS 0 control register L (8116)···CS 0 control register H (8216)···CS 1 control register L (8316)···CS 1 control register H (8C 16)···Area CS1 start address register (8416)···CS 2 control register L (8516)···CS 2 control register H (8616)···CS 3 control register L (8716)···CS 3 control register H (8A16)···Area CS0 start address register (DC 16)···DMA1 mode register L (DD 16)···DMA1 mode register H (DE 16)···DMA1 control register (EC 16)···DMA2 mode register L (ED 16)···DMA2 mode register H (8E16)···Area CS2 start address register (9016)···Area CS3 start address register Notes 1: The contents of the other registers and RAM are undefined at reset and must be initialized by software. 2: The status just after reset depends on the voltage level applied to pin MD0. 3: While Vss level voltage is applied to pin BYTE, these bits are “0”. While Vcc level voltage is applied to pin BYTE, on the other hand, these bits are “1”. 00000(A816)···DRAM control register (B216)···DMA0 interrupt control register 0000(B316)···DMA1 interrupt control register 0000(B416)···DMA2 interrupt control register (CC 16)···DMA0 mode register L 000(CE 16)···DMA0 control register (A016)···Real-time output control register (AC 16)···CTS/RTS separate select register (B016)···DMAC control register L 0000 000 0(CD 16)···DMA0 mode register H (B516)···DMA3 interrupt control register 00 000(EE 16)···DMA2 control register (FC 16)···DMA3 mode register L (FD 16)···DMA3 mode register H (FE 16)··· Address DMA3 control register 000 0000 000 0 010(Note 2) (Note 3) 10 01000 (Note 3) 10 01000 (Note 3) 10 01000 (Note 3) 10 000 0000 0000 0000 000 0 000000 0000 000 0 000 000 00010 000 00000 000 00000 000 00000 000 00000 000 00000000 00000000 00000000 0 0 00 00000 0 001 0 000 0 000 000 00000 000 00000 000 000 000(B116)···DMAC control register H 00

Notice: This is not a final specification. Some parametric limits are subject to change. output “L” voltage is raised, owing to an external load, etc. latch, and the pin remains floating. Each of Figures 8 and 9 shows the block diagram for each port pin. Table 2. Correspondence between external buses, bus control sig- standby state select bit’s contents.

Notice: This is not a final specification. Some parametric limits are subject to change. 16-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS Fig. 8 Block diagram for each port pin (1) [Inside dotted-line not included] P20/D8 to P27/D15, P33/BHW [Inside dotted-line included] P30/RDY , P43/HOLD, P61/TA1IN/DMAREQ 0, P63/TA3IN/DMAREQ 1, P65/TA4IN/DMAREQ 2, P66/DMAREQ 3, P81/RxD1, P85/RxD0, P120/INT0/TB0IN, P121/INT1/TB1IN, P122/INT2/TB2IN Data bus Direction register Port latch P40/ALE, P41/φ1, P44/HLDA, P60/TA1OUT /DMAACK 0, P62/TA3OUT /DMAACK 1, P64/TA4OUT /DMAACK 2, P80/TxD1, P84/TxD0, P91/CS1/RAS1, P92/CS2/RAS2, P93/CS3/RAS3, P94/CAS/W, P95/WRL/LCAS, P96/WRH/UCAS Data bus Direction register Port latch “1” Output (Internal peripheral devices) [Inside dotted-line not included] P52/RTP02, P53/RTP03, P54/RTP10, P55/RTP11 [Inside dotted-line included] P51/TA0IN/RTP01, P57/TA2IN/RTP13 Data bus Direction register Port latch Latch T Q CKTimer underflow signal P50/TA0OUT /RTP00, P56/TA2OUT /RTP12 Data bus Direction register Port latch “1” Latch T Q CKTimer underflow signal Output (Internal peripheral devices)

Notice: This is not a final specification. Some parametric limits are subject to change. M37920S4CGP 16-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS [Inside dotted-line not included] P70/AN0, P71/AN1 [Inside dotted-line included] P72/AN2/INT3, P73/AN3/ADTRG /INT4 Data bus Direction register Port latch Analog input P82/CTS0/CLK1, P83/CTS0/RTS0, P86/CLK0 Data bus Direction register Port latch “1” “0” Output (Internal peripheral devices) P42/TC Data bus Direction register Port latch “0” Output (TC) Fig. 9 Block diagram for each port pin (2) RD, BLW, CS0, A0 to A23, D0 to D7 Data bus Direction register Port latch “1” Output (Internal peripheral devices)

Notice: This is not a final specification. Some parametric limits are subject to change. 16-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS ABSOLUTE MAXIMUM RATINGS RECOMMENDED OPERATING CONDITIONS (Vcc = 5 V, Ta = –20 to 85 °C, unless otherwise noted) Unit V V V V mW Parameter Power source voltage Analog power source voltage Input voltage D 0–D7, D8/P20–D 15/P27, P30, P33, P40–P44, P50–P57, P60–P66, P70–P7 3, P80–P8 6, P91–P96, P120–P122, VREF , XIN, RESET, BYTE, MD0, MD1, NMI Output voltage A0–A23, RD, BLW, BHW/P33, CS0, D 0–D7, D8/P20–D 15/P27, P30, P40–P4 4, P50–P5 7, P60–P66, P70–P7 3, P80–P8 6, P91–P96, P120–P122, XOUT Power dissipation Operating temperature Storage temerature Symbol V CC AVCC VI VO Pd Topr Tstg Ratings –0.3 to 6.5 –0.3 to 6.5 –0.3 to V CC +0.3 –0.3 to VCC +0.3 300 –20 to 85 –40 to 150 Unit V V V V V V V V mA mA mA mA MHz Power source voltage Analog power source voltage Power source voltage Analog power source voltage High-level input voltage High-level input voltage Low-level input voltage Low-level input voltage High-level peak output current High-level average output current Low-level peak output current Low-level average output current External clock input frequency P20–P2 7, P30, P33, P40–P44, P50–P57, P60–P66, P70–P7 3, P80–P8 6, P91–P96, P120–P122, XIN, RESET , BYTE, MD0, MD1, NMI D 0–D7, D8–D 15 P20–P2 7, P30, P33, P40–P44, P50–P57, P60–P66, P70–P7 3, P80–P8 6, P91–P96, P120–P122, XIN, RESET , BYTE, MD0, MD1, NMI D 0–D7, D8–D 15 A0–A23, RD, BLW, BHW/P33, CS0, D 0–D7, D8/P20–D 15/P27, P30, P40–P4 4, P50–P57, P60–P6 6, P70–P7 3, P80–P86, P91–P96, P120–P122 A0–A23, RD, BLW, BHW/P33, CS0, D 0–D7, D8/P20–D 15/P27, P30, P40–P4 4, P50–P57, P60–P6 6, P70–P7 3, P80–P86, P91–P96, P120–P122 A0–A23, RD, BLW, BHW/P33, CS0, D 0–D7, D8/P20–D 15/P27, P30, P40–P4 4, P50–P57, P60–P6 6, P70–P7 3, P80–P86, P91–P96, P120–P122 A0–A23, RD, BLW, BHW/P33, CS0, D 0–D7, D8/P20–D 15/P27, P30, P40–P4 4, P50–P57, P60–P6 6, P70–P7 3, P80–P86, P91–P96, P120–P122 VCC AVCC VSS AVSS VIH VIH VIL VIL IOH (peak) IOH (avg) IOL (peak) IOL (avg) f(XIN) Notes 1: Average output current is the average value of an interval of 100 ms. 2: The sum of IOL(peak) for A0–A23, D0–D 7, D8/P20–D 15/P27, ports P80–P86 must be 80 mA or less, the sum of IOH(peak) for A0–A23, D0–D7, D8/P20–D 15/P27, ports P80–P86 must be 80 mA or less, the sum of IOL(peak) for ports P30, RD, BLW, BHW/P33, CS0, P40–P44, P50–P57, P60–P6 6, P70–P7 3, P91–P9 6, P120–P122 must be 80 mA or less, the sum of IOH(peak) for P30, RD, BLW, BHW/P3 3, CS0, P40–P4 4, P50–P5 7, P60–P6 6, P70–P7 3, P91–P9 6, P120–P122 must be 80 mA or less. 4.5 0.8VCC 0.5VCC 5.5 VCC VCC 0.2VCC 0.16VCC –10 ParameterSymbol Max.Typ.Min. Limits VCC

Notice: This is not a final specification. Some parametric limits are subject to change. 16-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS DC ELECTRICAL CHARACTERISTICS (Vcc = 5 V, Vss = 0 V, Ta = –20 to 85 °C, f(XIN) = 20 MHz, unless otherwise noted) Parameter High-level output voltage A0–A23, CS0, D 0–D 7, D 8/P20–D15/P27, P30, P40–P44, P50–P57, P60–P6 6, P70–P7 3, P80–P8 6, P91–P9 3, P12 0–P122 High-level output voltage A0–A23, CS0, D 0–D 7, D 8/P20–D15/P27, P40, P44, P91–P93 High-level output voltage RD, BLW, BHW/P33, P94/CAS/W, P95/WRL/LCAS, P96/WRH/UCAS Low-level output voltage A0–A23, CS0, D 0–D 7, D 8/P20–D15/P27, P30, P40–P44, P50–P57, P60–P6 6, P70–P7 3, P80–P8 6, P91–P9 3, P12 0–P122 Low-level output voltage A0–A23, CS0, D 0–D 7, D 8/P20–D15/P27, P40, P44, P91–P93 Low-level output voltage RD, BLW, BHW/P33, P94/CAS/W, P95/WRL/LCAS, P96/WRH/UCAS Hysteresis TA0IN–TA4IN, TB0IN–TB2 IN, INT0–INT4, DMAREQ 0–DMAREQ 3, AD TRG , CTS 0, CLK0, CLK1, NMI, RDY, HOLD, RxD 0, RxD1 Hysteresis RESET Hysteresis XIN High-level input currentD0–D 7, D8/P20–D15/P27, P30, P33, P40–P44, P50–P5 7, P60–P66, P70–P7 3, P80–P86, P91–P9 6, P120–P12 2, XIN, RESET, BYTE, MD0, MD1, NMI Low-level input currentD0–D 7, D8/P20–D15/P27, P30, P33, P40–P44, P50–P5 7, P60–P66, P70–P7 3, P80–P86, P91–P9 6, P120–P12 2, XIN, RESET, BYTE, MD0, MD1, NMI RAM hold voltage Power source current Unit V V V V V V V V V µA µA V mA µA f(XIN) = 20 MHz. Ta = 25 °C when clock is stopped. Ta = 80 °C when clock is stopped. Test conditions IOH = –10 mA IOH = –400 µA IOH = –10 mA IOH = –400 µA IOL = 10 mA IOL = 2 mA IOL = 10 mA IOL = 2 mA VI = 5.0 V VI = 0 V When clock is stoped. Symbol VOH VOH VOH VOL VOL VOL VT+ — VT – VT+ — VT – VT+ — VT – IIH IIL VRAM ICC Min. 4.7 3.4 4.8 0.4 0.5 0.1 Limits Typ. Max. 0.45 1.6 0.4 1.5 0.3 At reset in micro- processor mode, output-only pins are open, and the other pins are con- nected to Vss.

Notice: This is not a final specification. Some parametric limits are subject to change. 16-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS Resolution Absolute accuracy Ladder resistance Conversion time Reference voltage Analog input voltage R LADDER tCONV VREF VIA VREF = VCC VREF = VCC VREF = VCC f(XIN) ≤ 20 MHz Max. A-D CONVERTER CHARACTERISTICS (VCC = AVCC = 5 V ± 10 %, VSS = AVSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted) UnitParameterSymbol Test conditions Limits Min. 10-bit resolution mode 8-bit resolution mode 10-bit resolution mode 8-bit resolution mode 5.9 2.45 (Note) 2.7 ± 3 ± 2 VCC VREF Bits LSB LSB kΩ µs V V Note: This is applied when A-D conversion freguency (φAD ) = f1(φ).

Notice: This is not a final specification. Some parametric limits are subject to change. 16-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS tc(TA) tw(TAH) tw(TAL) f(XIN) ≤ 20 MHz f(XIN) ≤ 20 MHz f(XIN) ≤ 20 MHz PERIPHERAL DEVICE INPUT/OUTPUT TIMING (VCC = 5 V ± 10 %, VSS = 0 V, Ta = –20 to 85 °C, f(XIN) = 20 MHz unless otherwise noted) ∗ For limits depending on f(XIN), their calculation formulas are shown below. Also, the values at f(XIN) = 20 MHz are shown in ( ). Timer A input (Up-down input and Count input in event counter mode) tc(UP) tw(UPH) tw(UPL) tsu(UP-TIN) th(TIN-UP) Symbol TAiOUT input cycle time TAiOUT input high-level pulse width TAiOUT input low-level pulse width TAiOUT input setup time TAiOUT input hold time Parameter Limits Min. 2000 1000 1000 400 400 Max. ns ns ns ns ns Unit Timer A input (External trigger input in pulse width modulation mode) tw(TAH) tw(TAL) Symbol TAiIN input high-level pulse width TAiIN input low-level pulse width Parameter Min. Limits Max. ns ns Unit Limits Symbol Parameter Min. Max. Unit 8 × 109 f(XIN) (400)TAiIN input cycle time TAiIN input high-level pulse width TAiIN input low-level pulse width ns ns ns Timer A input (External trigger input in one-shot pulse mode) Limits Symbol Parameter Min. Max. Unit 16 × 109 f(XIN) 8 × 109 f(XIN) 8 × 109 f(XIN) (800) (400) (400) t c(TA) tw(TAH) tw(TAL) TAiIN input cycle time TAiIN input high-level pulse width TAiIN input low-level pulse width ns ns ns Timer A input (Gating input in timer mode) Note :The TAiIN input cycle time requires 4 or more cycles of a count source. The TAiIN input high-level pulse width and the TAiIN input low-level pulse width respectively require 2 or more cycles of a count source. The limits in this table are applied when the count source = f2 at f(XIN) ≤ 20 MHz. Timer A input (Count input in event counter mode) tc(TA) tw(TAH) tw(TAL) Symbol TAiIN input cycle time TAiIN input high-level pulse width TAiIN input low-level pulse width Parameter Min. Limits Max. ns ns ns Unit f(X IN) ≤ 20 MHz

Notice: This is not a final specification. Some parametric limits are subject to change. 16-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS tc(TA) tsu(TAjIN-TAjOUT) tsu(TAjOUT -TAjIN) Symbol Parameter Min. 800 200 200 Limits Max. ns ns ns Unit Timer A input (Two-phase pulse input in event counter mode) TAiIN input cycle time TAjIN input setup time TAjOUT input setup time tc(TA) tw(TAH) tw(TAL) tc(UP) tw(UPH) tw(UPL) th(TIN-UP) tsu(UP-TIN) tsu(TAjIN-TAjOUT ) tsu(TAjOUT -TAjIN) tsu(TAjIN-TAjOUT ) tsu(TAjOUT -TAjIN) tc(TA) tsu(TAjOUT -TAjIN) TAiIN input TAiOUT input (Up-down input)

• Up-down input and Count input in event counter mode
• Gating input in timer mode
• Count input in event counter mode
• External trigger input in one-shot pulse mode
• External trigger input in pulse width modulation mode TAi OUT input (Up-down input) TAiIN input (When count at falling) TAiIN input (When count at rising)
• Two-phase pulse input in event counter mode TAjIN input TAjOUT input Test conditions
• Vcc = 5 V ± 10 %, Ta = –20 to 85 °C
• Input timing voltage : V IL = 1.0 V, VIH = 4.0 V

Notice: This is not a final specification. Some parametric limits are subject to change. 16-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS f(XIN) ≤ 20 MHz f(XIN) ≤ 20 MHz f(XIN) ≤ 20 MHz f(XIN) ≤ 20 MHz f(XIN) ≤ 20 MHz f(XIN) ≤ 20 MHz tc(TB) tw(TBH) tw(TBL) tc(TB) tw(TBH) tw(TBL) Timer B input (Count input in event counter mode) Symbol TBiIN input cycle time (one edge count) TBiIN input high-level pulse width (one edge count) TBiIN input low-level pulse width (one edge count) TBiIN input cycle time (both edge count) TBiIN input high-level pulse width (both edge count) TBiIN input low-level pulse width (both edge count) Parameter Limits Min. 160 Max. ns ns ns ns ns ns Unit Limits Symbol Parameter Min. Max. Unit 16 × 109 f(XIN) 8 × 109 f(XIN) 8 × 109 f(XIN) (800) (400) (400) t c(TB) tw(TBH) tw(TBL) TBiIN input cycle time TBiIN input high-level pulse width TBiIN input low-level pulse width ns ns ns Timer B input (Pulse period measurement mode) Note: The TBiIN input cycle time requires 4 or more cycles of a count source. The TBiIN input high-level pulse width and the TBiIN input low-level pulse width respectively require 2 or more cycles of a count source. The limits in this table are applied when the count source = f2 at f(XIN) ≤ 20 MHz. Limits Symbol Parameter Min. Max. Unit 16 × 109 f(XIN) 8 × 109 f(XIN) 8 × 109 f(XIN) (800) (400) (400) t c(TB) tw(TBH) tw(TBL) TBiIN input cycle time TBiIN input high-level pulse width TBiIN input low-level pulse width ns ns ns Timer B input (Pulse width measurement mode) Note: The TBiIN input cycle time requires 4 or more cycles of a count source. The TBiIN input high-level pulse width and the TBiIN input low-level pulse width respectively require 2 or more cycles of a count source. The limits in this table are applied when the count source = f2 at f(XIN) ≤ 20 MHz. tc(AD) tw(ADL) Symbol AD TRG input cycle time (minimum allowable trigger) AD TRG input low-level pulse width Parameter Min. 1000 125 Limits Max. ns ns Unit A-D trigger input

Notice: This is not a final specification. Some parametric limits are subject to change. 16-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS tc(CK) tw(CKH) tw(CKL) td(C-Q) th(C-Q) tsu(D-C) th(C-D) Serial I/O Symbol CLK i input cycle time CLK i input high-level pulse width CLK i input low-level pulse width TX Di output delay time TX Di hold time R XD i input setup time R XD i input hold time Parameter Limits Min. 200 100 100 Max. ns ns ns ns ns ns ns Unit tw(INH) tw(INL) Symbol INTi input/NMI input high-level pulse width INTi input/NMI input low-level pulse width Parameter Min. 250 250 Limits Max. ns ns Unit External interrupt (INTi) input, NMI input tc(TB) tw(TBH) tw(TBL) tc(AD) tw(ADL) tsu(D-C) tc(CK) tw(CKH) tw(CKL) tw(INL) tw(INH) td(C-Q) th(C-D) th(C-Q) TBiIN input AD TRG input INTi input NMI input CLK i input TxD i output RxD i input Test conditions

• Vcc = 5 V ± 10 %, Ta = –20 to 85 °C
• Input timing voltage : V IL = 1.0 V, VIH = 4.0 V
• Output timing voltage : VOL = 0.8 V, VOH = 2.0 V, CL = 50 pF

Notice: This is not a final specification. Some parametric limits are subject to change. 16-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS td(φ1-HLDAL) td(RDH-HLDAL) td(BXWH-HLDAL) tpxz(HLDAL-RDZ) tpxz(HLDAL-BXWZ) tpxz(HLDAL-CSiZ) tpxz(HLDAL-ALEZ) tpxz(HLDAL-AZ) tpzx(HLDAL-RDZ) tpzx(HLDAL-BXWZ) tpzx(HLDAL-CSiZ) tpzx(HLDAL-ALEZ) tpzx(HLDAL-AZ) READY , HOLD TIMING Timing requirements (VCC = 5 V ± 10 %, VSS = 0 V, Ta = –20 to 85 °C, f(XIN) = 20 MHz, unless otherwise noted) tsu(RDY-φ1) tsu(HOLD-φ1) th(φ1-RDY) th(φ1-HOLD) Symbol RDY input setup time HOLD input setup time RDY input hold time HOLD input hold time Parameter Limits Min. Max. ns ns ns ns Unit Switching characteristics (VCC = 5 V ± 10 %, VSS = 0 V, Ta = –20 to 85 °C, f(XIN) = 20 MHz, unless otherwise noted) Symbol HLDA output delay time HLDA low-level output delay time after read HLDA low-level output delay time after write Floating start delay time Floating start delay time Floating start delay time Floating start delay time Floating start delay time Floating release delay time Floating release delay time Floating release delay time Floating release delay time Floating release delay time Parameter Min. tc –15 (Note) tc –15 (Note) –15 –15 –15 –15 –15 Limits Max. ns ns ns ns ns ns ns ns ns ns ns ns ns Unit Note: tc = 1/f(XIN).

Notice: This is not a final specification. Some parametric limits are subject to change. 16-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS Test conditions

• Vcc = 5 V ± 10 %, Ta = –20 to 85 °C
• RDY input, HOLD input : V IL = 1.0 V, VIH = 4.0 V
• HLDA output : VOL = 0.8 V, VOH = 2.0 V, CL = 50 pF /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines RDY input tsu(RDY-φ1) RD BLW BHW /LiteDiagLines/LiteDiagLines/LiteDiagLines : Wait inserted by software (The above is applied when 1 wait is selected.) : Wait inserted by Ready function RDY input th(φ1-RDY) HOLD input tsu(HOLD-φ1) td(φ1-HLDAL) tpxz(HLDAL-RDZ) tpxz(HLDAL-BXWZ) tpxz(HLDAL-CSiZ) tpxz(HLDAL-AZ) th(φ1-HOLD) td(φ1-HLDAL) tpzx(HLDAL-RDZ) tpzx(HLDAL-BXWZ) tpzx(HLDAL-CSiZ) tpzx(HLDAL-ALEZ) tpzx(HLDAL-AZ) Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z HOLD input HLDA output RD BLW BHW CS i A0–A23 output td(RDH-HLDAL) td(BXWH-HLDAL) tpxz(HLDAL-ALEZ) ALE

Notice: This is not a final specification. Some parametric limits are subject to change. 16-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS When ALE expansion wait is selected W = 0 (0 wait) W = 1 (1 wait) W = 2 (2 wait) tc = 1/f(X IN). External bus timing For limits depending on f(XIN), their calculation formulas are shown below. External clock input tr tf tw(L) tw(H) tw(half) f(XIN) tc Test conditions

• Vcc = 5 V ± 10 %, Ta = –20 to 85 °C
• Input timing voltage : V IL = 1.0 V, VIH = 4.0 V (tw(H), tw(L), tr, tf)
• Input timing voltage : 2.5 V (tc, tw(half)) Timing Requirements (VCC = 5 V ± 10 %, VSS = 0 V, Ta = –20 to 85 °C, f(XIN) = 20 MHz, unless otherwise noted) ns ns ns ns ns ns ns ns ns ns ns ns ns 0.45tc 0.5tc – 8 0.5tc – 8 0.55tc (2 + W)tc – 45 (1.5 + W)tc – 35 (1 + W)tc – 30 (1 + W)tc – 35 0.45tc 0.5tc – 8 0.5tc – 8 Limits External clock input cycle time External clock input pulse width with half input-volage External clock input high-level pulse width External clock input low-level pulse width External clock input rise time External clock input fall time Address access time Chip select access time Read access time Read data setup time Data input hold time after read Address access time at burst ROM access Data hold time after address at burst ROM access Parameter Max.Min. tc tw(half) tw(H) tw(L) tr tf ta(A-D) ta(CSiL-D) ta(RDL-D) tsu(D-RDL) th(RDH-D) ta(BA-D) th(BA-D) UnitSymbol Max.Min. When 0/1/2 wait is selected 0.55tc 4tc – 45 3.5tc – 35 2tc – 30 2tc – 35

Notice: This is not a final specification. Some parametric limits are subject to change. 16-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS Switching characteristics (VCC = 5 V ± 10 %, VSS = 0 V, Ta = –20 to 85 °C, f(XIN) = 20 MHz, unless otherwise noted) 0.5tc + 10 Read low-level output delay time Read high-level output delay time Write low-level output delay time Write high-level output delay time ALE pulse width ALE completion delay time after address stabilization Read output pulse width Read output high-level width (Note 1) Write disable valid time after read (Note 2) Address valid time before read Address hold time after read (Note 3) ALE completion delay time after read start Read disable valid time after ALE completion Chip select valid time before read Chip select output valid time before read completion Chip select hold time after read Next write cycle data output delay time after read (Note 2) Write output pulse width Write output high-level width (Note 1) Read disable valid time after write (Note 2) Address valid time before write Address hold time after write (Note 3) ALE completion delay time after write start Write disable valid time after ALE completion Chip select valid time before write Chip select output valid time before write completion Chip select hold time after write Data output valid time before write completion Data hold time after write Floating start delay time after write –10 –10 –10 –10 tc – 20 1.5tc – 30 2tc – 15 2tc – 15 tc – 15 2tc – 30 0.5tc – 20 1.5tc – 20 3.5tc – 20 0.5tc – 20 tc – 15 2tc – 15 2tc – 15 tc – 15 2tc-30 0.5tc – 20 1.5tc – 20 3.5tc – 20 0.5tc – 20 2tc – 20 0.5tc – 10 0.5tc + 10 –10 –10 –10 –10 0.5tc – 20 tc – 30 (1 + W)tc – 15 tc – 15 tc – 15 tc – 30 0.5tc – 20 (1.5 + W)tc – 20 0.5tc – 20 tc – 15 (1 + W)tc – 15 tc – 15 tc – 15 tc – 30 0.5tc – 20 (1.5 + W)tc – 20 0.5tc – 20 (1 + W)tc – 20 0.5tc – 10 td(φ1-RDL) td(φ1-RDH) td(φ1-BXWL) td(φ1-BXWH) tw(ALEH) td(A-ALEL) tw(RDL) tw(RDH) td(RDH-BXWH) td(A-RDH) th(RDH-A) td(RDH-ALEL) td(ALEL-RDH) td(CSiL-RDH) td(CSiL-RDL) th(RDH-CSiL) td(RDH-D) tw(BXWL) tw(BXWH) td(BXWH-RDH) td(A-BXWH) th(BXWH-A) td(BXWH-ALEL) td(ALEL-BXWH) td(CSiL-BXWH) td(CSiL-BXWL) th(BXWH-CSiL) td(D-BXWL) th(BXWH-D) tpxz(BXWH-DZ) ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Parameter Max.Min. UnitSymbol Limits Max.Min. When 0/1/2 wait is selectedWhen ALE expansion wait is selected Notes 1: When the bus cycle just before this parameter is for the area where the recovery cycle insertion is selected, this parameter is extended by tc (ns). 2: When accessing the area where the recovery cycle insertion is selected, this parameter is extended by tc (ns). 3: When accessing the area where the recovery cycle insertion is selected, this parameter is extended by tc (ns). However, except for the case at instruction prefetch.

Notice: This is not a final specification. Some parametric limits are subject to change. 16-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS Test conditions

• Vcc = 5 V ± 10 %, Ta = –20 to 85 °C
• Input timing voltage : V IL = 0.8 V, VIH = 2.5 V
• Output timing voltage : VOL = 0.8 V, VOH = 2.0 V, CL = 15 pF (CSi)
• Output timing voltage : VOL = 0.8 V, VOH = 2.0 V, CL = 50 pF (except for CSi) Bus cycle<At read> CS i A0–A23 D 0–D 7, D8–D 15 th(RDH-D) th(RDH-A) th(RDH-CSiL) RD tw(RDL) ta(CSiL-D) ta(RDL-D) ta(A-D) td(A-RDH) td(CSiL-RDL) td(CSiL-RDH) tsu(D-RDL) ALE tw(ALEH) td(RDH-ALEL) td(RDH-BXWH) tc f(XIN) <At write> CS i A0–A23 th(BXWH-A) th(BXWH-CSiL) RD td(A-BXWH) td(CSiL-BXWL) td(CSiL-BXWH) ALE td(BXWH-RDH) tw(BXWL) td(BXWH-ALEL) D 0–D 7, D8–D 15 td(D-BXWL) th(BXWH-D) tpxz(BXWH-DZ) Normal access: 0/1/2 wait td(A-ALEL) td(A-ALEL) tw(RDH) td(RDH-D) tw(BXWH) BLW BHW BLW BHW td(φ1-RDL) td(φ1-RDH) tw(ALEH) Bus cycle td(φ1-BXWL) td(φ1-BXWH)

Notice: This is not a final specification. Some parametric limits are subject to change. 16-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS Bus cycle td(CSiL-BXWL) td(CSiL-RDL) td(A-ALEL) th(RDH-D) th(RDH-A) th(RDH-CSiL) tw(RDL) ta(CSiL-D) ta(RDL-D) ta(A-D) td(A-RDH) td(CSiL-RDH) tsu(D-RDL) tw(ALEH) td(RDH-BXWH) tc <At write> th(BXWH-A) th(BXWH-CSiL) td(A-BXWH) td(CSiL-BXWH) tw(ALEH) td(BXWH-RDH) tw(BXWL) td(D-BXWL) th(BXWH-D) tpxz(BXWH-DZ) td(A-ALEL) tw(RDH) td(RDH-D) tw(BXWH) td(ALEL-RDH) td(ALEL-BXWH) Normal access : ALE extension wait td(φ1-RDL) td(φ1-RDH) Bus cycle td(φ1-BXWL) td(φ1-BXWH) <At read> CS i A0–A23 D 0–D 7, D8–D 15 RD ALE f(XIN) BLW BHW CS i A0–A23 RD ALE D 0–D 7, D8–D 15 BLW BHW Test conditions

• Vcc = 5 V ± 10 %, Ta = –20 to 85 °C
• Input timing voltage : V IL = 0.8 V, VIH = 2.5 V
• Output timing voltage : VOL = 0.8 V, VOH = 2.0 V, CL = 15 pF (CSi)
• Output timing voltage : VOL = 0.8 V, VOH = 2.0 V, CL = 50 pF (except for CSi)

Notice: This is not a final specification. Some parametric limits are subject to change. 16-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS Burst ROM access : 0/1/2 wait at instruction prefetch th(BA-D) td(RDH-BXWH) BLW BHW D 0–D 7, D8–D 15 RD ta(RDL-D) td(A-RDH) CS i th(RDH-A) ta(CSiL-D) ta(A-D) ta(BA-D) A0–A23 th(BA-D) th(BA-D) th(RDH-D) ta(BA-D) ta(BA-D) th(RDH-CSiL)td(CSiL-RDH) td(A-ALEL) tw(ALEH) ALE td(RDH-ALEL)tw(RDH) Test conditions

• Vcc = 5 V ± 10 %, Ta = –20 to 85 °C
• Input timing voltage : V IL = 0.8 V, VIH = 2.5 V
• Output timing voltage : VOL = 0.8 V, VOH = 2.0 V, CL = 15 pF (CSi)
• Output timing voltage : VOL = 0.8 V, VOH = 2.0 V, CL = 50 pF (except for CSi)

Notice: This is not a final specification. Some parametric limits are subject to change. 16-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS tw(RASH) td(CASH-RASH) th(RASL-CASH) th(CASL-RASL) tw(CASL) td(RA-RASH) th(RASL-RA) td(CA-CASH) th(CASH-CA) td(WH-CASH) td(WL-CASH) th(CASL-WL) td(D-CASH) th(CASL-D) tpxz(CASH-D) td(CAF-CASH) td(WFL-CASH) td(DF-CASH) tpxz(WH-D) ta(RASL-D) ta(CASL-D) th(CASH-D) ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 1.5tc – 20 1.5tc – 20 1.5tc – 20 tc – 15 tc – 15 0.5tc – 25 tc – 40 0.5tc – 20 3tc – 15 tc – 15 tc – 15 tc – 20 1.5tc – 15 0.5tc + 10 tc – 40 0.5tc – 20 0.5tc – 20 DRAM access Timing Requirements (VCC = 5 V ± 10 %, VSS = 0 V, Ta = 0 to 70 °C, f(XIN) = 20 MHz, unless otherwise noted) Limits RAS access time CAS access time Data input hold time after CAS Parameter Max.Min. UnitSymbol ns ns ns0 2.5tc – 35 tc – 30 Limits RAS high-level pulse width CAS high-level valid time before RAS CAS high-level hold time after RAS’s low level RAS hold time after CAS’s low level CAS low-level pulse width Row address valid time before RAS Row address hold time after RAS’s low level Column address valid time before CAS Column address hold time after CAS’s high level W high-level valid time before CAS W low-level valid time before CAS W hold time after CAS’s low level Data output valid time before CAS Data output hold time after CAS’s low level Floating start delay time after CAS Column address valid time before CAS (When fast page access ON is selected) W low-level valid time before CAS (When fast page access ON is selected) Data output valid time before CAS (When fast page access ON is selected) Floating start delay time after write Parameter Max.Min. UnitSymbol Switching characteristics (VCC = 5 V ± 10 %, VSS = 0 V , Ta = 0 to 70 °C, f(XIN) = 20 MHz, unless otherwise noted) 0.5tc + 10

Notice: This is not a final specification. Some parametric limits are subject to change. 16-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS th(RASL-RA) DRAM access : fast page access = OFF D 0–D 7, D8–D 15 RAS i A0–A23 LCAS,UCAS (CAS) W (WRL,WRH) Column address th(CASL-RASL) ta(CASL-D) th(CASH-D) tw(RASH) W (WRL,WRH) D 0–D 7, D8–D 15 RAS i A0–A23 td(RA-RASH) th(CASH-CA) tw(CASL) td(WH-CASH) ta(RASL-D) LCAS,UCAS (CAS) th(RASL-RA) td(CA-CASH) td(CASH-RASH) Row address Column address Row address th(RASL-CASH) th(CASL-D) tw(RASH) td(RA-RASH) th(CASH-CA) tw(CASL) td(D-CASH) <At write> td(WL-CASH) th(CASL-WL) td(CA-CASH) td(CASH-RASH) tpxz(CASH-D) th(CASL-RASL)th(RASL-CASH) Column addressRow address Column address Row address <At read> Test conditions

• Vcc = 5 V ± 10 %, Ta = 0 to 70 °C
• Input timing voltage : V IL = 0.8 V, VIH = 2.5 V
• Output timing voltage : VOL = 0.8 V, VOH = 2.0 V, CL = 15 pF (RASi)
• Output timing voltage : VOL = 0.8 V, VOH = 2.0 V, CL = 50 pF (except for RASi)

Notice: This is not a final specification. Some parametric limits are subject to change. 16-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS td(RA-RASH) DRAM access : fast page access = ON ta(CASL-D) th(CASH-D) tw(RASH) tw(CASL) td(RA-RASH) th(CASH-CA) td(WH-CASH) ta(RASL-D) tw(CASL) tw(CASL) th(CASH-CA) th(RASL-RA) td(CA-CASH) td(CAF-CASH) td(CAF-CASH) th(CASH-CA) ta(CASL-D) th(CASH-D) td(CASH-RASH) ta(CASL-D) th(CASH-D) th(CASL-RASL) th(RASL-CASH) Row address Column address Column address Column address tpxz(WH-D) tw(RASH) th(CASH-CA) tw(CASL) tw(CASL) tw(CASL) th(CASH-CA) th(RASL-RA) td(CA-CASH) td(CAF-CASH) td(CAF-CASH) th(CASH-CA) td(CASH-RASH) th(CASL-D)td(D-CASH) td(WL-CASH) th(CASL-D)td(DF-CASH) td(WFL-CASH) th(CASL-WL) th(CASL-D)td(DF-CASH) td(WFL-CASH) th(CASL-WL) th(CASL-RASL) th(RASL-CASH) Row address Column address Column address Column address th(CASL-WL) W (WRL,WRH) RASi A0–A23 LCAS,UCAS (CAS) <At read> D 0–D 7, D8–D 15 RASi A0–A23 LCAS,UCAS (CAS) W (WRL,WRH) D 0–D 7, D8–D 15 <At write> Test conditions

• Vcc = 5 V ± 10 %, Ta = 0 to 70 °C
• Input timing voltage : V IL = 0.8 V, VIH = 2.5 V
• Output timing voltage : VOL = 0.8 V, VOH = 2.0 V, CL = 15 pF (RASi)
• Output timing voltage : VOL = 0.8 V, VOH = 2.0 V, CL = 50 pF (except for RASi)

Notice: This is not a final specification. Some parametric limits are subject to change. 16-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS tw(RAS CBR L) tw(CAS CBR L) td(CASCBR L-RASCBR H) td(RASCBR L-CASCBR L) td(CASSLFR L-RASSLFR H) th(RASSLFR H-CAS SLFR L) 2tc – 15 2tc – 15 tc – 15 tc – 15 tc – 15 –15 ns ns ns ns ns ns DRAM refresh Switching characteristics (VCC = 5 V ± 10 %, VSS = 0 V , Ta = 0 to 70 °C, f(XIN) = 20 MHz, unless otherwise noted) Limits RAS low-level pulse width (At CAS before RAS refresh) CAS low-level pulse width (At CAS before RAS refresh) RAS high-level valid time after CAS’s low level start (At CAS before RAS refresh) CAS low-level valid time after RAS’s low level start (At CAS before RAS refresh) RAS high-level valid time after CAS’s low level start (At self refresh) CAS low-level hold time after RAS’s high level (At self refresh) Parameter Max.Min. UnitSymbol

Notice: This is not a final specification. Some parametric limits are subject to change. 16-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS td(CAS CBR L-RAS CBR H) DRAM refresh : CAS before RAS refresh td(RAS CBR L-CAS CBR L) tw(RAS CBR L) tw(CAS CBR L) Refresh cycle td(CAS SLFR L-RAS SLFR H) th(RAS SLFR H-CAS SLFR L) Refresh cycle DRAM refresh : self refresh W (WRL,WRH) RAS i LCAS,UCAS (CAS) W (WRL,WRH) RAS i LCAS,UCAS (CAS) Test conditions

• Vcc = 5 V ± 10 %, Ta = 0 to 70 °C
• Output timing voltage : V OL = 0.8 V, VOH = 2.0 V, CL = 15 pF (RASi)
• Output timing voltage : VOL = 0.8 V, VOH = 2.0 V, CL = 50 pF (except for RASi)

Notice: This is not a final specification. Some parametric limits are subject to change. 16-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS tw(TCL) td(RDH-TCL) td(BXWH-TCL) td(TCL-DMAACKL) Unit TC input setup time TC input pulse width DMAREQ i input setup time DMAREQ i input pulse width DMA transfer timing Timing Requirements (VCC = 5 V ± 10 %, VSS = 0 V, Ta = –20 to 85 °C, f(XIN) = 20 MHz, unless otherwise noted) Max. ParameterSymbol Unit Min. Limits tsu(TCINL-φ1) tw(TC INL) tsu(DRQL-φ1) tw(DRQL) ns ns ns ns tc + 20 tc TC output pulse width TC output start delay time after read TC output start delay time after write DMAACK low-level output valid time after TC output start Switching characteristics (V CC = 5 V ± 10 %, VSS = 0 V , Ta = –20 to 85 °C, f(XIN) = 20 MHz, unless otherwise noted) Max.ParameterSymbol Min. Limits ns ns ns ns tc – 20 tc – 15 tc – 15 2.5tc – 20 TC 50 pF 3 kΩ Test circuit for TC output

Notice: This is not a final specification. Some parametric limits are subject to change. 16-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS l TC input TC input tsu(TCINL-φ1) l DMAREQ i input DMAREQ i input tsu(DRQL-φ1) tw(DRQL) tw(TC INL) Test conditions

• Vcc = 5 V ± 10 %, Ta = –20 to 85 °C
• Input timing voltage : V IL = 1.0 V, VIH = 4.0 V
• Output timing voltage : VOL = 0.8 V, VOH = 2.0 V, CL = 50 pF CS i A0–A23 D 0–D 7, D8–D 15 RD BLW BHW ALE tw(TCL) TC DMAACK i td(RDH-TCL) td(BXWH-TCL) td(TCL-DMAACKL) Final tranfer cycle Terminate processing (Next bus cycle) l Transfer terminate timing Test conditions
• Vcc = 5 V ± 10 %, Ta = –20 to 85 °C
• Output timing voltage : V OL = 0.8 V, VOH = 2.0 V, CL = 50 pF

Y Notice: This is not a final specification. Some parametric limits are subject to change. 16-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS Notes regarding these materials

• These materials are intended as a reference to assist our customers in the selection of the Mitsubishi semiconductor product best suited to the customer’s application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Mitsubishi Electric Corporation or a third party.
• Mitsubishi Electric Corporation assumes no responsibility for any damage, or infringement of any third-party’s rights, originating in the use of any product data, diagrams, charts or circuit application examples contained in these materials.
• All information contained in these materials, including product data, diagrams and charts, represent information on products at the time of publication of these materials, and are subject to change by Mitsubishi Electric Corporation without notice due to product improvements or other reasons. It is therefore recommended that customers contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for the latest product information before purchasing a product listed herein. The information described here may contain technical inaccuracies or typographical errors. Mitsubishi Electric Corporation assumes no responsibility for any damage, liability or other loss rising from these inaccuracies or errors.
• Mitsubishi Electric Corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use.
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• Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for further details on these materials or the products contained therein. © 1999 MITSUBISHI ELECTRIC CORP. New publication, effective Sep. 1999. Specifications subject to change without notice. Keep safety first in your circuit designs!
• Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non-flammable material or (iii) prevention against any malfunction or mishap. QFP100-P-1420-0.65 1.58 W eight(g) JEDEC CodeEIAJ Package Code Lead Material Alloy 42 100P6S-A Plastic 100pin 145 20mm body QFP 0.1 0.2 Symbol Min Nom Max A b c D E H E L y Dimension in Millimeters H D 0.35 ––I2 1.3 ––M D 14.6 ––M E 20.6 10°0° 0.1 1.4 0.80.60.4 23.122.822.5 17.116.816.5 0.65 20.220.019.8 14.214.013.8 0.20.150.13 0.40.30.25 2.8 3.05 e e e E c H E H D D M D M E A Fb A1 A2 L y Recommended Mount Pad Detail F 100 PACKAGE OUTLINE

Rev. Rev. No. date

1.00 First Edition 990916

REVISION DESCRIPTION LIST M37920S4CGP Datasheet (1/1) Revision Description