Memory

M37920FCCGP

Mitsubishi Electric Sem...

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION

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M37920FCCGP MITSUBISHI | Alldatasheet

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These are single-chip microcomputers designed with high-perfor- mance CMOS silicon gate technology, including the internal flash memory. These are housed in 100-pin plastic molded QFP . These microcomputers support the 7900 Series instruction set, which are enhanced and expanded instruction set and are upper-compatible with the 7700/7751 Series instruction set. The CPU of these microcomputers is a 16-bit parallel processor that can also be switched to perform 8-bit parallel processing. Also, the bus interface unit of these microcomputers enhances the memory access efficiency to execute instructions fast. These microcomputers include the 4-channel DMA controller and the DRAM controller. Therefore, these microcomputers are suitable for office, business, and industrial equipment controller that require fast processing of large data. For the internal flash memory, single-power-supply programming and erasure, using a PROM programmer or the control by the cen- tral processing unit (CPU), is supported. Also, each of these micro- computers has the memory area dedicated for storing a certain software which controls programming and erasure (reprogramming control software). Therefore, on these microcomputers, the program can easily be changed even after they are mounted on the board. DISTINCTIVE FEATURES <Microcomputer mode>

Memory [M37920FCCGP, M37920FCCHP] [M37920FGCGP, M37920FGCHP] [All of the above computers]
Instruction execution time
DRAM controller
Real-time output ....4 bits × 2 channels, or 6 bits × 1 channel + 2 bits × 1 channel
12-bit watchdog timer <Flash memory mode> (Data protection per block is enabled.)
Programming/Erase control by software command APPLICATION Control devices for personal computer peripheral equipment such as CD-ROM drives, DVD-ROM drives, hard disk drives, high density FDD, printers Control devices for office equipment such as copiers and facsimiles Control devices for industrial equipment such as communication and measuring instruments

Y Notice: This is not a final specification. Some parametric limits are subject to change. M37920FCCGP, M37920FCCHP M37920FGCGP, M37920FGCHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION MITSUBISHI MICROCOMPUTERS Outline 100P6S-A M37920FxCGP PIN CONFIGURATION (TOP VIEW) P66/DMAREQ 3 ↔ P65/TA4IN/DMAREQ 2 ↔ P64/TA4OUT /DMAACK 2 ↔ P60/TA1OUT /DMAACK 0 ↔ P57/TA2IN/RTP13 ↔ P56/TA2OUT /RTP12 ↔ P55/RTP11 ↔ P54/RTP10 ↔ P53/RTP03 ↔ P52/RTP02 ↔ P51/TA0IN/RTP01 ↔ P50/TA0OUT /RTP00 ↔ P96/WRH/UCAS ↔ P95/WRL/LCAS ↔ P94/CAS/W ↔ P93/CS3/RAS3 ↔ P92/CS2/RAS2 ↔ P91/CS1/RAS1 ↔ P90/CS0 ↔ P44/HLDA ↔ P43/HOLD ↔ P42/TC ↔ P41/φ1 ↔ P40/ALE ↔ P33/BHW ↔ P32/BLW ↔ P31/RD ↔ 100 P63/TA3IN/DMAREQ 1 ↔ P62/TA3OUT /DMAACK 1 ↔ P61/TA1IN/DMAREQ 0 ↔ ↔ P30/RDY ← BYTE ← NMI ← RESET ← MD0 VSS ← XIN → XOUT VCC ↔ P27/D15 ↔ P26/D14 ↔ P25/D13 ↔ P24/D12 ↔ P23/D11 ↔ P22/D10 ↔ P21/D9 ↔ P20/D8 ↔ P17/D7 ↔ P14/D4 ↔ P13/D3 ↔ P12/D2 ↔ P11/D1 ↔ P10/D0 ← MD1 VSS ↔ P07/A23 ↔ P06/A22/MA11 ↔ P05/A21 ↔ P04/A20/MA10 ↔ P03/A19 ↔ P02/A18/MA9 ↔ P01/A17 ↔ P00/A16/MA8 ↔ P117/A15/MA7 ↔ P116/A14/MA6 ↔ P115/A13/MA5 ↔ P114/A12/MA4 ↔ P113/A11/MA3 ↔ P112/A10/MA2 ↔ P111/A9/MA1 ↔ P110/A8/MA0 ↔ P107/A7 ↔ P106/A6 ↔ P105/A5 ↔ P104/A4 ↔ P103/A3 ↔ P102/A2 ↔ P101/A1 ↔ P16/D6 ↔ P15/D5P100/A0 ↔ P86/CLK0 ↔ P85/RXD 0 ↔ P84/TXD 0 ↔ P83/CTS0/RTS0 ↔ P82/CTS0/CLK1 ↔ P81/RXD 1 ↔ VCC AV CC VREF AV SS VSS P73/AN3/ADTRG /INT4 ↔ P72/AN2/INT3 ↔ P71/AN1 ↔ P70/AN0 ↔ P122/INT2/TB2IN ↔ P121/INT1/TB1IN ↔ P120/INT0/TB0IN ↔ P80/TXD 1 ↔ M37920FCCGP M37920FGCGP

M37920FCCGP, M37920FCCHP M37920FGCGP, M37920FGCHPPRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION MITSUBISHI MICROCOMPUTERS M37920FxCHP PIN CONFIGURATION (TOP VIEW) Outline 100P6Q-A P66/DMAREQ 3 ↔ P65/TA4IN/DMAREQ 2 ↔ P64/TA4OUT /DMAACK 2 ↔ P60/TA1OUT /DMAACK 0 ↔ P57/TA2IN/RTP13 ↔ P56/TA2OUT /RTP12 ↔ P55/RTP11 ↔ P54/RTP10 ↔ P53/RTP03 ↔ P52/RTP02 ↔ P51/TA0IN/RTP01 ↔ P50/TA0OUT /RTP00 ↔ P96/WRH/UCAS ↔ P95/WRL/LCAS ↔ P94/CAS/W ↔ P93/CS3/RAS3 ↔ P92/CS2/RAS2 ↔ P91/CS1/RAS1 ↔ P90/CS0 ↔ P44/HLDA ↔ P43/HOLD ↔ P42/TC ↔ P41/φ1 ↔ P40/ALE ↔ 100 P63/TA3IN/DMAREQ 1 ↔ P62/TA3OUT /DMAACK 1 ↔ P61/TA1IN/DMAREQ 0 ↔ ↔ P30/RDY 28 ↔ P31/RD 27 ↔ P32/BLW 26 ↔ P33/BHW ← BYTE ← NMI ← RESET ← MD0 VSS ← XIN → XOUT VCC ↔ P27/D15 ↔ P26/D14 ↔ P25/D13 ↔ P24/D12 ↔ P23/D11 ↔ P22/D10 ↔ P21/D9 ↔ P20/D8 ↔ P17/D7 ↔ P14/D4 ↔ P13/D3 ↔ P12/D2 ↔ P11/D1 ↔ P10/D0 ← MD1 VSS ↔ P07/A23 ↔ P06/A22/MA11 ↔ P05/A21 ↔ P04/A20/MA10 ↔ P03/A19 ↔ P02/A18/MA9 ↔ P01/A17 ↔ P00/A16/MA8 ↔ P117/A15/MA7 ↔ P116/A14/MA6 ↔ P115/A13/MA5 ↔ P114/A12/MA4 ↔ P113/A11/MA3 ↔ P112/A10/MA2 ↔ P111/A9/MA1 ↔ P110/A8/MA0 ↔ P107/A7 ↔ P106/A6 ↔ P105/A5 ↔ P104/A4 ↔ P16/D6 ↔ P15/D5 P100/A0 ↔ P101/A1 ↔ P102/A2 ↔ P103/A3 ↔ P86/CLK0 ↔ P85/RXD 0 ↔ P84/TXD 0 ↔ P83/CTS0/RTS0 ↔ P82/CTS0/CLK1 ↔ P81/RXD 1 ↔ VCC AV CC VREF AV SS VSS P73/AN3/ADTRG /INT4 ↔ P72/AN2/INT3 ↔ P71/AN1 ↔ P70/AN0 ↔ P122/INT2/TB2IN ↔ P121/INT1/TB1IN ↔ P120/INT0/TB0IN ↔ P80/TXD 1 ↔ M37920FCCHP M37920FGCHP

Y Notice: This is not a final specification. Some parametric limits are subject to change. M37920FCCGP, M37920FCCHP M37920FGCGP, M37920FGCHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION MITSUBISHI MICROCOMPUTERS BLOCK DIAGRAM Data bank Register DT (8) Program Counter PC (16) Incrementer/Decrementer (24) Program Bank Register PG (8) Input Buffer Register IB (16) Direct Page Register DPR0 (16) Stack Pointer S (16) Index Register Y (16) Index Register X (16) Arithmetic Logic Unit (16) Accumulator B (16) Accumulator A (16) Instruction register (8) Central Processing Unit (CPU) Incrementer (24) Program Address Register PA (24) Data Address Register DA (24) Bus Interface Unit(BIU) RESET MD1 Reference voltage input V REF (0V)AV SS AVcc Vcc External data bus width select input BYTE Clock Generating Circuit Clock input X IN X OUT Data Buffer DQ0 (8) Instruction Queue Buffer Q0 (8) Data Bus (Odd) Address Bus A-D converter (10) Watchdog timerTimer TB1 (16)Timer TB2 (16)Timer TB0 (16) Timer TA1 (16)Timer TA2 (16)Timer TA3 (16)Timer TA4 (16)Timer TA0 (16) Input/Output port P8 Input/Output port P7 Input/Output port P4 Input/Output port P10 Input/Output port P6 Input/Output port P5 Input/Output port P11 Input/Output port P1 Input/Output port P2 Input/Output port P3 Input/Output port P0 MD0 (0V)Vss Processor Status Register PS (11) NMI Data Bus (Even) Data Buffer DQ1 (8) Data Buffer DQ2 (8) Data Buffer DQ3 (8) Instruction Queue Buffer Q1 (8) Instruction Queue Buffer Q2 (8) Instruction Queue Buffer Q3 (8) Instruction Queue Buffer Q4 (8) Instruction Queue Buffer Q5 (8) Instruction Queue Buffer Q6 (8) Instruction Queue Buffer Q7 (8) Instruction Queue Buffer Q8 (8) Instruction Queue Buffer Q9 (8) Direct Page Register DPR1 (16) Direct Page Register DPR2 (16) Direct Page Register DPR3 (16) Clock output Reset input Note: Flash memory RAM M37920FCCGP, M37920FCCHP

120 Kbytes 4096 bytes

M37920FGCGP, M37920FGCHP

248 Kbytes 6144 bytes

UART1(9)UART0(9) RAM(Note) P8(7) P7(4) P9(7) P4(5) P10(8) P6(7) P5(8) DRAM controoler DMA0(16)DMA1(16)DMA2(16)DMA3(16) P11(8) P12(3) P1(8) P2(8) P3(4) P0(8) Flash memory (Note) Input/Output port P9 Input/Output port P12

M37920FCCGP, M37920FCCHP M37920FGCGP, M37920FGCHPPRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION MITSUBISHI MICROCOMPUTERS Power supply voltage Power dissipation Ports’ input/output characteristics FUNCTIONS (Microcomputer mode) FunctionsParameter Number of basic machine instructions Instruction execution time External clock input frequency f(X IN) Memory size Programmable input/output ports Multi-functional timers Serial I/O A-D converter Watchdog timer DMA controller DRAM controller Chip-select wait control Real-time output Interrupts Clock generating circuit Input/Output withstand voltage Output current Flash memory (User ROM area) RAM Flash memory (Boot ROM area) P0–P2, P5, P10, P11 P3, P7 P6, P8, P9 P12 TA0–TA4 TB0 –TB2 UART0 and UART1 Memory expansion Operating ambient temperature range Device structure Package Flash memory M37920FCCGP, M37920FCCHP 120 Kbytes (User ROM area) M37920FGCGP, M37920FGCHP 248 Kbytes RAM M37920FCCGP, M37920FCCHP 4096 bytes M37920FGCGP, M37920FGCHP 6144 bytes Note: 203 50 ns (the fastest instruction at f(XIN) = 20 MHz) 20 MHz (Max.) (Note) (Note)

16 Kbytes

8-bit ✕ 6 4-bit ✕ 2 5-bit ✕ 1 7-bit ✕ 3 3-bit ✕ 1 16-bit ✕ 5 16-bit ✕ 3 (UART or Clock synchronous serial I/O) ✕ 2 10-bit successive approximation method ✕ 1 (4 channels) 12-bit ✕ 1 4 channels Maximum transfer rate 20 Mbytes/sec. (at f(XIN) = 20 MHz, 0 wait, 1-bus cycle transfer) 10 Mbytes/sec. (at f(XIN) = 20 MHz, 0 wait, 2-bus cycles transfer) 1 channel Incorporates 8-bit refresh timer. Supports CAS before RAS refresh method or self refresh method. Chip select area ✕ 4 (CS 0–CS 3). A wait number and bus width can be set for each chip select area. 4 bits ✕ 2 channels; or 6 bits ✕ 1 channel + 2 bits ✕ 1 channel 6 external types, 20 internal types. Each interrupt except NMI can be set to a priority level within the range of 0–7 by software. Built-in (externally connected to a ceramic resonator or quartz crystal resonator). 5 V±0.5 V 125 mW (at f(XIN) = 20 MHz) 5 V 5 mA Up to 16 Mbytes. Note that bank FF16 is a reserved area. –20 to 85 °C CMOS high-performance silicon gate process 100-pin plastic molded QFP

Y Notice: This is not a final specification. Some parametric limits are subject to change. M37920FCCGP, M37920FCCHP M37920FGCGP, M37920FGCHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION MITSUBISHI MICROCOMPUTERS User ROM area Boot ROM area Flash memory parallel I/O mode Flash memory serial I/O mode Flash memory CPU reprogramming mode Flash memory parallel I/O mode Flash memory serial I/O mode Flash memory CPU reprogramming mode Power supply voltage Programming/Erase voltage Flash memory mode Block division for erasure Programming method Erase method Programming/Erase control Data protection method Number of commands Maximum number of reprograms 5 V±0.5 V (in the flash memory parallel I/O mode, 3.3 V±0.3 V) 5 V±0.5 V (in the flash memory parallel I/O mode, 3.3 V±0.3 V) 3 modes: parallel I/O, serial I/O, and CPU reprogramming modes (Note 1) 1 block (16 Kbytes ✕ 1) (Note 2) Programmed per page (in a unit of 256 Kbytes) User ROM area + Boot ROM area User ROM area User ROM area Total erase/Block erase User ROM area + Boot ROM area User ROM area User ROM area Programming/Erase control by software commands Protected per block, by using a lock bit. 8 commands 100 FUNCTIONS (Flash memory mode) FunctionsParameter 2: On shipment, our reprogramming control firmware for the flash memory serial I/O mode has been stored into the boot ROM area. Note that the boot ROM area can be erased/programmed only in the flash memory parallel I/O mode. User ROM area M37920FCCGP , M37920FCCHP 5 blocks (8 Kbytes ✕ 3, 32 Kbytes ✕ 1, 64 Kbytes ✕ 1), total 120 Kbytes M37920FGCGP , M37920FGCHP 7 blocks (8 Kbytes ✕ 3, 32 Kbytes ✕ 1, 64 Kbytes ✕ 3), total 248 Kbytes Notes 1:

M37920FCCGP, M37920FCCHP M37920FGCGP, M37920FGCHPPRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION MITSUBISHI MICROCOMPUTERS Vcc, Vss MD0 MD1 RESET X IN XOUT BYTE AVcc, AVss VREF P00–P07 P10–P17 P20–P27 P30–P33 P40–P44 Power supply input MD0 MD1 Reset input Clock input Clock output External data bus width select input Analog power supply input Reference voltage input I/O port P0 I/O port P1 I/O port P2 I/O port P3 I/O port P4 Input Input Input Input Output Input Input I/O I/O I/O I/O I/O Apply 5 V±0.5 V to Vcc, and 0 V to Vss. This pin controls the processor mode. Connect this pin to V SS for the single-chip mode or memory expansion mode, and VCC for the microprocessor mode. Connect this pin to Vss. The microcomputer is reset when “L” level is applies to this pin. These are input and output pins of the internal clock generating circuit. Connect a ceramic or quartz- crystal resonator between the X IN and XOUT pins. When an external clock is used, the clock source should be connected to the XIN pin, and the XOUT pin should be left open. This pin determines whether the external data bus has an 8-bit width or 16-bit width for the memory expansion mode or microprocessor mode. The width is 16 bits when “L” signal is input, and 8 bits when “H ” signal is input. Power supply input pin for the A-D converter. Connect AVcc to Vcc, and AVss to Vss externally. This is the reference voltage input pin for the A-D converter. I In single-chip mode Port P0 is an 8-bit I/O port. This port has an I/O direction register, and each pin can be programmed for input or output. These pins enter the input mode at reset. I In memory expansion and microprocessor modes Address (A 16–A23) is output. In DRAM space is accessed, Multiplexed address (MA 8–MA 11) is output. I In single-chip mode These pins have the same functions as port P0. I In memory expansion and microprocessor modes The low-order 8 bits of data (D0–D 7) are input/output. I In single-chip mode or when 8-bit external data bus is used with “H ” level applied to pin BYTE in memory expansion or microprocessor mode These pins have the same functions as port P0. I When the 16-bit external data bus is used with “L” level applied to pin BYTE in memory expansion or microprocessor mode The high-order 8 bits of data (D 8–D 15) are input or output. I In single-chip mode These pins have the same functions as port P0. I In memory expansion mode P30 functions as an I/O port pin. According to the register setting, this pin funtions as an output pin of RDY. P31, P32, P33 funtion as output pins of RD, BLW, BHW, respectively. I In microprocessor mode P30 functions as an input pin of RDY; and P31, P32, P33 function as output pins of RD, BLW, BHW, respectively. I In single-chip mode These pins have the same functions as port P0. P42 also funtions as pin TC. I In memory expansion mode P40–P44 function as I/O port pins. According to the register setting, these pins function as output pins or input pins of ALE, φ1, TC, HOLD, HLDA, respectively. I In microprocessor mode P40 and P41 function as outpout pins of ALE, φ1. According to the register setting, these pins also funtion as I/O port pins. P42 funtions as an I/O port pin. Accord- ing to the register setting, this pin also funtions as pin TC. P43 functions as an in- put pin of HOLD, and P44 functions as an output pin of HLDA. PIN DESCRIPTION (MICROCOMPUTER MODE) FunctionsInput/ OutputNamePin

Y Notice: This is not a final specification. Some parametric limits are subject to change. M37920FCCGP, M37920FCCHP M37920FGCGP, M37920FGCHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION MITSUBISHI MICROCOMPUTERS I/O I/O I/O I/O I/O I/O I/O I/O Input FunctionsInput/ OutputNamePin P50–P57 P60–P66 P70–P73 P80–P86 P90–P96 P100–P107 P110–P117 P120–P122 NMI In addition to having the same functions as port P0 in the single-chip mode, these pins also function as I/O pins for timers A0, A2, and output pins for the real-time out- put. In addition to having the same functions as port P0 in the single-chip mode, these pins also function as I/O pins for timers A1, A3, A4, input pins for DMA requests, and output pins for DMA acknowledge signals. In addition to having the same functions as port P0 in the single-chip mode, these pins also function as input pins for the A-D converter. P7 2 and P73 also function as input pins for INT3 and INT4. In addition to having the same functions as port P0 in the single-chip mode, these pins also function as I/O pins for UART0, UART1. I In single-chip mode These pins have the same function as port P0. I In memory expansion or microprocessor mode According to the software setting, P90–P93 also funtion as chip select output pins. While DRAM space is selected, P94–P96 function as output pins for DRAM control signals. Some pins of P91–P93, coressponding to the selected DRAM space, function as pins RAS. I In single-chip mode These pins have the same functions as port P0. I In memory expansion and microprocessor modes Address (A0–A7) is output. I In single-chip mode These pins have the same functions as port P0. I In memory expansion or microprocessor mode Address (A8–A15) is output. While DRAM space is accessed, Multiplexed address (MA 0–MA 7) is output. In addition to having the same functions as port P0 in the single-ship mode, these pins also function as input pins for timers B0–B2. This pin is for a non-maskable interrupt. I/O port P5 I/O port P6 I/O port P7 I/O port P8 I/O port P9 I/O port P10 I/O port P11 I/O port P12 Non-maskable interrupt

M37920FCCGP, M37920FCCHP M37920FGCGP, M37920FGCHPPRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION MITSUBISHI MICROCOMPUTERS BASIC FUNCTION BLOCKS These microcomputers contain the following devices on the single chip: the flash memory, RAM, CPU, bus interface unit, and periph- eral devices such as the interrupt control circuit, timers, serial I/O, A-D converter, I/O ports, clock generating circuit, etc. MEMORY Figures 1 and 2 show the memory maps. The address space is 16 Mbytes from addresses 0 16 to FFFFFF16. The address space is di- vided into 64-Kbyte units called banks. The banks are numbered from 0 16 to FF16. Bank FF16 is a reserved area for the development support tool. Therefore, do not use bank FF16. Internal flash memory and internal RAM are assigned as shown in Figures 1 and 2. Addresses FFC016 to FFFF16 contain the RESET and the interrupt vector addresses, and the interrupt vectors are stored there. For details, refer to the section on interrupts. Assigned to addresses 0 16 to FF16 are peripheral devices such as I/O ports, A-D converter, UART, timers, interrupt control registers, DMA controoler, DRAM controller, etc. For the flash memory in the boot ROM area, refer to the section on the flash memory mode. Fig. 1 Memory map of M37920FCCGP and M37920FCCHP (Single-chip mode) /;/; /;/; /;/; INT4 A-D conversion Reserved area Reserved area Address matching detect Reserved area DMA0 DMA1 DMA2 DMA3 UART1 transmit UART1 receive UART0 transmit UART0 receive Timer B2 Timer B1 Timer B0 Interrupt vector table Timer A4 Timer A3 Timer A2 Timer A1 Timer A0 Watchdog timer BRK instruction Zero divide INT3 INT2 INT1 INT0 NMI RESET DBC 00000016 Bank 016 FFFFFF 16 FE0000 16 00FFFF 16 01000016 01FFFF 16 Bank FE16 00000016 00080016 0000FF16 00FFFE 16 00FFC0 16 Internal RAM 4096 bytes Internal flash memory

120 Kbytes

(User ROM area) Peripheral devices control registers 001FFF 16 00200016 FEFFFF 16 FF000016 0017FF16 00180016 00FFFF 16 00FFC0 16 Bank 116 Bank FF Reserved area for development support tool

Y Notice: This is not a final specification. Some parametric limits are subject to change. M37920FCCGP, M37920FCCHP M37920FGCGP, M37920FGCHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION MITSUBISHI MICROCOMPUTERS Fig. 2 Memory map of M37920FGCGP and M37920FGCHP (Single-chip mode) /;/; /;/; /;/; INT4 A-D conversion Reserved area Reserved area Address matching detect Reserved area DMA0 DMA1 DMA2 DMA3 UART1 transmit UART1 receive UART0 transmit UART0 receive Timer B2 Timer B1 Timer B0 Interrupt vector table Timer A4 Timer A3 Timer A2 Timer A1 Timer A0 Watchdog timer BRK instruction Zero divide INT3 INT2 INT1 INT0 NMI RESET DBC 00000016 Bank 016 FFFFFF 16 FE0000 16 00FFFF 16 01000016 01FFFF 16 Bank FE16 00000016 00080016 0000FF16 00FFFE 16 00FFC0 16 Internal RAM 6144 bytes Internal flash memory

248 Kbytes

(User ROM area) Peripheral devices control registers 001FFF 16 00200016 FEFFFF 16 FF000016 00FFFF 16 00FFC0 16 Bank 116 Bank FF 02000016 02FFFF 16 Bank 216 03000016 03FFFF 16 Bank 316 Reserved area for development support tool

M37920FCCGP, M37920FCCHP M37920FGCGP, M37920FGCHPPRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION MITSUBISHI MICROCOMPUTERS Fig. 4 Location of SFRs (1) 00000016 00000116 00000216 00000316 00000416 00000516 00000616 00000716 00000816 00000916 00000A16 00000B16 00000C 16 00000D 16 00000E16 00000F16 00001016 00001116 00001216 00001316 00001416 00001516 00001616 00001716 00001816 00001916 00001A16 00001B16 00001C 16 00001D 16 00001E16 00001F16 00002016 00002116 00002216 00002316 00002416 00002516 00002616 00002716 00002816 00002916 00002A16 00002B16 00002C 16 00002D 16 00002E16 00002F16 00003016 00003116 00003216 00003316 00003416 00003516 00003616 00003716 00003816 00003916 00003A16 00003B16 00003C 16 00003D 16 00003E16 00003F16 Port P2 register Port P3 register Port P1 direction register Port P0 direction register Port P1 register Port P0 register Port P2 direction register Port P3 direction register Port P4 register Port P5 register Port P4 direction register Port P5 direction register Port P6 register Port P7 register Port P6 direction register Port P7 direction register Port P8 register Port P8 direction register Port P10 register Port P11 register Port P10 direction register Port P11 direction register A-D control register 0 A-D control register 1 A-D register 1 A-D register 2 A-D register 3 UART0 transmit/receive mode register UART0 baud rate register (BRG0) UART0 transmit buffer register UART0 transmit/receive control register 1 UART0 receive buffer register UART1 transmit/receive mode register UART1 baud rate register (BRG1) UART1 transmit buffer register UART1 transmit/receive control register 0 UART1 transmit/receive control register 1 UART1 receive buffer register Address (Hexadecimal notation) 000040 00004116 00004216 00004316 00004416 00004516 00004616 00004716 00004816 00004916 00004A16 00004B16 00004C 16 00004D 16 00004E16 00004F16 00005016 00005116 00005216 00005316 00005416 00005516 00005616 00005716 00005816 00005916 00005A16 00005B16 00005C 16 00005D 16 00005E16 00005F16 00006016 00006116 00006216 00006316 00006416 00006516 00006616 00006716 00006816 00006916 00006A16 00006B16 00006C 16 00006D 16 00006E16 00006F16 00007016 00007116 00007216 00007316 00007416 00007516 00007616 00007716 00007816 00007916 00007A16 00007B16 00007C 16 00007D 16 00007E16 00007F16 Address (Hexadecimal notation) Count start register One-shot start register Timer A clock division select register Timer A0 register Timer A1 register Timer A2 register Timer A3 register Timer A4 register Timer B0 register Timer B1 register Timer B2 register Timer A1 mode register Timer A0 mode register Timer A2 mode register Timer A3 mode register Timer A4 mode register Timer B0 mode register Timer B1 mode register Timer B2 mode register Processor mode register 1 Watchdog timer register Particular function select register 0 Particular function select register 1 Debug control register 0 INT 3 interrupt control register UART0 transmit interrupt control register UART1 receive interrupt control register Timer A0 interrupt control register Timer A1 interrupt control register Timer A3 interrupt control register Timer A4 interrupt control register Timer B0 interrupt control register Timer B2 interrupt control register INT 1 interrupt control register Watchdog timer frequency select register Debug control register 1 INT4 interrupt control register UART1 transmit interrupt control register Timer A2 interrupt control register Timer B1 interrupt control register INT 2 interrupt control register Address comparison register 0 Address comparison register 1 Particular function select register 2 Reserved area (Note) Note: Do not write to this address. UART0 transmit/receive control register 0 Up-down register Processor mode register 0 A-D conversion interrupt control register UART0 receive interrupt control register INT0 interrupt control register Port P9 register Port P9 direction register Port P12 register Port P12 direction register A-D register 0 Reserved area (Note) Reserved area (Note)

Y Notice: This is not a final specification. Some parametric limits are subject to change. M37920FCCGP, M37920FCCHP M37920FGCGP, M37920FGCHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION MITSUBISHI MICROCOMPUTERS Fig. 5 Location of SFRs (2) 0000C0 16 0000C1 16 0000C2 16 0000C3 16 0000C4 16 0000C5 16 0000C6 16 0000C7 16 0000C8 16 0000C9 16 0000CA 16 0000CB 16 0000CC 16 0000CD 16 0000CE 16 0000CF 16 0000D0 16 0000D1 16 0000D2 16 0000D3 16 0000D4 16 0000D5 16 0000D6 16 0000D7 16 0000D8 16 0000D9 16 0000DA 16 0000DB 16 0000DC 16 0000DD 16 0000DE 16 0000DF 16 0000E016 0000E116 0000E216 0000E316 0000E416 0000E516 0000E616 0000E716 0000E816 0000E916 0000EA 16 0000EB 16 0000EC 16 0000ED 16 0000EE 16 0000EF 16 0000F016 0000F116 0000F216 0000F316 0000F416 0000F516 0000F616 0000F716 0000F816 0000F916 0000FA 16 0000FB 16 0000FC 16 0000FD 16 0000FE 16 0000FF16 0000A016 0000A116 0000A216 0000A316 0000A416 0000A516 0000A616 0000A716 0000A816 0000A916 0000AA 16 0000AB 16 0000AC 16 0000AD 16 0000AE 16 0000AF 16 0000B016 0000B116 0000B216 0000B316 0000B416 0000B516 0000B616 0000B716 0000B816 0000B916 0000BA 16 0000BB 16 0000BC 16 0000BD 16 0000BE 16 0000BF 16 Real-time output control register Pulse output data register 0 Pulse output data register 1 Reserved area (Note) CTS/RTS separate select register 000080 00008116 00008216 00008316 00008416 00008516 00008616 00008716 00008816 00008916 00008A16 00008B16 00008C 16 00008D 16 00008E16 00008F16 00009016 00009116 00009216 00009316 00009416 00009516 00009616 00009716 00009816 00009916 00009A16 00009B16 00009C 16 00009D 16 00009E16 00009F16 Address (Hexadecimal notation) CS 0 control register L CS 0 control register H CS 1 control register L CS 1 control register H CS 2 control register L CS 2 control register H CS 3 control register L CS 3 control register H Area CS 0 start address register Area CS 1 start address register Area CS 2 start address register Area CS 3 start address register Reserved area (Note) Reserved area (Note) Flash memory control register Note: Do not write to this address. Reserved area (Note) Reserved area (Note) Reserved area (Note) Reserved area (Note) Address (Hexadecimal notation) DRAM control register Refresh timer DMAC control register L DMAC control register H DMA0 interruput control register DMA1 interruput control register DMA2 interruput control register DMA3 interruput control register Source address register 0 L Source address register 0 M Source address register 0 H Destination address register 0 L Destination address register 0 M Destination address register 0 H Transfer counter register 0 L Transfer counter register 0 M Transfer counter register 0 H DMA0 mode register L DMA0 mode register H DMA0 control register Source address register 1 L Source address register 1 M Source address register 1 H Destination address register 1 L Destination address register 1 M Destination address register 1 H Transfer counter register 1 L Transfer counter register 1 M Transfer counter register 1 H DMA1 mode register L DMA1 mode register H DMA1 control register Source address register 2 L Source address register 2 M Source address register 2 H Destination address register 2 L Destination address register 2 M Destination address register 2 H Transfer counter register 2 L Transfer counter register 2 M Transfer counter register 2 H DMA 2 mode register L DMA 2 mode register H DMA 2 control register Source address register 3 L Source address register 3 M Source address register 3 H Destination address register 3 L Destination address register 3 M Destination address register 3 H Transfer counter register 3 L Transfer counter register 3 M Transfer counter register 3 H DMA 3 mode register L DMA 3 mode register H DMA 3 control register

M37920FCCGP, M37920FCCHP M37920FGCGP, M37920FGCHP MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. CENTRAL PROCESSING UNIT (CPU) The CPU has 13 registers, and they are shown in Figure 6. Each of these registers is described below. ACCUMULATOR A (A) Accumulator A is the main register of the microcomputer. It consists of 16 bits and the low-order 8 bits can be used separately. Data length flag m determines whether the register is used as 16-bit reg- ister or as 8-bit register. It is used as a 16-bit register when flag m is “0” and as an 8-bit register when flag m is “1”. Flag m is a part of the processor status register (PS) which is described later. Data operations such as calculations, data transfer, input/output, etc., are executed mainly through accumulator A. ACCUMULATOR B (B) Accumulator B has the same functions as accumulator A, but the use of accumulator B requires more instruction bytes and execution cycles than accumulator A. ACCUMULATOR E Accumulator E is a 32-bit register and consists of accumulator A (low-order 16 bits) and accumulator B (high-order 16 bits). It is used for 32-bit data processing. INDEX REGISTER X (X) Index register X consists of 16 bits and the low-order 8 bits can be used separately. Index register length flag x determines whether the register is used as 16-bit register or as 8-bit register. It is used as a 16-bit register when flag x is “0” and as an 8-bit register when flag x is “1”. Flag x is a part of the processor status register (PS) which is described later. In index addressing modes in which register X is used as the index register, the contents of this address are added to obtain the real ad- dress. Index register X functions as a pointer register which indicates an address of data table in instructions MVP , MVN, RMPA (Repeat MultiPly and Accumulate). INDEX REGISTER Y (Y) Index register Y consists of 16 bits and the low-order 8 bits can be used separately. The index register length flag x determines whether the register is used as 16-bit register or as 8-bit register. It is used as a 16-bit register when flag x is “0” and as an 8-bit register when flag x is “1”. Flag x is a part of the processor status register (PS) which is described later. In index addressing modes in which register Y is used as the index register, the contents of this address are added to obtain the real ad- dress. Index register Y functions as a pointer register which indicates an address of data table in instructions MVP , MVN, RMPA (Repeat MultiPly and Accumulate). 1 570 1 570 15 7 0 1 570 15 0 15 0 15 0 15 7 0 00000 IPL2 IPL1 IPL0 NVmxD I ZC DPR0 to DPR3 PC S YH YL XH XL BH BL AH AL Accumulator AAccumulator B Index register X Index register Y Stack pointer S Program counter PC Direct page registers DPR0 to DPR3 Processor status register PS Carry flag Zero flag Interrupt disable flag Decimal mode flag Index register length flag Data length flag Overflow flag Negative flag Processor interrupt priority level IPL PG Program bank register PG Data bank register DTDT 15 7 0 15 7 0 AH ALBH BL Accumulator E 31 0 Fig. 6 Register structure

M37920FCCGP, M37920FCCHP M37920FGCGP , M37920FGCHP MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. STACK POINTER (S) Stack pointer (S) is a 16-bit register. It is used during a subroutine call or interrupts. It is also used during stack, stack pointer relative, or stack pointer relative indirect indexed Y addressing mode. PROGRAM COUNTER (PC) Program counter (PC) is a 16-bit counter that indicates the low-order 16 bits of the next program memory address to be executed. There is a bus interface unit between the program memory and the CPU, so that the program memory is accessed through bus interface unit. This is described later. PROGRAM BANK REGISTER (PG) Program bank register is an 8-bit register that indicates the high-or- der 8 bits of the next program memory address to be executed. When a carry occurs by incrementing the contents of the program counter, the contents of the program bank register (PG) is increased by 1. Also, when a carry or borrow occurs after adding or subtracting the offset value to or from the contents of the program counter (PC) using the branch instruction, the contents of the program bank regis- ter (PG) is increased or decreased by 1, so that programs can be written without worrying about bank boundaries. DATA BANK REGISTER (DT) Data bank register (DT) is an 8-bit register. With some addressing modes, the data bank register (DT) is used to specify a part of the memory address. The contents of data bank register (DT) is used as the high-order 8 bits of a 24-bit address. Addressing modes that use the data bank register (DT) are direct indirect, direct indexed X indi- rect, direct indirect indexed Y , absolute, absolute bit, absolute in- dexed X, absolute indexed Y, absolute bit relative, and stack pointer relative indirect indexed Y. DIRECT PAGE REGISTERS 0 to 3 (DPR0 to DPR3) The direct page register is a 16-bit register. An addressing mode of which name includes ‘direct’ generates an address of data to be ac- cessed, regarding the contents of this register as the base address. The 7900 Series has been expanded direct page registers up to 4 (DPR0 to DPR3), in comparison to the 7700 Series which has the single direct page register. Accordingly, the 7900 Series’s direct ad- dressing method which uses direct page registers differs from that of the 7700 Series. However, the conventional direct addressing method, using only DPR0, is still be selectable, in order to make use of the 7700 Series software property. For more details, refer to the section on the direct page. PROCESSOR STATUS REGISTER (PS) Processor status register (PS) is an 11-bit register. It consists of flags to indicate the result of operation and CPU interrupt levels. Branch operations can be performed by testing the flags C, Z, V, and The details of each bit of the processor status register are described below. 1. Carry flag (C) The carry flag contains the carry or borrow generated by the ALU af- ter an arithmetic operation. This flag is also affected by shift and ro- tate instructions. This flag can be set and reset directly with the SEC and CLC instructions or with the SEP and CLP instructions. 2. Zero flag (Z) The zero flag is set if the result of an arithmetic operation or data transfer is zero and reset if it is not. This flag can be set and reset directly with the SEP and CLP instructions. 3. Interrupt disable flag (I) When the interrupt disable flag is set to “1”, all interrupts except ___ watchdog timer, NMI, and software interrupt are disabled. This flag is set to “1” automatically when an interrupt is accepted. It can be set and reset directly with the SEI and CLI instructions or SEP and CLP instructions. 4. Decimal mode flag (D) The decimal mode flag determines whether addition and subtraction are performed as binary or decimal. Binary arithmetic is performed when this flag is “0”. If it is “1”, decimal arithmetic is performed with each word treated as 2- or 4- digit decimal. Arithmetic operation is performed using four digits when data length flag m is “0” and with two digits when it is “1”. Decimal adjust is automatically performed. (Decimal operation is possible only with the ADC and SBC instruc- tions.) This flag can be set and reset with the SEP and CLP instruc- tions.

M37920FCCGP, M37920FCCHP M37920FGCGP , M37920FGCHP MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. BANK In order to effectively use the integrated hardware on the chip, this CPU core uses an address generating method with a 24-bit address split into high-order 8 bits and low-order 16 bits. In other words, the

64 Kbytes specified by the low-order 16 bits are one unit (referred to

as “bank”), and the address space is divided into 256 banks (0 16 to FF16) specified by the high-order 8 bits. In the program area on the address space, the bank is specified by the program bank register (PG), and the address in the bank is specified by the program counter (PC). As for each bank boundary, when an overflow has occurred in PC, the contents of PG are incremented by 1. When a borrow has oc- curred in PC, the contents of PG are decremented by 1. Under the normal conditions, therefore, programming without concern for the bank boundaries is possible. Furthermore, as for the data area on the address space, the bank is specified by the data bank register (DT), and the address in the bank is specified by the operation result by using the various addressing modes (Note). Note: Some addressing modes directly specify a bank. DIRECT PAGE The internal memory and control registers for internal peripheral de- vices, etc. are assigned to bank 016 (addresses 016 to FFFF16). The direct page and direct addressing modes have been provided for the effective access to bank 016. In the 7900 Series, two types of direct addressing modes are available: the conventional direct addressing mode which uses only DPR0, as in the 7700 Series, and the ex- panded direct addressing mode, which uses up to 4 direct page reg- isters as selected by the user. The addressing mode is selected according to the contents of bit 1 of the processor mode register 1. This bit 1 is cleared to “0” at reset. (In other words, the conventional direct addressing mode is selected.) However, once this bit 1 has been set to “1” by software, this bit cannot be cleared to “0” again, except by reset. That is to say, when one of these two direct address- ing modes has been selected just after reset, the selected address- ing mode cannot be switched to another one while the program is running. I Conventional direct addressing mode The direct page area consists of 256-byte space. Its bank address is “00 16”, and the base address of its low-order 16-bit address is speci- fied by the contents of the direct page register 0 (DPR0). In this con- ventional direct addressing modes, a value (1 byte) just after an instruction code is regarded as an offset value for the DPR0 con- tents, and the CPU accesses each address in the direct page area. I Expanded direct addressing mode The direct page area consists of four 64-byte spaces. Their bank address is “00 16”, and the four base addresses of their low-order 16- bit addresses are respectively specified by the contents of four direct page registers. In this expanded direct addressing mode, a value (1 byte) just after an instruction code is regarded as follows:

High-order 2 bits: regarded as a selection field for DPR0 to DPR3.
Low-order 6 bits: regarded as an offset value for the selected direct page register. Then, the CPU accesses each address in each direct page area: Refer to “7900 Series Software Manual” for details concerning the various addressing modes which use the direct page area. Instruction Set The CPU core of the 7900 Series has an expanded instruction set based on the existing 7700/7751 Series’ CPU core. In addition, its source code (mnemonic) has the complete upper compatibility with the 7700 Series instruction set. For details concerning addressing modes and instruction set, refer to “7900 Series Software Manual”.

M37920FCCGP, M37920FCCHP M37920FGCGP, M37920FGCHP MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. BUS INTERFACE UNIT Data transfer shown below is always performed via the bus interface unit (BIU), which is located between the CPU and the internal buses:

Between the CPU and the internal memory, internal peripheral de- vices, external areas
Between the DMA controller (DMAC) and the internal memory, in- ternal peripheral devices, external areas Figure 7 shows the BIU and the bus structure. The CPU and BIU, or DMAC and BIU are connected by a dedicated bus respectivery, and any transfer between the CPU and BIU, or DMAC and BIU is con- trolled by this dedicated bus. On the other hand, data transfer between the BIU and internal pe- ripheral devices uses the following internal common buses: 32-bit code bus, 16-bit data bus, 24-bit address bus, and control signals. The bus control method where the code bus and the data bus sepa- rate out (hereafter, this method is referred to as the separate code/ data bus method) is employed in order to improve data transfer ca- Fig. 7 BIU and bus structure Internal code bus (CB0 to CB31) Central Processing Unit (CPU) SFR : Special Function Register ❈ The CPU bus, DMAC bus, internal bus, and external bus separate out independently. External devices Internal control signal CPU bus Internal bus Internal data bus (DB0 to DB15) Internal memory Internal peripheral devices (SFR) External bus A0 to A23 (MA0 to MA11) D 0 to D7 D 8 to D15 Control signal Bus Interface Unit (BIU) Bus conversion circuit Internal address bus (AD0 to AD23) DMA controller (DMAC) DMAC bus Refresh request DRAM control signalDRAM controller (DRAMC) HOLD Hold request HLDA pabilities. As a result, the internal memory is connected to both the code bus and the data bus, and registers of all other internal periph- eral devices are connected only to the data bus. Each width of external buses are as follows: a 24-bit address bus, 16-bit data bus. The external data bus transfers instruction codes and data. When the code or data access occurs for the external, the external access is performed via the bus conversion circuit. When the DRAM is selected in external devices, the internal DMAC controller (DRAMC) is operated, and access for DRAM and DRAM refresh operation become enabled. For details, refer to the section on the chip select wait controller and DRAMC described later. When accessing the external devices, it is possible to insert the re- covery cycles. Refer to the section on the processor modes and chip select wait controller described later. When the burst ROM is used as an external device, refer to the sec- tion on the chip select wait controller described later.

Notice: This is not a final specification. Some parametric limits are subject to change. Table 1. Functions of each register Indicates a storage address for an instruction to be next taken into an instruction queue buffer. Temporarily stores an instruction which has been taken from a memory. Consists of 10 bytes. Indicates an address where data will be next read from or written to. peripheral devices, and external areas by the CPU or DMAC. Consists of 32 bits.

Notice: This is not a final specification. Some parametric limits are subject to change. the branch destination address. for instructions to be prefetched are categorized as listed in Table 2. passes it to the data buffer, and then, transfers it to the CPU. then, writes it into the specified address.

Whether the address area locates in the internal area or the ex- ternal area.
When the address area locates in the external area ➀ Whether the bus width of external devices = 16 bits or 8 bits: (a) When the external bus width = 16 bits: whether the start address for access locates at a 4- byte boundary or at an 8-byte boundary. (b) When the external bus width = 8 bits: whether the start address for access locates at an even-numbered address, a 4-byte boundary or at the 8- byte bound ary. ➁ Whether the prefetch operation is generated by a branch, or not. ➂ Number of waits ➃ Others: Whether any the burst ROM access and the DRAM space is specified or not. (For details, refer to the section on the chip select wait controller and DRAM controller described later.)

Table 2. Store addresses for instructions to be prefetched

Whether the address area locates in the internal area or the ex- ternal area.
Length of data to be transferred: byte, word, double word
When the address area locates in the external area: ➀ Whether the bus width of external devices = 16 bits or 8 bits: ➁ Number of waits ➂ Others: Whether the DRAM space is specified or not. (For details, refer to the section on the chip select wait controller and DRAM controller described later.) The BIU controls the bus cycle depending on the above conditions. Instruction prefetch and data access are performed as shown in Tables 3 to 10. X: 0 or 1

Notice: This is not a final specification. Some parametric limits are subject to change. Table 3. Instruction prefetch

Notice: This is not a final specification. Some parametric limits are subject to change. Table 4. Data access (1)

Notice: This is not a final specification. Some parametric limits are subject to change. Table 5. Data access (2)

Notice: This is not a final specification. Some parametric limits are subject to change. Table 6. Data access (3) Note: When the voltage level at pin BYTE = “L”, functions as pins D15 to D8 are valid. 15 to D8 and BHW become invalid.

Notice: This is not a final specification. Some parametric limits are subject to change. Table 7. Data access (4) the voltage level at pin BYTE = “H ”, these pins function as programmable I/O port (P2) pins.

Notice: This is not a final specification. Some parametric limits are subject to change. Table 8. Wait number (Instruction prefetch or data access)

M37920FCCGP, M37920FCCHP M37920FGCGP , M37920FGCHP MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. Fig. 9 Recovery cycle (at instruction prefetch) At double consecutive access (when address locates at 4-byte boundary or when branched) A23 to A0 ALE RD Address At quadruple consecutive access (when address locates at 8-byte boundary) A23 to A0 ALE RD Address + 2 Address Instruction prefetch Recovery cycle Next access cycle AddressAddress Address + 4 Address + 6 Address + 2 Instruction prefetch Next access cycle Note: External data bus width = 16 bits and at 0 wait. Fig. 10 Recovery cycle (at data access) A23 to A0 ALE RD, Address Access cycle Recovery cycle Next access cycle BLW, BHW Note: At 0 wait.

M37920FCCGP, M37920FCCHP M37920FGCGP, M37920FGCHPPRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION MITSUBISHI MICROCOMPUTERS Selection of processor mode Figures 11, 12 show the bit configurations of the processor mode registers 0, 1. Any of the three processor modes (single-chip mode, memory ex- pansion mode, microprocessor mode) can be selected with the fol- lowing:

Processor mode bits of the processor mode register 0 (bits 1 and 0 at address 5E 16; Figure 11) Table 9 lists the selection method of a processor mode. The memory map which the CPU can access depends on the se- lected processor mode. Figure 13 shows the memory maps in three processor modes. Also, the functions of ports P0 to P4, P10, P11, and part of port P9 depend on the selected processor mode. For details, see Table 10. In the single-chip mode, ports P0 to P4, P10, P11, and P9 function as I/O ports. In this mode, only the internal area (SFRs, internal RAM, internal ROM) is accessible. In the memory expansion and microprocessor modes, external de- vices assigned in the external memory area can be connected via buses. Therefore, ports P0 to P4, P10, P11, and part of port P9 func- tion as I/O pins for the address bus, data bus, bus control signals. (Some of port functions are selectable.) In the memory expansion mode, all of the internal area (SFRs, inter- nal RAM, internal ROM) and external area are accessible. In the mi- croprocessor mode, the internal area except for the internal ROM (in other words, SFRs and internal RAM) and the external area are ac- cessible. Note that, when the external devices are located to an area where the internal area and external area overlap, only the internal area can be read/written; the external area cannot be read/written. Table 11 lists each bus control signal’s function. Fig. 11 Bit configuration of processor mode register 0 76543210 Processor mode register 0 Processor mode bits 0 0 : Single-chip mode 0 1 : Memory expansion mode 1 0 : Microprocessor mode 1 1 : Do not select. Interrupt priority detection time select bits 0 0 : 7 cycles of φ 0 1 : 4 cycles of φ 1 0 : 2 cycles of φ 1 1 : Do not select. Software reset bit By a write of “1” to this bit, the microcomputer will be reset, and then, restarted. External bus wait number select bits 0 0 : 0 wait 0 1 : 1 wait 1 0 : 2 wait 1 1 : ALE expansion wait Clock φ 1 output select bit 0 : φ1 output is disabled. (P41 functions as an programmable I/O port pin.) 1 : φ1 output is enabled. (P41 functions as the clock φ1 output pin.) Address 5E16

Notice: This is not a final specification. Note: Do not access this area. 0 : No recovery cycle is inserted at access to the external area. 1 : Recovery cycle is inserted at access to the external area. 0 : HOLD input and HLDA output are disabled. 1 : HOLD input and HLDA output are enabled. Notes 1: After reset, this bit’s contents can be switched only once. During the software execution, be sure not to switch this bit’s contents. 2: In the single-chip mode, these bits’ functions are disabled regardless of these bits’ contents. on the other hand, each of these bits is “1” at reset. 4: In the memory expansion or microprocessor mode, if this bit’s contents is switched from “1” to “0”, this bit will be cleared to “0”. After this clearance, this bit cannot return to “1”. If it is necessary to set this bit to “1”, be sure to reset the microcomputer. 5: In the microprocessor mode, this bit is invalid. When the internal flash memory is reprogrammed in the CPU reprogramming mode, be sure to clear this bit to “0”. single-chip mode is selected.

Single-chip mode
Memory expansion mode
Microprocessor mode

Table 9. Selection method of processor mode

Microprocessor mode

Notice: This is not a final specification. Middle-order address (A8 to A15) is output. High-order address (A16 to A23) is output. numbered address) is input/output. odd-numbered address) is input/output. numbered address) is input/output. numbered address) is output. Low-order address (A0 to A7) is output. Middle-order address (A8 to A15) is output. High-order address (A16 to A23) is output. numbered address) is input/output. odd-numbered address) is input/output. bered address) is input/output. Ready signal RDY is input (Note 5). Table 10. Relationship between processor modes, memory area, and port function Notes 1: For details of the processor mode setting, see Table 9. 2: Processor mode bits = bits 1 and 0 of the processor mode register 0 (address 5E16). 3: While DRAM space is accessed, the multiplexed address is output. P43 can operate as pins for RDY input, ALE output, φ1 output, HLDA output, HOLD input, respectively. 5: In the memory expansion mode, port pin P90 can operate as the CS0 output pin by the CS0 output select bit of the CS0 control register L (bit 7 at address 8016). Clock φ1 is output (Note 4). Address latch enable signal ALE is output (Note 4). Clock φ1 is output (Note 4). Hold acknowledge signa HLDA is output (Note 4). Hold request signal HOLD is input (Note 4). Chip select signal CS0 is output (Note 5). Chip select signals CS1 to CS3 are output (Note 6). Address latch enable signal ALE is output. Hold acknowledge signal HLDA is output. Hold request signal HOLD is input. Chip select signal CS0 is output. Chip select signals CS1 to CS3 are output (Note 6).

Notice: This is not a final specification. Table 11. Each bus control signal’s function Read signal. Outputs “L” at read from the external area. Write signal. Outputs “L” at write to the external area. period just before signals RD, BLW, BHW become “L”. This is used to latch an address in the external. voltage is applied to this pin. quest to terminate the hold state. Hold acknowledge signal. Outputs “L” in the hold state. when Vcc, 8-bit width will be selected. pending on the external data bus width, see Table 5.

While ALE = “H ”, be sure to open a latch, so the address will pass it.
While ALE = “L”, be sure to hold the address. Acceptance and termination of a hold request is performed at completion of the bus cycle while the BIU operates. In the hold state, A 0–A23, D0–D 15, RD, BLW, BHW, ALE, CS 0–CS 3 enter the floating state. At termination of the hold state, simultaneously with the timing when HLDA becomes “H ” level, the above floating state is terminated. Then, bus access will be restarted 1 cycle of φ1 after. In the hold state, also, the CPU operates with access to the internal area. If the CPU accesses the external area, in the hold state, the CPU stops its operation. For details, refer to the section on the chip select wait con- troller. When BYTE = Vss level, by the register setting, each chip select area (CS 1 to CS3) can have the 8-bit data bus, inde- pendently. For details, refer to the section on the chip select wait con- troller.

Notice: This is not a final specification.

128 Kbytes,

256 Kbytes,

512 Kbytes,

1 Mbytes,

2 Mbytes,

4 Mbytes,

Determined by pin BYTE’s level.

4 Kbytes

Table 12. Function of areas CS0 to CS3 Notes 1: Burst ROM access is valid only when the external data bus width is 16 bits at instruction prefetch. 2: When BYTE = Vcc level, the external data bus width is fixed to 8 bits. be selected arbitrary (Note 2).

M37920FCCGP, M37920FCCHP M37920FGCGP, M37920FGCHPPRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION MITSUBISHI MICROCOMPUTERS 76543210 CS 0 control register L External data bus width select bit 0 : 16-bit width 1 : 8-bit width RDY control bit (Note 2) 0 : RDY control is valid. 1 : RDY control is invalid. Area CS 0 wait number select bits 0 0 : 0 wait 0 1 : 1 wait 1 0 : 2 wait 1 1 : ALE expansion wait (Note 1) Address Burst ROM access select bit (Note 3) 0 : Normal access 1 : Burst ROM access Recovery cycle insert select bit 0 : No recovery cycle is inserted at access to area CS0. 1 : Recovery cycle is inserted at access to area CS0. CS 0 output select bit 0 : CS0 output is disabled. (P90 functions as a programmble I/O port pin.) 1 : CS0 output is enabled. (P90 functions as pin CS0.) Notes 1: When the burst ROM access is specified (bit 5= 1), be sure not to select “112” (ALE expansion wait). 2: This bit is valid when the RDY input select bit (bit 2 at address 5F16) = “1”. 3: While VCC level voltage is applied to pin BYTE, the normal access is selected regardless of this bit’s contents.

76543210 CS 1 control register L

External data bus width select bit 0 : 16-bit width 1 : 8-bit width (Note 2) RDY control bit (Note 3) 0 : RDY control is valid. 1 : RDY control is invalid. Area CS j wait number select bits (j = 1 to 3) 0 0 : 0 wait 0 1 : 1 wait 1 0 : 2 wait 1 1 : ALE expansion wait (Note 1) DRAM space select bit 0 : Except DRAM space 1 : DRAM space Address 8416 8616 Burst ROM access select bit (Note 4) 0 : Normal access 1 : Burst ROM access Recovery cycle insert select bit (Note 5) 0 : No recovery cycle is inserted at access to area CSj. 1 : Recovery cycle is inserted at access to area CSj. CS j output select bit (j = 1 to 3) 0 : CSj output is disabled. (P9j functions as programmable I/O port pins.) 1 : CSj output is enabled. (P9j functions as pin CSj.) Notes 1: When the DRAM space is specified (bit 4 = 1), fix these bits to “012” (1 wait). Also, when the burst ROM access is specified (bit 5 = 1), be sure not to select “112” (ALE expansion wait). 2: While VCC level voltage is applied to pin BYTE, this bit is fixed to “1” (8-bit width). 3: This bit is valid when the RDY input select bit (bit 2 at address 5F16) = “1”. Also, when DRAM space is specified (bit 4 = 1), the RDY control is invalid regardless of this bit’s contets. 4: When only the external data bus width select bit (bit 2) = “1” or while VCC level voltage is applied to pin BYTE, the normal access is selected regardless of this bit’s contents. 5: When the DRAM space is specified (bit 4 = 1), fix this bit to “0” (no recovery cycle). “0” at read. Fig. 15 Bit configuration of CS0/CS1/CS2/CS3 control register Ls

M37920FCCGP, M37920FCCHP M37920FGCGP, M37920FGCHPPRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION MITSUBISHI MICROCOMPUTERS Fig. 16 Bit configuration of CS0/CS1/CS2/CS3 control register Hs 76543210 CS 0 control register H Area CS0 block size select bit 0 0 0 : 0 byte (Area CS0 is invalid.) 0 0 1 : 128 Kbytes 0 1 0 : Do not select. 0 1 1 : 512 Kbytes 1 0 0 : 1 Mbytes 1 0 1 : Do not select. 1 1 0 : Do not select. 1 1 1 : Do not select. Address 76543210 CS 1 control register H CS 2 control register H Area CSk block size select bit (k = 1, 2) Address 8316 8516 When mode 0 is selected 0 0 0 : 0 byte (Area CSk is invalid.) 0 0 1 : 128 Kbytes 0 1 0 : 256 Kbytes 0 1 1 : 512 Kbytes 1 0 0 : 1 Mbytes 1 0 1 : 2 Mbytes 1 1 0 : 4 Mbytes 1 1 1 : 8 Mbytes When mode 1 is selected 0 0 0 : 0 byte (Area CS k is invalid.) 0 0 1 : Do not select. 0 1 0 : Do not select. 0 1 1 : Do not select. 1 0 0 : 4 Kbytes 1 0 1 : 8 Kbytes 1 1 0 : Do not select. 1 1 1 : Do not select. 76543210 CS 3 control register H Area CS3 block size select bit 0 0 0 : 0 byte (Area CS3 is invalid.) 0 0 1 : 128 Kbytes 0 1 0 : 256 Kbytes 0 1 1 : 512 Kbytes 1 0 0 : 1 Mbytes 1 0 1 : 2 Mbytes 1 1 0 : 4 Mbytes 1 1 1 : 8 Mbytes Address Area CSk setting mode select bit (k = 1, 2) 0 : Mode 0 (A block can be set to 16-Mbyte space in a unit of 128 Kbytes.) 1 : Mode 1 (A block can be set to bank 0 in a unit of 4 Kbytes.) “0” at read. “0” at read. “0” at read.

M37920FCCGP, M37920FCCHP M37920FGCGP, M37920FGCHPPRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION MITSUBISHI MICROCOMPUTERS Area CS0 start address register These bits determine A8 to A15 of the area CS0 start address. Any of the following values can be set to these bits: “1016”, “2016”, “4016”, and “8016”. (Bits 0 to 3 are always “0” at read.) Address 8A16 Area CS1 start address register Area CS2 start address register When mode 0 is selected, these bits determine A16 to A23 of the area CS1/CS2 start address. When mode 1 is selected, these bits determine A8 to A15 of the area CS1/CS2 start address. (Bit 0 is always “0” at read.) Address 8C 16 8E16 Area CS3 start address register These bits determine A16 to A23 of the area CS3 start address. (Bit 0 is always “0” at read.) Address 9016 Note: Do not set a value other than “1016”, “2016”, “4016”, and “8016”. See Figure 18. Note: The start address setting depends on the block size, which has been selected by the area CS1/CS2 block size select bits (bits 0 to 2 at address 8316, bits 0 to 2 at address 8516). See Figures 19 and 20. Note: The start address setting depends on the block size, which has been selected by the area CS3 block size select bits (bits 0 to 2 at address 8716). See Figure 20. 76543210 “0” at read. 76543210 “0” at read. 76543210 “0” at read. Fig. 17 Bit configuration of area CS0/CS1/CS2/CS3 start address registers

128 Kbytes

512 Kbytes

1 Mbytes

Start address : 1000 Value to be set to area CS 0 start address register = “10 Block size Start address : 2000 Value to be set to area CS 0 start address register = “20 Block size Start address : 4000 Value to be set to area CS 0 start address register = “40 Block size Start address : 8000 Value to be set to area CS 0 start address register = “80 Block size : Area CS 0 cannot be assigned here. Note: When an area where area CS 0 and the internal area overlap is accessed, the internal area will be accessed. In this case, pin CS 0 outputs “H” level. 1000 1FFFF 7FFFF FFFFF 2000 4000 8000

M37920FCCGP, M37920FCCHP M37920FGCGP, M37920FGCHPPRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION MITSUBISHI MICROCOMPUTERS Fig. 19 Area CS1/CS2 (mode 1) 016 100016 200016 ( FFFF16) Block size : 4 Kbytes Addresses which can be start address (Address FFFF 16 is not included; Note 1) 300016 400016 500016 600016 700016 800016 016 200016 (FFFF16) Block size : 8 Kbytes Addresses which can be start address (Address FFFF 16 is not included; Note 1) 400016 600016

8 Kbytes

Notes 1: Only A8 to A15 of one of these addresses can be set to the area CS1/CS2 start address register. Do not set another address not shown here. 2: When an area where area CS 1/CS2 and the internal area overlap is accessed, the internal area will be accessed. In this case, pin CS 1/CS2 outputs “H ” level.

M37920FCCGP, M37920FCCHP M37920FGCGP, M37920FGCHPPRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION MITSUBISHI MICROCOMPUTERS Fig. 20 Area CS1/CS2 (mode 0) and area CS3 Notes 1: Only A to A of one of these addresses can be set to the area CS 1/CS 2/CS 3 start address register. Do not set another address not shown here. When an area where area CS 1/CS 2/CS 3 and the internal area overlap is accessed, the internal area will be accessed. In this case, pin CS 1/CS 2/CS 3 outputs “H” level. /;/;/; Block size : 128 Kbytes Addresses which can be start address(Addresses 0 and FF0000 to FFFFFF are not included; Note 1 : Area CS 1/CS 2/CS 3 cannot be assigned here. 20000 40000 60000 80000 A0000 C0000 E0000 100000 F60000 F80000 FA0000 FC0000 FE0000 ( FF0000 ( FFFFFF 120000 /;/;/; Block size : 256 Kbytes Addresses which can be start address(Addresses 0 and FF0000 to FFFFFF are not included; Note 1 40000 80000 C0000 100000 F80000 FC0000 ( FF0000 ( FFFFFF /;/;/; Block size : 512 Kbytes Addresses which can be start address(Addresses 0 and FF0000 to FFFFFF are not included; Note 1 80000 100000 F80000 ( FF0000 ( FFFFFF /;/;/; Block size : 1 Mbytes Addresses which can be start address(Addresses 0 and FF0000 to FFFFFF are not included; Note 1 100000 200000 300000 400000 500000 600000 700000 800000 B00000 C00000 D00000 E00000 F00000 ( FF0000 ( FFFFFF 900000 A00000 /;/;/; Block size : 2 Mbytes Addresses which can be start address(Addresses 0 and FF0000 to FFFFFF are not included; Note 1 200000 400000 600000 800000 C00000 E00000 ( FF0000 ( FFFFFF A00000 /;/;/; Block size : 4 Mbytes Addresses which can be start address(Addresses 0 and FF0000 to FFFFFF are not included; Note 1 400000 800000 C00000 ( FF0000 ( FFFFFF /;/;/;Block size : 8 Mbytes Addresses which can be start address(Addresses 0 and FF0000 to FFFFFF are not included; Note 1 800000 ( FF0000 ( FFFFFF : Reserved area. Do not access this area.

M37920FCCGP, M37920FCCHP M37920FGCGP, M37920FGCHPPRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION MITSUBISHI MICROCOMPUTERS Fig. 21 Operating waveform example at burst ROM access Note: The above is applied when 0 wait is selected. (b) External address bus RD External data bus Data (instruction) External data bus Data (instruction) Data (instruction) Data (instruction) Address Address (a) External address bus (A0 to A23) RD External data bus (D0 to D7) Data (instruction) External data bus Data (instruction) Data (instruction) Data (instruction) Address Address Address Address Data (instruction) Data (instruction) Data (instruction) Data (instruction) (D8 to D15) (A0 to A23) (D0 to D7) (D8 to D15)

M37920FCCGP, M37920FCCHP M37920FGCGP, M37920FGCHP MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. INTERRUPTS Table 13 shows the interrupt sources and the corresponding inter- rupt vector addresses. Reset is also described as a type of interrupt in this section, too. DBC and BRK instruction are interrupts used only for debugging. Therefore, do not use these interrupts. Interrupts other than reset, watchdog timer, zero divide, NMI, and address matching detection all have interrupt control registers. Table 14 shows the addresses of the interrupt control registers, and Figure 22 shows the bit configuration of the interrupt control register. The interrupt request bit is automatically cleared by the hardware during reset or when processing an interrupt. Also, interrupt request bits other than watchdog timer and NMI can be cleared by software. Any of INT 2 through INT0 interrupt requests is generated by an ex- ternal input. INT 2 to INT0 are external interrupts; whether to cause an interrupt at the input level (level sense) or at the edge (edge sense) can be se- lected with the level/edge select bit. Furthermore, the polarity of the interrupt input can be selected with the polarity select bit. Timer and UART interrupts are described in the respective section. The priorities of interrupts when multiple interrupt requests are caused simultaneously are partially fixed by hardware, but, the other can be adjusted by software as shown in Figure 23. The hardware priority is fixed as the following: reset > NMI > watchdog timer > other interrupts Interrupts DMA3 DMA2 DMA1 DMA0 Address matching detection interrupt INT4 external interrupt INT3 external interrupt A-D conversion UART1 transmit UART1 receive UART0 transmit UART0 receive Timer B2 Timer B1 Timer B0 Timer A4 Timer A3 Timer A2 Timer A1 Timer A0 INT 2 external interrupt INT1 external interrupt INT0 external interrupt NMI external interrupt Watchdog timer DBC (Do not select.) Break instruction (Do not select.) Zero divide Reset Table 13 Interrupt sources and interrupt vector addresses Vector addresses 00FFC0 16 00FFC116 00FFC2 16 00FFC316 00FFC4 16 00FFC516 00FFC6 16 00FFC716 00FFCA 16 00FFCB16 00FFD0 16 00FFD116 00FFD2 16 00FFD316 00FFD4 16 00FFD5 16 00FFD6 16 00FFD7 16 00FFD8 16 00FFD9 16 00FFDA 16 00FFDB 16 00FFDC 16 00FFDD 16 00FFDE 16 00FFDF 16 00FFE0 16 00FFE1 16 00FFE2 16 00FFE3 16 00FFE4 16 00FFE5 16 00FFE6 16 00FFE7 16 00FFE8 16 00FFE9 16 00FFEA 16 00FFEB 16 00FFEC 16 00FFED 16 00FFEE 16 00FFEF 16 00FFF0 16 00FFF116 00FFF2 16 00FFF3 16 00FFF4 16 00FFF5 16 00FFF6 16 00FFF7 16 00FFF8 16 00FFF9 16 00FFFA 16 00FFFB 16 00FFFC 16 00FFFD 16 00FFFE 16 00FFFF 16 Fig. 22 Bit configuration of interrupt control register 76543210 Interrupt priority level Interrupt request bit 0 : No interrupt requested 1 : Interrupt requested 76543210 Interrupt priority level Interrupt request bit 0 : No interrupt requested 1 : Interrupt requested Polarity select bit 0 : Interrupt request bit is set to “1” at “H” level when level sense is selected; this bit is set to “1” at falling edge when edge sense is selected. 1 : Interrupt request bit is set to “1” at “L” level when level sense is selected; this bit is set to “1” at rising edge when edge sense is selected. Level/Edge select bit 0 : Edge sense 1 : Level sense Bit configuration of interrupt control registers for DMA0 to DMA3, A-D converter, UART0, UART1, timers A0 to A4, and timers B0 to B2, and INT 3, INT4. Bit configuration of interrupt control registers for INT0– INT2.

Notice: This is not a final specification. Some parametric limits are subject to change. Other interrupts previously mentioned are A-D converter, UART, etc. Figure 24 shows a diagram of the interrupt priority detection circuit. orities are the same, the one above has priority. interrupt disable flag I to “0” and enable further interrupts. Table 14. Addresses of interrupt control registers processor interrupt level (IPL) is set as shown in Table 15. Priority can be changed by software inside ➃ .

Notice: This is not a final specification. Some parametric limits are subject to change. Table 15. Value loaded in processor interrupt level (IPL) during an interrupt Table 16. Relationship between interrupt priority detection time select

M37920FCCGP, M37920FCCHP M37920FGCGP, M37920FGCHP MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. Fig. 26 Bit configuration of processor mode register 0 76543210 Processor mode register 0 Processor mode bits 0 0 : Single-chip mode 0 1 : Memory expansion mode 1 0 : Microprocessor mode 1 1 : Do not select. Interrupt priority detection time select bits 0 0 : 7 cycles of φ 0 1 : 4 cycles of φ 1 0 : 2 cycles of φ 1 1 : Do not select. Software reset bit By a write of “1” to this bit, the microcomputer will be reset, and then, restarted. External bus wait number select bits 0 0 : 0 wait 0 1 : 1 wait 1 0 : 2 wait 1 1 : ALE expansion wait Clock φ 1 output select bit 0 : φ1 output is disabled. (P41 functions as a programmable I/O port pin.) 1 : φ1 output is enabled. (P41 functions as the clock φ1 output pin.) Address 5E16

Notice: This is not a final specification. Some parametric limits are subject to change. start bit is “0”, “L” is output from TAiOUT pin. 4 is “0”, TAiIN can be used as a normal port pin. can be used to measure the pulse width of the TAiIN input signal. more cycles of the timer count source. same data is also written to the reload register and the counter. 1 0 : Count only while TAiIN input is “L”. 1 1 : Count only while TAiIN input is “H ”. 0 : Always “0” in timer mode. Table 17. Relationship between timer A clock division select bits, timer A clock division select bits.

M37920FCCGP, M37920FCCHP M37920FGCGP, M37920FGCHP MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. Fig. 30 Bit configuration of count start register Fig. 31 Count waveform when gate function is available 76543210 Timer A0 count start bit Timer A1 count start bit Timer A2 count start bit Timer A3 count start bit Timer A4 count start bit Timer B0 count start bit Timer B1 count start bit Timer B2 count start bit Count start register (Stop at “0”, Start at “1”) Address Selected clock source fi TAiIN Bit 4 Bit 3 Timer mode register Bit 4 Bit 3 Timer mode register

M37920FCCGP, M37920FCCHP M37920FGCGP, M37920FGCHP MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. (2) Event counter mode [01] Figure 32 shows the bit configuration of the timer Ai mode register during event counter mode. In event counter mode, bit 0 of the timer Ai mode register must be “1” and bits 1 and 5 must be “0”. The input signal from the TAi IN pin is counted when the count start bit shown in Figure 30 is “1” and counting is stopped when it is “0”. Count is performed at the fall of the input signal when bit 3 is “0” and at the rise of the signal when it is “1”. In event counter mode, whether to increment or decrement the count can be selected with the up-down bit or the input signal from the TAi OUT pin. When bit 4 of the timer Ai mode register is “0”, the up-down bit is used to determine whether to increment or decrement the count (decrement when the bit is “0” and increment when it is “1”). Figure 33 shows the bit configuration of the up-down register. When bit 4 of the timer Ai mode register is “1”, the input signal from the TAi OUT pin is used to determine whether to increment or decre- ment the count. However, note that bit 2 must be “0” if bit 4 is “1.” It is because if bit 2 is “1”, TAiOUT pin becomes an output pin to output pulses. The count is decremented when the input signal from the TAi OUT pin is “L” and incremented when it is “H ”. Determine the level of the input signal from the TAiOUT pin before a valid edge is input to the TAiIN pin. An interrupt request signal is generated and the interrupt request bit in the timer Ai interrupt control register is set when the counter reaches 0000 16 (decrement count) or FFFF16 (increment count). At the same time, the contents of the reload register is transferred to the counter and the count is continued. When bit 2 is “1,” each time the counter reaches 000016 (decrement count) or FFFF16(increment count), the waveform’s polarity is re- versed and is output from TAiOUT pin. If bit 2 is “0”, TAiOUT pin can be used as a normal port pin. However, if bit 4 is “1” and the TAiOUT pin is used as an output pin, the output from the pin changes the count direction. Therefore, bit 4 must be “0” unless the output from the TAiOUT pin is to be used to se- lect the count direction. Fig. 32 Bit configuration of timer Ai mode register during event counter mode Fig. 33 Bit configuration of up-down register 76543210 100×× 0 1 : Always “01” in event counter mode 0 : No pulse output 1 : Pulse output 0 : Count at the falling edge of input signal 1 : Count at the rising edge of input signal 0 : Increment or decrement according to up/down bit 1 : Increment or decrement according to TAi OUT pin input signal level 0 : Always “0” in event counter mode × × : Not used in event counter mode Timer A0 mode register Timer A1 mode register Timer A2 mode register Timer A3 mode register Timer A4 mode register Addresses 5716 5816 5916 5A16 Timer A0 up-down bit Timer A1 up-down bit Timer A2 up-down bit Timer A3 up-down bit Timer A4 up-down bit Timer A2 two-phase pulse signal processing select bit 0 : Two-phase pulse signal processing disabled 1 : Two-phase pulse signal processing mode Timer A3 two-phase pulse signal processing select bit 0 : Two-phase pulse signal processing disabled 1 : Two-phase pulse signal processing mode Timer A4 two-phase pulse signal processing select bit 0 : Two-phase pulse signal processing disabled 1 : Two-phase pulse signal processing mode Up-down register

76543210 Address

M37920FCCGP, M37920FCCHP M37920FGCGP, M37920FGCHP MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. nored. (See Figure 36.) Note that bits 5, 6, and 7 of the up-down reg- ister (address 4416) are the two-phase pulse signal processing se- lect bits for timers A2, A3 and A4 respectively. Each timer operates in normal event counter mode when the corresponding bit is “0” and performs two-phase pulse signal processing when it is “1”. Count is started by setting the count start bit to “1”. Data write and read are performed in the same way as for normal event counter mode. Note that the direction register of the input port must be set to input mode because two kinds of pulse signals, described above, are input. Also, there can be no pulse output in this mode. Data write and data read are performed in the same way as for timer mode. That is, when data is written to timer Ai halted, it is also writ- ten to the reload register and the counter. When data is written to timer Ai which is busy, the data is written to the reload register, but not to the counter. The counter is reloaded with new data from the reload register at the next reload time. The counter can be read at any time. In event counter mode, whether to increment or decrement the counter can also be determined by supplying two kinds of pulses of which phases differ by 90° to timer A2, A3, or A4. There are two types of two-phase pulse processing operations. One uses timers A2 and A3, and the other uses timer A4. In both processing operations, two pulses described above are input to the TA jOUT (j = 2 to 4) pin and TAjIN pin respectively. When timers A2 and A3 are used, as shown in Figure 34, the count is incremented when a rising edge is input to the TAk IN pin after the level of TAkOUT (k=2, 3) pin changes from “L” to “H ”, and when the falling edge is input, the count is decremented. For timer A4, as shown in Figure 35, when a phase-related pulse with a rising edge input to the TA4 IN pin is input after the level of TA4OUT pin changes from “L” to “H ”, the count is incremented at the respective rising edge and falling edge of the TA4OUT pin and TA4IN pin. When a phase-related pulse with a falling edge input to the TA4OUT pin is input after the level of TA4IN pin changes from “H ” to “L”, the count is decremented at the respective rising edge and falling edge of the TA4 IN pin and TA4OUT pin. When performing this two-phase pulse signal processing, timer Aj mode register bit 0 and bit 4 must be set to “1” and bits 1, 2, 3, and 5 must be “0”. Bits 6 and 7 are ig- Fig. 36 Bit configuration of timer Aj mode register when performing two-phase pulse signal processing in event counter mode Fig. 34 Two-phase pulse processing operation of timers A2 and A3 Fig. 35 Two-phase pulse processing operation of timer A4 76543210 100010×× 0 1 : Always “01” in event counter mode 0 1 0 0 : Always “0100” when processing two-phase pulse signal × × : Not used in event counter mode Timer A2 mode register Timer A3 mode register Timer A4 mode register Addresses 5916 5A16 TAkOUT TAkIN (k = 2, 3) Increment- count Increment- count Increment- count Decrement- count Decrement- count Decrement- count TA4 OUT TA4 IN Decrement-count at each edgeIncrement-count at each edge Decrement-count at each edgeIncrement-count at each edge

M37920FCCGP, M37920FCCHP M37920FGCGP, M37920FGCHP MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. Fig. 39 Pulse output example when external rising edge is selected Fig. 40 Example when trigger is re-issued during pulse output Selected clock source fi TAiIN (rising edge) TAiOUT Example when the contents of the reload register is 000316 Selected clock source fi TAiIN (rising edge) TAiOUT Example when the contents of the reload register is 000416

M37920FCCGP, M37920FCCHP M37920FGCGP, M37920FGCHP MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. (4) Pulse width modulation mode [11] Figure 41 shows the bit configuration of the timer Ai mode register during pulse width modulation mode. In pulse width modulation mode, bits 0, 1, and 2 must be set to “1”. Bit 5 is used to determine whether to perform 16-bit length pulse width modulator or 8-bit length pulse width modulator. 16-bit length pulse width modulator is selected when bit 5 is “0” and 8-bit length pulse width modulator is selected when it is “1”. The 16-bit length pulse width modulator is described first. The pulse width modulator can be started with a software trigger or with an input signal from a TAi IN pin (external trigger). The software trigger mode is selected when bit 4 is “0”. Pulse width modulator is started and a pulse is output from TAiOUT when the count start bit is set to “1”. The external trigger mode is selected when bit 4 is “1”. Pulse width modulation starts when a trigger signal is input from the TAi IN pin when the count start bit is “1”. Whether to trigger at the fall or rise of the trigger signal is determined by bit 3. The trigger is at the fall of the trigger signal when bit 3 is “0” and at the rise when it is “1”. When data is written to timer Ai with the pulse width modulator halted, it is written to the reload register and the counter. Then when the count start bit is set to “1” and a software trigger or an external trigger is issued to start modulation, the waveform shown in Figure 42 is output continuously. Once modulation is started, triggers are not accepted. If the value in the reload register is m, the duration “H ” of pulse is × m and the output pulse period is × (2 16 –1). An interrupt request signal is generated and the interrupt request bit in the timer Ai interrupt control register is set at each fall of the output pulse. The width of the output pulse is changed by updating timer data. The update can be performed at any time. The output pulse width is changed at the rise of the pulse after data is written to the timer. The contents of the reload register are transferred to the counter just before the rise of the next pulse so that the pulse width is changed from the next output pulse. Undefined data is read when timer Ai is read. The 8-bit length pulse width modulator is described next. The 8-bit length pulse width modulator is selected when the timer Ai mode register bit 5 is “1”. The reload register and the counter are both divided into 8-bit halves. selected clock frequency selected clock frequency The low-order 8 bits function as a prescaler and the high-order 8 bits function as the 8-bit length pulse width modulator. The prescaler counts the clock selected by bits 6, 7, and the contents of the timer A clock division select register. (See Table 17.) A pulse is generated when the counter reaches 0000 16 as shown in Figure 43. At the same time, the contents of the reload register is transferred to the counter and count is continued. Fig. 41 Bit configuration of timer Ai mode register during pulse width modulation mode 76543210 111 1 1 : Always “11” in pulse width modulation mode 1 : Always “1” in pulse width modulation mode 0 × : Software trigger 1 0 : Trigger at the falling of TAi IN input 1 1 : Trigger at the rising of TAiIN input 0 : 16-bit pulse width modulator 1 : 8-bit pulse width modulator Clock source select bits (See Table 17.) Timer A0 mode register Timer A1 mode register Timer A2 mode register Timer A3 mode register Timer A4 mode register Addresses 5716 5816 5916 5A16

M37920FCCGP, M37920FCCHP M37920FGCGP, M37920FGCHP MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. high-order 8 bits of the reload register are m, the duration “H ” of pulse is And the output pulse period is selected clock frequency Therefore, if the low-order 8 bits of the reload register are n, the pe- riod of the generated pulse is × (n + 1). The high-order 8 bits function as an 8-bit length pulse width modula- tor using this pulse as input. The operation is the same as for 16-bit length pulse width modulator except that the length is 8 bits. If the selected clock frequency selected clock frequency Fig. 42 16-bit length pulse width modulator output pulse example Fig. 43 8-bit length pulse width modulator output pulse example Selected clock source fi TAiIN (rising edge) TAiOUT 1/fi × (216 – 1) 1/fi × (m) This trigger is not accepted Example when the contents of the reload register is 000316 Selected clock source fi TAiIN (falling edge) Prescaler output (when n = 2) 8-bit length pulse width modulator output (when m = 2) 8 – 1) 1/fi × (n + 1) × (n + 1) × m.

M37920FCCGP, M37920FCCHP M37920FGCGP, M37920FGCHPPRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION MITSUBISHI MICROCOMPUTERS When timer Bi is read, the contents of the reload register is read. Note that in this mode, the interval between the fall of the TBiIN pin input signal to the next rise or from the rise to the next fall must be at least two cycles of the timer count source. Timer Bi overflow flag which is bit 5 of timer Bi mode register is set to “1” when the timer Bi counter reaches 0000 16, which indicates that a pulse width or pulse period is longer than that which can be mea- sured by a 16-bit length. This flag is cleared by writing data to the corresponding timer Bi mode register. This flag is set to “1” at reset. Fig. 48 Pulse period measurement mode operation (example of measuring the interval between the falling edge to next falling one) Fig. 49 Pulse width measurement mode operation Selected clock source fi TBiIN Reload register ← Counter Counter ← 0 Count start bit Interrupt request signal Selected clock source fi TBiIN Reload register ← Counter Counter ← 0 Count start bit Interrupt request signal

M37920FCCGP, M37920FCCHP M37920FGCGP, M37920FGCHPPRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION MITSUBISHI MICROCOMPUTERS Serial I/O mode select bits 0 0 0 : Programmable I/O port (Serial I/O is invalid.) 0 0 1 : Clock synchronous 1 0 0 : 7-bit UART 1 0 1 : 8-bit UART 1 1 0 : 9-bit UART Internal/External clock select bit 0 : Internal clock 1 : External clock Stop bit length select bit (Valid in UART mode.) 0 : 1 stop bit 1 : 2 stop bits Odd/Even parity select bit (Valid in UART mode with the parity enable bit = “1”.) 0 : Odd parity 1 : Even parity Parity enable bit (Valid in UART mode) 0 : No parity 1 : With parity Sleep select bit (Valid in UART mode) 0 : No sleep 1 : Sleep

76543210 UART 0 Transmit/Receive mode register

UART 1 Transmit/Receive mode register Addresses 3816 SERIAL I/O PORTS Two independent serial I/O ports are provided. Figure 50 shows a block diagram of the serial I/O ports. Bits 0 to 2 of the UARTi(i = 0,1) transmit/receive mode register shown in Figure 51 are used to determine whether to use port P8 as a programmable I/O port, clock synchronous serial I/O port, or asyn- chronous (UART) serial I/O port which uses start and stop bits. Figures 52 and 53 show the block diagrams of the receiver/transmit- ter. Figure 54 shows the bit configuration of the UARTi transmit/receive control register. Each communication method is described below. Fig. 51 Bit configuration of UARTi transmit/receive mode register Fig. 50 Block diagram of serial I/O port UARTi receive register TXD i R XD i Receive control circuit Transmit control circuit UARTi transmit register 1/16 divider 1/2 divider 1/(n + 1) divider 1/16 divider Transfer clock Transfer clock UARTi transmit buffer register UART Clock synchronous Clock synchronous Clock synchronous (when internal clock selected) BRG count source select bits f16 f64 f512 Clock synchronous (Internal clock) UART D 7 D 6 D 5 D 4 D 3 D 2 D 1 UARTi receive buffer registerD 0 D 7D 8 D 6 D 5 D 4 D 3 D 2 D 1 D 0 0D 8000000 BRGi UART0 (Addresses 3316, 3216) UART1 (Addresses 3B16, 3A16) UART0 (Addresses 3716, 3616) UART1 (Addresses 3F16, 3E16) CTS 0/RTS0 Clock synchronous (External clock) n = a value set into the UARTi baud rate register (BRGi) CLK 1 CTS 0 CTS 0/CLK1 CLK 0 Data bus (even) Data bus (odd) Bit converter Data bus (odd) Data bus (even) Bit converter

M37920FCCGP, M37920FCCHP M37920FGCGP, M37920FGCHPPRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION MITSUBISHI MICROCOMPUTERS Data bus (odd) Data bus (even) D 0D 1D 2D 3D 4D 5D 6D 7D 8 SP SP PAR No parity UARTi receive register R XD i UARTi receive buffer register 9-bit UART 7-bit UART7-bit UART 8-bit UART Synchronous UART 8-bit UART 9-bit UART Synchronous Synchronous Parity2SP 1SP 0000000 SP : Stop bit PAR : Parity bit Fig. 52 Block diagram of receiver Fig. 53 Block diagram of transmitter D 0D 1D 2D 3D 4D 5D 6D 7D 8 SP PAR TXD i 2SP SP 1SP UART Data bus (odd) Data bus (even) No parity 7-bit UART 9-bit UART Synchronous 7-bit UART 8-bit UART 9-bit UART Synchronous 8-bit UART Synchronous Parity SP : Stop bit PAR : Parity bit UARTi transmit register UARTi receive transmit register

M37920FCCGP, M37920FCCHP M37920FGCGP, M37920FGCHPPRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION MITSUBISHI MICROCOMPUTERS Fig. 54 Bit configuration of UARTi transmit/receive control register /LSB MSB TX EPTY 76543210 R/C CS 1 CS 0 BRG count source select bits 00 : f2 01 : f16 10 : f64 11 : f512 CTS/RTS function select bit (Note 1) 0 : CTS function is selected. 1 : RTS function is selected. Transmit register empty flag 0 : Data is present in the transmit register. (Transmission is in progress.) 1 : No data is present in the transmit register. (Transmission is completed.) CTS/RTS enable bit (Note 2) 0 : CTS, RTS function is enabled. 1 : CTS, RTS function is disabled. UART receive interrupt mode select bit 0 : Reception interrupt 1 : Reception error interrupt CLK polarity select bit (This bit is used in the clock synchronous serial I/O mode.) (Note 3) 0 : At the falling edge of a transfer clock, transmit data is output; at the rising edge, receive data is input. When not in transfer, pin CLK’s level is “H ”. 1 : At the rising edge of a transfer clock, transmit data is output; at the falling edge, receive data is input. When not in transfer, pin CLK’s level is “L”. Transfer format select bit (This bit is used in the clock synchronous serial I/O mode.) (Note 3) 0 : LSB (Least Significant Bit) first 1 : MSB (Most Significant Bit) first 76543210 RERIOERFERPERSUM TI TE Transmit enable bit Transmit buffer empty flag Receive enable bit Receive complete flag Overrun error flag Framing error flag (Note 4) Parity error flag (Note 4) Error sum flag (Note 4) UART0 transmit/receive control register 0 UART1 transmit/receive control register 0 Address 3C 16 UART0 transmit/receive control register 1 UART1 transmit/receive control register 1 Address 3D 16 CPL Notes 1: Valid when the CTS/RTS enable bit = “0”. 2: Fix this bit to “1” in UART1 transmit/receive control register 0. (UART1 is not equipped with the CTS/RTS function.) 3: Fix this bit to “0” in UART mode or when serial I/O is invalid. 4: Valid in UART mode.

M37920FCCGP, M37920FCCHP M37920FGCGP, M37920FGCHPPRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION MITSUBISHI MICROCOMPUTERS CLOCK SYNCHRONOUS SERIAL COMMUNI- CATION A case where communication is performed between two clock syn- chronous serial I/O ports as shown in Figure 55 will be described. (The transmission side will be denoted by subscript j and the receiv- ing side will be denoted by subscript k.) Bit 0 of the UARTj transmit/receive mode register and UARTk trans- mit/receive mode register must be set to “1” and bits 1 and 2 must be “0”. The length of the transmission data is fixed at 8 bits. Bit 3 of the UARTj transmit/receive mode register of the clock send- ing side is cleared to “0” to select the internal clock. Bit 3 of the UARTk transmit/receive mode register of the clock receiving side is set to “1” to select the external clock. Bits 4, 5 and 6 are ignored in clock synchronous mode. Bit 7 must always be “0”. The clock source is selected by bit 0 (CS 0) and bit 1 (CS1) of the clock-sending-side UARTj transmit/receive control register 0. As shown in Figure 50, the selected clock is divided by (n + 1), then by 2, is passed through a transmission control circuit, and is output as transmission clock CLKj. Therefore, when the selected clock is fi, Bit Rate = f i/ {(n + 1) × 2} On the clock receiving side, the CS0 and CS1 bits of the UARTk transmit/receive control register 0 are ignored because an external clock is selected. UART0 is equipped with the CTS and RTS functions. UART1 is not equipped with the CTS/RTS function. Bit 4 of the UART0 transmit/receive control register 0 is used to de- termine whether to use CTS 0 or RTS0 signal. Bit 4 must be “0” when CTS 0 or RTS0 signal is used. Bit 4 must be “1” when CTS0 and RTS0 signals are not used. When CTS0 and RTS0 signals are not used, CTS 0/RTS0 pin can be used as a normal port pin. When using this pin as pin CTS0/RTS0, :

If bit 2 of the UART0 transmit/receive control register 0 is cleared to “0”, CTS0 input is selected.
If bit 2 is set to “1”, RTS0 output is selected. Figure 56 shows the bit configuration of the CTS/RTS separate se- lect register. By using bit 0 of the CTS/RTS separate select register (CTS/RTS separate select bit), the function of the CTS 0/RTS0 pin can be separated into two functions. When bit 0 = “1”, the above separation is performed. When bit 0 = “0”, no separation is per- formed. When the CTS0/RTS0 pin is separated, RTS0 function is selected. When the CTS0/CLK1 pin is separated, CTS0 function is selected. The following describes the case where the CTS and RTS signals are used. When the CTS and RTS signals are not used, however, the CTS input is not necessary, and there is no RTS output. Since UART1 is not equipped with the CTS/RTS function, UART1 is regarded as the case where the CTS and RTS signals are not used. Fig. 55 Clock synchronous serial communication UARTj transmit register TxDj RxDj CLKj CTSj UARTj transmit buffer register UARTj receive buffer register UARTj receive register UARTj Transmit/Receive mode register UARTj Transmit/Receive control register 0 UARTj Transmit/Receive control register 1 00 0 0TX EPTY CS 1 CS 0 RERIOERFERPER CPL CPL SUM TI TE UARTk transmit register UARTk transmit buffer register UARTk receive buffer register UARTk receive register UARTk Transmit/Receive mode register UARTk Transmit/Receive control register 0 UARTk Transmit/Receive control register 1 01 1 0 1TX EPTY MSB /LSB RERIOERFERPERSUM TI TE TxDk RxDk CLKk RTSk MSB /LSB

M37920FCCGP, M37920FCCHP M37920FGCGP, M37920FGCHPPRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION MITSUBISHI MICROCOMPUTERS Transmission Transmission is started when bit 0 (TEj flag: transmit enable bit) of UARTj transmit/receive control register 1 is “1”, bit 1 (TIj flag) of one is “0”, and CTSj input is “L”. The TIj flag indicates whether the trans- mit buffer register is empty or not. It is cleared to “0” when data is written in the transmit buffer register ; it is set to “1” when the con- tents of the transmit buffer register is transferred to the transmit reg- ister and the transmit buffer register becomes empty. When all of the transmit conditions are satisfied, the transmit data in the transmit buffer register are transferred to the transmit register, and transmission starts. As shown in Figure 57, data is output from T XDj pin each time when transmission clock CLKj changes from “H” to “L”. (In the clock synchronous serial I/O mode, the polarity of a transfer clock can be changed. For details, refer to the section on the selection of the transfer clock polarity.) The data is output from the least significant bit. When the transmit register becomes empty after the contents has been transmitted, data is transferred automatically from the transmit buffer register to the transmit register if the next transmission start condition is satisfied. The next transmission is performed succeedingly. Once transmission has started, the TEj flag, TIj flag, and CTSj signals are ignored until data transmission completes. Therefore, transmission is not interrupt when CTSj input is changed to “H” during transmission. The transmission start condition indicated by TEj flag, TIj flag, and CTSj is checked while the T END j signal (shown in Figure 57) is “H”. Therefore, data can be transmitted continuously if the next transmis- sion data is written in the transmit buffer register and TIj flag is cleared to “0” before theT END j signal goes “H”. Bit 3 (TXEPTYj flag) of UARTj transmit/receive control register 0 changes to “1” at the next cycle just after the TEND j signal goes “H” and changes to “0” when transmission starts. Therefore, this flag can be used to determine whether data transmission has completed. When the TIj flag changes from “0” to “1”, the interrupt request bit in the UARTj transmit interrupt control register is set to “1”. Receive When bit 2 of the UARTk transmit/receive control register 1 is set to “1”, reception becomes enabled. In this case, when the CLKk signal is input, the receive operation starts simultaneously with this signal. The RTSk output is “H” when the REK flag is “0”. When the REK flag is set to “1”, the RTSk output becomes “L”. This informs the transmit- ter side that reception becomes enabled. When the receive opera- tion starts, the RTSk output automatically becomes “H”. When the receive operation starts, the receiver takes data from pin RxDk each time when the transmit clock (CLKj) turns from “L” to “H”. Simultaneously with reception, the contents of the receiver register is shifted bit by bit. (Note that, in the clock synchronous serial communication, the polar- ity of a transfer clock can be inverted. For details, refer to the section on the polarity of the transfer clock.) When an 8-bit data is received, the contents of the receive register is transferred to the receive buffer register and bit 3 (RIk flag) of UARTk transmit/receive control regis- ter 1 is set to “1”. In other words, the setting “1” to the RIk flag indi- cates that the receive buffer register contains the received data. At this time, if the low-order byte of the UARTk receive buffer register is read out, the RTSk output turns back to “L”. This indicates that the next data reception becomes enabled. Bit 4 (OERk flag) of UARTk transmit/receive control register 1 is set to “1” when the next data is transferred from the receive register to the receive buffer register while RIk flag is “1”, and indicates that the next data was transferred to the receive register before the contents of the receive buffer regis- ter was read. (In other words, this indicates that an overrun error has occurred.) RIk flag is automatically cleared to “0” when the low-order byte of the receive buffer register is read or when the REk flag is cleared to “0”. The OERk flag is cleared when the REk flag is cleared. Bit 5 (FERk flag), bit 6 (PERk flag), and bit 7 (SUMk flag) are ignored in clock synchronous mode. As shown in Figure 50, with clock synchronous serial communica- tion, data cannot be received unless the transmitter is operating be- cause the receive clock is created from the transmission clock. Therefore, the transmitter must be operating even when there is no need to sent data from UARTk to UARTj. 0 000000 76543210 CTS/RTS separate select bit (Note) 0 : CTS/RTS are multiplexed. 1 : CTS/RTS are separate. Must be “0”. CTS/RTS separate select register Address AC 16 Note: Valid when the CTS/RTS enable bit (bit 4 at address 3416) = “0”. Fig. 56 Bit configuration of CTS/RTS separate select register

Each reception
When an error occurs at reception If bit 5 of the UARTk transmit/receive control register 0 (UARTk re- ceive interrupt mode select bit) is cleared to “0”, the interrupt request bit is set to “1” at each reception. If bit 5 is set to “1”, the interrupt re- quest bit is set to “1” only when an error occurs. (In the clock syn- chronous serial communication, only when an overrun error occurs, the interrupt request bit is set to “1”.) Note that a DMA request is affected by the UART receive interrupt mode select bit if the UARTi reception is selected as a DMA request source of the DMA controller. When the UARTk receive interrupt mode select bit is cleared to “0”, a DMA request is generated at each UART reception. When the UARTk receive interrupt mode select bit is set to “1”, a DMA request is generated only at normal UART reception. (In other words, no DMA request is generated when an error has occurred.) Polarity of transfer clock In the clock synchronous serial communication, by bit 6 of the UARTj transmit/receive control register 0 (CPL), the polarity of a transfer clock can be selected. As shown in Figure 58, when bit 6 = “0”, the polarity is as follows:
In transmission, transmit data is output at the falling edge of CLKj.
In reception, receive data is input at the rising edge of CLKk.
When not in transfer, CLKi is at “H ” level. When bit 6 = “1”, the polarity is as follows:
In transmission, transmit data is output at the rising edge of CLKj.
In reception, receive data is input at the rising edge of CLKk.
When not in transfer, CLKi is at “L” level.

M37920FCCGP, M37920FCCHP M37920FGCGP, M37920FGCHPPRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION MITSUBISHI MICROCOMPUTERS Fig. 58 Polarity of transfer clock I CLK polarity select bit = 0 CLK i TxD i RxD i D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7 D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7 ❇ Transmit data is output to pin TxDi at the falling edge of transfer clock, and receive data is input from pin RxDi at the rising edge of transfer clock. When not in transfer, pin CLKi’s level is “H ”. I CLK polarity select bit = 1 CLK i TxD i RxD i D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7 D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7 ❇ Transmit data is output to pin TxDi at the rising edge of transfer clock, and receive data is input from pin RxDi at the falling edge of transfer clock. When not in transfer, pin CLKi’s level is “L”.

M37920FCCGP, M37920FCCHP M37920FGCGP, M37920FGCHPPRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION MITSUBISHI MICROCOMPUTERS Selection of transfer format In clock synchronous serial communication, transfer format can be selected by bit 7 of the transmit/receive control register 0. When bit 7 is “0”, transfer format is LSB first. When bit 7 is “1”, transfer format is MSB first. This function is realized by changing connection relation between the transmit buffer register and the receive buffer register when writ- ing transmit data to the transmit buffer register or reading receive data from the receive buffer register. Accordingly, the transmitter’s operation is the same in both transfer formats. Figure 59 shows the connection relation. Fig. 59 Connection relation between transmit buffer register, receive buffer register, and data bus Bit 7 in transmit/receive control register 0 Write to transmit buffer register Read from receive buffer register (LSB first) (MSB first) Transmit buffer register DB 7 Data bus D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 DB 6 DB 5 DB 4 DB 3 DB 2 DB 1 DB 0 Transmit buffer register DB 7 Data bus D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 DB 6 DB 5 DB 4 DB 3 DB 2 DB 1 DB 0 Receive buffer register DB 7 Data bus D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 DB 6 DB 5 DB 4 DB 3 DB 2 DB 1 DB 0 Receive buffer register DB 7 Data bus D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 DB 6 DB 5 DB 4 DB 3 DB 2 DB 1 DB 0

Each reception
When an error occurs at reception If bit 5 of the UARTk transmit/receive control register 0 (UART re- ceive interrupt mode select bit) is cleared to “0”, the interrupt request bit is set to “1” at each reception. If bit 5 is set to “1”, the interrupt re- quest bit is set to “1” only when an error occurs. (In the clock asyn- chronous serial communication, when an overrun error, framing error, or parity error occurs, the interrupt request bit is set to “1”.) Sleep mode The sleep mode is used to communicate only between certain micro- computers when multiple microcomputers are connected through serial I/O. The microcomputer enters the sleep mode when bit 7 of UARTi transmit/receive mode register is set to “1.” The operation of the sleep mode for an 8-bit asynchronous commu- nication is described below. When sleep mode is selected, the contents of the receive register is not transferred to the receive buffer register if bit 7 (bit 6 if 7-bit asyn- chronous communication and bit 8 if 9-bit asynchronous communi- cation) of the received data is “0”. Also the RIi, OERi, FERi, PERi, and the SUMi flags are unchanged. Therefore, the interrupt request bit of the UARTi receive interrupt control register is also unchanged. Normal receive operation takes place when bit 7 of the received data is “1”. The following is an example of how the sleep mode can be used. The main microcomputer first sends data: bit 7 is “1” and bits 0 to 6 are set to the address of the subordinate microcomputer to be com- municated with. Then all subordinate microcomputers receive this data. Each subordinate microcomputer checks the received data, clears the sleep bit to “0” if bits 0 to 6 are its own address and sets the sleep bit to “1” if not. Next, the main microcomputer sends data with bit 7 cleared. Then the microcomputer which cleared the sleep bit will receive the data, but the microcomputers which set the sleep bit to “1” will not. In this way, the main microcomputer is able to com- municate only with the designated microcomputer.

M37920FCCGP, M37920FCCHP M37920FGCGP , M37920FGCHPPRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION MITSUBISHI MICROCOMPUTERS A-D CONVERTER The A-D converter is a 10-bit successive approximation converter. Figure 63 shows the block diagram of the A-D converter, Figure 64 shows the bit configuration of the A-D control register 0 (address 16), and the bit configuration of the A-D control register 1 (address 1F16). A-D conversion accuracy Bit 3 of A-D control register 1 is used to select whether to regard the conversion result as 10-bit or as 8-bit data. The conversion result is regarded as 10-bit data when bit 3 is “1” and as 8-bit data when bit 3 is “0”. When the conversion result is used as 10-bit data, the low-order 8 bits of the conversion result is stored in the even-numbered address of the corresponding A-D register and the high-order 2 bits are stored in bits 0 and 1 at the odd-numbered address of the corre- sponding A-D register. Bits 2 to 7 of the A-D register odd-numbered Fig. 63 Block diagram of A-D converter address are “0000002” when read. When the conversion result is used as 8-bit data, the conversion re- sult are stored in even-numbered address of the corresponding A-D register. In this case, the value at the A-D register’s odd-numbered address is “00 16” when read. A-D conversion frequency An operation clock (φAD ) of an A-D converter can be selected with bit 7 of the A-D control register 0 and bit 4 of the A-D control register 1. When bit 4 of the A-D control register 1 is “0”, φAD becomes f2/4 when bit 7 of the A-D control register 0 is “0”, φAD becomes f2/2 when bit 7 of the A-D control register 0 is “1”. When bit 4 of the A-D control register 1 is “1”, φAD becomes f2 when bit 7 of the A-D control register 0 is “0”, φAD becomes f1 when bit 7 of the A-D control register 0 is “1”. Note that φAD = f1 (in other words, the fastest speed) can be selected only in the 8-bit mode. φAD during A-D conversion must be 250 kHz or more because the comparator uses a capacity coupling amplifier. Data bus (even) Selector Successive approximation register Decoder A-D control register 0 (Address 1E16) Resistor ladder network VREF AV SS Vref AN 0 AN 1 AN 2 AN 3/ADTRG Comparator A-D register 0 (Address 2016) A-D register 1 (Address 2216) A-D register 2 (Address 2416) A-D register 3 (Address 2616) A-D register 0 (Address 2116) A-D register 1 (Address 2316) A-D register 2 (Address 2516) A-D register 3 (Address 2716) Data bus (odd) A-D control register 1 (Address 1F16) 1/2 1/2f2 φAD A-D conversion frequency selection VREF connection select bit

M37920FCCGP, M37920FCCHP M37920FGCGP , M37920FGCHPPRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION MITSUBISHI MICROCOMPUTERS Operation mode The operation mode is selected by bits 3 and 4 of A-D control regis- ter 0. The available operation modes are one-shot, repeat, single sweep, and repeat sweep. Analog input port pins are multiplexed with port P7 pins. Therefore, bits which correspond to pins for A-D conversion must be “0” (input mode). (1) One-shot mode One-shot mode is selected when bits 3 and 4 of A-D control register 0 are “0” is “0”. The A-D conversion pins are selected with bits 0 and 1 of A-D control register 0. When a software trigger is selected, A-D conversion is started when bit 6 (A-D conversion start bit) is set to “1”. When bit 3 of the A-D control register 1 is “1”, A-D conversion ends after 59 φAD cycles, and the interrupt request bit of the A-D interrupt control register is set to “1”. At the same time, bit 6 of A-D control reg- ister 0 (A-D conversion start bit) is cleared to “0” and A-D conversion stops. The result of A-D conversion is stored in the A-D register cor- responding to the selected pin. If an external trigger is selected, A-D conversion starts when the A-D conversion start bit is “1” and a valid edge is input to the AD TRG pin, This operation is the same as that for software trigger except that the A-D conversion start bit is not cleared after A-D conversion and a retrigger can be available during A-D conversion. (2) Repeat mode Repeat mode is selected when bit 3 of A-D control register 0 is “1” and bit 4 is “0”. The operation of this mode is the same as the operation of one-shot mode except that when A-D conversion of the selected pin is com- plete and the result is stored in the A-D register, conversion does not stop, but is repeated. No interrupt request is generated in this mode. Furthermore, if a soft- ware trigger is selected, the A-D conversion start bit is not cleared. The contents of the A-D register can be read at any time. (3) Single sweep mode Single sweep mode is selected when bit 3 of A-D control register 0 is “0” and bit 4 is “1”. In the single sweep mode, the number of analog input pins to be swept can be selected. Analog input pin is selected by bit 0 of the A- D control register 1 (address 1F16). Two pins, or four pins can be se- lected as analog input pins, depending on the contents of these bits. A-D conversion is performed only for selected input pins. After A-D conversion is performed for input of AN 0 pin, the conversion result is stored in A-D register 0, and in the same way, A-D conversion is per- formed for selected pins one after another. After A-D conversion is performed for all selected pins, the sweep is stopped. A-D conversion can be started with a software trigger or with an ex- ternal trigger input. A software trigger is selected when bit 5 of the A- D control register 0 (address 1E 16) is “0” and an external trigger is selected when it is “1”. When a software trigger is selected, A-D conversion is started when bit 6 of A-D control register 0 (A-D conversion start bit) is set to “1”. When A-D conversion of all selected pins end, the interrupt request bit of the A-D conversion interrupt control register is set to “1”. At the same time, A-D conversion start bit is cleared to “0” and A-D conver- sion stops. When an external trigger is selected, A-D conversion starts when the A-D conversion start bit is “1” and a valid edge is input to the AD TRG pin. In this case, the A-D conversion result which is stored in the A-D register 3 becomes invalid. The operation by external trigger is the same as that by a software trigger except that the A-D conversion start bit is not cleared to “0” after A-D conversion and that a retrigger can be available during A-D conversion. (4) Repeat sweep mode Repeat sweep mode is selected when bit 3 of A-D control register 0 is “1” and bit 4 is “1”. The difference from the single sweep mode is that A-D conversion does not stop after conversion for all selected pins, but repeats again from the AN 0 pin. The repeat is performed among the selected pins. Also, no interrupt request is generated. Furthermore, if a software trigger is selected, the A-D convension start bit is not cleared. The A-D register can be read at any time. Precautions for A-D conversion interrupt function Clear the interrupt request bit of the A-D interrupt control register (bit 3 at address 7016) before using an A-D interrupt. It is because this interrupt request bit is undefined just after reset.

M37920FCCGP, M37920FCCHP M37920FGCGP, M37920FGCHPPRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION MITSUBISHI MICROCOMPUTERS Fig. 66 DMA controll-related register memory map 0000C0 16 0000C1 16 0000C2 16 0000C3 16 0000C4 16 0000C5 16 0000C6 16 0000C7 16 0000C8 16 0000C9 16 0000CA 16 0000CB 16 0000CC 16 0000CD 16 0000CE 16 0000CF 16 0000D0 16 0000D1 16 0000D2 16 0000D3 16 0000D4 16 0000D5 16 0000D6 16 0000D7 16 0000D8 16 0000D9 16 0000DA 16 0000DB 16 0000DC 16 0000DD 16 0000DE 16 0000DF 16 0000E016 0000E116 0000E216 0000E316 0000E416 0000E516 0000E616 0000E716 0000E816 0000E916 0000EA 16 0000EB 16 0000EC 16 0000ED 16 0000EE 16 0000EF 16 0000F016 0000F116 0000F216 0000F316 0000F416 0000F516 0000F616 0000F716 0000F816 0000F916 0000FA 16 0000FB 16 0000FC 16 0000FD 16 0000FE 16 0000FF16 0000B016 0000B116 0000B216 0000B316 0000B416 0000B516 Address (Hexadecimal notation) Address (Hexadecimal notation) DMAC control register L DMAC control register H DMA0 interruput control register DMA1 interruput control register DMA2 interruput control register DMA3 interruput control register Source address register 0 Destination address register 0 Transfer counter register 0 DMA0 mode register L DMA0 mode register H DMA0 control register Source address register 1 Destination address register 1 Transfer counter register 1 DMA1 mode register L DMA1 mode register H DMA1 control register Source address register 2 Destination address register 2 Transfer counter register 2 DMA 2 mode register L DMA 2 mode register H DMA 2 control register Source address register 3 Destination address register 3 Transfer counter register 3 DMA 3 mode register L DMA 3 mode register H DMA 3 control register L M H L M H L M H L M H L M H L M H L M H L M H L M H L M H L M H L M H

M37920FCCGP, M37920FCCHP M37920FGCGP , M37920FGCHPPRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION MITSUBISHI MICROCOMPUTERS Fig. 67 Bit configuration of DMAC control registers L and H 76543210 DMAC control register L DMA0 request bit 0: No request. 1: Requested (Note). Priority select bit 0: Fixed. 1: Rotating. Address DMA1 request bit 0: No request. 1: Requested (Note). Note: Even when “1”s are written to bits 4 to 7 by software, these bits’ status do not change. 76543210 DMAC control register H Software DMA0 request bit 1: DMA request. Valid when the software DMA source is selected. The value is “0” at reading. Address B116 TC pin validity bit 0: Invalid. Pin P42 functions as a programmable I/O port (CMOS) pin. 1: Valid. Pin P42 functions as pin TC (N-channel open-drain). DMA2 request bit 0: No request. 1: Requested (Note). DMA3 request bit 0: No request. 1: Requested (Note). Software DMA1 request bit 1: DMA request. Valid when the software DMA source is selected. The value is “0” at reading. Software DMA2 request bit 1: DMA request. Valid when the software DMA source is selected. The value is “0” at reading. Software DMA3 request bit 1: DMA request. Valid when the software DMA source is selected. The value is “0” at reading. DMA0 enable bit 0: Disabled. 1: Enabled. DMA1 enable bit 0: Disabled. 1: Enabled. DMA2 enable bit 0: Disabled. 1: Enabled. DMA3 enable bit 0: Disabled. 1: Enabled.

M37920FCCGP, M37920FCCHP M37920FGCGP, M37920FGCHPPRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION MITSUBISHI MICROCOMPUTERS Fig. 68 Bit configuration of DMAi control register 76543210 DMA0 control register DMA1 control register DMA2 control register DMA3 control register DMA request source select bits 0 0 0 0 : Do not select. 0 0 0 1 : External source (DMAREQ 0 0 1 0 : Software DMA source 0 0 1 1 : Timer A0 0 1 0 0 : Timer A1 0 1 0 1 : Timer A2 0 1 1 0 : Timer A3 0 1 1 1 : Timer A4 1 0 0 0 : Timer B0 1 0 0 1 : Timer B1 1 0 1 0 : Timer B2 1 0 1 1 : UART0 receive 1 1 0 0 : UART0 transmit 1 1 0 1 : UART1 receive 1 1 1 0 : UART1 transmit 1 1 1 1 : A-D conversion Address CE DE 16 EE 16 FE 16 Edge sense/Level sense select bit (Note 1) (Used when both of the external source and burst transfer mode are selected.) 0 : Edge sense (Rising edge) 1 : Level sense (“L” level) DMAACK i validity bit (Note 2) 0 : Invalid. Pin DMAACKi functions as a programmable I/O port pin. 1 : Valid. Functions as pin DMAACKi are valid. Notes 1: Be sure to fix this bit to “0” in any of the following cases:

When the external source is selected by using bits 0 to 3
In the cycle steal transfer mode Level sense can be selected only when both of the external source and burst transfer mode are selected. 2: DMA3 is not equipped with the DMAACK output function. For the DMA3 control register, be sure to clear this bit to “0”. The value is “0” at reading.

M37920FCCGP, M37920FCCHP M37920FGCGP , M37920FGCHPPRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION MITSUBISHI MICROCOMPUTERS Fig. 69 Bit configuration of DMAi control registers L and H 76543210 Transfer mode select bit 0 : Burst transfer mode 1 : Cycle steal transfer mode Transfer-unit-bit-number select bit 0 : 16 bits 1 : 8 bits Fix this bit to “0”. Note: For the DMA3 mode register L, be sure to fix this bit to “0” (2-bus cycle transfer). In this case, 1-bus cycle transfer cannot be used. Additionally, be sure to fix this bit to “0” when either transfer source or transfer destination is in an internal area. In this case, also, 1-bus cycle transfer cannot be used. 76543210 Transfer destination select bit (Used in 1-bus cycle transfer.) (Note) 0 : From memory to I/O 1 : From I/O to memory Transfer method select bit 0 : 2-bus cycle transfer 1 : 1-bus cycle transfer (Note) Transfer-source-address-direction select bits 0 0 : Fixed 0 1 : Forward 1 0 : Backward 1 1 : Do not select. Transfer-destination-address-direction select bits 0 0 : Fixed 0 1 : Forward 1 0 : Backward 1 1 : Do not select. The value is “0” at reading. Fix this bit to “0”. The value is “0” at reading. Operating mode select bits 0 0 : Single transfer 0 1 : Repeat transfer 1 0 : Array chain transfer 1 1 : Link array chain transfer DMA0 mode register L DMA1 mode register L DMA2 mode register L DMA3 mode register L Address CC DC 16 EC 16 FC 160 DMA0 mode register H DMA1 mode register H DMA2 mode register H DMA3 mode register H Address CD DD 16 ED 16 FD 1600 Note: Be sure to fix this bit to “0” in 2-bus cycle transfer. 000

M37920FCCGP, M37920FCCHP M37920FGCGP, M37920FGCHPPRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION MITSUBISHI MICROCOMPUTERS Fig. 70 Connection example with external memories in 2-bus cycle transfer Fig. 71 Connection example with external memories and external I/Os in 1-bus cycle transfer M37920 Address bus Data bus (D8 to D15) Data bus (D0 to D7) RD BHW BLW Note: External circuits are not considered. Address (Transfer source) Data (Read) Data (Write) Address (Transfer destination) BLW, BHW RD Transfer source memory (even-numbered address) Transfer destination memory (even-numbered address) Transfer source memory (odd-numbered address) Transfer destination memory (odd-numbered address) DMAACK i Address (Memory) Data (Read) DMAACK i RD I/O M37920 Address bus Data bus (D8 to D15) Data bus (D0 to D7) RD BHW BLW DMAACK j DMAREQ j I/O Notes 1: External circuits are not considered. 2: When the external data bus width = 16 bits and “1 transfer unit” = 8 bits, 1-bus cycle transfer cannot be used for the transfer between a memory and I/O if they are connected to the different data buses (D0 to D7, D8 to D15), one for one. Write/Read acknowledge DMA DMA request Write/Read acknowledge DMA DMA request j = 0 to 2 Memory (even-number- ed address) Memory (odd-numbered address)

Notice: This is not a final specification. Some parametric limits are subject to change. request source select bits (bits 0 to 3) and DMA request sources. The request timing is the same as that for interrupts. tomatically selected after reset removal. Table 18. Relationship between DMA request source select bits ternal source) is selected as a request source.

Channel i’s DMA enable bit is cleared to “0” (forced termination of
Channel i’s DMA request bit is cleared to “0”.
All of channel i’s DMA transfers are completed (normal termination
“L” level is input to pin TC during channel i’s transfer (forced termi-

Figure 72 shows a burst transfer example in edge sense mode. priority is for DRAM refresh, HOLD, DMA controller, and CPU. transfer as shown in Figure 72, such a request will not be accepted.

M37920FCCGP, M37920FCCHP M37920FGCGP, M37920FGCHPPRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION MITSUBISHI MICROCOMPUTERS Fig. 72 Burst transfer example (in edge sense mode) DMAREQ 0 DMA0 request bit DMA0 enable bit DMA1 DMA1 DMA0 Channel 0 entire data transferChannel 1 entire data transfer The above example applies on the following conditions : DMA1(CPU) (CPU) DMAREQ 1 DMA1 request bit DMA1 enable bit DRAM refresh request Bus user refresh DRAM

DMA request sources of DMA0 and DMA1: external source (edge sense)
Channel priority : fixed (channel 0 > channel 1) Fig. 73 Burst transfer example (in level sense mode) DMAREQ 0 DMA0 request bit DMA0 enable bit (CPU) DMA1 (CPU) DMA1 (CPU) The above example applies on the following conditions :
DMA request sources of DMA0 and DMA1: external source (level sense)
Channel priority : fixed (channel 0 > channel 1) DMA0 DMAREQ 1 DMA1 request bit DMA1 enable bit DRAM refresh request Bus user refresh DRAM When channel 1’s DMA transfer is entirely completed, the right to use bus is once passed to the CPU, and the DMA transfer request from channel 0 is later accepted at the end of the current bus cycle. When bit 4 of the DMAi control register is set to “1”, the level sense mode is selected. The level sense mode can be used only for the DMA request from pin DMAREQ i. When selecting another source, be sure to select the edge sense mode. In the level sense mode, the DMAi request bit is set to “1” to initiate the DMA transfer only while pin DMAREQ i’s input level is “L”. If pin DMAREQ i’s input level returns to “H ” in the middie of transfer, the DMA operation is interrupted at the end of the current transfer bus cycle or next transfer bus cycle so that the right to use bus is re- turned to the CPU. At this time, the DMA enable bit is not cleared. When pin DMAREQ i’s input level returns to “L”, the transfer opera- tion is resumed at the address which is next to the point of interrup- tion. In the level sense mode, the DMA request bit varies only with the input level at pin DMAREQ i. Therefore, while pin DMAREQi’s in- put level is “L”, the DMA request bit remains to be “1” even if the transfer is completed. Figure 73 shows a burst transfer example in level sense mode. When pin DMAREQ i’s input level for channel 1 changes from “H ” to “L” during CPU operation, the DMA1 request bit will be set to “1” so that the DMA controller will acquire the right to use bus and initiate transfer. When pin DMAREQ i’s input level returns to “H ”, the DMA1 request bit is cleared to “0”. This causes the DMA transfer operation to be interrupted and returns the right to use bus to the CPU.

M37920FCCGP, M37920FCCHP M37920FGCGP , M37920FGCHPPRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION MITSUBISHI MICROCOMPUTERS Fig. 74 Example of cycle steal transfer DMAREQ 0 DMA0 request bit DMA0 enable bit (CPU) DMA1 (CPU) (CPU) The above example applies on the following conditions :

DMA request sources of DMA0 and DMA1: external source
Channel priority : fixed (channel 0 > channel 1) DMA0 DMA1 DMA0DMA1 DMA1 DMAREQ 1 DMA1 request bit DMA1 enable bit DRAM refresh request Bus user DRAM refresh (2) Cycle steal transfer mode When bit 2 of the DMAi mode register L is set to “1”, the cycle steal transfer mode is selected. In the cycle steal transfer mode, be sure to select the edge sense mode. When a DMA request occurs in the cycle steal transfer mode, the corresponding DMA request bit is set to “1” as in the burst transfer mode. When the DMA request from the channel is accepted, DMA transfer starts. However, the DMA request bit is automatically cleared to “0” at the start of the first DMA transfer cycle. Therefore, if there is no DMA request from any channel when 1-transfer-unit data has been transferred, the DMA controller returns the right to use bus to the CPU. If there is a DMA request from a channel, the DMA con- troller continues to use the bus and initiates DMA transfer for the channel. In the cycle steal transfer mode, the priorities of the chan- nels are detected at all times to assure that the DMA request from a channel having the highest priority is accepted to initiate the DMA transfer execution. The DMA request bit is cleared to “0”, at each time when 1-transfer-unit data has been transferred. At this time, however, the DMA enable bit will not be cleared to “0” although the DMA request bit is cleared to “0” at each transfer of 1 transfer unit. Therefore, when the DMA request bit is set to “1” next, transfer is re- sumed at the point of interruption. When the transfer counter register’s value is “0” in the single transfer, or when both of the trans- fer counter register’s value and transfer block counter’s value are “0” in the array chain transfer, the DMA enable bit will be cleared to ”0” to terminate the whole DMA transfer operation. Figure 74 shows an example of cycle steal transfer. When pin DMAREQ i’s input level changes from “H” to “L”, the DMA1 request bit will be set to “1” and the DMA controller will acquire the right to use bus and initiate DMA transfer. The DMA1 request bit is cleared to “0” when the channel 1 transfer cycle starts. Therefore, if there is no DMA transfer request from the other channels, the DMA control- ler returns the right to use bus to the CPU at the end of 1 transfer cycle. In the example shown in Figure 74, however, DMA0 transfer cycle execution continues because the channel 0’s request bit is set to “1”. When the DMA0 transfer cycle is terminated, the DMA re- quest bits of all channels are cleared to “0” so that the DMA control- ler returns the right to use bus to the CPU. When the DMA1 request bit is set to “1”, only one cycle of transfer operation is performed. Even if the DMA1 request bit is cleared to “0” at this time, the DMA1 request bit is set to “1” again to perform continuous transfer, as long as pin DMAREQ i’s input level goes “L” before the end of the next transfer cycle. In the cycle steal transfer, the priorities of individual channels are detected at the end of each transfer cycle. Therefore, if the request is issued from channel 0, which has a higher priority than channel 1, channel 0 transfer is executed first. Furthermore, if a re- quest to use bus which has a higher priority (for example, a refresh request from the DRAM controller) is generated, this request takes the precedence.

M37920FCCGP, M37920FCCHP M37920FGCGP, M37920FGCHPPRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION MITSUBISHI MICROCOMPUTERS Priority Priorities are assigned to all DMA channels. Either the fixed or rota- tive priority can be selected. When bit 0 (priority select bit) of the DMAC control register is cleared to “0”, the fixed priority is selected. Note that the fixed priority is automatically selected after the reset removal. In the fixed priority, the channels are given fixed priorities and DMA transfer is executed in the order of priority. From high to low, the priorities are assigned to channels 0, 1, 2, and 3. As indi- cated in Figure 76, the priorities are detected at each cycle in the cycle steal transfer mode or when the first DMA request is accepted in the burst transfer mode. When bit 0 of the DMAC control register is set to “1”, the rotative pri- Fig. 75 Rotative priority Channel 0 Channel 0 Channel 1 Channel 1 Channel 3 Channel 1 Channel 1 Channel 2 Channel 2 Channel 0 Channel 2 Channel 2 Channel 3 Channel 3 Channel 1 Channel 3 Channel 3 Channel 0 Channel 0 Channel 2 (1) Before start of transfer (after reset removal) (2) After completion of channel 0’s transfer (3) After completion of channel 2’s transfer ority is selected. From high to low, the initial priorities are assigned to channels 0, 1, 2, and 3 as is the case with the fixed priority. When a DMA transfer for one channel is normally terminated with the rota- tive priority employed, the priorities are rotated in such a manner that the channel, for which transfer has just been completed, has the low- est priority. For example, when channel 0’s transfer is normally ter- minated as shown in Figure 75, the priorities are rotated upon completion of transfer so that the new priorities are, in decreasing order, channel 1, channel 2, channel 3, and channel 0. The priorities remain unchanged when DMA transfer is forcibly terminated by pin TC ’s input or the DMA enable bit clearance, etc.

M37920FCCGP, M37920FCCHP M37920FGCGP , M37920FGCHPPRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION MITSUBISHI MICROCOMPUTERS Fig. 76 Example of channel priority detection G Priority level: fixed DMA0 request bit DMA1 request bit DMA2 request bit DMA3 request bit Channel priority : 0 > 1 > 2 > 3 DMA-transfer-executing channel 120 13 (None) 021 1 03 G Priority level: rotating DMA0 request bit DMA1 request bit DMA2 request bit DMA3 request bit Channel priority DMA-transfer-executing channel 123 13 (None) 023 1 33 The above applies on the following conditions :

No DRAM refresh request, no Hold request.
All of DMAi enable bits are “1”.

M37920FCCGP, M37920FCCHP M37920FGCGP , M37920FGCHPPRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION MITSUBISHI MICROCOMPUTERS Fig. 77 Example of address directions and transfer results in 2-bus cycle transfer (1 transfer unit = 16 bits) Transfer source Address direction Transfer destination Transfer unit: 16 bits (Note) Transfer unit: 8 bits Data arrangement in transfer destination memory (transfer result) Data arrangement in transfer destination memory (transfer result) Data arrangement in transfer source memory Data arrangement in transfer source memory Transfer order Transfer order External data bus width: 16 bits or 8 bits (1) Forward (2) Forward Forward (3) Forward Backward (4) Backward Fixed High order Low order High order Low order Data 1 High order Low order Data 2 High order Low order Data 3 High order Low order Data 1 High order Low order Data 2 High order Low order Data 3 High order Low order Data 1 High order Low order Data 2 High order Low order Data 3 High order Low order Data 3 High order Low order Data 2 High order Low order Data 1 High order Low order Data 3 High order Low order Data 2 High order Low order Data 1 High order Low order Data 1 High order Low order Data 2 High order Low order Data 3 High order Low order Data 1 to 6 Data 1 Data 2 Data 3 Data 4 Data 5 Data 6 Data 1 Data 2 Data 3 Data 4 Data 5 Data 6 Data 1 Data 2 Data 3 Data 4 Data 5 Data 6 Data 1 Data 2 Data 3 Data 4 Data 5 Data 6 Data 6 Data 5 Data 4 Data 3 Data 2 Data 1 Data 6 Data 5 Data 4 Data 3 Data 2 Data 1 Fixed Data 1 to 6 Note: The relationship of position between 16-bit data’s high-order byte and its low-order byte is fixed, regardless of the address direction. (Data is transferred by the 16 bits.) Data 1 to 3 Data 1 to 3

M37920FCCGP, M37920FCCHP M37920FGCGP, M37920FGCHPPRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION MITSUBISHI MICROCOMPUTERS DMA continuous transfer (1) Single transfer mode In the single transfer mode, only the preselected number of bytes are transferred. As shown in Figure 69, first, set up the number of bits per 1 transfer unit, transfer method, transfer mode, and transfer address direction by using the DMAi mode registers L and H. Then, write the transfer source block’s first transfer address (the block’s lowest ad- dress in the forward or fixed transfer address direction, or the block’s highest address in the backward address direction) into the source address register (hereinafter referred to as SAR). Further, write the destination block’s first transfer address (the lowest address in the forward or fixed transfer address direction, or the highest address in the backward transfer address direction) into the destination address register (hereinafter referred to as DAR). Also write the desired num- ber of bytes to be transferred, into the transfer counter register (here- inafter referred to as TCR). Write the value 1 or more into TCR. Each of SAR, DAR, and TCR consists of 24 bits, therefore, be sure to write into all these bits. The SAR, DAR, and TCR are located at the ad- dresses shown in Figure 66. The next is to set a DMA source and others by the DMAi control register shown in Figure 68. Set up bit 0 (priority select bit) and bit 1 (TC pin validity bit) of the DMAC control register L shown in Figure 67, and finally set the DMAC control reg- ister H’s DMA enable bit to “1” so as to make the DMA request ac- ceptable. When the contents of TCR are cleared to “0”, the terminal count sig- nal (TC) is output, and at the same time, the interrupt request bit of the DMA interrupt control register is set to “1”. To forcedly terminate the DMA transfer, input “L” level to pin TC or write the value “0” to the DMA enable bit. At this time, the interrupt request bit of the DMA interrupt control register is not set to “1”. Figure 78 shows a timing diagram example in the single transfer mode on the following conditions:

Transfer unit: 16 bits
Transfer method: 2-bus cycle transfer
Transfer mode: Burst transfer mode (edge sense)
Transfer source address direction: Forward.
Transfer destination address direction: Forward.
Transfer source wait: 0 wait
Transfer destination wait: 0 wait As 2-bus cycle transfer mode is selected, a read operation is per- formed in the first bus cycle. First, the address written into the SAR is output to the address bus and then inputted into the incrementor/ decrementor (hereinafter referred to as I/D). The I/D adds 1 or 2 to the inputted address and outputs the result back to the SAR. If one 16-bit transfer operation is not enough to complete the read opera- tion, the read operation is performed within 2 bus cycles to achieve the purpose. The operation is performed in the next bus cycle. First, the address written in the DAR is output to the address bus and then inputted into the I/D. The I/D adds 1 or 2 to the inputted address and outputs the result back to the DAR. If one 16-bit transfer operation is not enough to complete the write operation, the write operation is performed within 2 bus cycles to achieve the purpose. The operation performed so far is called the write cycle. The data stored in the BIU’s data latch in the read cycle is output to the data bus in the write cycle and writ- ten into the destination memory or external I/O. The operations per- formed so far complete the transfer of 1 transfer unit. In the 2-bus cycle transfer, the read and write cycle combination is called the DMA transfer cycle. DMA transfer is executed by repeating the DMA transfer cycle. In the 2-bus cycle transfer, the TCR varies in the read cycle. The re- maining transfer bytes are read from the TCR in concurrence with address output from SAR in the read cycle and inputted into the decrementor (hereinafter referred to as D). The D subtracts 1 or 2 from the number of remaining bytes and outputs the result back to the TCR. In this manner, the contents of the TCR decrease each time when 1-transfer-unit data has been transferred. When the num- ber of remaining bytes, which was read from the TCR, becomes “0”, the DMA controller outputs the terminal count signal (TC) to pin TC, and at the same time, sets the interrupt request bit of the DMA inter- rupt control register to “1”. At this time, the DMA enable bit is cleared to “0”. As the burst transfer mode is selected in this example, the DMA request bit is also cleared to “0”. To forcedly terminate transfer, input “L” level to pin TC (P4 2) or write the value “0” to the DMA enable bit. In the single transfer, the first values written in the SAR, DAR, and TCR are retained in the internal latches. Therefore, if DMA transfer is to be performed under the same conditions, it can be initiated sim- ply by setting the DMA enable bit to “1”.

M37920FCCGP, M37920FCCHP M37920FGCGP , M37920FGCHPPRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION MITSUBISHI MICROCOMPUTERS Read cycle Transfer of 1 transfer unit Terminate processing sar dar sar + 2 dar + 2 sar + 4 dar + 4 Data0L Data0H Write cycle ALE RD A0–A23 D 0–D 7 DMAACK i TC BLW BHW (CPU) (CPU) G This example applies on the following conditions: Data0 Data1 Data2 Data0 Data1 Data2 L H L H L H dar dar + 5 sar sar + 5 L H L H L H D 8–D 15 Data0L Data0H Data1L Data1H Data1L Data1H Data2L Data2H Data2L Data2H External data bus width : 16 bits Transfer unit : 16 bits Transfer method : 2-bus cycle transfer Transfer source address direction : Forward Transfer destination address direction : Forward Transfer source area’s wait : 0 wait Transfer destination area’s wait sar dar Value which has been set to TCR Bus user : 0 wait : Value which has been set to SARi (even) : Value which has been set to DARi (even) : 6 : CPU → DMAC → CPU Transfer destination memory Transfer source memory Transfer Fig. 78 Timing diagram example in single transfer mode (burst transfer mode)

M37920FCCGP, M37920FCCHP M37920FGCGP, M37920FGCHPPRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION MITSUBISHI MICROCOMPUTERS (2) Repeat transfer mode In the repeat transfer mode, the single transfer is repeated. First, set up the number of bits per 1 transfer unit, transfer method, transfer mode, and transfer address direction by using the DMAi mode regis- ter L. Next, write the transfer source block’s transfer start address in the SAR and the transfer destination block’s transfer start address in the DAR. Further, write the desired number of bytes to be trans- ferred, into the TCR, and set up the DMAi control register and DMAC control register. The DMA request is now acceptable. When the DMA request occurs in this state, DMA transfer starts. Even when the number of remaining bytes, which was read from the TCR, becomes 0, the DMA enable bit is not cleared to “0”. When the burst transfer mode is selected, the DMA request bit is not cleared to “0”, also. When the cycle steal transfer mode is selected, the DMA request bit is cleared to “0” each time when 1-transfer-unit data has been trans- ferred. Fig. 79 Timing diagram example in repeat transfer mode (burst transfer mode) ALE RD DMAACK i TC sar dar sar + 4 dar + 4 sar dar H BLW BHW (CPU) Data0 Data1 Data2 L H L H L H sar sar + 5 Data0 Data1 Data2 dar dar + 5 L H L H L H A0–A23 D 0–D 7 D 8–D 15 Transfer of 1 transfer unit Data0L Data0H Data0L Data0H Data2L Data2H Data2L Data2H Data0L Data0H G This example applies on the following conditions: External data bus width : 16 bits Transfer unit : 16 bits Transfer method : 2-bus cycle transfer Transfer source address direction : Forward Transfer destination address direction : Forward Transfer source area’s wait : 0 wait Transfer destination area’s wait sar dar Value which has been set to TCR Bus user : 0 wait : Value which has been set to SARi (even) : Value which has been set to DARi (even) : 6 : CPU → DMAC Transfer destination memory Transfer source memory Transfer Transfer of entire data (first) Transfer of entire data (second) The values written in the SAR, DAR, and TCR first are retained in the internal latches. The contents of the latches are transferred to the SAR, DAR and TCR at the end of the last transfer cycle. Therefore, when the burst transfer mode is selected, the transfer operation is re- peated starting with the values written first. When the cycle steal transfer mode is selected, these values are used as the initial values and transfer is performed each time the DMA request bit is set to “1”. To forcedly terminate transfer, input “L” level to the pin TC or write the value “0” to the DMA enable bit. In the repeat transfer mode, TC signal output and the setting the in- terrupt request bit of the DMA interrupt control register to “1” are not performed. Figure 78 shows the timing diagram example in the repeat transfer mode.

M37920FCCGP, M37920FCCHP M37920FGCGP, M37920FGCHPPRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION MITSUBISHI MICROCOMPUTERS In the array chain transfer, the transfer parameters are first read from the transfer parameter memory and then written into the SAR, DAR, and TCR. This operations state is called the “array state”. Figures 83 and 84 show timing diagram examples in the array chain transfer mode (burst transfer mode). The DMA controller outputs the start ad- dress of the transfer parameter memory to the address bus, and se- quentially stores the read data into the SAR, DAR, and TCR. When the transfer parameters for 1 block are completely stored, the contents of the TBC are decremented by 1, and then, the first DMA transfer starts in accordance with the stored parameters. These op- erations for storing parameters are called “array state”. In contrast to the array state, the state in which DMA transfer is ac- tive is called “transfer state”. In the transfer state, the same opera- tions are performed as in the single transfer mode. Each time when 1-transfer-unit data has been transferred, the contents of the TCR are decremented by 1 in 8-bit transfer or by 2 in 16-bit transfer. Even when the contents of the TCR become 0, the DMA request bit and DMA enable bit are not cleared to “0” and the array state of the next block starts. When the contents of the TBC are 0 at the start of the array state, the entire transfer operation is considered to be completed, and “L” level is output into pin TC to clear the DMA request bit and DMA en- able bit and terminate array chain transfer. At the same time, the in- terrupt request bit of the DMA interrupt control register is set to “1”. In the cycle steal transfer at the array chain transfer mode, one array state and transfer cycle of 1 transfer unit are made by one DMA re- quest.

M37920FCCGP, M37920FCCHP M37920FGCGP , M37920FGCHPPRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION MITSUBISHI MICROCOMPUTERS Fig. 83 Timing diagram example in array chain transfer mode (burst transfer mode) (1) Fig. 84 Timing diagram example in array chain transfer mode (burst transfer mode) (2) ALE RD A0–A23 D 0–D 7 D 8–D 15 DMAACK i TC BLW BHW G This example applies on the following conditions: G The Bus request caused by DRAM refresh or Hold is sampled while the bus request sampling signal is “1”, and is accepted. External data bus width Transfer unit Transfer method Transfer source address direction Transfer destination address direction Transfer source area’s wait Transfer destination area’s wait Transfer parameter memory’s wait sa1, sa2, da1, da2 tp Transfer block’s number Bus user : 16 bits : 16 bits : 2-bus cycle transfer : Forward : Forward : 1 wait : 1 wait : 0 wait : Transfer parameters (even) : Start address of first block’s transfer parameter memory : 2 : CPU → DMAC → CPU Memory Memory First block transfer Second block transfer Memory sa1 da1 m sa2 da2 n tp First block’s transfer parameters Second block’s transfer parameters tp + 4 tp + 8 tp + 12 tp + 16 tp + 20 sa1 sa1 + m - 1 sa1 + m sa2 + n - 1 sa2 + n sa2 da1 da1 + m - 1 da1 + m da2 + n - 1 da2 + n da2 Continue to Figure 84. tp tp + 2 tp + 4 tp + 6 tp + 8 tp + 10 sa1 da1 H Transfer of 1 transfer parameter Array state sa1H da1L da1H m L m H Transfer of 1 transfer unit Transfer state DataL DataH DataL DataH sa1L sa1M Dummy data Dummy data Dummy datada1M m M da1 + m - 2(CPU) DataL DataH Array state Transfer state Terminate Processing tp + 12 tp + 20 da2 + n - 4 sa2 + n - 2sa2 From proceeding Figure 83. tp + 22 ALE RD BLW BHW da2 + n - 2 (CPU)A0–A23 D 0–D 7 D 8–D 15 DMAACK i TC nL nH nM sa2L DataL DataH DataL DataH DataL DataH DataL DataHsa2M Dummy data

M37920FCCGP, M37920FCCHP M37920FGCGP, M37920FGCHPPRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION MITSUBISHI MICROCOMPUTERS (4) Link array chain transfer mode Figure 85 shows the perameter memory map in the link array chain transfer mode. As shown in this figure, not only the transfer source’s transfer start address, transfer destination’s transfer start address, and number of transfer bytes, but also the start address of the memory block which contains the next transfer parameters is stored. In the transfer parameter of the last block, be sure to set “00000016” as the start address of the next transfer parameter. For 1-bus cycle transfer, the external I/O side’s parameters are not needed. In the link array chain transfer, also, the DMAi mode registers L and H, DMAi control register, and DMAC control registers L and H must be set up. Into the SAR, write the start address of the memory block that stores the parameters for the first transfer. This value is then written into the TPR. Be sure that an even-numbered address is set to the start address. Nothing needs to be written in the DAR. Write the value 1 or more into the TCR. When the DMA enable bit is set to “1“ after completion of the above setup, DMA transfer becomes enabled. In the link array chain transfer, the transfer parameters are first read from the transfer parameter memory and then written into the SAR, DAR, and TCR. Further, the start address of the memory block that contains the next parameters has been written into the TPR. In the link array chain transfer mode, the state so far is referred to as the array state. The DMA controller sequentially outputs the transfer parameters to the address bus, beginning with the start address of the memory block, storing the transfer parameters. The read data are sequen- tially stored into the SAR, DAR, and TCR, and then the start address of the memory block, containing the next parameters, is written into the TPR. A DMA transfer is made in accordance with the parameters read from the transfer parameter memory. The transfer state is the same as in the single transfer mode. The contents of the TCR are decremented by 1 or 2 each time when 1-transfer-unit data has been transferred. Even when the contents of the TCR become 0, the DMA request bit and DMA enable bit are not cleared to “0” but the array state starts again. When the contents of the TPR are 0 at this time, however, “L” level is output into pin TC to clear the DMA request bit and DMA en- able bit to “0” and terminate the link array chain transfer. At the same timing, the interrupt request bit of the DMA interrupt control register is set to “1”. In the cycle steal transfer at the link array chain transfer mode, one array state and the transfer cycle of 1 transfer unit are made by one DMA request. Figures 86 and 87 show timing diagram examples in the link array chain transfer mode (burst transfer mode). Fig. 85 Parameter memory map example in link array chain trans- fer mode Transfer source’s transfer start address 1 Transfer destination’s transfer start address 1 Number of transfer bytes 1 Transfer parameter address 2 Transfer source’s transfer start address 4 Transfer destination’s transfer start address 4 Number of transfer bytes 4 Transfer parameter address 5 Transfer parameters for 1 block Transfer parameter address 4 Transfer source’s transfer start address 3 Transfer destination’s transfer start address 3 Number of transfer bytes 3 Transfer parameter address 4 Transfer parameter address 3 Transfer source’s transfer start address 2 Transfer destination’s transfer start address 2 Number of transfer bytes 2 Transfer parameter address 3 Transfer parameter address 2

M37920FCCGP, M37920FCCHP M37920FGCGP , M37920FGCHPPRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION MITSUBISHI MICROCOMPUTERS Fig. 86 Timing diagram example in link array chain transfer mode (burst transfer mode) (1) Fig. 87 Timing diagram example in link array chain transfer mode (burst transfer mode) (2) tp1 tp1 + 2 tp1 + 4 tp1 + 6 tp1 + 8 H H H tp1 + 10 (tp1+8)M tp1 + 12 Continue to Figure 87. tp1 + 14 (tp1 sa1 sa1 + m - 1 sa1 + m sa2 + n - 1 sa2 + n sa2 da1 da1 + m - 1 da1 + m da2 + n - 1 da2 + n da2 Memory Memory Memory sa1 da1 m tp2 sa2 da2 n 00000016 tp1 tp1 + 4 tp1 + 8 tp1 + 12 tp2 tp2 + 4 tp2 + 8 tp2 + 12 (CPU) ALE RD A0–A23 D 0–D 7 D 8–D 15 DMAACK i TC BLW BHW sa1H da1L da1H m L m H tp2L tp2H tp2M sa1L sa1M Dummy data Dummy data Dummy data Dummy datada1M m M Transfer of 1 transfer parameter Array state G This example applies on the following conditions: External data bus width Transfer unit Transfer method Transfer source address direction Transfer destination address direction Transfer source area’s wait Transfer destination area’s wait sa1, sa2, da1, da2 tp1 Transfer block’s number Bus user : 16 bits : 16 bits : 2-bus cycle transfer : Forward : Forward : 0 wait : 0 wait : Transfer parameters (even) : Start address of first block’s transfer parameter memory : 2 : CPU → DMAC → CPU First block’s transfer parameter Second block’s transfer parameter First block transfer Second block transfer sa1 da1 + m - 2 tp2 tp2 + 14 sa2da1 da2 + n - 4 From preceding Figure 86. sa2 + n - 2 da2 + n - 2 0016 (CPU) ALE RD BLW BHW A0–A23 D 0–D 7 D 8–D 15 DMAACK i TC DataL DataH DataL DataH DataL DataH DataL DataH DataL DataH DataL DataH DataL DataH sa2L sa2M Dummy data Array stateTransfer state Transfer state Transfer of 1 transfer unit Terminate processing

Notice: This is not a final specification. Some parametric limits are subject to change. Table 19. Functions of DRAM-related signals Table 20. Relationship between external data bus width and multiplexed addresses “L” when a column address at an odd-numbered address is output. “L” when a row address is output. “L” when a column address at an even-numbered address is output. “L” when a row address is output. “L” when data at an even-numbered address is written.“L” when data is written. : These signals are not used.

M37920FCCGP, M37920FCCHP M37920FGCGP, M37920FGCHPPRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION MITSUBISHI MICROCOMPUTERS Fig. 89 Bit configuration of CSj control register L with use of DRAM controller (j = 1 to 3) Area CSj wait number select bits 0 1 : 1 wait Address 8216 8416 8616 CS j output select bit 1 : CSj output is enabled. (Port pin P9j functions as pin CSj. RAS output is enabled.) Note: In order to use the DRAM controller, setup for bits 0, 1, 4 to 7 are necessary as above. 10101 0 External data bus width select bit 0 : 16-bit width 1 : 8-bit width Invalid. (It may be “0” or “1”.) DRAM space designation select bit 1: DRAM space Burst ROM access select bit 0 : Normal access Recovery cycle insert select bit 0 : No recovery cycle is inserted at access to area CS X

Notice: This is not a final specification. Some parametric limits are subject to change. Table 21. Relationship between byte control select bit and pin functions Note: When the external data bus width = 8 bits, be sure to set this bit to “0” (1CAS/2W). The value is “0” at reading. The value is “0” at reading. The value is “0” at reading.

M37920FCCGP, M37920FCCHP M37920FGCGP, M37920FGCHPPRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION MITSUBISHI MICROCOMPUTERS Fig. 91 Operating waveform example of DRAM control signals, address bus, and data buses with 1CAS/2W selected Operating waveform example when 16-bit data is accessed with the external data bus width = 16 bits, starting at an even-numbered address Column D 0–D 7 D 8–D 15 RAS j(CSj) CAS WRL At reading At writing Row addressaddress WRH Address RD (odd) RD (even) WD (even) WD (odd) (Note) Note: When DRAM is continuously accessed with the fast page access OFF, 1 cycle of φ1 will be inserted between bus cycles. Row address Columnaddress Fig. 92 Operating waveform example of DRAM control signals, address bus, and data buses with 2CAS/1W selected Operating waveform example when 16-bit data is accessed with the external data bus width = 16 bits, starting at an even-numbered address RAS j(CSj) W LCAS UCAS Address (Note) Note: When DRAM is continuously accessed with the fast page access OFF, 1 cycle of φ1 will be inserted between bus cycles. D 0–D 7 D 8–D 15 address Row Columnaddress Row address Columnaddress RD (odd) RD (even) WD (even) WD (odd) At reading At writing

M37920FCCGP, M37920FCCHP M37920FGCGP , M37920FGCHPPRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION MITSUBISHI MICROCOMPUTERS Fig. 95 Operating waveform example of DRAM control signals at self-refresh RAS j H CAS W Refresh cycle(Preceding bus cycle) Bus request (DRAMC) sampled j = 1 to 3 (Next bus cycle) RAS j CAS Value of watchdog timer 7FF16 Interrupt request to be used for stop mode termination (Interrupt request bit) FFF16 Wf32 ✕ 2048 counts Stop mode φBIU f(XIN) Refresh cycle (Interrupt request which has been used for stop mode termination) (Preceding bus cycle) W H Fig. 94 Operating waveform example of DRAM control signals at CAS before RAS refresh

M37920FCCGP, M37920FCCHP M37920FGCGP, M37920FGCHPPRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION MITSUBISHI MICROCOMPUTERS REAL-TIME OUTPUT Each of these microcomputers is equipped with the 8-bit real-time output function. Whether to use the real-time output function is decided by the wave- form output select bits of the 8-bit real-time output control register (bits 0 and 1 at address A0 16). (See Figure 96.) Also, the real-time output controlled by the pulse output mode select bit of the real-time output control register (bit 2 at address A0 16) and is used in one of the following ways:

4 bits ✕ 2 channels
6 bits ✕ 1 channel + 2 bits ✕ 1 channels (1) Pulse mode 0 When the pulse output mode select bit is cleared to “0”, the micro- computer enters pulse output port is controlled by 2 groups of 4 bits. Figures 97 and 98 show the pulse output data register 0/1 (address 16/A416) bit configuration and real-time output structure in pulse mode 0, respectively. When the waveform output select bits are set to “01” (bit 1 = “0” and bit 0 = “1”), RTP03 to RTP00 become pulse output port pins, in other words, RTP0 is selected. When the waveform output select bits are set to “10” (bit 1 = “1” and bit 0 = “0”), RTP1 3 to RTP10 become pulse output port pins, in other words, RTP1 is selected. When the waveform output select bits are set to “11” (bit 1 = “1” and bit 0 = “1”), two groups consisting of RTP13 to RTP10 and RTP03 to RTP0 0 become pulse output port pins, in other words, RTP1 and RTP0 are selected. When the waveform output select bits are set to “00” (bit 1 = bit 0 = “0”), port P5 pins become normal programmable I/O port pins. The contents of the pulse output data register 1 (high-order 4 bits at address A4 16), which corresponds to RTP13 to RTP10, is output to these ports each time when the contents of timer A1 counter be- comes “0000 16”. The contents of the pulse output data register 0 Fig. 96 Bit configuration of real-time output control register Fig. 97 Bit configuration of pulse output data register Real-time output register A016 Waveform output select bits 00 : Programmable I/O port 01 : RTP0 selected When pulse mode 0 is selected: RTP0 When pulse mode 1 is selected: RTP0 1, RTP00 10 : RTP1 selected When pulse mode 0 is selected: RTP1 When pulse mode 1 is selected: RTP1, RTP0 3, RTP02 11 : RTP1 and RTP0 selected When pulse mode 0 is selected: RTP1 and RTP0 When pulse mode 1 is selected: RTP1, RTP0 3, RTP0 2 and RTP01, RTP0 0 Pulse output mode select bit 0 : Pulse mode 0 1 : Pulse mode 1 “0” at read.

Note 1: Used only in pulse mode 0 2: Used only in pulse mode 1 Pulse output data register 0 RTP0 0 pulse output data bit RTP0 1 pulse output data bit RTP0 2 pulse output data bit (Note 1) RTP0 3 pulse output data bit (Note 1) A216 Pulse output data register 1 RTP0 2 pulse output data bit (Note 2) RTP0 3 pulse output data bit (Note 2) RTP1 0 pulse output data bit RTP1 1 pulse output data bit RTP1 2 pulse output data bit RTP1 3 pulse output data bit (low-order 4 bits at address A216), which corresponds to RTP03 to RTP0 0, is output to these ports each time when the contents of timer A0 counter becomes “000016”. When “0” is written to a specified bit of the pulse output data register, a low-level signal is output to a pulse output port if the counter con- tents of the timer which corresponds to the bit becomes “000016”: when “1” is written to the bit, a high-level signal is output to a pulse output port which corresponds to the bit at the same timing.

M37920FCCGP, M37920FCCHP M37920FGCGP , M37920FGCHP PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION MITSUBISHI MICROCOMPUTERS Fig. 98 Real-time output structure in pulse mode 0 (2) Pulse mode 1 When the pulse output mode select bit is set to “1”, the microcom- puter enters pulse mode 1, and a pulse output port pins are sepa- rately controlled (6 bits and 2 bits). Figure 99 shows the real-time output structure in pulse mode 1. When the waveform output select bits are set to “01” (bit 1 = “0” and bit 0 = “1”), RTP1 3 to RTP10, RTP03, and RTP02 become program- mable I/O port pins. Simultaneously, RTP01 and RTP00 become pulse output port pins. When the waveform output select bits are set to “10” (bit 1 = “1” and bit 0 = “0”), RTP1 3 to RTP10, RTP03, and RTP02 become pulse out- put port pins. At this time, RTP01 and RTP00 become programmable I/O port pins. When the waveform output select bits are set to “11” (bit 1 = bit 0 = T DQ DQ DQ DQ T DQ DQ DQD 6 D 5 D 4 D 3 D 2 D 1 D 0 Timer A0 Timer A2 P53/RTP03 P52/RTP02 P51/RTP01 P50/RTP00 Port P5i latch Waveform output select bit (Address A016) bit 1 Pulse output data register 0 (Address A216) Pulse output data register 1 (Address A416) Data bus (Even) Pulse output mode select bit (Address A0 16) 0 D 7 T T T DQ T T T a a a a a a a a Waveform output select bit (Address A016) bit 0 P57/RTP13 P56/RTP12 P55/RTP11 P54/RTP10 Port P5i direction register “1” “0”(i = 7 to 0) a (Address D16) (Address B16) “1”), pulse output port pins are divided into two groups; one consists of RTP13 to RTP10, RTP03, RTP02 and the other consists of RTP01 and RTP00. When the waveform output select bits are set to “00” (bit 1 = bit 0 = “0”), port P5 pins become normal programmable I/O port pins. RTP1 3 to RTP10, RTP03, and RTP02 are controlled by timer A2. Also, RTP01 and RTP00 are controlled by timer A0. The contents of the pulse output data register 1 (high-order 6 bits at address A416), which corresponds to RTP13 to RTP10, RTP03, and RTP0 2, are output to this port each time when the contents of timer A2 counter becomes “000016”. The contents of the pulse output data register 0 (low-order 2 bits at address A216), which corresponds to RTP0 1 and RTP00, are output to this port each time when the con- tents of timer A0 counter become “000016”.

Notice: This is not a final specification. rection registers are set to the output mode. mode, and port P5i (i = 0 to 7) pins function as normal I/O port pins. sponding bits of the port P5 direction register to the output mode. P5 register, output level of pins can be read out. Table 22. Port P5/RTP pin output

M37920FCCGP, M37920FCCHP M37920FGCGP , M37920FGCHP PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION MITSUBISHI MICROCOMPUTERS Watchdog timer frequency select bit Writing to watchdog timer register Watchdog timer “FFF16” is set. 1/16 Wf32 Wf512 HLDA Wait mode DMA transfer Watchdog timer interrupt request Access to external area RESET STP instruction 0 ❈ External clock input select bit

Watchdog timer register : address 6016
Watchdog timer frequency select register : bit 0 at address 6116 ❈ When the most significant bit of the watchdog timer becomes “0”, this signal will be generated. At the STP instruction execution, however, Wf32 is selected compulsorily. Disables watchdog timer WATCHDOG TIMER The watchdog timer is used to detect unexpected execution se- quence caused by software runaway and others. Figure 100 shows the block diagram of the watchdog timer. The watchdog timer consists of a 12-bit binary counter. The watchdog timer counts clock Wf 32, which is obtained by dividing the peripheral devices’ clock f2 by 16; or clock Wf512, which is ob- tained by doing it by 256. The watchdog timer frequency select reg- ister (bit 0 = watchdog timer frequency select bit) shown in Figure 101 selects which clock is to be counted. Wf 512 is selected when this bit 0 is “0”, and Wf32 is selected when this bit 0 is “1”. This bit 0 is cleared to “0” after reset. FFF 16 is set in the watchdog timer when “L” level voltage is applied to pin RESET, STP instruction is executed, data is written to the watchdog timer register (address 60 16), or the most significant bit of the watchdog timer becomes “0”. After FFF 16 is set in the watchdog timer, when the watchdog timer counts Wf32 or Wf512 by 2048 counts, the most significant bit of watchdog timer becomes “0”, the watchdog timer interrupt request bit is set to “1”, and FFF 16 is set again in the watchdog timer. In program coding, make sure that data is written in the watchdog timer before the most significant bit of the watchdog timer becomes “0”. If this routine is not executed owing to unexpected program ex- ecution or others, the most significant bit of the watchdog timer be- Fig. 100 Block diagram of watchdog timer Fig. 101 Bit configuration of watchdog timer frequency select register 76543210 Watchdog timer frequency select register Watchdog timer frequency select bit 0 : Wf512 is selected. 1 : Wf32 is selected.

comes “0” and an interrupt is generated. The microcomputer can generate a reset pulse by writing “1” to bit 6 (software reset bit) of processor mode register 0 in an interrupt rou- tine and can be restarted. The watchdog timer can also be used to return from the STP state, where a clock has stopped its operation owing to the STP instruction execution. For details, refer to the sections on the clock generating circuit. The watchdog timer stops its operation in the following cases, and at this time, input to the watchdog timer is disabled:

When the external area is accessed in the hold state
In the wait mode
In the stop mode

M37920FCCGP, M37920FCCHP M37920FGCGP, M37920FGCHPPRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION MITSUBISHI MICROCOMPUTERS 102 How to disable watchdog timer When not using the watchdog timer, it can be disabled. When the watchdog timer is disabled, it’s operation stops and no watchdog timer interrupt has been generated. Setting for disabling the watchdog timer is possible by writing “79 16” and “5016” to the particular function select register 2 (address 6416) sequentially with the following instructions:

MOVMB/STAB instruction, or
MOVM/STA instruction (m = 1) If any method other than above has been adopted in order to access (in other words, read/write) the particular function select register 2, the watchdog timer will not be disabled until reset operation is per- formed. (Also, reset is the only one method to remove the setting for disabling the watchdog timer.)

Notice: This is not a final specification. of an interrupt request or reset. or WIT instruction will be executed. dates the STP instruction, and the STP instruction will be ignored. the STP instruction is valid. cleared to “0” by software at termination of the STP or the WIT mode. watchdog timer frequency select bit. I/O communication is active only while an external clock is selected. vide clocks f1(φ) to f4096, Wf32 and Wf512 is also restarted. tion-stabilizing time has elapsed. section on “Stop of oscillation circuit” of the power saving function. Timers A, B, Serial I/O, A-D converter: Operation is enabled. DRAM controller: Reflesh timer is operated. Timers A, B: Operation is enabled only in the event counter mode. A-D converter, DMA controller: Stopped. DRAM controller: Reflesh timer is operated. Timers A, B: Operation is enabled only in the event counter mode. A-D converter, DMA controller: Stopped. Table 23. Microcomputer’s operation in STP and WIT modes

M37920FCCGP, M37920FCCHP M37920FGCGP, M37920FGCHPPRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION MITSUBISHI MICROCOMPUTERS 104 Fig. 103 Bit configuration of particular function select register 1 76543210 Particular function select register 1 STP-instruction-execution status bit (Note 1) 0: Normal operation. 1: STP instruction has been executed. WIT-instruction-execution status bit (Note 1) 0: Normal operation. 1: WIT instruction has been executed. Standby state select bit 0: External bus 1: Programmable I/O port Internal clock stop select bit at WIT (Note 2) 0: In wait mode, internal peripheral devices’ operation clock is active. 1: In wait mode, internal peripheral devices’ operation clock is stopped. “0” at read. Address Notes 1: At power-on reset, this bit becomes “0”. At hardware reset or software reset, this bit retains the status just before reset. Even when “1” is written, the bit status will not change. 2: Setting this bit to “1” must be performed just before execution of the WIT instruction. Also, after the WIT state is terminated, this bit must be cleared to “0” immediately. Fig. 102 Bit configuration of particular function select register 0 76543210 Particular function select register 0 External clock input select bit (Note) 0: Oscillation circuit is active. (Oscillator is connected.) Watchdog timer is used at stop mode termination. 1: Oscillation circuit is inactive. (Clock which is generated in the external is input.) Watchdog timer is not used at stop mode termination. “0” at read. STP instruction invalidity select bit 0: STP instruction is valid. 1: STP instruction is invalid. Address Note: Writing to these bits requires the following procedure:

Write “5516” to this register. (The bit status does not change only by this writing.)
Succeedingly, write “0” or “1” to each bit. troller is operating, DRAM reflesh is performed. Note that the watch- dog timer is stopped. On the other hand, when the WIT instruction is executed with the in- ternal clock stop select bit at WIT = “1”, the oscillation circuit is oper- ating, while φBIU, φCPU , and divide clocks f1(φ) to f4096 stop operating. As a result, the A-D converter, DMA controller, and watchdog timer, which use divide clocks f1(φ) to f4096, Wf32 and Wf512, are stopped. Because the reflesh timer of the DRAM controller is operating, DRAM reflesh is performed. At this time, timers A and B operate only in the event counter mode, and serial I/O communication is active only while an external clock is selected. If the internal peripheral de- vices are not used in the WIT mode, the latter is better because the current dissipation is more saved. Note that the internal clock stop select bit at WIT is to be set to “1” immediately before execution of the WIT instruction and cleared to “0” immediately after the WIT mode is terminated. The WIT state is terminated by acceptance of an interrupt request, and then, supply of φBIU and φCPU will restart. Since the oscillation circuit is operating in the WIT mode, an interrupt processing can be executed just after the WIT mode termination.

Notice: This is not a final specification. bus control signals become valid. Table 24. Correspondence between external buses, bus control sig- standby state select bit’s contents. dissipation of the microcomputer can be saved. For details, refer to the section on the Stop and Wait modes.

the external clock input select bit (bit 1 of the particular function select register 0) = “1”.
the oscillation driver circuit between pins X IN and XOUT stops its operation. At this time, the output level at pin XOUT is fixed to “H ”. When the STP mode is terminated by an interrupt request occurrence, the watch- dog timer is not used. Therefore, an instruction can be executed just after the termination of the STP mode. For details, refer to the sec- tion on the clock generating circuit and stop and wait modes. (4) Disconnection from pin VREF When not using the A-D converter, by setting the VREF connection select bit (bit 6 of the A-D control register 1) to “1”, the ladder network of the A-D converter will be disconnected from the reference voltage input pin (VREF ). In this case, no current flows from pin VREF to the ladder network, and the power dissipation can be saved. Note that, after the V REF connection select bit changes from “1” (VREF discon- nected) to “0” (VREF connected), be sure that the A-D conversion starts a period of 1 µs or more has elapsed. For details, refer to the section on the A-D converter.

M37920FCCGP, M37920FCCHP M37920FGCGP, M37920FGCHPPRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION MITSUBISHI MICROCOMPUTERS 106 Fig. 104 Microcomputer internal register’s status just after reset (1) (0416)··· Address Port P0 direction register 00 16 (0516)···Port P1 direction register (0816)···Port P2 direction register (0916)···Port P3 direction register (1516)···Port P9 direction register 0016 (0C 16)···Port P4 direction register (0D 16)···Port P5 direction register 00 16 (1016)···Port P6 direction register (1116)···Port P7 direction register (1416)···Port P8 direction register (5616)···Timer A0 mode register 00 16 (5716)···Timer A1 mode register 00 16 (5816)···Timer A2 mode register 00 16 (5916)···Timer A3 mode register 00 16 (5A16)···Timer A4 mode register 00 16 (1816)···Port P10 direction register 00 16 (1916)···Port P11 direction register 00 16 Notes 1: The contents of the other registers and RAM are undefined at reset and must be initialized by software. 2: The status just after reset depends on the voltage level applied to pin MD0. 3: At power-on reset, these bits are clear to “0”. At hardware or software reset, on the other hand, these bits retain the state just before reset. 00000 ???(1E16)···A-D control register 0 0000 001(1F16)···A-D control register 1 100 000(3416)···UART 0 Transmit/Receive control register 0 100 000(3C 16)···UART 1 Transmit/Receive control register 0 00000 010(3516)···UART 0 Transmit/Receive control register 1 00000 010(3D 16)···UART 1 Transmit/Receive control register 1 00 000(4216)···One-shot start register 00(4516)···Timer A clock division select register (1C 16)···Port P12 direction register (3016)···UART 0 Transmit/Receive mode register 0016 (3816)···UART 1 Transmit/Receive mode register 0016 00000 000(4416)···Up-down register (4016)···Count start register 00 16 00?0 000(5B16)···Timer B0 mode register 00?0 000(5C 16)···Timer B1 mode register 00?0 000(5D 16)···Timer B2 mode register 1000(Note 2) 0 (Note 2) 0(5E16)···Processor mode register 0 (5F16)···Processor mode register 1 (6016)··· Address Watchdog timer (Note 3) 0 0 000 0000 FFF 16 (6116)···Watchdog timer frequency select register (6216)···Particular function select register 0 (6316)···Particular function select register 1 (6616)···Debug control register 0 (6716)···Debug control register 1 INT2 interrupt control register Processor status register PS 0016 0016 Program bank register PG Contents at address FFFF16Program counter PCH Contents at address FFFE16Program counter PCL 000016 (6E16)···INT3 interrupt control register (6F16)···INT4 interrupt control register 0000 ?000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 (72 16)···UART 0 receive interrupt control register (7316)···UART 1 transmit interrupt control register (7416)···UART 1 receive interrupt control register (7716)···Timer A2 interrupt control register (7816)···Timer A3 interrupt control register (7916)···Timer A4 interrupt control register (7A16)···Timer B0 interrupt control register 000 000 (7C 16)···Timer B2 interrupt control register 000 (7E16)···INT1 interrupt control register (7016)···A-D conversion interrupt control register (7116)···UART 0 transmit interrupt control register (7516)···Timer A0 interrupt control register (7616)···Timer A1 interrupt control register 000 000 (7D 16)···INT0 interrupt control register (7B16)···Timer B1 interrupt control register Direct page registers DPR0 to DPR3 (7F16)··· 000 1??000??000 Data bank register DT 0016 (Note 2)0 (Note 2) 100 0 (Note 3) 0000 00 000 0000 000 0000 0000 000 0000 000 FFF 16Stack pointer 000 (Note 3)(Note 3)

M37920FCCGP, M37920FCCHP M37920FGCGP , M37920FGCHP PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION MITSUBISHI MICROCOMPUTERS Fig. 105 Microcomputer internal register’s status just after reset (2) (8016)··· Address CS 0 control register L (8116)···CS 0 control register H (8216)···CS 1 control register L (8316)···CS 1 control register H (8C 16)···Area CS1 start address register (8416)···CS 2 control register L (8516)···CS 2 control register H (8616)···CS 3 control register L (8716)···CS 3 control register H (8A16)···Area CS0 start address register (DC 16)···DMA1 mode register L (DD 16)···DMA1 mode register H (DE 16)···DMA1 control register (EC 16)···DMA2 mode register L (ED 16)···DMA2 mode register H (8E16)···Area CS2 start address register (9016)···Area CS3 start address register Notes 1: The contents of the other registers and RAM are undefined at reset and must be initialized by software. 2: The status just after reset depends on the voltage level applied to pin MD0. 3: While Vss level voltage is applied to pin BYTE, these bits are “0”. While Vcc level voltage is applied to pin BYTE, on the other hand, these bits are “1”. 00000(A816)···DRAM control register (B216)···DMA0 interrupt control register 0000(B316)···DMA1 interrupt control register 0000(B416)···DMA2 interrupt control register (CC 16)···DMA0 mode register L 000(CE 16)···DMA0 control register (A016)···Real-time output control register (AC 16)···CTS/RTS separate select register (B016)···DMAC control register L 0000 000 0(CD 16)···DMA0 mode register H (B516)···DMA3 interrupt control register 00 000(EE 16)···DMA2 control register (FC 16)···DMA3 mode register L (FD 16)···DMA3 mode register H (FE 16)··· Address DMA3 control register 000 0000 000 0 010(Note 2) (Note 3) 10 01000 (Note 3) 10 01000 (Note 3) 10 01000 (Note 3) 10 000 0000 0000 0000 000 0 000000 0000 000 0 000 000 00010 000 00000 000 00000 000 00000 000 00000 000 00000000 00000000 00000000 0 0 00 00000 0 001 0 000 0 000 000 00000 000 00000 000 (9E16)···Flash memory control register 000 001 000 000(B116)···DMAC control register H 00 RESET CIRCUIT While the power source voltage satisfies the recommended operat- ing condition, reset state is removed if pin RESET’s level returns from the stabilized “L” level to the “H ” level. As a result, program ex- ecution starts from the reset vector address. This reset vector ad- dress is expressed as shown below:

A 23 to A16 = 0016
A15 to A8 = Contents at address FFFF16
A7 to A0 = Contents at address FFFE16 Figures 104 and 105 show the microcomputer internal register’s sta- tus just after reset, and Figure 106 shows an operation example of the reset circuit. Apply “L” level voltage to pin RESET for a period (2 µs or more) under the following conditions:
Pin Vcc’s level satisfies the recommended operating condition.
Oscillator’s operation has been stabilized. Fig. 106 Operation example of reset circuit (Note that proper evalu- ation is necessary in the system development stage.) VCC RESET Power on VCC level 0.2VCC level Oscillation stabilized 2 µs f(XIN)

M37920FCCGP, M37920FCCHP M37920FGCGP, M37920FGCHPPRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION MITSUBISHI MICROCOMPUTERS 108 INPUT/OUTPUT PINS Each of ports P0 to P12 has an direction register, and each bit can be programmed for input or output. A pin becomes an output pin when the corresponding bit of direction register is “1”, and an input pin when it is “0”. When a pin is programmed as an output pin, the data written to its port latch is output to the output pin. When a pin is programmed as an output pin, the contents of the port latch are read out instead of the value of the pin. Accordingly, a previously output value can be read out correctly even when the output “H ” voltage is lowered or the output “L” voltage is raised, owing to an external load, etc. A pin programmed as an input pin is placed in the flooting state, and the value input to the pin can be read out correctly. When a pin is pro- grammed as an input pin, the data can be written only in the port latch, and the pin remains floating. Each of Figures 107 and 108 shows the block diagram for each port pin.

M37920FCCGP, M37920FCCHP M37920FGCGP , M37920FGCHPPRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION MITSUBISHI MICROCOMPUTERS Fig. 107 Block diagram for each port pin (1) [Inside dotted-line not included] P00 to P07, P10 to P17, P20 to P27, P31 to P33, P100 to P107, P110 to P117 [Inside dotted-line included] P30/RDY, P43/HOLD, P61/TA1IN/DMAREQ 0, P63/TA3IN/DMAREQ 1, P65/TA4IN/DMAREQ 2, P66/DMAREQ 3, P81/RxD1, P85/RxD0, P120/INT0/TB0IN, P121/INT1/TB1IN, P122/INT2/TB2IN Data bus Direction register Port latch P40/ALE, P41/φ1, P44/HLDA, P60/TA1OUT /DMAACK 0, P62/TA3OUT /DMAACK 1, P64/TA4OUT /DMAACK 2, P80/TxD1, P84/TxD0, P90/CS0, P91/CS1/RAS1, P92/CS2/RAS2, P93/CS3/RAS3, P94/CAS/W, P95/WRL/LCAS, P96/WRH/UCAS Data bus Direction register Port latch “1” Output (Internal peripheral devices) [Inside dotted-line not included] P52/RTP02, P53/RTP03, P54/RTP10, P55/RTP11 [Inside dotted-line included] P51/TA0IN/RTP01, P57/TA2IN/RTP13 Data bus Direction register Port latch Latch T Q CKTimer underflow signal P50/TA0OUT /RTP00, P56/TA2OUT /RTP12 Data bus Direction register Port latch “1” Latch T Q CKTimer underflow signal Output (Internal peripheral devices)

M37920FCCGP, M37920FCCHP M37920FGCGP, M37920FGCHPPRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION MITSUBISHI MICROCOMPUTERS 110 [Inside dotted-line not included] P70/AN0, P71/AN1 [Inside dotted-line included] P72/AN2/INT3, P73/AN3/ADTRG /INT4 Data bus Direction register Port latch Analog input P82/CTS0/CLK1, P83/CTS0/RTS0, P86/CLK0 Data bus Direction register Port latch “1” “0” Output (Internal peripheral devices) P42/TC Data bus Direction register Port latch “0” Output (TC) Fig. 108 Block diagram for each port pin (2)

M37920FCCGP, M37920FCCHP M37920FGCGP , M37920FGCHPPRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION MITSUBISHI MICROCOMPUTERS CLOCK GENERATING CIRCUIT In the clock generating circuit, the basic clock which is used to oper- ate the CPU and each internal peripheral device is made by a clock input from pin X IN. Figure 111 shows the block diagram of the clock generating circuit. The clock which is input from the external clock in- put pin, XIN, generates the following;

φ, which is used to operate the microcomputer
φBIU, which is used to operate the BIU
φCPU , which is used to operate the CPU φ is stopped only when the external clock input is disabled by STP instruction. φBIU is stopped when to STP or WIT instruction is ex- ecuted. Also, φCPU is stopped when STP or WIT instruction is ex- ecuted or when a CPU wait request is issued by the BIU. f 1(φ) is the basic clock for internal peripheral devices. This basic clock is divided furthermore in the divide circuit, as shown in Figure 111, and some frequency types are generated. Serial I/O communication and timer B can use any of four clocks (f 2, f16, f64, f512), respectively. Timer A can use any of six clocks (f2, f16, f64, f512, and f1(φ) and f4096). “f2” indicates that this clock is f1(φ) divided by 2. For operation of the watchdog timer, refer to section on the watchdog timer. When the STP instruction is executed, φ, φBIU, and φCPU stop at the “L” state. The STP mode is terminated by acceptance of an interrupt, and the oscillation is started. Simultaneously, supply of φ is started. When the watchdog timer starts to count down with Wf32 and the most significant bit of the watchdog timer is cleared to “0”, supply of φBIU and φCPU is restarted. The count source of the watchdog timer is back to the count source which was selected before execution of the STP instruction, and the generated interrupt request is accepted. When the WIT instruction is executed, φBIU and φCPU stops at the “L” state. However, φ is not stopped. Immediately after the interrupt re- quest is accepted, φBIU and φCPU start their operations. In order to terminate the STP or WIT mode by a non-maskable inter- rupt, it is necessary to make the interrupt request acceptable before execution of the STP or WIT instruction. For setting method, refer to the section on interrupts. Figure 109 shows a circuit example with an external ceramic reson- ator or a quartz crystal oscillator. The constants such as capacitance etc. depend on a resonator. Therefore, for these constants, adopt the oscillator/resonator manufacturer’s recommended values. Figure 110 shows a circuit e example with an external clock source. Fig. 109 Circuit example with external ceramic resonator or quartz crystal oscillator Fig. 110 Circuit example with external clock source XIN R f XOUT R d C IN C OUT XIN XOUT Left open. External oscillation circuit Vcc Vss

M37920FCCGP, M37920FCCHP M37920FGCGP, M37920FGCHPPRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION MITSUBISHI MICROCOMPUTERS 112 Fig. 111 Block diagram of clock generating circuit f2 f64 f512 WIT instruction f4096 RSQ Q RS Q RS STP instruction Interrupt request φ φBIU φCPU CPU wait request from BIU Reset Watchdog timer frequency select bit : bit 0 at address 61 External clock input select bit : bit 1 at address 62 Internal clock stop select bit at WIT : bit 3 at address 63 CPU : Central Processing UnitBIU : Bus Interface Unit❈ : Signal generated when the watchdog timer’s most significant bit becomes “0”. Operating clock for serial I/O, timer B Watchdog timer Wf Wf 512f16f1( A-D conversion frequency ( φAD clock source Operating clock for timer A Watchdog timer frequency select bit DMA transfer Internal clock stop select bit at WIT X IN X OUT External clock input select bit Access to external area HLDA External clcok input select bit Reflesh counter

M37920FCCGP, M37920FCCHP M37920FGCGP , M37920FGCHPPRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION MITSUBISHI MICROCOMPUTERS Fig. 112 Block diagram of debug function Address compare register 0 Address compare register 1 Debug control register 0 Matching • Compare register Matching • Compare register Address matching detect circuit Debug control register 1 Internal data bus (DB0 to DB 15) CPU bus (Address) Address matching detection interrupt DEBUG FUNCTION When the CPU fetches an instruction code, an interrupt request will be generated if a selected condition is satisfied, as a resultant of comparison between a specified address and the start address where the instruction code is stored (the contents of PG and PC). The decision whether this condition is satisfied or not is called ad- dress matching detection, and the interrupt generated by this detec- tion is called an address matching detection interrupt. (For interrupt vector addresses, refer to the section on interrupts.) In the address matching detection, a non-maskable interrupt routine is proceeded without execution of the original instruction which has been allocated to the target address. The debug function provides the following two modes:

the address matching detection mode, which is used to avoid the area where program exists or modify a program.
the out-of-address-area detection mode, which is used to detect a program runaway. Figure 112 shows the block diagram of the debug function. Figures 113 and 114 show the bit configurations of the debug control regis- ters 0, 1, and address compare registers 0,1, respectively. The detect condition select bits of the debug control register 0 can select one condition between the following 4 conditions. When the selected address condition is satisfied, an address matching detec- tion interrupt request will be generated: (1) Address matching detection 0 The contents of PG and PC match with the address which has been set in the address compare register 0. (2) Address matching detection 1 The contents of PG and PC match with the address which has been set in the address compare register 1. (3) Address matching detection 2 The contents of PG and PC match with the address which has been set in either of the address compare register 0 or address compare register 1. (4) Out-of-address-area detection The contents of PG and PC are less than the address which has been set in the address compare register 0 or larger than the ad- dress which has been set in the address compare register 1. By setting the detect enable bit of the debug control register 0 to “1”, an address matching detection interrupt request will be generated if any one of the above address conditions is satisfied. Clearing the detect enable bit to “0” generates no interrupt request even if any of the above address conditions is satisfied. The address compare register access enable bit of the debug con- trol register 1 must be set to “1” by the instruction just before the ac- cess operation (read/write). Then, this bit must be cleared to “0” (disabled) by the next instruction. While this bit = “0”, the address compare registers 0, 1 cannot be accessed. The address-matching-detection 2 decision bit of the debug control register 1 decides, whether the address which has been set in the address compare register 0 or 1 matches with the contents of PG, PC, when the address matching detection 2 is selected. The con- tents of this bit is invalid when address matching detection 0 or 1 is selected. In order to use the debug function to avoid the area where program exists or modify a program, perform the necessary processing within an address matching interrupt routine. As a result, the contents of PG, PC, PS at acceptance of an address matching detection inter- rupt request (i.e. the address at which an address matching detec- tion condition is satisfied) have been pushed on to the stack. If a return destination address after the interrupt processing is to be al- tered, rewrite the contents of the stack, and then return by the RTI instruction. To use the debug function to detect a program runaway, set an ad- dress area where no program exists into the address compare regis- ters 0 and 1 by using the out-of-address-area detection. When the CPU fetches instruction codes from this address area and executes them, an address matching detection interrupt request will be gener- ated. The above debug function cannot be evaluated by a debugger, so that the debug function must not be used while a debugger is run- ning.

M37920FCCGP, M37920FCCHP M37920FGCGP, M37920FGCHPPRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION MITSUBISHI MICROCOMPUTERS 114 Fig. 113 Bit configuration of debug control register 0, 1 Fig. 114 Bit configuration of address compare register 0, 1 76543210 Debug control register 0 Detect condition select bits (Note 1) 000: Do not select. 001: Address matching detection 0 010: Address matching detection 1 011: Address matching detection 2 100: Do not select. 101: Out-of-address-area detection 110: Do not select. 111: Do not select. Fix this bit to “0” (Note 1). Detect enable bit (Note 1) 0: Detection disabled. 1: Detection enabled. Fix this bit to “0” (Note 1). “1” at read. Address 76543210 Debug control register 1 Fix this bit to “0” (Note 1). “0” at read (Note 1). Address compare register access enable bit (Note 2) 0: Disabled 1: Enabled Fix this bit to “1” when using the debug function. Fix this bit to “0” (Note 1). While debugger is not used, “0” at read. While debugger is used, “1” at read. Address-matching-detection 2 decision bit ❈ Valid when address matching detection 2 is selected. 0: Matches with the contents of the address compare register 0. 1: Matches with the contents of the address compare register 1. “0” at read. Address 000 010 Notes 1: At power-on reset, these bits = “0”; at hardware reset or software reset, these bits retain the value just before reset. 2: Set this bit to “1” with the instruction just before the address compare register 0, 1 (addresses 6816 to 6D16) is accessed. And then, clear this bit to “0” with the instruction just after the access.

0 Address compare register 0

Address compare register 1 The address to be detected (in other words, the start address of instruction) is set here. Address 6816, 6916, 6A16 6B16, 6C16, 6D16 (23) (8)(15)(16) 0707

M37920FCCGP, M37920FCCHP M37920FGCGP, M37920FGCHPPRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION MITSUBISHI MICROCOMPUTERS FLASH MEMORY MODE These microcomputers contain the DINOR (DIvided bit line NOR)- type flash memory; and single-power-supply reprogramming is avail- able to this. These microcomputers have the following three modes, enabling reading/programming/erasure for the flash memory:

Flash memory parallel I/O mode and Flash memory serial I/O mode, where the flash memory is handled by using an external pro- grammer.
CPU reprogramming mode, where the flash memory is handled by the central processing unit (CPU). As shown in Figures 116 and 117, the flash memory is divided into several blocks, and erasure per block is possible. Each of these blocks is provided with a lock bit, which determines the validity of erasure/program execution. Therefore, data protection per block is possible. This internal flash memory has the boot ROM area storing the repro- gramming control software for reprogramming in the CPU repro- gramming mode and flash memory serial I/O mode, as well as the user ROM area storing a certain control software for the normal op- eration in the microcomputer mode. Although our reprogramming control firmware for the flash memory serial I/O mode has been stored into this boot ROM area on ship- ment, the user-original reprogramming control software which is more appropriate for the user’s system is reprogrammable into this area, instead. Note that the reprogramming for the boot ROM area is enabled only in the flash memory parallel I/O mode. Fig. 116 M37920FCCGP, M37920FCCHP: block configuration of internal flash memory

Boot ROM areaUser ROM area

32 Kbytes

Byte Addresses Word Addresses

64 Kbytes

Notes 1: In the flash memory mode, the read/programming/erase operation cannot be performed for areas except for the internal flash memory area. 2: The boot ROM area can be reprogrammed only in the flash memory parallel I/O mode. When the boot ROM area is read out by the CPU, these addresses are shifted to addresses 00C00016–00FFFF 16 (byte addresses). 3: The reserved area for the serial programmer is assigned to addresses FFB016–FFBF 16 (byte addresses). When the flash memory serial I/O mode is used, do not program to this area.

M37920FCCGP, M37920FCCHP M37920FGCGP, M37920FGCHPPRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION MITSUBISHI MICROCOMPUTERS 116 Fig. 117 M37920FGCGP, M37920FGCHP: block configuration of internal flash memory Notes 1: In the flash memory mode, the read/programming/erase operation cannot be performed for areas except for the internal flash memory area. 2: The boot ROM area can be reprogrammed only in the flash memory parallel I/O mode. When the boot ROM area is read out by the CPU, these addresses are shifted to addresses 00C00016–00FFFF 16 (byte addresses). 3: The reserved area for the serial programmer is assigned to addresses FFB016–FFBF 16 (byte addresses). When the flash memory serial I/O mode is used, do not program to this area. Boot ROM areaUser ROM area Byte Addresses Word Addresses

Notice: This is not a final specification. Some parametric limits are subject to change. from erasing/programming (in other words, block lock). Table 25. Software commands (flash memory parallel I/O mode) address assigned in the range of 0016— FF16 (byte addresses). the flash memory parallel I/O mode. address out of this area is prohibited). area if the user uses the flash memory serial I/O mode. I/O mode, do not program to this area. 16— FFFF 16 (byte addresses).

M37920FCCGP, M37920FCCHP M37920FGCGP, M37920FGCHPPRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION MITSUBISHI MICROCOMPUTERS 118 PIN DESCRIPTION (FLASH MEMORY SERIAL I/O MODE) VCC , VSS MD0 MD1 RESET X IN XOUT BYTE AVcc, AVss V REF P00–P07 P10–P17 P20–P27 P30–P33 P40, P41 P42 P43 P44 P50–P57 P60–P66 P70–P73 P80–P86 P90–P96 P100–P107 P110–P117 P120–P122 NMI Pin Power supply input MD0 MD1 Reset input Clock input Clock output BYTE Analog supply input Reference voltage input Input port P0 Input port P1 Input port P2 Input port P3 Input port P4 SDA I/O BUSY output SCLK input Input port P5 Input port P6 Input port P7 Input port P8 Input port P9 Input port P10 Input port P11 Input port P12 Non-maskable interrupt Name Input Input Input Input Output Input Input Input Input Input Input Input I/O Output Input Input Input Input Input Input Input Input Input Input Input /Output Functions Apply 5 V ± 0.5 V to Vcc, and 0 V to Vss. Connect this pin to Vss. Connect this pin to Vss via a resistor of 10 kΩ to 100 kΩ . The reset input pin. Connect a ceramic resonator between the X IN and XOUT pins, or input an external clock from the XIN pin with the XOUT pin left open. Connect this pin to Vcc or Vss. (This is not used in the flash memory serial I/O mode.) Connect AVcc to Vcc, and AVss to Vss. Input an arbitrary level within the range of VSS –VCC . (This is not used in the flash memory serial I/O mode.) Input “H ” or “L”, or leave them open. (This is not used in the flash memory serial I/O mode.) Input “H ” or “L”, or leave them open. (This is not used in the flash memory serial I/O mode.) Input “H ” or “L”, or leave them open. (This is not used in the flash memory serial I/O mode.) Input “H ” or “L”, or leave them open. (This is not used in the flash memory serial I/O mode.) Input “H ” or “L”, or leave them open. (This is not used in the flash memory serial I/O mode.) This is an I/O pin for serial data. Connect this pin to VCC via a resistor (about 1 kΩ ). This is an output pin for the BUSY signal. This is an input pin for a serial clock. Input “H ” or “L”, or leave them open. (This is not used in the flash memory serial I/O mode.) Input “H ” or “L”, or leave them open. (This is not used in the flash memory serial I/O mode.) Input “H ” or “L”, or leave them open. (This is not used in the flash memory serial I/O mode.) Input “H ” or “L”, or leave them open. (This is not used in the flash memory serial I/O mode.) Input “H ” or “L”, or leave them open. (This is not used in the flash memory serial I/O mode.) Input “H ” or “L”, or leave them open. (This is not used in the flash memory serial I/O mode.) Input “H ” or “L”, or leave them open. (This is not used in the flash memory serial I/O mode.) Input “H ” or “L”, or leave them open. (This is not used in the flash memory serial I/O mode.) Input “H ”, or leave this pin open.

M37920FCCGP, M37920FCCHP M37920FGCGP, M37920FGCHPPRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION MITSUBISHI MICROCOMPUTERS Flash Memory Serial I/O Mode In the flash memory serial I/O mode, addresses, data, and software commands, which are required to read/program/erase the internal flash memory, are serially input and output with a fewer pins and the dedicated serial programmer. In this mode, being different from the flash memory parallel I/O mode, the CPU controls reprogramming of the flash memory (using the CPU reprogramming mode), serial input of the reprogramming data, etc. The reprogramming control firmware for the flash memory serial I/O mode has been stored in the boot ROM area on shipment of the product from us. Note that, then, the flash memory serial I/O mode will become unavailable if the boot ROM area has been repro- grammed in the flash memory parallel I/O mode. Note that, also, this reprogramming control firmware for the flash memory serial I/O mode is subject to change. Figures 118 and 119 show the pin connections in the flash memory serial I/O mode. The three pins, SCLK, SDA, and BUSY, are used to input and output serial data. The SCLK pin is the input pin of external transfer clocks. The SDA pin is the I/O pin of transmit and receive data, and its output acts as the N-channel open-drain output. To the SDA pin, connect an exter- nal pullup resistor (about 1 kΩ ). The BUSY pin is the output pin of the BUSY flag (CMOS output) and goes “H ” during BUSY periods owing to a certain operation, such as transmit, receive, erase, program- ming, etc. Transmit and receive data are serially transferred 8 bits at a time. In the flash memory serial I/O mode, only the user ROM area can be reprogrammed; the boot ROM area is not accessible. Addresses FFB0 16 to FFBF16 are the reserved area for the serial programmer. Therefore, when the user uses the flash memory serial I/O mode, do not program to this area.

M37920FCCGP, M37920FCCHP M37920FGCGP, M37920FGCHPPRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION MITSUBISHI MICROCOMPUTERS 120 Fig.118 Pin connection of M37920FxCGP in flash memory serial I/O mode Output 100P6S-A ✼ : Connect to the ceramic oscillation circuit. SCLK P66/DMAREQ 3 ↔ P65/TA4IN/DMAREQ 2 ↔ P64/TA4OUT /DMAACK 2 ↔ P60/TA1OUT /DMAACK 0 ↔ P57/TA2IN/RTP13 ↔ P56/TA2OUT /RTP12 ↔ P55/RTP11 ↔ P54/RTP10 ↔ P53/RTP03 ↔ P52/RTP02 ↔ P51/TA0IN/RTP01 ↔ P50/TA0OUT /RTP00 ↔ P96/WRH/UCAS ↔ P95/WRL/LCAS ↔ P94/CAS/W ↔ P93/CS3/RAS3 ↔ P92/CS2/RAS2 ↔ P91/CS1/RAS1 ↔ P90/CS0 ↔ P44/HLDA ↔ P43/HOLD ↔ P42/TC ↔ P41/φ1 ↔ P40/ALE ↔ P33/BHW ↔ P32/BLW ↔ P31/RD ↔ 100 P63/TA3IN/DMAREQ 1 ↔ P62/TA3OUT /DMAACK 1 ↔ P61/TA1IN/DMAREQ 0 ↔ ↔ P30/RDY ← BYTE ← NMI ← RESET ← MD0 VSS ← XIN → XOUT VCC ↔ P27/D15 ↔ P26/D14 ↔ P25/D13 ↔ P24/D12 ↔ P23/D11 ↔ P22/D10 ↔ P21/D9 ↔ P20/D8 ↔ P17/D7 ↔ P14/D4 ↔ P13/D3 ↔ P12/D2 ↔ P11/D1 ↔ P10/D0 ← MD1 VSS ↔ P07/A23 ↔ P06/A22/MA11 ↔ P05/A21 ↔ P04/A20/MA10 ↔ P03/A19 ↔ P02/A18/MA9 ↔ P01/A17 ↔ P00/A16/MA8 ↔ P117/A15/MA7 ↔ P116/A14/MA6 ↔ P115/A13/MA5 ↔ P114/A12/MA4 ↔ P113/A11/MA3 ↔ P112/A10/MA2 ↔ P111/A9/MA1 ↔ P110/A8/MA0 ↔ P107/A7 ↔ P106/A6 ↔ P105/A5 ↔ P104/A4 ↔ P103/A3 ↔ P102/A2 ↔ P101/A1 ↔ P16/D6 ↔ P15/D5P100/A0 ↔ P86/CLK0 ↔ P85/RXD 0 ↔ P84/TXD 0 ↔ P83/CTS0/RTS0 ↔ P82/CTS0/CLK1 ↔ P81/RXD 1 ↔ VCC AV CC VREF AV SS VSS P73/AN3/ADTRG /INT4 ↔ P72/AN2/INT3 ↔ P71/AN1 ↔ P70/AN0 ↔ P122/INT2/TB2IN ↔ P121/INT1/TB1IN ↔ P120/INT0/TB0IN ↔ P80/TXD 1 ↔ M37920FCCGP M37920FGCGP VSS RESET VCC BUSY SDA

M37920FCCGP, M37920FCCHP M37920FGCGP, M37920FGCHPPRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION MITSUBISHI MICROCOMPUTERS Fig.119 Pin connection of M37920FxCHP in flash memory serial I/O mode Output 100P6Q-A SCLK VSS RESET VCC BUSY SDA P66/DMAREQ 3 ↔ P65/TA4IN/DMAREQ 2 ↔ P64/TA4OUT /DMAACK 2 ↔ P60/TA1OUT /DMAACK 0 ↔ P57/TA2IN/RTP13 ↔ P56/TA2OUT /RTP12 ↔ P55/RTP11 ↔ P54/RTP10 ↔ P53/RTP03 ↔ P52/RTP02 ↔ P51/TA0IN/RTP01 ↔ P50/TA0OUT /RTP00 ↔ P96/WRH/UCAS ↔ P95/WRL/LCAS ↔ P94/CAS/W ↔ P93/CS3/RAS3 ↔ P92/CS2/RAS2 ↔ P91/CS1/RAS1 ↔ P90/CS0 ↔ P44/HLDA ↔ P43/HOLD ↔ P42/TC ↔ P41/φ1 ↔ P40/ALE ↔ 100 P63/TA3IN/DMAREQ 1 ↔ P62/TA3OUT /DMAACK 1 ↔ P61/TA1IN/DMAREQ 0 ↔ ↔ P30/RDY 28 ↔ P31/RD 27 ↔ P32/BLW 26 ↔ P33/BHW ← BYTE ← NMI ← RESET ← MD0 VSS ← XIN → XOUT VCC ↔ P27/D15 ↔ P26/D14 ↔ P25/D13 ↔ P24/D12 ↔ P23/D11 ↔ P22/D10 ↔ P21/D9 ↔ P20/D8 ↔ P17/D7 ↔ P14/D4 ↔ P13/D3 ↔ P12/D2 ↔ P11/D1 ↔ P10/D0 ← MD1 VSS ↔ P07/A23 ↔ P06/A22/MA11 ↔ P05/A21 ↔ P04/A20/MA10 ↔ P03/A19 ↔ P02/A18/MA9 ↔ P01/A17 ↔ P00/A16/MA8 ↔ P117/A15/MA7 ↔ P116/A14/MA6 ↔ P115/A13/MA5 ↔ P114/A12/MA4 ↔ P113/A11/MA3 ↔ P112/A10/MA2 ↔ P111/A9/MA1 ↔ P110/A8/MA0 ↔ P107/A7 ↔ P106/A6 ↔ P105/A5 ↔ P104/A4 ↔ P16/D6 ↔ P15/D5 P100/A0 ↔ P101/A1 ↔ P102/A2 ↔ P103/A3 ↔ P86/CLK0 ↔ P85/RXD 0 ↔ P84/TXD 0 ↔ P83/CTS0/RTS0 ↔ P82/CTS0/CLK1 ↔ P81/RXD 1 ↔ VCC AV CC VREF AV SS VSS P73/AN3/ADTRG /INT4 ↔ P72/AN2/INT3 ↔ P71/AN1 ↔ P70/AN0 ↔ P122/INT2/TB2IN ↔ P121/INT1/TB1IN ↔ P120/INT0/TB0IN ↔ P80/TXD 1 ↔ M37920FCCHP M37920FGCHP ✼ : Connect to the ceramic oscillation circuit.

M37920FCCGP, M37920FCCHP M37920FGCGP, M37920FGCHPPRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION MITSUBISHI MICROCOMPUTERS 122 CPU Reprogramming Mode The CPU reprogramming mode is used to perform the operations for the internal flash memory (reading, programming, erasing) under control of the CPU. In this mode, only the user ROM area can be reprogrammed; the boot ROM area cannot be reprogrammed. The user-original reprogramming control software for the CPU repro- gramming mode can be stored in either the user ROM area or the boot ROM area. Because the CPU cannot read out the flash memory in the CPU reprogramming mode, the above software must be trans- ferred to the internal RAM in advance to be executed. Boot Mode The user-original reprogramming control software for the CPU re- programming mode must be stored into the user ROM area or the boot ROM area in the flash memory parallel I/O mode in advance. (If this program has been stored into the boot ROM area, the flash memory serial I/O mode will become unavailable). Note that addresses of the boot ROM area depend on the accessing ways to the boot ROM area, When accessing in the flash memory parallel I/O mode, these addresses will be shifted to 0000 16 to 3FFF 16 (byte address). On the other hand, when accessing with the CPU, these addresses will be shifted to C00016 to FFFF16 (byte address). Reset removal with both of the MD0 and MD1 pins held “L” invokes the normal microcomputer mode, and the CPU operates using the control software stored in the user ROM area. In this case, the boot ROM area is not accessible. Removing reset with the MD0 pin held “L” and the MD1 pin “H”, the CPU starts its operation using the reprogramming control software stored in the boot ROM area. This mode is called the boot mode. The reprogramming control software in the boot ROM area can also re- program the user ROM area. After reset removal, be sure not to change the status at pins MD0 and MD1. Fig. 120 Bit configuration of flash memory control register Flash memory control register RY/BY status bit 0: Busy (Programming or erasing is active.) 1: Ready CPU reprogramming mode select bit (Note 2) 0: Normal mode (Software commands are ignored.) 1: CPU reprogramming mode (Software commands are acceptable.) Lock bit invalidity select bit (Note 3) 0: Block lock by lock bit data is valid. 1: Block lock by lock bit data is invalid. Flash memory reset bit (Note 4) 0: Normal operation 1: Reset Must be “0”. User ROM area select bit (Note 5) (Valid only in the boot mode.) 0: Boot ROM area access 1: User ROM area access Address 765432 10 Notes 1: The contents of the flash memory control register after reset is removed are “XX000001 2”. 2: To set “1”, writing of “0” to bit 1 and subsequent writing of “1” to bit 1 are necessary. Writing to bit 1 must be performed by the user-original reprogramming control software in the internal RAM. 3: To set “1”, writing of “0” to bit 2 and subsequent writing of “1” to bit 2 are necessary while bit 1 = “1”. 4: Valid only when bit 1 = “1”. Set bit 3 to “1” (reset), and then clear to “0”. This bit 3 must be controlled with the CPU reprogramming mode select bit (bit 1) = “1”. 5: Writing to bit 5 must be performed by the user-original reprogramming control software in the internal RAM.

M37920FCCGP, M37920FCCHP M37920FGCGP, M37920FGCHPPRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION MITSUBISHI MICROCOMPUTERS 124 Fig. 121 CPU reprogramming mode set/termination flowchart Software Commands Table 26 lists the software commands. By writing a software command after the CPU reprogramming select bit has been set to “1”, erasing, programming, etc. can be specified. Note that, at software commands’ input, the high-order byte (D D 15) is ignored. (Except for the write data at the 2nd cycle of a page programming command.) Software commands are explained as below. Read Array Command (FF 16) By writing command code “FF16” at the 1st bus cycle, the microcom- puter enters the read array mode. If an address to be read is input in the next or the following bus cycles, the contents at the specified ad- dress are output to the data bus (D0 to D15) in a unit of 16 bits. The read array mode is maintained until writing of another software command. Read Status Register Command (7016) Writing command code “7016” at the 1st bus cycle outputs the con- tents of the status register to the data bus (D0-D7) by a read at the 2nd bus cycle. The status register is explained later. Clear Status Register Command (5016) This command clears three status bits (SR.3–5) each of which is set to “1” to indicate that the operation has been terminated by an error. To clear these bits, write command code “50 16” at the 1st bus cycle. Page Programming Command (41 16) Page programming facilitates quick programming of 128 words (a page = 256 bytes) at a time. To initiate page programming, write command code “41 16” at the 1st bus cycle; then, program a series of data, in a unit of 16 bits, sequentially from the 2nd to the 129th bus cycle. It is necessary, at this time, to increment address A0–A7 from “0016” to “FE16” by +2. (Programmed to even addresses.) Upon completion of data loading, automatic programming (data pro- gramming and verification) operation is started. The completion of the automatic programming operation is recog- nized by a read of the status register or a read of the flash memory control register. As the automatic programming operation starts, the microcomputer enters the read status register mode automatically to allow reading out the contents of the status register. Bit 7 of the sta- tus register (SR.7) is cleared to “0” simultaneously with the start of the automatic programming operation; and also, bit 7 returns to “1” by the end of it. Until writing of the read array command (FF 16), writ- ing of the read lock bit status command (7116), or performing the re- set operation with the flash memory reset bit, this read status register mode is maintained. In continuous programming, if there is no pro- gramming error, page programming commands can be executed with the read status register mode kept. Completed Start Read array command is executed, or reset is performed by setting the flash memory reset bit. (Writing of “1” → Writing of “0”) (Note 2) Single-chip mode, Memory expansion mode, or Boot mode The processor mode register is set (Note 1). Flag I is set to “1”. Operations such as erasing, programming are executed by using software commands. (If necessary, the lock bit invalidity select bit is set.) Jump to the above software in the internal RAM. (The operations shown below will be executed by the above software in this RAM.) The user-original reprogramming control software for the CPU reprogramming mode is transferred to the internal RAM. (Only in the boot mode.) Writing of “0” to user ROM area select bit (Note 3). Writing of “0” to the CPU reprogramming mode select bit. (Only in the boot mode.) The user ROM area select bit is set to “1”. Writing of “1” to the CPU reprogramming mode select bit. (Writing of “0” → Writing of “1”) Notes 1: The processor mode register 1’s bit 7 (address 5F16, the internal ROM access wait bit) must be “0” (1 wait). 2: To terminate the CPU reprogramming mode after the erase and programming operations have been completed, be sure to execute the read array command or perform the flash memory reset operation. 3: This bit may remain “1”. However, if this bit is “1”, the user ROM area access is specified.

M37920FCCGP, M37920FCCHP M37920FGCGP, M37920FGCHPPRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION MITSUBISHI MICROCOMPUTERS 126 Fig.122 Page programming flowchart Fig.123 Block erase flowchart Fig.125 Read lock bit status flowchart Fig.124 Lock bit programming flowchart n = FE16 Start Write 4116 n = 0 Write Addressn, Datan SR.7 = 1? Status Register Read Full status check Page programming completed n = n + 2 NO YES NO YES Write 2016 Write D016 Status Register Read SR.7 = 1? Full Status Check Block Erase Completed NO YES Block Address Start SR.7 = 1? Write 7716 Write D016 NO YES SR.4 = 0? NO Lock Bit Programming Completed Block Address Lock Bit Programming Error YES Start Block: unlocked Write 7116 D 6 = 0? Block: locked NO YES Block Address Start

Notice: This is not a final specification. Table 27. Bit definition of status register cleared to “0” (BUSY), however, set to “1” upon completion of them.

the system power is turned on.
reset is removed.
the clear status register command (5016) is executed. Programming Status Bit (SR.4) This bit reports the status of the automatic programming operation. This bit is set to “1” if a programming error occurs and returns to “0” if one of the following conditions is satisfied:
the system power is turned on.
reset is removed.
the clear status register command (5016) is executed. Block Status After Programming Bit (SR.3) This bit is set to “1”, upon completion of the page programming op- eration, if the excessive programming (Note) occurs. That is, the sta- tus register becomes “8016” when the programming operation is terminated normally, “9016” when the programming operation is failed, and “8816” when the excessive programming occurs. Under the condition that any of SR.5, SR.4 and SR.3 = “1”, none of the page programming, block erase, erase all unlocked block, and lock bit programming commands can be accepted. To execute these commands, in advance, execute the clear status register command (50 16) to clear the status register. Both of SR.4 and SR.5 are set to “1” under the following conditions (Command Sequence Error): (1) when data other than “D0 16” and “FF16” is written to the data in the 2nd bus cycle of the lock bit programming command (7716/ D0 16) (2) when data other than “D0 16” and “FF16” is written to the data in the 2nd bus cycle of the block erase command (2016/D016) (3) when data other than “D0 16” and “FF16” is written to the data in the 2nd bus cycle of the erase all unlocked block command (A7 16/D016) Note that, writing of “FF16” forces the microcomputer into the read array mode. Simultaneously with this, the command written in the 1st bus cycle will be canceled. Note: The excessive programming means the status that memory cells are too depleted, so data cannot be read out correctly. Full Status Check The full status check reports the results of the erase or programming operation. Figure 126 shows the full status check flowchart and actions to be taken if an error has occurred.

M37920FCCGP, M37920FCCHP M37920FGCGP, M37920FGCHPPRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION MITSUBISHI MICROCOMPUTERS Fig.126 Full status check flowchart and actions to be taken if an error has ocurred Status Register Read SR.4 = 1 NO Command Sequence Error YES SR.5 = 0? YES Block Erase Error NO SR.4 = 0? YES Programming Error (Page, Lock bit) NO SR.3 = 0? YES Programming Error (Block) NO End (Block erase, Programming) and SR.5 = 1 Execute the clear status register command (5016) to clear the status register. After verifying the command to be correctly input, start the operation again. Examine whether a lock is active or not by executing the read lock bit status command (7116). After removing the lock, perform block erase again. If the same error still occurs, this page cannot be used. Examine whether a lock is active or not by executing the read lock bit status command (7116). After removing the lock, perform programming again. If the same error still occurs, this page cannot be used. After erasing the block where an error has occured, perform programming again. If the same error still occurs, this block cannot be used. Note: Under the condition that any of SR.5, SR.4 and SR.3 = “1”, none of the page programming, block erase, erase all unlocked block, and lock bit programming commands can be accepted. To execute these commands, in advance, execute the clear status register command (50 16). The limits of parameters other than the above are same as those in the microcomputer mode. Note: f(XIN) indicates the system clock (XIN) frequency. Symbol Parameter Limits Unit Icc1 Icc2 Icc3 Icc4 Min. Typ. Max. VCC power source current (at read) VCC power source current (at write) VCC power source current (at programming) VCC power source current (at erasing) 30 48 Limits of VIH, VIL, VOH , VOL , IIH, and IIL for each pin are the same as those in the microcomputer mode. Note: f(XIN) indicates the system clcok (XIN) frequency. mA mA mA mA Parameter Page programming time Block erase time Erase all unlocked block time Lock bit programming time Limits UnitMin. Typ. Max. 50 ✕ n 120 600 600 ✕ n 120 ms ms ms ms n = Number of blocks to be erased

M37920FCCGP, M37920FCCHP M37920FGCGP, M37920FGCHPPRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION MITSUBISHI MICROCOMPUTERS 130 Power source voltage Analog power source voltage Power source voltage Analog power source voltage High-level input voltage High-level input voltage High-level input voltag Low-level input voltage Low-level input voltage Low-level input voltage High-level peak output current High-level average output current Low-level peak output current Low-level average output current External clock input frequency P00–P07, P30–P33, P40–P44, P50–P57, P60–P66, P70–P73, P80–P86, P91–P96, P101–P107, P111–P117, P120–P122, XIN, RESET, BYTE, MD0, MD1, NMI P10–P17, P20–P27 (In single-chip mode) P10–P17, P20–P27 (In memory expansion and microprocessor modes) 0–P07, P30–P33, P40–P44, P50–P57, P60–P66, P70–P73, P80–P86, P91–P96, P101–P107, P111–P117, P120–P122, XIN, RESET, BYTE, MD0, MD1, NMI P10–P17, P20–P27 (In single-chip mode) P10–P17, P20–P27 (In memory expansion and microprocessor modes) 0–P07, P10–P17, P20–P27, P30–P33, P40–P44, P50–P57, P60–P66, P70–P73, P80–P86, P90–P96, P100–P107, P110–P117, P120–P122 P00–P07, P10–P17, P20–P27, P30–P33, P40–P44, P50–P57, P60–P66, P70–P73, P80–P86, P90–P96, P100–P107, P110–P117, P120–P122 P00–P07, P10–P17, P20–P27, P30–P33, P40–P44, P50–P57, P60–P66, P70–P73, P80–P86, P90–P96, P100–P107, P110–P117, P120–P122 P00–P07, P10–P17, P20–P27, P30–P33, P40–P44, P50–P57, P60–P66, P70–P73, P80–P86, P90–P96, P100–P107, P110–P117, P120–P122 VCC AV CC VSS AV SS VIH VIH VIH VIL VIL VIL IOH (peak) IOH (avg) IOL (peak) IOL (avg) f(XIN) Parameter Power source voltage Analog power source voltage Input voltage D 0–D 7, D8/P20–D 15/P27, P30, P33, P40–P44, P50–P57, P60–P66, P70–P73, P80–P86, P91–P96, P100–P107, P110–P117, P120–P122, VREF , XIN, RESET, BYTE, MD0, MD1, NMI Output voltage D0–D 7, D8/P20–D 15/P27, P30, P40–P44, P50–P57, P60–P66, P70–P73, P80–P86, P91–P96, P100–P107, P110–P117, P120–P122, XOUT Power dissipation Operating ambient temperature Storage temerature Symbol V CC AV CC VI VO Pd Topr Tstg ABSOLUTE MAXIMUM RATINGS RECOMMENDED OPERATING CONDITIONS (Vcc = 5 V, Ta = –20 to 85 °C, unless otherwise noted) Notes 1: Average output current is the average value of an interval of 100 ms. 2: The sum of IOL(peak) for ports P0–P2, P8, P10, and P11 must be 80 mA or less, the sum of IOH(peak) for ports P0–P2, P8, P10, and P11 must be 80 mA or less, the sum of IOL(peak) for ports P3–P7, P9, and P12 must be 80 mA or less, the sum of IOH(peak) for ports P3–P7, P9, and P12 must be 80 mA or less. Unit V V V V mW Ratings –0.3 to 6.5 –0.3 to 6.5 –0.3 to V CC +0.3 –0.3 to VCC +0.3 300 –20 to 85 –40 to 150 Unit V V V V V V V V V V mA mA mA mA MHz 4.5 0.8VCC 0.8VCC 0.5VCC 5.5 VCC VCC VCC 0.2VCC 0.2VCC 0.16VCC –10 ParameterSymbol Max.Typ.Min. Limits VCC

M37920FCCGP, M37920FCCHP M37920FGCGP, M37920FGCHPPRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION MITSUBISHI MICROCOMPUTERS Unit V V V V V V V V V µA µA V mA µA f(XIN) = 20 MHz. Ta = 25 °C when clcock is stopped. Ta = 80 °C when clcock is stopped. Test conditions IOH = –10 mA IOH = –400 µA IOH = –10 mA IOH = –400 µA IOL = 10 mA IOL = 2 mA IOL = 10 mA IOL = 2 mA VI = 5.0 V VI = 0 V When clock is stoped. Parameter High-level output voltage P00–P07, P10–P17, P20–P27, P30, P40–P44, P50–P57, P60–P66, P70–P73, P80–P86, P90–P93, P100–P107, P110–P117, P120–P122 High-level output voltage P00–P07, P10–P17, P20–P27, P40, P44, P90–P93, P100–P107, P110–P117 High-level output voltage P31–P33, P94–P96 Low-level output voltage P00–P07, P10–P17, P20–P27, P30, P40–P44, P50–P57, P60–P66, P70–P73, P80–P86, P90–P93, P100–P107, P110–P117, P120–P122 Low-level output voltage P00–P07, P10–P17, P20–P27, P40, P44, P90–P93, P100–P107, P110–P117 Low-level output voltage P31–P33, P94–P96 Hysteresis TA0IN–TA4IN, TB0IN–TB2 IN, INT0–INT4, DMAREQ 0–DMAREQ 3, AD TRG , CTS 0, CLK0, CLK1, RxD0, RxD 1, NMI, RDY , HOLD Hysteresis RESET Hysteresis XIN High-level input currentP00–P07, P10–P17, P20–P27, P30–P33, P40–P44, P50–P57, P60–P66, P70–P73, P80–P86, P91–P96, P100–P107, P110–P117, P120–P122, XIN, RESET, BYTE, MD0, MD1, NMI Low-level input currentP00–P07, P10–P17, P20–P27, P30–P33, P40–P44, P50–P57, P60–P66, P70–P73, P80–P86, P91–P96, P100–P107, P110–P117, P120–P122, XIN, RESET, BYTE, MD0, MD1, NMI RAM hold voltage Power source current Symbol V OH VOH VOH VOL VOL VOL VT+ — VT – VT+ — VT – VT+ — VT – IIH IIL VRAM ICC DC ELECTRICAL CHARACTERISTICS (Vcc = 5 V, Vss = 0 V, Ta = –20 to 85 °C, f(XIN) = 20 MHz, unless otherwise noted) Min. 4.7 3.4 4.8 0.4 0.5 0.1 Limits Typ. Max. 0.45 1.6 0.4 1.5 0.3 At reset in micro- processor mode, output-only pins are open, and the other pins are con- nected to Vss.

M37920FCCGP, M37920FCCHP M37920FGCGP, M37920FGCHPPRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION MITSUBISHI MICROCOMPUTERS 132 Resolution Absolute accuracy Ladder resistance Conversion time Reference voltage Analog input voltage R LADDER tCONV VREF VIA VREF = VCC VREF = VCC VREF = VCC f(XIN) ≤ 20 MHz Max. A-D CONVERTER CHARACTERISTICS (VCC = AVCC = 5 V ± 0.5 V, VSS = AVSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted) UnitParameterSymbol Test conditions Limits Min. 10-bit resolution mode 8-bit resolution mode 10-bit resolution mode 8-bit resolution mode 5.9 2.45 (Note) 2.7 ± 3 ± 2 VCC VREF Bits LSB LSB kΩ µs V V Note: This is applied when A-D conversion freguency (φAD ) = f1(φ).

M37920FCCGP, M37920FCCHP M37920FGCGP, M37920FGCHPPRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION MITSUBISHI MICROCOMPUTERS tc(TA) tw(TAH) tw(TAL) f(XIN) ≤ 20 MHz f(XIN) ≤ 20 MHz f(XIN) ≤ 20 MHz PERIPHERAL DEVICE INPUT/OUTPUT TIMING (VCC = 5 V ± 0.5 V, VCC = 0 V, Ta = –20 to 85 °C, f(XIN) = 20 MHz unless otherwise noted) ∗ For limits depending on f(XIN), their calculation formulas are shown below. Also, the values at f(XIN) = 20 MHz are shown in ( ). Timer A input (Up-down input and Count input in event counter mode) tc(UP) tw(UPH) tw(UPL) tsu(UP-TIN) th(TIN-UP) Symbol TAiOUT input cycle time TAiOUT input high-level pulse width TAiOUT input low-level pulse width TAiOUT input setup time TAiOUT input hold time Parameter Limits Min. 2000 1000 1000 400 400 Max. ns ns ns ns ns Unit Timer A input (External trigger input in pulse width modulation mode) tw(TAH) tw(TAL) Symbol TAiIN input high-level pulse width TAiIN input low-level pulse width Parameter Min. Limits Max. ns ns Unit Limits Symbol Parameter Min. Max. Unit 8 × 109 f(XIN) (400)TAiIN input cycle time TAiIN input high-level pulse width TAiIN input low-level pulse width ns ns ns Timer A input (External trigger input in one-shot pulse mode) Limits Symbol Parameter Min. Max. Unit 16 × 109 f(XIN) 8 × 109 f(XIN) 8 × 109 f(XIN) (800) (400) (400) t c(TA) tw(TAH) tw(TAL) TAiIN input cycle time TAiIN input high-level pulse width TAiIN input low-level pulse width ns ns ns Timer A input (Gating input in timer mode) Note :The TAiIN input cycle time requires 4 or more cycles of a count source. The TAiIN input high-level pulse width and the TAiIN input low-level pulse width respectively require 2 or more cycles of a count source. The limits in this table are applied when the count source = f2 at f(XIN) ≤ 20 MHz. Timer A input (Count input in event counter mode) tc(TA) tw(TAH) tw(TAL) Symbol TAiIN input cycle time TAiIN input high-level pulse width TAiIN input low-level pulse width Parameter Min. Limits Max. ns ns ns Unit f(X IN) ≤ 20 MHz

M37920FCCGP, M37920FCCHP M37920FGCGP, M37920FGCHPPRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION MITSUBISHI MICROCOMPUTERS 134 tc(TA) tsu(TAjIN-TAjOUT) tsu(TAjOUT-TAjIN) Symbol Parameter Min. 800 200 200 Limits Max. ns ns ns Unit Timer A input (Two-phase pulse input in event counter mode) TAiIN input cycle time TAjIN input setup time TAjOUT input setup time TAiIN input TAiOUT input (Up-down input) TAiOUT input (Up-down input) TAiIN input (When count by falling) TAiIN input (When count by rising) TAjIN input TAjOUT input Test conditions

VCC = 5 V±0.5 V, Ta = –20 to 85 °C
Input timing voltage : VIL = 1.0 V, VIH = 4.0 V
Up-down and Count input in event counter mode
Two-phase pulse input in event counter mode
Gating input in timer mode
Count input in event counter mode
External trigger input in one-shot pulse mode
External trigger input in pulse width modulation mode tc (TA) tw(TAH) tw(TAL) tc(UP) tw(UPH) tw(UPL) th(TIN-UP) tsu(TAjIN-TAjOUT ) tsu(TAjIN-TAjOUT ) tsu(TAjOUT -TAjIN) tsu(TAjOUT -TAjIN) tc(TA) tsu(UP-TIN)

M37920FCCGP, M37920FCCHP M37920FGCGP, M37920FGCHPPRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION MITSUBISHI MICROCOMPUTERS f(XIN) ≤ 20 MHz f(XIN) ≤ 20 MHz f(XIN) ≤ 20 MHz f(XIN) ≤ 20 MHz f(XIN) ≤ 20 MHz f(XIN) ≤ 20 MHz tc(TB) tw(TBH) tw(TBL) tc(TB) tw(TBH) tw(TBL) Timer B input (Count input in event counter mode) Symbol TBiIN input cycle time (one edge count) TBiIN input high-level pulse width (one edge count) TBiIN input low-level pulse width (one edge count) TBiIN input cycle time (both edge count) TBiIN input high-level pulse width (both edge count) TBiIN input low-level pulse width (both edge count) Parameter Limits Min. 160 Max. ns ns ns ns ns ns Unit Limits Symbol Parameter Min. Max. Unit 16 × 109 f(XIN) 8 × 109 f(XIN) 8 × 109 f(XIN) (800) (400) (400) t c(TB) tw(TBH) tw(TBL) TBiIN input cycle time TBiIN input high-level pulse width TBiIN input low-level pulse width ns ns ns Timer B input (Pulse period measurement mode) Note: The TBiIN input cycle time requires 4 or more cycles of a count source. The TBiIN input high-level pulse width and the TBiIN input low-level pulse width respectively require 2 or more cycles of a count source. The limits in this table are applied when the count source = f2 at f(XIN) ≤ 20 MHz. Limits Symbol Parameter Min. Max. Unit 16 × 109 f(XIN) 8 × 109 f(XIN) 8 × 109 f(XIN) (800) (400) (400) t c(TB) tw(TBH) tw(TBL) TBiIN input cycle time TBiIN input high-level pulse width TBiIN input low-level pulse width ns ns ns Timer B input (Pulse width measurement mode) Note: The TBiIN input cycle time requires 4 or more cycles of a count source. The TBiIN input high-level pulse width and the TBiIN input low-level pulse width respectively require 2 or more cycles of a count source. The limits in this table are applied when the count source = f2 at f(XIN) ≤ 20 MHz. tc(AD) tw(ADL) Symbol AD TRG input cycle time (minimum allowable trigger) AD TRG input low-level pulse width Parameter Min. 1000 125 Limits Max. ns ns Unit A-D trigger input

M37920FCCGP, M37920FCCHP M37920FGCGP, M37920FGCHPPRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION MITSUBISHI MICROCOMPUTERS 136 tc(CK) tw(CKH) tw(CKL) td(C-Q) th(C-Q) tsu(D-C) th(C-D) Serial I/O Symbol CLK i input cycle time CLK i input high-level pulse width CLK i input low-level pulse width TXD i output delay time TXD i hold time R XD i input setup time R XD i input hold time Parameter Limits Min. 200 100 100 Max. ns ns ns ns ns ns ns Unit tw(INH) tw(INL) Symbol INTi input/NMI input high-level pulse width INTi input/NMI input low-level pulse width Parameter Min. 250 250 Limits Max. ns ns Unit External interrupt (INTi) input, NMI input tc(TB) tw(TBH) tw(TBL) tc(CK) tw(CKH) tw(CKL) th(C - Q) td(C - Q) tsu(D - C) tw(INH) tw(INL) th(C - D) tc(AD) tw(ADL) TBiIN input INTi input, AD TRG input CLKi input TxDi output RxDi input NMI input Test conditions

Vcc = 5 V ± 0.5 V, Ta = –20 to 85 °C
Input timing voltage : VIL = 1.0 V, VIH = 4.0 V
Output timing voltage : VOL = 0.8 V, VOH = 2.0 V, CL = 50 pF

M37920FCCGP, M37920FCCHP M37920FGCGP, M37920FGCHPPRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION MITSUBISHI MICROCOMPUTERS td(φ1-HLDAL) td(RDH-HLDAL) td(BXWH-HLDAL) tpxz(HLDAL-RDZ) tpxz(HLDAL-BXWZ) tpxz(HLDAL-CSiZ) tpxz(HLDAL-ALEZ) tpxz(HLDAL-AZ) tpzx(HLDAL-RDZ) tpzx(HLDAL-BXWZ) tpzx(HLDAL-CSiZ) tpzx(HLDAL-ALEZ) tpzx(HLDAL-AZ) READY, HOLD TIMING Timing requirements (VCC = 5 V ± 0.5 V, VSS = 0 V, Ta = –20 to 85 °C, f(XIN) = 20 MHz, unless otherwise noted) tsu(RDY-φ1) tsu(HOLD-φ1) th(φ1-RDY) th(φ1-HOLD) Symbol RDY input setup time HOLD input setup time RDY input hold time HOLD input hold time Parameter Limits Min. Max. ns ns ns ns Unit Switching characteristics (VCC = 5 V ± 0.5 V, VSS = 0 V, Ta = –20 to 85 °C, f(XIN) = 20 MHz, unless otherwise noted) Symbol HLDA output delay time HLDA low-level output delay time after read HLDA low-level output delay time after write Floating start delay time Floating start delay time Floating start delay time Floating start delay time Floating start delay time Floating release delay time Floating release delay time Floating release delay time Floating release delay time Floating release delay time Parameter Min. tc –15 (Note) tc –15 (Note) –15 –15 –15 –15 –15 Limits Max. ns ns ns ns ns ns ns ns ns ns ns ns ns Unit Note: tc = 1/f(XIN).

M37920FCCGP, M37920FCCHP M37920FGCGP, M37920FGCHPPRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION MITSUBISHI MICROCOMPUTERS 138 RDY input tsu (RDY-φ1) RD, BLW, BHW : Wait inserted by software (The above is applied when 1 wait is selected.) : Wait inserted by Ready function RDY input th (φ1-RDY) Test conditions

VCC = 5 V ± 0.5 V, Ta= –20 to 85 °C
RDY input, HOLD input : VIL = 1.0 V, VIH = 4.0 V
HLDA output : V OL = 0.8 V, VOH = 2.0 V, CL = 50 pF HOLD input tsu (HOLD-φ1) td (φ1-HLDAL) tpxz (HLDAL-RDZ) tpxz (HLDAL-BXWZ) tpxz (HLDAL-CSiZ) tpxz (HLDAL-AZ) th (φ1-HOLD) td (φ1-HLDAL) tpzx (HLDAL-RDZ) tpzx (HLDAL-BXWZ) tpzx (HLDAL-CSiZ) tpzx (HLDAL-ALEZ) tpzx (HLDAL-AZ) Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z HOLD input HLDA output RD BLW BHW CS i A0–A23 output td (RDH-HLDAL) td (BXWH-HLDAL) tpxz (HLDAL-ALEZ) ALE

M37920FCCGP, M37920FCCHP M37920FGCGP, M37920FGCHPPRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION MITSUBISHI MICROCOMPUTERS When ALE expansion wait is selected W = 0 (0 wait) W = 1 (1 wait) W = 2 (2 wait) tc = 1/f(X IN). External bus timing For limits depending on f(XIN), their calculation formulas are shown below. External clock input Test conditions

Vcc = 5 V ± 0.5 V, Ta = –20 to 85 °C
Input timing voltage : VIL = 1.0 V, VIH = 4.0 V (tw(H), tw(L), tr, tf)
Output timing voltage : 2.5 V (tc, tw(half)) tr tf tw(L) tw(H) tw(half) f(XIN) tc Timing Requirements (VCC = 5 V ± 0.5 V, VSS = 0 V, Ta = –20 to 85 °C, f(XIN) = 20 MHz, unless otherwise noted) ns ns ns ns ns ns ns ns ns ns ns ns ns 0.45tc 0.5tc-8 0.5tc-8 0.55tc (2 + W)tc-45 (1.5 + W)tc-35 (1 + W)tc-30 (1 + W)tc-35 0.45 tc 0.5tc-8 0.5tc-8 Limits External clock input cycle time External clock input pulse width with half input-volage External clock input high-level pulse width External clock input low-level pulse width External clock input rise time External clock input fall time Address access time Chip select access time Read access time Read data setup time Data input hold time after read Address access time at burst ROM access Data hold time after address at burst ROM access Parameter Max.Min. tc tw(half) tw(H) tw(L) tr tf ta(A-D) ta(CSiL-D) ta(RDL-D) tsu(D-RDL) th(RDH-D) ta(BA-D) th(BA-D) UnitSymbol Max.Min. When 0/1/2 wait is selected 0.55tc 4tc-45 3.5tc–35 2tc-30 2tc-35

M37920FCCGP, M37920FCCHP M37920FGCGP, M37920FGCHPPRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION MITSUBISHI MICROCOMPUTERS 140 Switching characteristics (VCC = 5 V ± 0.5 V, VSS = 0 V, Ta = –20 to 85 °C, f(XIN) = 20 MHz, unless otherwise noted) 0.5tc+10 Read low-level output delay time Read high-level output delay time Write low-level output delay time Write high-level output delay time ALE pulse width ALE completion delay time after address stabilization Read output pulse width Read output high-level width (Note 1) Write disable valid time after read (Note 2) Address valid time before read Address hold time after read (Note 3) ALE completion delay time after read start Read disable valid time after ALE completion Chip select valid time before read Chip select output valid time before read completion Chip select hold time after read Next write cycle data output delay time after read (Note 2) Write output pulse width Write output high-level width (Note 1) Read disable valid time after write (Note 2) Address valid time before write Address hold time after write (Note 3) ALE completion delay time after write start Write disable valid time after ALE completion Chip select valid time before write Chip select output valid time before write completion Chip select hold time after write Data output valid time before write completion Data hold time after write Floating start delay time after write –10 –10 –10 –10 tc-20 1.5tc-30 2tc-15 2tc-15 tc-15 2tc-30 0.5tc-20 1.5tc-20 3.5tc-20 0.5tc-20 tc-15 2tc-15 2tc-15 tc-15 2tc-30 0.5tc-20 1.5tc-20 3.5tc-20 0.5tc-20 2tc-20 0.5tc-10 0.5tc+10 –10 –10 –10 –10 0.5tc-20 tc-30 (1+W)tc-15 tc-15 tc-15 tc-30 0.5tc-20 (1.5 + W)tc-20 0.5tc-20 tc-15 (1 + W)tc-15 tc-15 tc-15 tc-30 0.5tc-20 (1.5 + W)tc-20 0.5tc-20 (1 + W)tc-20 0.5tc-10 t d(φ1-RDL) td(φ1-RDH) td(φ1-BXWL) td(φ1-BXWH) tw(ALEH) td(A-ALEL) tw(RDL) tw(RDH) td(RDH-BXWH) td(A-RDH) th(RDH-A) td(RDH-ALEL) td(ALEL-RDH) td(CSiL-RDH) td(CSiL-RDL) th(RDH-CSiL) td(RDH-D) tw(BXWL) tw(BXWH) td(BXWH-RDH) td(A-BXWH) th(BXWH-A) td(BXWH-ALEL) td(ALEL-BXWH) td(CSiL-BXWH) td(CSiL-BXWL) th(BXWH-CSiL) td(D-BXWL) th(BXWH-D) tpxz(BXWH-DZ) ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Parameter Max.Min. UnitSymbol Limits Max.Min. When 0/1/2 wait is selectedWhen ALE expansion wait is selected Notes 1: When the bus cycle just before this parameter is for the area where the recovery cycle insertion is selected, this parameter is extended by tc (ns). 2: When accessing the area where the recovery cycle insertion is selected, this parameter is extended by tc (ns). 3: When accessing the area where the recovery cycle insertion is selected, this parameter is extended by tc (ns). However, except for the case at instruction prefetch.

M37920FCCGP, M37920FCCHP M37920FGCGP, M37920FGCHPPRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION MITSUBISHI MICROCOMPUTERS Bus cycle<At read> CS i A0–A23 D 0–D 7, D8–D 15 th(RDH-D) th(RDH-A) th(RDH-CSiL) RD tw(RDL) ta(CSiL-D) ta(RDL-D) ta(A-D) td(A-RDH) td(CSiL-RDL) td(CSiL-RDH) tsu(D-RDL) ALE tw(ALEH) td(RDH-ALEL) td(RDH-BXWH) tc f(XIN) <At write> CS i th(BXWH-A) th(BXWH-CSiL) RD td(A-BXWH) td(CSiL-BXWL) td(CSiL-BXWH) ALE td(BXWH-RDH) tw(BXWL) td(BXWH-ALEL) td(D-BXWL) th(BXWH-D) tpxz(BXWH-DZ) Normal access : 0/1/2 wait td(A-ALEL) td(A-ALEL) tw(RDH) td(RDH-D) tw(BXWH) BLW BHW BLW BHW td(φ1-RDL) td(φ1-RDH) tw(ALEH) Bus cycle td(φ1-BXWL) td(φ1-BXWH) A0–A23 D 0–D 7, D8–D 15 Test conditions

VCC = 5 V ± 0.5 V, Ta = –20 to 85 °C
Input timing voltage : VIL=0.8 V, VIH=2.5 V
Output timing voltage: VOL =0.8 V, VOH =2.0 V, CL=15 pF (CSi)
Output timing voltage: VOL =0.8 V, VOH =2.0 V, CL=50 pF (except for CSi)

M37920FCCGP, M37920FCCHP M37920FGCGP, M37920FGCHPPRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION MITSUBISHI MICROCOMPUTERS 142 Bus cycle CS i RD ALE BLW BHW f(XIN) CS i RD ALE BLW BHW td(CSiL-BXWL) td(CSiL-RDL) td(A-ALEL) <At read> th(RDH-D) th(RDH-A) th(RDH-CSiL) tw(RDL) ta(CSiL-D) ta(RDL-D) ta(A-D) td(A-RDH) td(CSiL-RDH) tsu(D-RDL) tw(ALEH) td(RDH-BXWH) tc <At write> th(BXWH-A) th(BXWH-CSiL) td(A-BXWH) td(CSiL-BXWH) tw(ALEH) td(BXWH-RDH) tw(BXWL) td(D-BXWL) th(BXWH-D) tpxz(BXWH-DZ) td(A-ALEL) tw(RDH) td(RDH-D) tw(BXWH) td(ALEL-RDH) td(ALEL-BXWH) Normal access : ALE expansion wait td(φ1-RDL) td(φ1-RDH) Bus cycle td(φ1-BXWL) td(φ1-BXWH) A0–A23 D 0–D 7, D8–D 15 A0–A23 D 0–D 7, D8–D 15 Test conditions

VCC = 5 V ± 0.5 V, Ta = –20 to 85 °C
Input timing voltage : VIL=0.8 V, VIH=2.5 V
Output timing voltage: VOL =0.8 V, VOH =2.0 V, CL=15 pF (CSi)
Output timing voltage: VOL =0.8 V, VOH =2.0 V, CL=50 pF (except for CSi)

M37920FCCGP, M37920FCCHP M37920FGCGP, M37920FGCHPPRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION MITSUBISHI MICROCOMPUTERS Burst ROM access : 0/1/2 wait at instruction prefetch th(BA-D) td(RDH-BXWH) BLWBHW RD ta(RDL-D) td(A-RDH) CS i th(RDH-A) ta(CSiL-D) ta(A-D) ta(BA-D) th(BA-D) th(BA-D) th(RDH-D) ta(BA-D) ta(BA-D) th(RDH-CSiL) td(CSiL-RDH) td(A-ALEL) tw(ALEH) ALE td(RDH-ALEL) tw(RDH) A 0–A D 0–D 7, D 8–D Test conditions • V CC = 5 V ± 0.5 V, Ta = –20 to 85

Input timing voltage : V IL =0.8 V, V IH =2.5 V
Output timing voltage: V OL =0.8 V, V OH =2.0 V, C L=15 pF (CS
Output timing voltage: V OL =0.8 V, V OH =2.0 V, C L=50 pF (except for CS

M37920FCCGP, M37920FCCHP M37920FGCGP, M37920FGCHPPRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION MITSUBISHI MICROCOMPUTERS 144 tw(RASH) td(CASH-RASH) th(RASL-CASH) th(CASL-RASL) tw(CASL) td(RA-RASH) th(RASL-RA) td(CA-CASH) th(CASH-CA) td(WH-CASH) td(WL-CASH) th(CASL-WL) td(D-CASH) th(CASL-D) tpxz(CASH-D) tpxz(WH-D) ta(RASL-D) ta(CASL-D) th(CASH-D) ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 1.5tc-20 1.5tc-20 1.5tc-20 tc-15 tc-15 0.5tc-25 tc-40 0.5tc-20 3tc-15 tc-15 tc-15 tc-20 1.5tc-15 0.5tc+10 DRAM access Timing Requirements (VCC = 5 V ± 0.5 V, VSS = 0 V, Ta = 0 to 70 °C, f(XIN) = 20 MHz, unless otherwise noted) Limits RAS access time CAS access time Data input hold time after CAS Parameter Max.Min. UnitSymbol ns ns ns0 2.5tc-35 tc-30 Limits RAS high-level pulse width CAS high-level valid time before RAS CAS high-level hold time after RAS’s low level RAS hold time after CAS’s low level CAS low-level pulse width Row address valid time before RAS Row address hold time after RAS’s low level Column address valid time before CAS Column address hold time after CAS’s high level W high-level valid time before CAS W low-level valid time before CAS W hold time after CAS’s low level Data output valid time before CAS Data output hold time after CAS’s low level Floating start delay time after CAS Floating start delay time after write Parameter Max.Min. UnitSymbol Switching characteristics (VCC = 5 V ± 0.5 V, VSS = 0 V, Ta = 0 to 70 °C, f(XIN) = 20 MHz, unless otherwise noted) 0.5tc+10

M37920FCCGP, M37920FCCHP M37920FGCGP, M37920FGCHPPRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION MITSUBISHI MICROCOMPUTERS th(RASL-RA) DRAM access RAS i LCAS,UCAS (CAS) W (WRL,WRH) Column th(CASL-RASL) ta(CASL-D) th(CASH-D) tw(RASH) W (WRL,WRH) RAS i td(RA-RASH) th(CASH-CA) tw(CASL) td(WH-CASH) ta(RASL-D) LCAS,UCAS (CAS) th(RASL-RA) td(CA-CASH) td(CASH-RASH) Row address Column address Row address th(RASL-CASH) th(CASL-D) tw(RASH) td(RA-RASH) th(CASH-CA) tw(CASL) td(D-CASH) <At write> td(WL-CASH) th(CASL-WL) td(CA-CASH) td(CASH-RASH) tpxz(CASH-D) th(CASL-RASL)th(RASL-CASH) Row address Column address Row address <At read> A0–A23 D 0–D 7, D8–D 15 A0–A23 D 0–D 7, D8–D 15 Test conditions

VCC = 5 V ± 0.5 V, Ta = 0 to 70 °C
Input timing voltage : VIL=0.8 V, VIH=2.5 V
Output timing voltage: VOL =0.8 V, VOH =2.0 V, CL=15 pF (RASi)
Output timing voltage: VOL =0.8 V, VOH =2.0 V, CL=50 pF (except for RASi) address Column address

M37920FCCGP, M37920FCCHP M37920FGCGP, M37920FGCHPPRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION MITSUBISHI MICROCOMPUTERS 146 tw(RAS CBR L) tw(CAS CBR L) td(CASCBR L-RASCBR H) td(RASCBR L-CASCBR L) td(CASSLFR L-RASSLFR H) th(RASSLFR H-CAS SLFR L) 2tc–15 2tc–15 tc–15 tc–15 tc–15 –15 ns ns ns ns ns ns DRAM refresh Switching characteristics (VCC = 5 V ± 0.5 V, VSS = 0 V, Ta = 0 to 70 °C, f(XIN) = 20 MHz, unless otherwise noted) Limits RAS low-level pulse width (At CAS before RAS refresh) CAS low-level pulse width (At CAS before RAS refresh) RAS high-level valid time after CAS’s low level start (At CAS before RAS refresh) CAS low-level valid time after RAS’s low level start (At CAS before RAS refresh) RAS high-level valid time after CAS’s low level start (At selfrefresh) CAS low-level hold time after RAS’s high level (At selfrefresh) Parameter Max.Min. UnitSymbol

M37920FCCGP, M37920FCCHP M37920FGCGP, M37920FGCHPPRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION MITSUBISHI MICROCOMPUTERS td(CAS CBR L-RAS CBR H) DRAM refresh : CAS before RAS refresh td(RAS CBR L-CAS CBR L) tw(RAS CBR L) W (WRL,WRH) RAS i tw(CAS CBR L) LCAS,UCAS (CAS) Refresh cycle td(CAS SLFR L-RAS SLFR H) th(RAS SLFR H-CAS SLFR L) W (WRL,WRH) RAS i LCAS,UCAS (CAS) Refresh cycle DRAM refresh : selfrefresh Test conditions

VCC = 5 V ± 0.5 V, Ta = 0 to 70 °C
Output timing voltage: VOL =0.8 V, VOH =2.0 V, CL=15 pF (RASi)
Output timing voltage: VOL =0.8 V, VOH =2.0 V, CL=50 pF (except for RASi)

M37920FCCGP, M37920FCCHP M37920FGCGP, M37920FGCHPPRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION MITSUBISHI MICROCOMPUTERS 148 tw(TCL) td(RDH-TCL) td(BXWH-TCL) td(TCL-DMAACKL) Unit TC input setup time TC input pulse width DMAREQ i input setup time DMAREQ i input pulse width DMA transfer timing Timing Requirements (VCC = 5 V ± 0.5 V, VSS = 0 V, Ta = –20 to 85 °C, f(XIN) = 20 MHz, unless otherwise noted) Max.ParameterSymbol UnitMin. Limits tsu(TCINL-φ1) tw(TC INL) tsu(DRQL-φ1) tw(DRQL) ns ns ns ns tc + 20 tc TC output pulse width TC output start delay time after read TC output start delay time after write DMAACK low-level output valid time after TC output start Switching characteristics (V CC = 5 V ± 0.5 V, VSS = 0 V, Ta = –20 to 85 °C, f(XIN) = 20 MHz, unless otherwise noted) Max.ParameterSymbol Min. Limits ns ns ns ns tc-20 tc-15 tc-15 2.5tc-20 TC 50 pF 3 kΩ Test circuit for TC output

TC input TC input tsu(TCINL-φ1)
DMAREQ i input DMAREQ i input tsu(DRQL-φ1) tw(DRQL) tw(TC INL) Test conditions
Vcc = 5 V ± 0.5 V, Ta = –20 to 85 °C
Input timing voltage : VIL = 1.0 V, VIH = 4.0 V
Output timing voltage : VOL = 0.8 V, VOH = 2.0 V, CL = 50 pF CS i RD BLW BHW ALE tw(TCL) TC DMAACK i td(RDH-TCL) td(BXWH-TCL) td(TCL-DMAACKL) Final transfer cycle Terminate processing (Next bus cycle)
Transfer terminate timing A0–A23 D 0–D 7, D8–D 15 Test conditions
VCC = 5 V ± 0.5 V, Ta = –20 to 85 °C
Output timing voltage : VOL = 0.8 V, VOH = 2.0 V, CL = 50 pF

M37920FCCGP, M37920FCCHP M37920FGCGP, M37920FGCHPPRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION MITSUBISHI MICROCOMPUTERS 150 QFP100-P-1420-0.65 1.58 Weight(g) JEDEC CodeEIAJ Package Code Lead Material Alloy 42 100P6S-A Plastic 100pin 14✕ 20mm body QFP 0.1 0.2 Symbol Min Nom Max A b c D E H E L y Dimension in Millimeters H D 0.35 ––I2 1.3 ––M D 14.6 ––M E 20.6 10°0° 0.1 1.4 0.80.60.4 23.122.822.5 17.116.816.5 0.65 20.220.019.8 14.214.013.8 0.20.150.13 0.40.30.25 2.8 3.05 e e e E c H E H D D M D M E A Fb A A L y Recommended Mount Pad Detail F 100 PACKAGE OUTLINE LQFP100-P-1414-0.50 Weight(g) JEDEC CodeEIAJ Package Code Lead Material Cu Alloy 100P6Q-A Plastic 100pin 14✕ 14mm body LQFP 0.1 0.2 Symbol Min Nom Max A b c D E H E L y Dimension in Millimeters H D 0.225 ––I2 1.0 ––M D 14.4 ––M E 14.4 10°0° 0.1 1.0 0.70.50.3 16.216.015.8 16.216.015.8 0.5 14.114.013.9 14.114.013.9 0.1750.1250.105 0.280.180.13 1.4 1.7 e e e E c H E 5026 H D D M D M E A F b A A L y Recommended Mount Pad Detail F 100

M37920FCCGP, M37920FCCHP M37920FGCGP, M37920FGCHPPRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION MITSUBISHI MICROCOMPUTERS © 2000 MITSUBISHI ELECTRIC CORP. New publication, effective Jun., 2000. Specifications subject to change without notice. Notes regarding these materials

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Rev. Rev. No. date

1.0 First Edition 990602

2.0 Refer to Corrections and Supplementary Explanation for “M37920FxCGP/HP Datasheet (REV.A)”. 000628 Revision History M37920FCCGP/HP, M37920FGCGP/HP Datasheet (1/1) Revision Description

Corrections and Supplement ar y Explanation for M37920FxC Dat asheet (REV. A) NO.1 Page Erro r Correction (1/6) Page 4, BL O C K DIAGRA M No t Note: RAM 2048 bytes 4096 bytes 6144 bytes M37920F8 CGP ,M37920F8C H P M37920FCCGP,M37920FCCHP M37920FGCGP,M37920FGCHP Flash memory

60 Kbytes

Note: All pages, H eader Page 3, PIN CONFI GUR AT ION Page 121, Fig 119, Pi n conne ct i on of M3792 xC HP in f l ash m emory M37920F8 C G P , M37920F 8C HP , M37920FC CG P, M37920FC CHP M37920FGCGP, M 7920FGCHP M37920F C CG P, M37920F CC H P, M37920F G C G P , M37920FGCH P Page 1 DISTI N CTI VE FEAT U RES M emory [M 379 20F8CG P , M37920F8C HP] Fl ash memor y (User R O M ar ea .... .... ... .... .... .60 Kbytes RA M ... .... .... .... ... .... .... .... ... .... .... .... .... ... .... .... .... .2048 bytes (Deleted) M37920F8 C HP M37920FC CHP M37920FGCH P M37920F CC HP M37920FGCHP (Type) (Type) Page 5, Chip-select wait control C hip select area ✕ 4 (C S0–C S3). A wait number and bus width can be set for each chip select area. C hip select area ✕ 4 (C S0–C S3). A bus cycle type and bus width can be set for each chip select area. Page 2, PIN CONFIGURATIO N Page 120, Fig. 118, Pin connection of M37920FxCGP in flash memory M37920F8 C G P M37920FC CGP M37920FGCGP M37920F CCG P M37920FGCGP (Type) (Type) RAM 4096 bytes 6144 bytes M37920F CCGP ,M37920FCC H P M37920FGCGP,M37920FGCHP Flash memory Pa ge 5, Parameter Oper a t i ng temperat ure r a nge •••••• Operating ambient temperature range ••••• Page 5, No t Note: RAM 2048 bytes 4096 bytes 6144 bytes M37920F8 C G P,M37920F8C H P M37920FC CGP ,M3792 C CHP M37920FGCGP, M 37920FG C HP Flash memory (User ROM area) M37920F8 C G P,M37920F8C H P M37920FC CGP ,M3792 C CHP M37920FGCGP, M 37920FG C HP Note: RAM 4096 bytes M37920F CCGP ,M37920FCC H PFlash memory (User ROM area) M37920F CCGP ,M37920FCC H P M37920F GCGP ,M37920FGC H P 248 Kbytes M37920F GCGP ,M37920FGC H P 6144 bytes Pa ge 6 , N o t e User R O M area M37920F8C G M 37920F8CH P 4 bl M37920FC CGP , M37920FCC HP 5 bl M37920FGCGP, M37920 F GCH P 7 bl Note: User R O M area M37920FC CGP , M37920FCC HP 5 bl M37920FGCGP, M37920 F GCH P 7 bl Note: Page 1 DESCRIPTI ON; Li nes These microcom p ut ers includ e the 4-channel DMA contr o ller a nd the DR AM con t rolle r with enhanced fast page mode. These microcomputers include the 4-channel DMA controller and the DRAM controller. Page 1 DISTI N CTI VE FEAT U RES I nterrupts sources, 7 leve ls sources, 7 levels Page 5, DRAM controller 1 channel Supports fast page access mode. Incorparates 8-bit refresh timer. Supports CAS before RAS refresh method •••••• 1 channel Incorparates 8-bit refresh timer. Supports CAS before RAS refresh method •••••• Page 5, Interrupts 6 external types, 17 internal types. Each interrupt ••••••6 external types, 20 internal types. Each interrupt ••••••

Corrections and Supplement ar y Explanation for M37920FxC Dat asheet (REV. A) NO.2 Page Erro r Correction (2/6) Page 9, Fig. 1 Fig. 2. Memory map of M37920FCCG P and M37920FCCHP (Single-chip mode) Fig. 1. Memory map of M37920FCCG P and M37920FCCHP (Single-chip mode) Mem ory m ap of M 379 20F8CG P and M37920F 8C HP (Singl chi p m ode) (Deleted) Fi g. 3. M emory map of M37920F G C G P and M37920FGCH P ( S ingle-chip mode) Fig. 2. Memory map of M37920FGCG P and M37920FGCHP (Single-chip mode) Page 10, Fig. 2 Page 11, Fig. 4; address 0016, 0116 00000016 00000116 00000016 00000116 Reserved area (Note) Reserved area (Note) b31 b0 DB Data buff er b31 b0 D Q Data buff er Page 18, Fig. 8 Data buff er Temporarity stores data which has been ••••••••, and external areas by the BIU or which is to be Temporarily stores data which has been ••••••••, and external areas by the BIU; or temporarily stores data which is to be written to internal Page 18, Table 1 Instruction queue buffer Temporarity stores an instruction which ••••••••. Temporarily stores an instruction which ••••••••. (this contents is published for one page) ALE is an addr ess latch enabl e si gnal. ••• ••••• No t e: The chip select wait contr ol ler, by the chip select wait contr o ller. (Deleted) T he f i nal page of S election of p r ocessor m ode” Processor mode register 1 10243567 Recovery cycle insert select bit

••• H O LD input, HLDA output select bit (P40 and P44 function as •••) ALE output select bit
••• RDY input select bit
••• Direct page register switch bit
••• Page 28, Fig. 12 Processor mode register 1 10243567 Recovery cycle insert select bit (Notes 2 and 3)
••• H O LD input, HLDA output select bit (Notes 2 to 4) (P43 and P44 function as •••) ALE output select bit (Notes 2 and 3)
••• RDY input select bit (Notes 2 to 4)
••• Direct page register switch bit (Note 1)
••• Internal RO M access wait bit
••• Internal RO M access wait bit (Note 5)
•••

Corrections and Supplement ar y Explanation for M37920FxC Dat asheet (REV. A) NO.3 Page Erro r Correction (3/6) Page 3 5 , Fig. 17, Area CSx st art address regi st er = 0 to 3) Area C S x start address r eg ister = 1, 01 01 Area C S x start address r eg ister = 1, “0” at read. 2 2 Area C S x start address r eg ister = 0, 01 01 These bi t s determ i ne ••••• Area C S3 start address r e gister = 0, “0” at read. 2 2 These bits determine ••••• Page 61, Interrupt request at completion of reception

•••• control register 0 (UART receive interrupt mode
•••• control register 0 (UARTk receive interrupt mode Page 51, Left column, Lines 14, 17, (Line 9) (Line 9)
•••• UARTi receive interrupt mode select bit ••••• (Lines 18, 20)
•••• UARTk receive interrupt mode select bit ••••• (Lines 18, 20) Ladder n et w or k Resistor ladder network Page 67, Fig. 63 Page 68, VR E F c o n n e c t i o the ladder net w or k can be cut off by disconnecting ladd er network • the r esi st or ladder net w or k can be cut o f f by disconnect- ing resistor la dder network •••
••• (Lines 2, 3) (Lines 2, 3) (Li ne 7) (Line 7) Notes 1: After reset, this bit’s contents can be switched only once. During the sof tware execution, be sure not to switch this bit’s contents. 2: In the single-chip mode, these bits’ functions are disabled regardless of these bits’ contents 3: While VSS level voltage is applied to pin MD0, each of these bits is “0” at reset. While VCC level voltage is applied to pin MD0, on the other hand, each of these bits is “1” at reset. 4: In the memory expansion or microprocessor mode, if this bit’s contents is switched from “1” to “0”, this bit will be cleared to “0”. After this clearance, this bit cannot return to “1”. If it is necessary to set this bit to “1”, be sure to reset the microcomputer. 5: In the microprocessor mode, this bit is invalid. When the internal flash memory is reprogram- med in the CPU reprogramming mode, be sure to clear this bit to “0”. Page 28, Fig. 12

Corrections and Supplement ar y Explanation for M37920FxC Dat asheet (REV. A) NO.4 Page Erro r Correction (4/6) Page 92, Left column, Lines 28, 29 Bi t 2 of the DR AM con t rol register is the access m ode select bit. Whe n bi t 2 is “0” , nor mal access is selected, when it is “1” , f a st page access is selected. When t he fast page access is selected, t h e access suppo r ting the f ast page access mode o f DR AM i s perfor med, if the range whi ch can be speci f i ed with t he same r ow ad dr ess is continuousl y a ccessed. If the row address cha nges during the f ast page access, the new row addresses will be output ag ain aft er t ha t fast pag e acce ss i s term i nat ed Then the f ast page access wil l r estart Fi gur e 93 shows an operating waveform example of the DR AM control signal s and add r ess bus in the f ast page access. Bi t 4 of the DR AM Bi t 4 of the DR AM DR AM control r eg ister Access mode select bit 0: Nor mal access 1: Fast pa ge a ccess 2Page 95, Fig. 90 DR AM control r eg ister Fi x this bit to “0”. 000 Operating waveform example of DRAM control signals and address bus in fast page access (Deleted) Page 117, Right column, Lines 15 to 17 area if the user use s the flash m emory se r ial I/O mode. Note that, when the boot ROM area i s area if the user uses the flash memory serial I/O mode. Addresses FFB016 to FFBF16 are the reserved area for the serial programmer. Therefore, when the user uses the flash memory serial I/O mode, do not program to this area. Note that, when the boot ROM area is read ••••••••• M37920F8 C G P , M37920F 8C HP : block configuration of internal flash m emory (Deleted) Page 118 RESET; [Function] The reset i nput pi n. Input “ H ” aft e r “ L ” is input. The reset input pin. P42; [Function] This is an I/O pin for serial data. This is an I/O pin for serial data. C onnect this pin to VCC via a resistor (about 1 kΩ ). Thi s i s an i nput pi n for a serial cl ock. C o nnect this pin to VC C via a resistor (about 1 kΩ ) This is an input pin for a serial clock.P44; [Function] NMI; [Function] Input “H”. Input “H”, or leave this pin open. Page 122, Boot mode progr am the u ser ROM area. program the user ROM area. After reset removal, be sure not to change the status at pins MD0 and MD1. (Li nes 22, 23) (Li nes 22, 23) Page 122, Fig. 120, Note 4 4: V alid onl y w hen bit 1 = “ 1”. Set b it 3 to “ 1” ( reset) , and then clear to “0” 4: Valid only when bit 1 = “1”. Set bit 3 to “1” (reset), and then clear to “0”. This bit 3 must be controlled with the CPU reprogramming mode select bit (bit 1) = “1”. Page 99, Right column, Lines 1 to 3 When the wavefor m output sel ect bits are set to “11” ( bit 1 = bit 0 = “ 1”), RT P13 to R TP10, RT P03, and RTP become pulse output po r t pins. When the wavefor When the waveform output select bits are set to “11” (bit 1 = bit 0 = “1”), pulse output port pins are divided into two groups; one consists of RTP1 3 to RTP10, RTP03, RTP02 and the other consists of RTP01 and RTP00.

Corrections and Supplement ar y Explanation for M37920FxC Dat asheet (REV. A) NO.5 Page Erro r Correction (5/6) Page 123, Right column, After line 24 request occu r rence. request occu r rence. In the C PU reprogr amming m od e, be sure no t to use the ST P and WIT instr uction Page 124, Fig. 121 The C P U r e pr ogramm i ng mode select bit is set to “ 1”. (Wr iting of “ 0” → Writing of “1”) Writing of “1” to t h e C PU repr og r amm i ng m ode sele ct bit. (Wr iting of “ 0” → Writing of “1”) Page 124, Software Commands 5) is ignored. (Li nes 6, 7) 5) is ignored. ( E xcept for the write data at the 2nd cycle of a page progr a m ming comm and.) (Li nes 6, 7) Page 125, Page program Command

••••••, the same way as bit 7 of the status register. (Lines 4 to 7)
••••••, the same wayas bit 7 of the status register. Before execution of the next command, be sure to verify that bit 7 of the status register (SR.7) or the RY/BY status bit is set to “1” (READY). During the automatic programming operation, writing of commands and access to the flash memory must not be performed. Page 125, Block Erase Command (Li nes 20 to 2 3)
••••••, the same way as bit 7 of the status register. (Li nes 20 to 2 3)
••••••, the same way as bit 7 of the status register. Before execution of the next command, be sure to verify that bit 7 of the status register (SR.7) or the RY/BY status bit is set to “1” (READY). During the automatic erase operation, writing of commands and access to the flash memory must not be performed. Page 127, E r ase Al l Unlocked B lock Co m mand (Lines 9 to 11)
•••••• is also reported by a read of the status register. (Lines 9 to 11)
•••••• is also reported by a read of the status register. During the automatic erase execution ( when the RY/BY status bit = “0” ), writing of commands and access to the flash memory must not be performed. (Lines 4 to 7) Page 124, Page program Command (After line 20) (After line 20)
•••••• mode is m ai nt a ined. I n continuou s program ming, if t h er e is no progr amming er ror, page program ming comm ands can be executed with the r ead status regi st er mode kept Page 123, Left column, Lines 15 to 19 Therefore, a soft w ar e comm a nd co nsists of 8-bit un its must be written only t o an even address; therefor e, any data writt en to an odd addr ess wi ll be inval id. The write stat e Therefore, a soft w ar e comm a nd co nsisting of 8 bits must be writt e n to an even address; theref o r e, any com mand written to an odd address will be in valid. Since the write data at the 2nd cycle of a program ming comm an d con si- sts o f 16 bits, thi s data must be written to even and odd addresses. The write stat e Page 127, D ata P r otect F unction (Blo ck Lock) (Aft er li ne 20) lock bit is ter minated. (Aft er li ne 20) lock bit is ter minated. To perfor m er ase or pr ogramm i ng, be sure t o do one of the f ol lowi ng.
By executing the r ead lock bi t status command, verify that the lock of t he target bl ock i s i nvalid.
Set t he lo ck bi t inva lidity select bit t o “1” to invali date the lock. When the block er ase or pr ogramm i ng i s p er form ed wi t h the lock va lid, t he erase stat us bit (SR.5) an d program ming st a t us bit (SR.4) are set to “ term i nated by error (Titll e) Pag e P r og r am C om mand (4116) (Titlle) Page Programming C ommand (4116)

Corrections and Supplement ar y Explanation for M37920FxC Dat asheet (REV. A) NO.6 Page Erro r Correction (6/6) Page 144, Swi t ch ing ch ar acteristics Mi n. 0.5tc–20 Lim its Max.Symbol td(C AF-CA SH) tc–40 Parameter Unit td(WFL-C ASH td(DF-CASH) tpxz(WH-D) Co lumn address vali d time bef ore CA S ( When fast page a ccess ON is sel ect ed) W l ow-l evel vali d time bef ore CAS (When fast page access O N i s sel ect ed) Data output valid time before CAS (When fast page access ON is selected) Fl oat i ng start dela y time after wri t e tpxz(C ASH-D ) Fl oat i ng start dela y time after CA S 0.5tc–20 0.5t c+10 0.5tc+10 ns ns ns ns ns Mi n. Lim its Max.Symbol Parameter Uni t tpxz(WH-D) Floating start delay time after write tpxz(CASH-D) Floating start delay time after CAS 0.5t c+10 0.5t c+10 ns ns Page 145, DRAM access DR AM access : f ast page access OFF (Title) DR AM access (Title) Timing of DRAM access : fast page access OFF (Deleted) Page 130, AB SOLUT E MAX IM UM RA TINGS; Topr Oper a t i ng temperat ure •••••• Oper a t i ng a m bie nt tem p er ature •••••

Product Information

M37920FCCGP specifications and overview.

Summary

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION

Description

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION

Source title M37920FCCGP Datasheet(PDF) - Mitsubishi Electric Semiconductor

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