M37906F8CFP

DATASHEET SEARCH SITE | WWW.ALLDATASHEET.COM

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 34

Technical content

M37906F8CFP, M37906F8CSP PRELIMINAR Y Notice: This is not a final specification. Som e param etric limits are subject to change. 16-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS

DESCRIPTION

These are single-chip 16-bit microcomputers designed with high-per- formance CMOS silicon gate technology, including the internal flash memory and being packaged in 42-pin plastic molded SSOP or shrink plastic molded DIP. These microcomputers support the 7900 Series instruction set, which are enhanced and expanded instruction set and are upper-compatible with the 7700/7751 Series instruction set. The CPU of these microcomputers is a 16-bit parallel processor that can also be switched to perform 8-bit parallel processing. Also, the bus interface unit of these microcomputers enhances the memory access efficiency to execute instructions fast. Therefore, these mi- crocomputers are suitable for office, business, and industrial equip- ment controller that require high-speed processing of large data. Also, they are suitable for motor-control equipment since each of them includes the motor control circuit. For the internal flash memory, single-power-supply programming and erasure, using a PROM programmer or the control by the cen- tral processing unit (CPU), is supported. Also, each of these micro- computers has the memory area dedicated for storing a certain software which controls programming and erasure (reprogramming control software). Therefore, on these microcomputers, the program can easily be changed even after they are mounted on the board. DISTINCTIVE FEATURES <Microcomputer mode>

• Memory
• Instruction execution time (Three-phase motor drive waveform or Pulse motor drive waveform output is available.)
• 12-bit watchdog timer <Flash memory mode> M37906F8CFP, M37906F8CSP
• Programming/Erase control by software command APPLICATION
• Control devices for office equipment such as copiers and facsimiles
• Control devices for industrial equipment such as communication and measuring instruments
• Control devices for equipment, requiring motor control, such as inverter air conditioners and general-purpose inverters

M37906F8CFP, M37906F8CSP PRELIMINAR Y Notice: This is not a final specification. Som e param etric lim its are subject to change. 16-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS P70/AN0 P71/AN1 P72/AN2 P73/AN3/DA0 AV SS P74/AN4/DA1/INT3/RTPTRG0 VREF P10/CTS0/RTS0 P11/CTS0/CLK0 P14/CTS1/RTS1 P20/TA4OUT P21/TA4IN P22/TA9OUT P23/TA9IN P25(/TB1IN) P26(/TB2IN) P27(/INT3/RTPTRG0 ) MD1 XOUT P24(/TB0IN) P15/CTS1/CLK1 P16/RxD1 AV CC P12/RxD0 P13/TxD0 P17/TxD1 XIN VSS P65/TA2IN/U/RTP11 P64/TA2OUT /V/RTP10 P63/TA1IN/W/RTP0 3 P62/TA1OUT /U/RTP02 P61/TA0IN/V/RTP01 P60/TA0OUT /W/RTP0 0 P57/INT7/TB2IN/IDU P56/INT6/TB1IN/IDV P55/INT5/TB0IN/IDW MD0 VCONT RESET M37906F8CFP P6OUT CUT /INT4 VCC (Note) (Note) (Note) M37906F8CFP PIN CONFIGURATION (TOP VIEW) Outline 42P2R-E Note: Allocation of pins TB0IN to TB2IN and INT3/RTPTRG0 can be switch- ed by software.

M37906F8CFP, M37906F8CSP PRELIMINAR Y Notice: This is not a final specification. Som e param etric lim its are subject to change. 16-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS M37906F8CSP PIN CONFIGURATION (TOP VIEW) Outline 42P4B P70/AN0 P71/AN1 P72/AN2 P73/AN3/DA0 AV SS P74/AN4/DA1/INT3/RTPTRG0 VREF P10/CTS0/RTS0 P11/CTS0/CLK0 P14/CTS1/RTS1 P20/TA4OUT P21/TA4IN P22/TA9OUT P23/TA9IN P25(/TB1IN) P26(/TB2IN) P27(/INT3/RTPTRG0 ) MD1 XOUT P24(/TB0IN) P15/CTS1/CLK1 P16/RxD1 AV CC P12/RxD0 P13/TxD0 P17/TxD1 XIN VSS P65/TA2IN/U/RTP11 P64/TA2OUT /V/RTP10 P63/TA1IN/W/RTP0 3 P62/TA1OUT /U/RTP02 P61/TA0IN/V/RTP01 P60/TA0OUT /W/RTP0 0 P57/INT7/TB2IN/IDU P56/INT6/TB1IN/IDV P55/INT5/TB0IN/IDW MD0 VCONT RESET M37906F8CSP P6OUT CUT /INT4 VCC (Note) (Note) (Note) Note: Allocation of pins TB0IN to TB2IN and INT3/RTPTRG0 can be switch- ed by software.

M37906F8CFP, M37906F8CSP PRELIMINAR Y Notice: This is not a final specification. Som e param etric lim its are subject to change. 16-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS Data bank Register DT (8) Program Counter PC (16) Incrementer/Decrementer (24) Program Bank Register PG (8) Input Buffer Register IB (16) Direct Page Register DPR0 (16) Stack Pointer S (16) Index Register Y (16) Index Register X (16) Arithmetic Logic Unit (16) Accumulator B (16) Accumulator A (16) Instruction Register (8) Central Processing Unit (CPU) Incrementer (24) Program Address Register PA (24) Data Address Register DA (24) Bus Interface Unit(BIU) RESET MD1 Reference Voltage Input V REF (0V)AV SS AVcc Vcc Clock Generating Circuit Clock input X IN V CONT X OUT Data Buffer DQ0 (8) Instruction Queue Buffer Q0 (8) Data Bus (Odd) Address Bus A-D Converter (10) UART1 (9)UART0 (9) Watchdog TimerTimer TB1 (16)Timer TB2 (16)Timer TB0 (16) D-A

1 Converter (8)

Timer TA1 (16)Timer TA2 (16)Timer TA3 (16)Timer TA4 (16)Timer TA0 (16) RAM 3072 bytes P5(3) Input/Output port P5 P2(8) Input/Output port P2 P6(6) Input/Output port P6 P1(8) Input/Output port P1 P7(5) Input/Output port P7 MD0 (0V)Vss Processor Status Register PS (11) P6OUT CUT Flash Memory60 Kbytes D-A

0 Converter (8)

Data Bus (Even) Data Buffer DQ1 (8) Data Buffer DQ2 (8) Data Buffer DQ3 (8) Instruction Queue Buffer Q1 (8) Instruction Queue Buffer Q2 (8) Instruction Queue Buffer Q3 (8) Instruction Queue Buffer Q4 (8) Instruction Queue Buffer Q5 (8) Instruction Queue Buffer Q6 (8) Instruction Queue Buffer Q7 (8) Instruction Queue Buffer Q8 (8) Instruction Queue Buffer Q9 (8) Direct Page Register DPR1 (16) Direct Page Register DPR2 (16) Direct Page Register DPR3 (16) Clock output Reset input Timer TA6 (16)Timer TA7 (16)Timer TA8 (16)Timer TA9 (16)Timer TA5 (16) BLOCK DIAGRAM

M37906F8CFP, M37906F8CSP PRELIMINAR Y Notice: This is not a final specification. Som e param etric lim its are subject to change. 16-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS Memory expansion Operating ambient temperature range Device structure Package Ports’ input/output characteristics Power supply voltage Power dissipation Number of basic machine instructions Instruction execution time External clock input frequency f(X IN) System clock input frequency f(fsys) Memory size Programmable input/output ports Multi-functional timers Serial I/O A-D converter D-A converter Dead-time timer Watchdog timer Interrupts Clock generating circuit PLL frequency multiplier Flash memory (User ROM area) RAM Flash memory (Boot ROM area) P1, P2 TA0–TA9 TB0 –TB2 UART0 and UART1 FUNCTIONS (Microcomputer mode) FunctionsParameter Input/Output withstand voltage Output current Maskable interrups Non-maskable interrups 203 50 ns (the fastest instruction at f(fsys) = 20 MHz) 20 MHz (Max.) 20 MHz (Max.)

60 Kbytes

8 Kbytes

8-bit ✕ 2 3-bit ✕ 1 6-bit ✕ 1 5-bit ✕ 1 16-bit ✕ 10 16-bit ✕ 3 (UART or Clock synchronous serial I/O) ✕ 2 10-bit successive approximation method ✕ 1 (5 channels) 8-bit ✕ 2 8-bit ✕ 3 12-bit ✕ 1 5 external sources, 18 internal sources. Each interrupt can be set to a priority level within the range of 0–7 by software. 3 internal sources Incorporated (externally connected to a ceramic resonator or quartz-crystal resonator). The following multiplication ratios are available: ✕ 2, ✕ 3, ✕ 4 5 V±0.5 V 125 mW (at f(fsys) = 20 MHz, Typ.; the PLL frequency multiplier is inactive.) 5 V 5 mA Not available (single-chip mode only). –20 to 85 °C CMOS high-performance silicon gate process (Note) Packages M37906F8CFP 42-pin plastic molded SSOP (42P2R-E) M37906F8CSP 42-pin shrink plastic molded DIP (42P4B) Note:

M37906F8CFP, M37906F8CSP PRELIMINAR Y Notice: This is not a final specification. Som e param etric lim its are subject to change. 16-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS Power supply voltage Programming/Erase voltage Flash memory mode Block division for erasure Programming method Erase method Programming/Erase control Number of commands Maximum number of reprograms User ROM area Boot ROM area Flash memory parallel I/O mode Flash memory serial I/O mode Flash memory CPU reprogramming mode Flash memory parallel I/O mode Flash memory serial I/O mode Flash memory CPU reprogramming mode 5 V±0.5 V 5 V±0.5 V 3 modes: parallel I/O, serial I/O, and CPU reprogramming modes 4 blocks (8 Kbytes ✕ 2, 16 Kbytes ✕ 1, 28 Kbytes ✕ 1); total of 1 block (8 Kbytes ✕ 1) (Note) Programmed per word User ROM area + Boot ROM area User ROM area User ROM area Total erase/Block erase User ROM area + Boot ROM area User ROM area User ROM area Programming/Erase control by software commands 6 commands 100 FUNCTIONS (Flash memory mode) FunctionsParameter Note: On shipment, our reprogramming control firmware for the flash memory serial I/O mode has been stored into the boot ROM area.

M37906F8CFP, M37906F8CSP PRELIMINAR Y Notice: This is not a final specification. Som e param etric lim its are subject to change. 16-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS Vcc, Vss MD0 MD1 RESET X IN XOUT VCONT AVcc, AVss VREF P10–P17 P20–P27 P50–P57 P60–P65 P70–P74 P6OUT CUT Power supply input MD0 MD1 Reset input Clock input Clock output Filter circuit connection Analog power supply input Reference voltage input I/O port P1 I/O port P2 I/O port P5 I/O port P6 I/O port P7 P6OUT CUT input Input Input Input Input Output Input I/O I/O I/O I/O I/O Input Apply 5 V±0.5 V to Vcc, and 0 V to Vss. Connect this pin to V SS . Connect this pin to Vss. The microcomputer is reset when “L” level is applied to this pin. These are input and output pins of the internal clock generating circuit. Connect a ceramic or quartz-crystal oscillator between the X IN and XOUT pins. When an external clock is used, the clock source should be connected to the XIN pin, and the XOUT pin should be left open. When using the PLL frequency multiplier, connect this pin to the filter circuit. When not using the PLL frequency multiplier, this pin should be left open. Power supply input pins for the A-D converter and the D-A converter. Connect AVcc to Vcc, and AVss to Vss externally. This is the reference voltage input pin for the A-D converter and the D-A converter. Port P1 is an 8-bit I/O port. This port has an I/O direction register, and each pin can be programmed for input or output. These pins enter the input mode at reset. These pins also function as I/O port pins of UART0 and UART1. In addition to having the same functions as port P1, these pins also function as I/O pins for timers A4 and A9. By software setting, these pins also function as input pins for timers B0–B2, an input pin for INT 3, and a trigger input pin in the pulse output port mode. In addition to having the same functions as port P1, these pins also function as input pins for INT5–INT7, input pins for timers B0–B2, and input pins for position- data-input pins in the three-phase waveform mode. In addition to having the same functions as port P1, these pins also function as I/O pins for timers A0–A2, and output pins for the motor drive waveform. In addition to having the same functions as port P1, these pins also function as input pins for the A-D converter. P73 functions as an output pin for the D-A converter; P74 functions as an output pin for the D-A converter, an input pin for INT3, and a trigger input pin in the pulse output port mode. This pin has the function to forcibly place port P6 pins in the input mode. Also, this pin functions as an input pin for INT4; and this pin is used to input a signal, which forcibly cuts off a motor drive waveform output. PIN DESCRIPTION (MICROCOMPUTER MODE) FunctionsInput/ OutputNamePin

M37906F8CFP, M37906F8CSP PRELIMINAR Y Notice: This is not a final specification. Som e param etric lim its are subject to change. 16-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS PIN DESCRIPTION (FLASH MEMORY SERIAL I/O MODE) VCC , VSS MD0 MD1 ____ RESET X IN XOUT AVcc, AVss V REF P10–P17 P20–P23, P27 P24 P25 P26 P6OUT CUT P55–P57 P60–P65 P70–P74 VCONT Pin Power supply input MD0 MD1 Reset input Clock input Clock output Analog supply input Reference voltage input Input port P1 Input port P2 SCLK input SDA I/O BUSY output P6OUT CUT input Input port P5 Input port P6 Input port P7 Filter circuit connection Name Input Input Input Input Output Input Input Input Input I/O Output Input Input Input Input Input /Output Functions Apply 5 V ± 0.5 V to Vcc, and 0 V to Vss. Connect this pin to Vss. Connect this pin to Vss via a resistor of 10 kΩ to 100 kΩ . The reset input pin. Connect a ceramic oscillator between the X IN and XOUT pins, or input an external clock from the XIN pin with the XOUT pin left open. Connect AVcc to Vcc, and AVss to Vss. Input an arbitrary level within the range of VSS –VCC . (This is not used in the flash memory serial I/O mode.) Input “H ” or “L”, or leave them open. (This is not used in the flash memory serial I/O mode.) Input “H ” or “L”, or leave them open. (This is not used in the flash memory serial I/O mode.) This is an input pin for a serial clock. This is an I/O pin for serial data. Connect this pin to V CC via a resistor (about 1 kΩ ). This is an output pin for the BUSY signal. Input “H”. Input “H ” or “L”, or leave them open. (This is not used in the flash memory serial I/O mode.) Input “H ” or “L”, or leave them open. (This is not used in the flash memory serial I/O mode.) Input “H ” or “L”, or leave them open. (This is not used in the flash memory serial I/O mode.) Connect this pin to the filter circuit, or leave this pin open. (This is not used in the flash memory serial I/O mode.)

M37906F8CFP, M37906F8CSP PRELIMINAR Y Notice: This is not a final specification. Som e param etric lim its are subject to change. 16-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS BASIC FUNCTION BLOCKS Each of the M37906F8CFP and M37906F8CSP has the same func- tion as that of the M37906M4C-XXXFP except for the following. Therefore, for details except for the following, refer to the datasheet of the M37906M4C-XXXFP.

• Flash memory size
• RAM size MEMORY Figure 1 shows the memory map. Fig. 1 Memory map of M37906F8CFP, M37906F8CSP (Single-chip mode) Interrupt vector table 00000016 Bank 016 00FFFF 16 00000016 00040016 0000FF16 00FFFE 16 00FFB4 16 Internal RAM 3072 bytes Internal ROM

Peripheral devices’ control registers 000FFF 16 00100016 0003FF16 Unused area 00FFB4 16 00FFFF 16 Timer A6 Timer A7 Timer A8 Timer A9 Reserved area Reserved area 00000016 0000FF16 Peripheral devices’ control registers (See Figures 2 and 3.) 00010016 INT4 A-D conversion Reserved area Reserved area Address matching detect Reserved area INT5 INT6 INT7 Timer A5 UART1 transmit UART1 receive UART0 transmit UART0 receive Timer B2 Timer B1 Timer B0 Timer A4 Timer A3 Timer A2 Timer A1 Timer A0 Watchdog timer BRK instruction Zero divide INT3 Reserved area Reserved area Reserved area Reserved area RESET DBC

M37906F8CFP, M37906F8CSP PRELIMINAR Y Notice: This is not a final specification. Som e param etric lim its are subject to change. 16-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS Fig. 2 Location of SFRs (1) 00000016 00000116 00000216 00000316 00000416 00000516 00000616 00000716 00000816 00000916 00000A16 00000B16 00000C 16 00000D 16 00000E16 00000F16 00001016 00001116 00001216 00001316 00001416 00001516 00001616 00001716 00001816 00001916 00001A16 00001B16 00001C 16 00001D 16 00001E16 00001F16 00002016 00002116 00002216 00002316 00002416 00002516 00002616 00002716 00002816 00002916 00002A16 00002B16 00002C 16 00002D 16 00002E16 00002F16 00003016 00003116 00003216 00003316 00003416 00003516 00003616 00003716 00003816 00003916 00003A16 00003B16 00003C 16 00003D 16 00003E16 00003F16 Port P2 register Reserved area (Note) Port P1 direction register Reserved area (Note) Port P1 register Reserved area (Note) Port P2 direction register Reserved area (Note) Reserved area (Note) Port P5 register Reserved area (Note) Port P5 direction register Port P6 register Port P7 register Port P6 direction register Port P7 direction register Reserved area (Note) Reserved area (Note) Reserved area (Note) Reserved area (Note) Reserved area (Note) Reserved area (Note) A-D control register 0 A-D control register 1 A-D register 0 A-D register 1 A-D register 2 A-D register 3 A-D register 4 Reserved area (Note) Reserved area (Note) Reserved area (Note) UART0 transmit/receive mode register UART0 baud rate register (BRG0) UART0 transmit buffer register UART0 transmit/receive control register 1 UART0 receive buffer register UART1 transmit/receive mode register UART1 baud rate register (BRG1) UART1 transmit buffer register UART1 transmit/receive control register 0 UART1 transmit/receive control register 1 UART1 receive buffer register Address (Hexadecimal notation) 000040 00004116 00004216 00004316 00004416 00004516 00004616 00004716 00004816 00004916 00004A16 00004B16 00004C 16 00004D 16 00004E16 00004F16 00005016 00005116 00005216 00005316 00005416 00005516 00005616 00005716 00005816 00005916 00005A16 00005B16 00005C 16 00005D 16 00005E16 00005F16 00006016 00006116 00006216 00006316 00006416 00006516 00006616 00006716 00006816 00006916 00006A16 00006B16 00006C 16 00006D 16 00006E16 00006F16 00007016 00007116 00007216 00007316 00007416 00007516 00007616 00007716 00007816 00007916 00007A16 00007B16 00007C 16 00007D 16 00007E16 00007F16 Address (Hexadecimal notation) Count start register 0 One-shot start register 0 Timer A clock division select register Timer A0 register Timer A1 register Timer A2 register Timer A3 register Timer A4 register Timer B0 register Timer B1 register Timer B2 register Timer A1 mode register Timer A0 mode register Timer A2 mode register Timer A3 mode register Timer A4 mode register Timer B0 mode register Timer B1 mode register Timer B2 mode register Processor mode register 1 Watchdog timer register Particular function select register 0 Particular function select register 1 Debug control register 0 INT 3 interrupt control register UART0 transmit interrupt control register UART1 receive interrupt control register Timer A0 interrupt control register Timer A1 interrupt control register Timer A3 interrupt control register Timer A4 interrupt control register Timer B0 interrupt control register Timer B2 interrupt control register Reserved area (Note) Watchdog timer frequency select register Debug control register 1 INT 4 interrupt control register UART1 transmit interrupt control register Timer A2 interrupt control register Timer B1 interrupt control register Reserved area (Note) Address comparison register 0 Address comparison register 1 Particular function select register 2 Reserved area (Note) Note: Do not write to this address. UART0 transmit/receive control register 0 Up-down register 0 Processor mode register 0 A-D conversion interrupt control register UART0 receive interrupt control register Reserved area (Note) Reserved area (Note) Reserved area (Note) Reserved area (Note) Count start register 1 One-shot start register 1 Reserved area (Note) Reserved area (Note)

M37906F8CFP, M37906F8CSP PRELIMINAR Y Notice: This is not a final specification. Som e param etric lim its are subject to change. 16-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS Fig. 3 Location of SFRs (2) 0000C0 16 0000C1 16 0000C2 16 0000C3 16 0000C4 16 0000C5 16 0000C6 16 0000C7 16 0000C8 16 0000C9 16 0000CA 16 0000CB 16 0000CC 16 0000CD 16 0000CE 16 0000CF 16 0000D0 16 0000D1 16 0000D2 16 0000D3 16 0000D4 16 0000D5 16 0000D6 16 0000D7 16 0000D8 16 0000D9 16 0000DA 16 0000DB 16 0000DC 16 0000DD 16 0000DE 16 0000DF 16 0000E016 0000E116 0000E216 0000E316 0000E416 0000E516 0000E616 0000E716 0000E816 0000E916 0000EA 16 0000EB 16 0000EC 16 0000ED 16 0000EE 16 0000EF 16 0000F016 0000F116 0000F216 0000F316 0000F416 0000F516 0000F616 0000F716 0000F816 0000F916 0000FA 16 0000FB 16 0000FC 16 0000FD 16 0000FE 16 0000FF16 0000A016 0000A116 0000A216 0000A316 0000A416 0000A516 0000A616 0000A716 0000A816 0000A916 0000AA 16 0000AB 16 0000AC 16 0000AD 16 0000AE 16 0000AF 16 0000B016 0000B116 0000B216 0000B316 0000B416 0000B516 0000B616 0000B716 0000B816 0000B916 0000BA 16 0000BB 16 0000BC 16 0000BD 16 0000BE 16 0000BF 16 Reserved area (Note) Reserved area (Note) Reserved area (Note) Waveform output mode register Serial I/O pin control register 00008016 00008116 00008216 00008316 00008416 00008516 00008616 00008716 00008816 00008916 00008A16 00008B16 00008C 16 00008D 16 00008E16 00008F16 00009016 00009116 00009216 00009316 00009416 00009516 00009616 00009716 00009816 00009916 00009A16 00009B16 00009C 16 00009D 16 00009E16 00009F16 Address (Hexadecimal notation) Reserved area (Note) Reserved area (Note) Reserved area (Note) Reserved area (Note) Reserved area (Note) Reserved area (Note) Reserved area (Note) Reserved area (Note) Reserved area (Note) Reserved area (Note) Reserved area (Note) Reserved area (Note) Reserved area (Note) D-A control register D-A register 0 D-A register 1 Note: Do not write to this address. Clock control register 0 Reserved area (Note) Reserved area (Note) Address (Hexadecimal notation) Reserved area (Note) Reserved area (Note) Dead-time timer Three-phase output data register 0 Three-phase output data register 1 Position-data-retain function control register Port P2 pin function control register Reserved area (Note) Reserved area (Note) Reserved area (Note) Reserved area (Note) Reserved area (Note) Reserved area (Note) Reserved area (Note) Reserved area (Note) Comparator result register 0 Reserved area (Note) Reserved area (Note) Reserved area (Note) Reserved area (Note) Reserved area (Note) Reserved area (Note) Reserved area (Note) Reserved area (Note) Reserved area (Note) Reserved area (Note) Reserved area (Note) Reserved area (Note) Reserved area (Note) Reserved area (Note) Reserved area (Note) Reserved area (Note) Reserved area (Note) Reserved area (Note) Reserved area (Note) Timer A5 interrupt control register Timer A6 interrupt control register Timer A8 interrupt control register Timer A9 interrupt control register Timer A7 interrupt control register INT5 interrupt control register INT6 interrupt control register INT7 interrupt control register Up-down register 1 Timer A5 register Timer A6 register Timer A7 register Timer A8 register Timer A9 register Timer A0 1 register Timer A11 register Timer A21 register Timer A5 mode register Timer A6 mode register Timer A7 mode register Timer A8 mode register Timer A9 mode register Reserved area (Note) Comparator function select register 0 Reserved area (Note) External interrupt input read-out register Reserved area (Note) Reserved area (Note) Reserved area (Note) Reserved area (Note) Flash memory control register

M37906F8CFP, M37906F8CSP 16-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS PRELIMINAR Y Notice: This is not a final specification. Som e param etric lim its are subject to change. FLASH MEMORY MODE These microcomputers contain the flash memory; and single-power- supply reprogramming is available to this. These microcomputers have the following three modes, enabling reading/programming/era- sure for the flash memory:

• Flash memory parallel I/O mode and Flash memory serial I/O mode, where the flash memory is handled by using an external pro- grammer.
• CPU reprogramming mode, where the flash memory is handled by the central processing unit (CPU). As shown in Figure 4, the flash memory is divided into several blocks, and erasure per block is possible. Fig. 4 M37906F8CFP, M37906F8CSP: block configuration of internal flash memory This internal flash memory has the boot ROM area storing the repro- gramming control software for reprogramming in the CPU repro- gramming mode and flash memory serial I/O mode, as well as the user ROM area storing a certain control software for the normal op- eration in the microcomputer mode. Although our reprogramming control firmware for the flash memory serial I/O mode has been stored into this boot ROM area on ship- ment, the user-original reprogramming control software which is more appropriate for the user’s system is reprogrammable into this area, instead. Note that the reprogramming for the boot ROM area is enabled only in the flash memory parallel I/O mode.

28 Kbytes

16 Kbytes

Notice: This is not a final specification. Table 1. Software commands (flash memory parallel I/O mode) the flash memory parallel I/O mode. area if the user uses the flash memory serial I/O mode. the reserved area for the programmer. lel I/O mode, do not program to this area.

M37906F8CFP, M37906F8CSP 16-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS PRELIMINAR Y Notice: This is not a final specification. Som e param etric lim its are subject to change. Flash Memory Serial I/O Mode In the flash memory serial I/O mode, addresses, data, and software commands, which are required to read/program/erase the internal flash memory, are serially input and output with a fewer pins and the dedicated serial programmer. In this mode, being different from the flash memory parallel I/O mode, the CPU controls reprogramming of the flash memory (using the CPU reprogramming mode), serial input of the reprogramming data, etc. The reprogramming control firmware for the flash memory serial I/O mode has been stored in the boot ROM area on shipment of the product from us. Note that, then, the flash memory serial I/O mode will become unavailable if the boot ROM area has been repro- grammed in the flash memory parallel I/O mode. Note that, also, this reprogramming control firmware for the flash memory serial I/O mode is subject to change. Figures 5 and 6 show the pin connections in the flash memory serial I/O mode. The three pins, SCLK, SDA, and BUSY, are used to input and output serial data. The SCLK pin is the input pin of external transfer clocks. The SDA pin is the I/O pin of transmit and receive data, and its output acts as the N-channel open-drain output. To the SDA pin, connect an exter- nal pullup resistor (about 1 kΩ ). The BUSY pin is the output pin of the BUSY flag (CMOS output) and goes “H ” during BUSY periods owing to a certain operation, such as transmit, receive, erase, program- ming, etc. Transmit and receive data are serially transferred 8 bits at a time. In the flash memory serial I/O mode, only the user ROM area can be reprogrammed; the boot ROM area is not accessible. Addresses FF90 16 to FF9F16 are the reserved area for the serial programmer. Therefore, when the user uses the flash memory serial I/O mode, do not program to this area.

M37906F8CFP, M37906F8CSP MITSUBISHI MICROCOMPUTERS PRELIMINAR Y Notice: This is not a final specification. Som e param etric lim its are subject to change. Fig. 5 Pin connection of M37906F8CFP in flash memory serial I/O mode (outline: 42P2R-E) Outline 42P2R-E AVss 21 22 VREF P74/AN4/DA1/INT3/RTPTRG0 P73/AN3/DA0 P72/AN2 P71/AN1 P70/AN0 P65/TA2IN/U/RTP11 P64/TA2OUT /V/RTP10 MD0 VCONT Vcc AVcc P12/RXD 0 P13/TXD 0 P16/RXD 1 P17/TXD 1 P20/TA4OUT P21/TA4IN P22/TA9OUT P23/TA9IN P24(/TB0IN) P25(/TB1IN) P26(/TB2IN) MD1 XOUT XIN Vss P63/TA1IN/W/RTP0 3 P62/TA1OUT /U/RTP02 P61/TA0IN/V/RTP01 P60/TA0OUT /W/RTP0 0 P6OUT CUT /INT4 RESET P27(/INT3/RTPTRG0 ) P15/CTS1/CLK1 P14/CTS1/RTS1 P11/CTS0/CLK0 P10/CTS0/RTS0 P57/INT7/TB2IN/IDU P56/INT6/TB1IN/IDV P55/INT5/TB0IN/IDW Notes 1: Allocation of pins TB0IN to TB2IN and INT3/RTPTRG0 can be switched by software. 2: Connected to the oscillation circuit. 3: Recommended to be connected with VCC via a resistor. : Connected to a serial programmer. (Note 3) (Note 1) MD1 BUSY SDA SCLK (Note 2) (Note 1) (Note 1) VCC VSS RESET M37906F8CFP

M37906F8CFP, M37906F8CSP 16-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS PRELIMINAR Y Notice: This is not a final specification. Som e param etric lim its are subject to change. Fig. 6 Pin connection of M37906F8CSP in flash memory serial I/O mode (outline: 42P4B) AVss 21 22 VREF P74/AN4/DA1/INT3/RTPTRG0 P73/AN3/DA0 P72/AN2 P71/AN1 P70/AN0 P65/TA2IN/U/RTP11 P64/TA2OUT /V/RTP10 MD0 VCONT Vcc AVcc P12/RXD 0 P13/TXD 0 P16/RXD 1 P17/TXD 1 P20/TA4OUT P21/TA4IN P22/TA9OUT P23/TA9IN P24(/TB0IN) P25(/TB1IN) P26(/TB2IN) MD1 XOUT XIN Vss P63/TA1IN/W/RTP0 3 P62/TA1OUT /U/RTP02 P61/TA0IN/V/RTP01 P60/TA0OUT /W/RTP0 0 RESET P27(/INT3/RTPTRG0 ) P15/CTS1/CLK1 P14/CTS1/RTS1 P11/CTS0/CLK0 P10/CTS0/RTS0 P57/INT7/TB2IN/IDU P56/INT6/TB1IN/IDV P55/INT5/TB0IN/IDW (Note 1) MD1 BUSY SDA SCLK (Note 2) (Note 1) (Note 1) VCC VSS RESET (Note 3) P6OUT CUT /INT4 Notes 1: Allocation of pins TB0IN to TB2IN and INT3/RTPTRG0 can be switched by software. 2: Connected to the oscillation circuit. 3: Recommended to be connected with VCC via a resistor. : Connected to a serial programmer. M37906F8CSP Outline 42P4B

M37906F8CFP, M37906F8CSP MITSUBISHI MICROCOMPUTERS PRELIMINAR Y Notice: This is not a final specification. Som e param etric lim its are subject to change. CPU Reprogramming Mode The CPU reprogramming mode is used to perform the operations for the internal flash memory (reading, programming, erasing) under control of the CPU. In this mode, only the user ROM area can be reprogrammed; the boot ROM area cannot be reprogrammed. The user-original reprogramming control software for the CPU repro- gramming mode can be stored in either the user ROM area or the boot ROM area. Because the CPU cannot read out the flash memory in the CPU re- programming mode, the above software must be transferred to the internal RAM in advance to be executed. Boot Mode The user-original reprogramming control software for the CPU repro- gramming mode must be stored into the user ROM area or the boot ROM area in the flash memory parallel I/O mode in advance. (If this program has been stored into the boot ROM area, the flash memory serial I/O mode will become unavailable). Note that addresses of the boot ROM area depend on the accessing ways to the boot ROM area, When accessing in the flash memory parallel I/O mode, these addresses will be shifted to 0000 16 to 1FFF 16. On the other hand, when accessing with the CPU, these ad- dresses will be shifted to E00016 to FFFF16. Reset removal with both of the MD0 and MD1 pins held “L” invokes the normal microcomputer mode, and the CPU operates using the control software stored in the user ROM area. In this case, the boot ROM area is not access ble. Removing reset with the MD0 pin held “L” and the MD1 pin “H”, the CPU starts its operation using the reprogramming control software stored in the boot ROM area. This mode is called the boot mode. The reprogramming control software in the boot ROM area can also re- program the user ROM area. After reset removal, be sure not to change the status at pins MD0 and MD1. Fig. 7 Bit configuration of flash memory control register Flash memory control register RY/BY status bit 0: Busy (Programming or erasing is active.) 1: Ready CPU reprogramming mode select bit (Note 2) 0: Normal mode (Software commands are ignored.) 1: CPU reprogramming mode (Software commands are acceptable.) Flash memory reset bit (Note 3) 0: Normal operation 1: Reset User ROM area select bit (Note 4) (Valid only in the boot mode.) 0: Boot ROM area access 1: User ROM area access Notes 1: The contents of the flash memory control register after reset is removed are “XX000001”. 2: To set “1”, writing of “0” to bit 1 and subsequent writing of “1” to bit 1 are necessary. Writing to bit 1 must be performed by the user-original reprogramming control software in the internal RAM. 3: This bit is valid only when bit 1 = “1”. Before setting this bit to “0”, be sure to confirm that bit 0 = “1” after setting this bit to “1” (reset). This bit 3 must be controlled with bit 1 = “1”. 4: Writing to bit 5 must be performed by the user-original reprogramming control software in the internal RAM. 765432 1

0 Address

M37906F8CFP, M37906F8CSP MITSUBISHI MICROCOMPUTERS PRELIMINAR Y Notice: This is not a final specification. Som e param etric lim its are subject to change. Fig. 8 CPU reprogramming mode set/termination flowchart Software Commands Table 2 lists the software commands. By writing a software command after the CPU reprogramming mode select bit has been set to “1”, erasing, programming, etc. can be specified. Note that, at software commands’ input, the high-order byte (D 8–D 15) is ignored. (Except for the write data at the 2nd cycle of a programming command.) Software commands are explained as below. Read Array Command (FF 16) By writing command code “FF16” at the 1st bus cycle, the microcom- puter enters the read array mode. If an address to be read is input in the next or the following bus cycles, the contents at the specified ad- dress are output to the data bus (D 0 to D15) in a unit of 16 bits. The read array mode is maintained until writing of another software command. Read Status Register Command (7016) Writing command code “7016” at the 1st bus cycle outputs the con- tents of the status register to the data bus (D0-D7) by a read at the 2nd bus cycle. The status register is explained later. Clear Status Register Command (5016) This command clears two status bits (SR.4, 5) each of which is set to “1” to indicate that the operation has been terminated by an error. To clear these bits, write command code “50 16” at the 1st bus cycle. Programming Command (40 16) This command facilitates programming of 1 word (2 bytes) at a time. To initiate programming, write command code “4016” at the 1st bus cycle; when write data is written in a unit of 16 bits at the 2nd bus cycle, the address is specified at the same time. Upon completion of data writing, automatic programming (data programming and verifi- cation) operation is started. The completion of the automatic programming operation is con- firmed by a read of the flash memory control register. The RY/BY sta- tus bit of the flash memory control register goes “0” during the automatic programming operation; and also, it goes “1” after the end of it. Before execution of the next command, be sure to confirm that the RY/BY status bit is set to “1” (READY). During the automatic pro- gramming operation, writing of commands and access to the flash memory must not be performed. When programming continuously, the programming command can be executed with the read status register mode kept if there is no programming error. Simultaneously with start of the automatic pro- gramming, the read status register mode is automatically active. In this case, the read status register mode is retained until the next read array command (FF 16) is written or until the reset is performed by using the flash memory reset bit. Reading out the status register after the automatic programming op- eration is completed reports the result of it. For details, refer to the section on the status register. Figure 9 shows an example of the programming flowchart. Additional programming to any word that has already been pro- grammed is prohibited. Completed Start Read array command is executed, or reset is performed by setting the flash memory reset bit. (Writing of “1” → Writing of “0”) (Note 2) Single-chip mode, Memory expansion mode, or Boot mode The processor mode register 1 is set (Note 1). Flag I is set to “1”. Operations such as erasing, programming are executed by using software commands. Jump to the above software in the internal RAM. (The operations shown below will be executed by the above software in this RAM.) The user-original reprogramming control software for the CPU reprogramming mode is transferred to the internal RAM. (Only in the boot mode.) Writing of “0” to user ROM area select bit (Note 3). Writing of “0” to the CPU reprogramming mode select bit. (Only in the boot mode.) The user ROM area select bit is set to “1”. Writing of “1” to the CPU reprogramming mode select bit. (Writing of “0” → Writing of “1”) Notes 1: The processor mode register 1’s bit 7 (address 5F16, the internal ROM bus cycle select bit) must be “0” (bus cycle = 3φ). 2: To terminate the CPU reprogramming mode after the erase and programming operations have been completed, be sure to execute the read array command or perform the flash memory reset operation. 3: This bit may remain “1”. However, if this bit is “1”, the user ROM area access is specified.

Notice: This is not a final specification. Table 2. Software commands (CPU reprogramming mode) Notes 1: At software commands’ input, the high-order byte of data (D8–D 15) is ignored. 4: WA = Write Address, WD = Write Data (16 bits). 5: Block address: the maximum address of each block must be input. Note that address A0 = “0”. Figure 10 shows an example of the block erase flowchart.

M37906F8CFP, M37906F8CSP MITSUBISHI MICROCOMPUTERS PRELIMINAR Y Notice: This is not a final specification. Som e param etric lim its are subject to change. Fig. 9 Programming flowchart Fig. 10 Block erase flowchart Start Write 4016 Write, Address, Data Flash memory control register Read Full status check Programming Completed NO YES RY/BY Status Bit = 1? Write 2016 Write D016, Flash memory control register Read Full status check Block erase Completed NO YES Block address Start RY/BY Status Bit = 1? Erase All Block Command (2016/2016) Writing command code “2016” at the 1st bus cycle and writing com- mand code “2016” at the subsequent 2nd bus cycle initiate the con- tinuous block erase (chip erase) operations for all the blocks. The completion of the chip erase operation, as well as of the block erase operation, is confirmed by a read of the flash memory control register. The result of the automatic erase operation is also reported by a read of the status register. During the automatic erase operation (when the RY/BY status bit = “0”), writing of commands and access to the flash memory must not be performed. Status Register The status register is used to indicate whether the programming/ erase operation has been completed normally or terminated by an error. By writing the read status register command (7016), the con- tents of the status register can be read out; by writing the clear sta- tus register command (50 16), the contents of the status register can be cleared. Table 3 lists the definition of each bit of the status register. The status register outputs “8016” after reset is removed. The status of each bit is described below.

Notice: This is not a final specification. tus register command (5016) is written. This bit reports the status of the automatic programming operation. taken if an error has occurred. Table 3. Bit definition of status register

M37906F8CFP, M37906F8CSP MITSUBISHI MICROCOMPUTERS PRELIMINAR Y Notice: This is not a final specification. Som e param etric lim its are subject to change. Fig. 11 Full status check flowchart and actions to be taken if an error has ocurred Symbol Parameter Limits UnitMin. Typ. Max. VCC power source current (at read) VCC power source current (at write) VCC power source current (at programming) VCC power source current (at erasing) Limits of VIH, VIL, VOH , VOL , IIH, and IIL for each pin are the same as those in the microcomputer mode. Note: f(fsys) indicates the system clcok (fsys) frequency. mA mA mA mA Parameter 256-byte programming time Block erase time Erase all block time Limits UnitMin. Typ. Max. 0.6 0.6 ✕ n 8 ✕ n ms s s n = Number of blocks to be erased Icc1 Icc2 Icc3 Icc4 The limits of parameters other than the above are same as those in the microcomputer mode. Note: f(fsys) indicates the system clock (fsys) frequency. Status Register Read SR.4 = 1 NO Command Sequence Error YES SR.5 = 0? YES Block Erase Error NO SR.4 = 0? YES Programming Error NO End (Block erase, Programming) and SR.5 = 1 ➀ Execute the clear status register command (5016) to clear the status register. ➁ Confirm whether the command has correctly been input or not; and then, start the operation again. Perform the block erase operation again. If an error occurs even after the above operation is performed, the block cannot be used. Perform the programming operation again. If an error occurs even after the above operation is performed, the word cannot be used. Note: Under the condition that any of SR.5 and SR.4 = “1”, none of the programming, block erase, and erase all block commands can be accepted. Before execution of these commands, execute the clear status register command (50 16) in advance.

M37906F8CFP, M37906F8CSP PRELIMINAR Y Notice: This is not a final specification. Som e param etric lim its are subject to change. 16-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS Unit V V V V V V mA mA mA mA mA mA MHz MHz Max. 5.5 Vcc 0.2 V CC –10 Parameter Power source voltage Analog power source voltage Power source voltage Analog power source voltage High-level input voltage P1 0–P17, P20–P27, P55–P57, P60–P65, P70–P74, P6OUT CUT , XIN, RESET, MD0, MD1 Low-level input voltage P10–P17, P20–P27, P55–P57, P60–P65, P70–P74, P6OUT CUT , XIN, RESET, MD0, MD1 High-level peak output current P10–P17, P20–P27, P55–P57, P60–P65, P70–P74 High-level average output current P10–P17, P20–P27, P55–P57, P60–P65, P70–P74 Low-level peak output current P10–P17, P20–P27, P55–P57, P70–P74 Low-level peak output current P60–P65 Low-level average output current P10–P17, P20–P27, P55–P57, P70–P74 Low-level average output current P60–P65 External clock input frequency (Note 1) System clock frequency Symbol VCC AV CC VSS AV SS VIH VIL IOH(peak) IOH(avg) IOL(peak) IOL(peak) IOL(avg) IOL(avg) f(XIN) f(fsys) Parameter Power source voltage Analog power source voltage Input voltage P1 0–P17, P20–P27, P55–P57, P60–P65, P70–P74, P6OUT CUT , VCONT , VREF , XIN, RESET, BYTE, MD0, MD1 Output voltage P10–P17, P20–P27, P55–P57, P60–P65, P70–P74, XOUT Power dissipation Operating ambient temperature Storage temerature Symbol V CC AV CC VI VO Pd Topr Tstg ABSOLUTE MAXIMUM RATINGS RECOMMENDED OPERATING CONDITIONS (Vcc = 5 V, Ta = –20 to 85 °C, unless otherwise noted) Notes 1: When using the PLL frequency multiplier, be sure hat f(fsys) = 20 MHz or less. 2: The average output current is the average value of an interval of 100 ms. 3: The sum of IOL(peak) must be 110 mA or less, the sum of IOH(peak) must be 80 mA or less. Unit V V V V mW Ratings –0.3 to 6.5 –0.3 to 6.5 –0.3 to V CC +0.3 –0.3 to VCC +0.3 300 –20 to 85 –40 to 150 Limits Min. 4.5

0.8 Vcc

Typ. 5.0 VCC

M37906F8CFP, M37906F8CSP PRELIMINAR Y Notice: This is not a final specification. Som e param etric lim its are subject to change. 16-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS Unit V V V V V µA µA V mA µA f(fsys) = 20 MHz. CPU is active. Ta = 25 °C when clock is inactive. Ta = 85 °C when clock is inactive. Test conditions IOH = –10 mA IOL = 10 mA VI = 5.0 V VI = 0 V When clock is inactive. Parameter High-level output voltage P10–P17, P20–P27, P55–P57, P60–P65, P70–P74 Low-level output voltage P10–P17, P20–P27, P55–P57, P60–P65, P70–P74 Hysteresis TA0IN–TA2IN, TA4N , TA9IN, TA0OUT –TA2OUT , TA4OUT , TA9OUT , TB0 N –TB2 IN, INT3–INT7, CTS0, CTS 1, CLK0, CLK1, RxD0, RxD1, RTP TRG0 , P6OUTCUT Hysteresis RESET Hysteresis XIN High-level input currentP10–P17, P20–P27, P55–P57, P60–P65, P70–P74, P6OUTCUT , XIN, RESET, MD0, MD1 Low-level input currentP10–P17, P20–P27, P55–P57, P60–P65, P70–P74, P6OUTCUT , XIN, RESET, MD0, MD1 RAM hold voltage Power source current Symbol V OH VOL VT+ — VT – VT+ — VT – VT+ — VT – IIH IIL VRAM ICC DC ELECTRICAL CHARACTERISTICS (Vcc = 5 V, Vss = 0 V, Ta = –20 to 85 °C, f(fsys) = 20 MHz) Min. 0.4 0.5 0.1 Limits Typ. Max. 1.5 0.3 Output-only pins are open, and the other pins are con- nected to Vss or Vcc. An external square-waveform clock is input. (Pin X OUT is open.) The PLL frequency multiplier is inac- tive.

M37906F8CFP, M37906F8CSP PRELIMINAR Y Notice: This is not a final specification. Som e param etric lim its are subject to change. 16-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS Resolution Absolute accuracy Ladder resistance Conversion time Reference voltage Analog input voltage R LADDER tCONV VREF VIA VREF = VCC VREF = VCC VREF = VCC f(fsys) ≤ 20 MHz Max. A-D CONVERTER CHARACTERISTICS (VCC = AVCC = 5 V ± 0.5 V, VSS = AVSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted) UnitParameterSymbol Test conditions Limits Min. 10-bit resolution mode 8-bit resolution mode Comparater 10-bit resolution mode 8-bit resolution mode Comparater 5.9 2.45 (Note) 0.7 (Note) 2.7 ± 3 ± 2 ± 40 VCC VREF Bits V LSB LSB mV kΩ µs V V Note: This is applied when A-D conversion freguency (φAD ) = f1 (φ). D-A CONVERTER CHARACTERISTICS (VCC = 5 V, VSS = AVSS = 0 V, VREF = 5 V, Ta = –20 to 85 °C, unless otherwise noted) UnitParameterSymbol Limits Typ.Min. Max.Test conditions Resolution Absolute accuracy Set time Output resistance Reference power source input current t su R O IVREF (Note) 2 3.5 ± 1.0 4.5 3.2 Bits µs kΩ mA Note: The test conditions are as follows:

• One D-A converter is used.
• The D-A register value of the unused D-A converter is “00 16.”
• The reference power source input current for the ladder resistance of the A-D converter is excluded. µsRESET input low-level pulse widthtw(RESETL) Symbol Parameter Min. Limits Unit RESET INPUT Reset input timing requirements (VCC = 5 V ± 0.5 V, VSS = 0V, Ta = –20 to 85 °C, unless otherwise noted) Max.Typ. RESET input tw(RESETL) A-D converter Comparator 256

1 VREF

Typ.

M37906F8CFP, M37906F8CSP PRELIMINAR Y Notice: This is not a final specification. Som e param etric lim its are subject to change. 16-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS tc(TA) tw(TAH) tw(TAL) f(fsys) ≤ 20 MHz f(fsys) ≤ 20 MHz f(fsys) ≤ 20 MHz PERIPHERAL DEVICE INPUT/OUTPUT TIMING (VCC = 5 V±0.5 V, VSS = 0 V, Ta = –20 to 85 °C, f(fsys) = 20 MHz unless otherwise noted) ∗ For limits depending on f(fsys), their calculation formulas are shown below. Also, the values at f(fsys) = 20 MHz are shown in ( ). Timer A input (Up-down input and Count input in event counter mode) tc(UP) tw(UPH) tw(UPL) tsu(UP-TIN) th(TIN-UP) Symbol TAiOUT input cycle time TAiOUT input high-level pulse width TAiOUT input low-level pulse width TAiOUT input setup time TAiOUT input hold time Parameter Limits Min. 2000 1000 1000 400 400 Max. ns ns ns ns ns Unit Timer A input (External trigger input in pulse width modulation mode) tw(TAH) tw(TAL) Symbol TAiN input high-level pulse width TAiN input low-level pulse width Parameter Min. Limits Max. ns ns Unit Limits Symbol Parameter Min. Max. Unit 8 × 109 f(fsys) (400)TAiIN input cycle time TAiIN input high-level pulse width TAiIN input low-level pulse width ns ns ns Timer A input (External trigger input in one-shot pulse mode) Limits Symbol Parameter Min. Max. Unit 16 × 109 f(fsys) 8 × 109 f(fsys) 8 × 109 f(fsys) (800) (400) (400) t c(TA) tw(TAH) tw(TAL) TAiN input cycle time TAiN input high-level pulse width TAiN input low-level pulse width ns ns ns Timer A input (Gating input in timer mode) Note :The TAiIN input cycle time requires 4 or more cycles of a count source. The TAiN input high-level pulse width and the TAiN input low-level pulse width respectively require 2 or more cycles of a count source. The limits in this table are applied when the count source = f2 at f(fsys) ≤ 20 MHz. Timer A input (Count input in event counter mode) tc(TA) tw(TAH) tw(TAL) Symbol TAiN input cycle time TAiN input high-level pulse width TAiN input low-level pulse width Parameter Min. Limits Max. ns ns ns Unit f(f sys) ≤ 20 MHz

M37906F8CFP, M37906F8CSP PRELIMINAR Y Notice: This is not a final specification. Som e param etric lim its are subject to change. 16-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS tc(TA) tsu(TAjIN-TAjOUT) tsu(TAjOUT-TAjIN) Symbol Parameter Min. 800 200 200 Limits Max. ns ns ns Unit Timer A input (Two-phase pulse input in event counter mode) TAjN input cycle time TAjN input setup time TAjOUT input setup time tc(TA) tw(TAH) tw(TAL) tc(UP) tw(UPH) tw(UPL) th(TIN-UP) tsu(UP-TIN) tsu(TAjIN-TAjOUT ) tsu(TAjOUT -TAjIN) tsu(TAjIN-TAjOUT ) tsu(TAjOUT -TAjIN) tc(TA)

• Gating input in timer mode
• Count input in event counter mode
• External trigger input in one-shot pulse mode
• External trigger input in pulse width modulation mode TAiIN input TAiOUT input (Up-down input) TAiOUT input (Up-down input)
• Up-down and Count input in event counter mode TAiIN input (When count by falling) TAiIN input (When count by rising) TAjIN input TAjOUT input
• Two-phase pulse input in event counter mode Test conditions
• VCC = 5 V ± 0.5 V, Ta = –20 to 85 °C
• Input timing voltage : VIL = 1.0 V, VIH = 4.0 V

M37906F8CFP, M37906F8CSP PRELIMINAR Y Notice: This is not a final specification. Som e param etric lim its are subject to change. 16-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS f(fsys) ≤ 20 MHz f(fsys) ≤ 20 MHz f(fsys) ≤ 20 MHz f(fsys) ≤ 20 MHz f(fsys) ≤ 20 MHz f(fsys) ≤ 20 MHz tc(TB) tw(TBH) tw(TBL) tc(TB) tw(TBH) tw(TBL) Timer B input (Count input in event counter mode) Symbol TBiIN input cycle time (one edge count) TBiIN input high-level pulse width (one edge count) TBiIN input low-level pulse width (one edge count) TBiIN input cycle time (both edge count) TBiIN input high-level pulse width (both edge count) TBiIN input low-level pulse width (both edge count) Parameter Limits Min. 160 Max. ns ns ns ns ns ns Unit Limits Symbol Parameter Min. Max. Unit 16 × 109 f(fsys) 8 × 109 f(fsys) 8 × 109 f(fsys) (800) (400) (400) t c(TB) tw(TBH) tw(TBL) TBiN input cycle time TBiN input high-level pulse width TBiN input low-level pulse width ns ns ns Timer B input (Pulse period measurement mode) Note: The TBiIN input cycle time requires 4 or more cycles of a count source. The TBiIN input high-level pulse width and the TBiIN input low-level pulse width respectively require 2 or more cycles of a count source. The limits in this table are applied when the count source = f2 at f(fsys) ≤ 20 MHz. Limits Symbol Parameter Min. Max. Unit 16 × 109 f(fsys) 8 × 109 f(fsys) 8 × 109 f(fsys) (800) (400) (400) t c(TB) tw(TBH) tw(TBL) TBiN input cycle time TBiN input high-level pulse width TBiN input low-level pulse width ns ns ns Timer B input (Pulse width measurement mode) Note: The TBiIN input cycle time requires 4 or more cycles of a count source. The TBiIN input high-level pulse width and the TBiIN input low-level pulse width respectively require 2 or more cycles of a count source. The limits in this table are applied when the count source = f2 at f(fsys) ≤ 20 MHz. tc(CK) tw(CKH) tw(CKL) td(C-Q) th(C-Q) tsu(D-C) th(C-D) Serial I/O Symbol CLK i input cycle time CLK i input high-level pulse width CLK i input low-level pulse width TXD i output delay time TXD i hold time R XD i input setup time R XD i input hold time Parameter Limits Min. 200 100 100 Max. ns ns ns ns ns ns ns Unit

M37906F8CFP, M37906F8CSP PRELIMINAR Y Notice: This is not a final specification. Som e param etric lim its are subject to change. 16-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS tw(INH) tw(INL) Symbol INTi input high-level pulse width INTi input low-level pulse width Parameter Min. 250 250 Limits Max. ns ns Unit External interrupt (INTi) input tc(TB) tw(TBH) tw(TBL) tsu(D-C) tc(CK) tw(CKH) tw(CKL) tw(INL) tw(INH) td(C-Q) th(C-D) th(C-Q) TBiIN input INTi input CLK i input TxD i output RxD i input Test conditions

• Vcc = 5 V ± 0.5 V, Ta = –20 to 85 °C
• Input timing voltage : VIL = 1.0 V, VIH = 4.0 V
• Output timing voltage : VOL = 0.8 V, VOH = 2.0 V, CL = 50 pF

M37906F8CFP, M37906F8CSP PRELIMINAR Y Notice: This is not a final specification. Som e param etric lim its are subject to change. 16-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS tc tw(half) tw(H) tw(L) tr tf Max. 0.55 tc Min. 0.45 tc 0.5 tc – 8 0.5 tc – 8 External clock input cycle time External clock input pulse width with half input-volage External clock input high-level pulse width External clock input low-level pulse width External clock input rise time External clock input fall time Limits External clock input Symbol Parameter ns ns ns ns ns ns Unit External clock input tr tf tw(L) tw(H) tw(half) XIN tc Test conditions

• Vcc = 5 V ± 0.5 V, Ta = –20 to 85 °C
• Input timing voltage : VIL = 1.0 V, VIH = 4.0 V (tw(H), tw(L), tr, tf)
• Input timing voltage : 2.5 V (tc, tw(half)) Timing Requirements (VCC = 5 V±0.5 V , VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)

M37906F8CFP, M37906F8CSP PRELIMINAR Y Notice: This is not a final specification. Som e param etric lim its are subject to change. 16-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS PACKAGE OUTLINE SSOP42-P-450-0.80 Weight(g) JEDEC Code 0.63 Alloy 42/Cu Alloy 42P2R-E Plastic 42pin 450mil SSOP Symbol Min Nom Max A b c D E L y Dimension in Millimeters H E .350 .050 .130 .317 .28 .6311 .30 .271 .02 .40 .150 .517 .48 .80 .9311 .50 .7651 .4311 .42 .50 .20 .717 .68 .2312 .70 .150 b2 – .50 – 0° – 10° e 42 22 211 H E E D e y F A A2 A1 L c e b2 Recommended Mount Pad Detail F z Z1 Detail G –Z1 0.75 0.9 z b G SDIP42-P-600-1.78 Weight(g) JEDEC Code 4.1 Alloy 42/Cu Alloy 42P4B Plastic 42pin 600mil SDIP Symbol Min Nom Max A b c E D L Dimension in Millimeters A1 0.51 –– – 3.8 – 0.35 0.45 0.55 0.9 1.0 1.3 0.63 0.73 1.03 0.22 0.27 0.34 36.5 36.7 36.9 12.85 13.0 13.15 – 1.778 – – 15.24 – 3.0 –– 0° – 15° –– 5.5 e 42 22 211 E ce1 A2A1 bb1 b2e L A SEATING PLANE D

M37906F8CFP, M37906F8CSP PRELIMINAR Y Notice: This is not a final specification. Som e param etric lim its are subject to change. 16-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS Notes regarding these materials

• These materials are intended as a reference to assist our customers in the selection of the Mitsubishi semiconductor product best suited to the customer’s application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Mitsubishi Electric Corporation or a third party.
• Mitsubishi Electric Corporation assumes no responsibility for any damage, or infringement of any third-party’s rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials.
• All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by Mitsubishi Electric Corporation without notice due to product improvements or other reasons. It is therefore recommended that customers contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for the latest product information before purchasing a product listed herein. The information described here may contain technical inaccuracies or typographical errors. Mitsubishi Electric Corporation assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. Please also pay attention to information published by Mitsubishi Electric Corporation by various means, including the Mitsubishi Semiconductor home page (http://www.mitsubishichips.com).
• When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. Mitsubishi Electric Corporation assumes no responsibility for any damage, liability or other loss resulting from the information contained herein.
• Mitsubishi Electric Corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use.
• The prior written approval of Mitsubishi Electric Corporation is necessary to reprint or reproduce in whole or in part these materials.
• If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited.
• Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for further details on these materials or the products contained therein. © 2001 MITSUBISHI ELECTRIC CORP. New publication, effective Jun., 2001. Specifications subject to change without notice. Keep safety first in your circuit designs
• Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non-flammable material or (iii) prevention against any malfunction or mishap.

REVISION HISTORY M37906F8CFP/SP DATASHEET Rev. Date Description Page Summary (1/1) First Edition Some English expressions and the following are corrected:

• DESCRIPTION; line 3 <Error> •••• silicon gate technology, being packaged •••• <Correction> •••• silicon gate technology, including the internal flash memory and being packaged ••••
• Figure 7; Note 3 <Error> •••• after setting this bit to “1” (reset). <Correction> •••• after setting this bit to “1” (reset). This bit 3 must be controlled with bit 1 = “1”.
• Programming Command (40 16); lines 18,19 <Error> •••• be executed with the read status register mode kept. •••• <Correction> •••• be executed with the read status register mode kept if there is no programming error. ••••
• Figure 11 <Error> Status Register Error <Correction> Status Register Read 1.0 3/02/01 2.0 6/26/01