M37905F8CFP

M37905F8CFP MITSUBISHI | Alldatasheet

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Technical content

M37905F8CFP, M37905F8CSP PRELIMINAR Y Notice: This is not a final specification. Som e param etric limits are subject to change. 16-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS

DESCRIPTION

These are single-chip 16-bit microcomputers designed with high-per- formance CMOS silicon gate technology, including the internal flash memory and, being packaged in 64-pin plastic molded QFP or shrink plastic molded DIP. These microcomputers support the 7900 Series instruction set, which are enhanced and expanded instruction set and are upper-compatible with the 7700/7751 Series instruction set. The CPU of these microcomputers is a 16-bit parallel processor that can also be switched to perform 8-bit parallel processing. Also, the bus interface unit of these microcomputers enhances the memory access efficiency to execute instructions fast. Therefore, these mi- crocomputers are suitable for office, business, and industrial equip- ment controller that require high-speed processing of large data. Also, they are suitable for motor-control equipment since each of them includes the motor control circuit. For the internal flash memory, single-power-supply programming and erasure, using a PROM programmer or the control by the cen- tral processing unit (CPU), is supported. Also, each of these micro- computers has the memory area dedicated for storing a certain software which controls programming and erasure (reprogramming control software). Therefore, on these microcomputers, the program can easily be changed even after they are mounted on the board. DISTINCTIVE FEATURES <Microcomputer mode>

• Memory
• Instruction execution time (Three-phase motor drive waveform or Pulse motor drive waveform output is available.)
• 12-bit watchdog timer <Flash memory mode> M37905F8CFP , M37905F8CSP
• Programming/Erase control by software command APPLICATION
• Control devices for office equipment such as copiers and facsimiles
• Control devices for industrial equipment such as communication and measuring instruments
• Control devices for equipment, requiring motor control, such as inverter air conditioners and general-purpose inverters

M37905F8CFP, M37905F8CSP PRELIMINAR Y Notice: This is not a final specification. Som e param etric lim its are subject to change. 16-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS P73/AN3 P72/AN2 P71/AN1 P65/TA2IN/U/RTP11 P64/TA2OUT /V/RTP10 P63/TA1IN/W/RTP0 3 P62/TA1OUT /U/RTP02 P61/TA0IN/V/RTP01 P60/TA0OUT /W/RTP0 0 P57/INT7/TB2IN/IDU P56/INT6/TB1IN/IDV P55/INT5/TB0IN/IDW P6OUT CUT /INT4 P70/AN0 P67/TA3IN/RTP13 P66/TA3OUT /RTP12 MD0 RESET XIN XOUT VCONT VSS P53/INT3/RTPTRG0 P52/INT2/RTPTRG1 P51/INT1 P4OUT CUT /INT0 P47/TA8IN/RTP33 P46/TA8OUT /RTP32 P45/TA7IN/RTP31 P44/TA7OUT /RTP30 P43/TA6IN/RTP23 P42/TA6OUT /RTP22 P23/TA9IN P22/TA9OUT P21/TA4IN P20/TA4OUT P17/TxD1 P16/RxD1 P15/CTS1/CLK1 P14/CTS1/RTS1 P13/TxD0 P83/AN11/TXD 2 P82/AN10/RXD 2 P81/AN9/CTS2/CLK2 VCC AV CC VREF AV SS VSS P77/AN7/DA0 P76/AN6 P75/AN5 P74/AN4 P80/AN8/CTS2/RTS2/DA1 M37905F8CFP P11/CTS0/CLK0 P10/CTS0/RTS0 P41/TA5IN/RTP21 P40/TA5OUT /RTP20 MD1 P27 P26(/TB2IN) P25(/TB1IN) P24(/TB0IN) P12/RXD 0 Note Note M37905F8CFP PIN CONFIGURATION (TOP VIEW) Outline 64P6N-A Note: Allocation of pins TB0IN to TB2IN can be switched by software.

M37905F8CFP, M37905F8CSP PRELIMINAR Y Notice: This is not a final specification. Som e param etric lim its are subject to change. 16-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS M37905F8CSP PIN CONFIGURATION (TOP VIEW) Outline 64P4B P75/AN5 P76/AN6 P77/AN7/DA 0 P80/AN8/CTS 2/RTS2/DA 1 P82/AN10/RxD2 P81/AN9/CTS2/CLK2 P10/CTS0/RTS0 P11/CTS0/CLK0 P14/CTS1/RTS1 P20/TA4OUT P21/TA4IN P22/TA9OUT P23/TA9IN P25(/TB1IN) P26(/TB2IN) P27 MD1 VSS P24(/TB0IN) P15/CTS1/CLK1 P16/RxD1 AV CC P12/RxD0 P13/TxD0 P17/TxD1 VREF P65/TA2IN/U/RTP11 P64/TA2OUT /V/RTP10 P63/TA1IN/W/RTP0 3 M37905F8CSP P62/TA1OUT /U/RTP02 P61/TA0IN/V/RTP01 P60/TA0OUT /W/RTP0 0 P57/INT7/TB2IN/IDU P56/INT6/TB1IN/IDV P55/INT5/TB0IN/IDW MD0 VCONT RESET P6OUT CUT /INT4 VSS P40/TA5OUT /RTP20 P41/TA5IN/RTP21 P42/TA6OUT /RTP22 P44/TA7OUT /RTP30 P45/TA7IN/RTP31 P46/TA8OUT /RTP32 P43/TA6IN/RTP23 P83/AN11/TxD2 P73/AN3 P74/AN4 P71/AN1 P72/AN2 P70/AN0 P67/TA3IN/RTP13 P66/TA3OUT /RTP12 XIN XOUT P53/INT3/RTPTRG0 P52/INT2/RTPTRG1 VCC AV SS P47/TA8IN/RTP33 P4OUT CUT /INT0 P51/INT1 Note Note Note: Allocation of pins TB0IN to TB2IN can be switched by software.

M37905F8CFP, M37905F8CSP PRELIMINAR Y Notice: This is not a final specification. Som e param etric lim its are subject to change. 16-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS Central Processing Unit (CPU) Bus Interface Unit(BIU) RESET MD1 V ReferenceVoltage Input Instruction Register (8) REF (0V)AV SS AV CC V CC X Clock input Clock Generating Circuit Reset input Clock output IN X OUT Address Bus Data Bus (Odd) Data Bus (Even) A-D Converter (12) UART1 (9)UART0 (9) Watchdog TimerTimer TB1 (16)Timer TB2 (16)Timer TB0 (16) D-A

1 Converter (8)

Timer TA1 (16)Timer TA2 (16)Timer TA3 (16)Timer TA4 (16)Timer TA0 (16) RAM 3072 bytes P6(8) Input/Output P6 P5(6) Input/Output P5 P7(8) Input/Output P7 P4(8) Input/Output P4 D-A

0 Converter (8)

P8(4) Input/Output P8 MD0 (0V)V SS P4OUT CUT ROM

60 Kbytes

V CONT Timer TA6 (16)Timer TA7 (16)Timer TA8 (16)Timer TA9 (16)Timer TA5 (16) P6OUT CUT P2(8) Input/Output P2 P1(8) Input/Output P1 UART2 (9) Data Buffer DQ0 (8) Data Buffer DQ1 (8) Data Buffer DQ2 (8) Data Buffer DQ3 (8) Instruction Queue Buffer Q0 (8) Instruction Queue Buffer Q1 (8) Instruction Queue Buffer Q2 (8) Instruction Queue Buffer Q3 (8) Instruction Queue Buffer Q4 (8) Instruction Queue Buffer Q5 (8) Instruction Queue Buffer Q6 (8) Instruction Queue Buffer Q7 (8) Instruction Queue Buffer Q8 (8) Instruction Queue Buffer Q9 (8) Program Address Register PA (24) Data Address Register DA (24) Incrementer (24) Incrementer/Decrementer (24) Input Buffer Register IB (16) Program Counter PC (16) Program Bank Register PG (8) Processor Status Register PS (11) Direct Page Register DPR0 (16) Direct Page Register DPR1 (16) Direct Page Register DPR2 (16) Direct Page Register DPR3 (16) Stack Pointer S (16) Index Register Y (16) Index Register X (16) Accumulator B (16) Accumulator A (16) Arithmetic Logic Unit (16) Data Bank Register DT (8) BLOCK DIAGRAM

M37905F8CFP, M37905F8CSP PRELIMINAR Y Notice: This is not a final specification. Som e param etric lim its are subject to change. 16-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS 203 50 ns (the fastest instruction at f(fsys) = 20 MHz) 20 MHz (Max.) 20 MHz (Max.)

8 Kbytes

8-bit ✕ 5 6-bit ✕ 1 4-bit ✕ 1 16-bit ✕ 10 16-bit ✕ 3 (UART or Clock synchronous serial I/O) ✕ 3 10-bit successive approximation method ✕ 1 (12 channels) 8-bit ✕ 2 8-bit ✕ 3 12-bit ✕ 1 8 external sources, 20 internal sources. Each interrupt can be set to a priority level within the range of 0–7 by software. 3 internal sources. Incorporated (externally connected to a ceramic resonator or quartz crystal resonator). The following multiplication ratios are available: ✕ 2, ✕3, ✕4. 5 V±0.5 V 125 mW (at f(f sys) = 20 MHz, Typ., ; the PLL frequency multiplier is inactive.) 5 V 5 mA Not available (single-chip mode only). –20 to 85 °C CMOS high-performance silicon gate process (Note) Number of basic machine instructions Instruction execution time External clock input frequency f(X IN) System clock frequency f(fsys) Memory size Programmable input/output ports Multi-functional timers Serial I/O A-D converter D-A converter Dead-time timer Watchdog timer Interrupts Clock generating circuit PLL frequency multiplier Power supply voltage Power dissipation Ports’ input/output characteristics Memory expansion Operating ambient temperature range Device structure Package Flash memory (User ROM area) RAM Flash memory (Boot ROM area) P1, P2, P4, P6, P7 TA0–TA9 TB0 –TB2 UART0, UART1, and UART2 FUNCTIONS (Microcomputer mode) FunctionsParameter Input/Output withstand voltage Output current Maskable interrups Non-maskable interrups Note: Packages M37905F8CFP 64-pin plastic molded QFP (64P6N-A) M37905F8CSP 64-pin shrink plastic moldeds DIP (64P4B)

M37905F8CFP, M37905F8CSP PRELIMINAR Y Notice: This is not a final specification. Som e param etric lim its are subject to change. 16-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS Power supply voltage Programming/Erase voltage Flash memory mode Block division for erasure Programming method Erase method Programming/Erase control Number of commands Maximum number of reprograms User ROM area Boot ROM area Flash memory parallel I/O mode Flash memory serial I/O mode Flash memory CPU reprogramming mode Flash memory parallel I/O mode Flash memory serial I/O mode Flash memory CPU reprogramming mode 5 V±0.5 V 5 V±0.5 V 3 modes: parallel I/O, serial I/O, and CPU reprogramming modes 4 blocks (8 Kbytes ✕ 2, 16 Kbytes ✕ 1, 28 Kbytes ✕ 1); total of 1 block (8 Kbytes ✕ 1) (Note) Programmed per word User ROM area + Boot ROM area User ROM area User ROM area Total erase/Block erase User ROM area + Boot ROM area User ROM area User ROM area Programming/Erase control by software commands 6 commands 100 FUNCTIONS (Flash memory mode) FunctionsParameter Note: On shipment, our reprogramming control firmware for the flash memory serial I/O mode has been stored into the boot ROM area.

M37905F8CFP, M37905F8CSP PRELIMINAR Y Notice: This is not a final specification. Som e param etric lim its are subject to change. 16-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS PIN DESCRIPTION (MICROCOMPUTER MODE) Vcc, Vss MD0 MD1 RESET X IN XOUT VCONT AVcc, AVss VREF P10–P17 P20–P27 P40–P47 P51–P53, P55–P57 P60–P67 P70–P77 P80–P83 P4OUT CUT P6OUT CUT Power supply input MD0 MD1 Reset input Clock input Clock output Filter circuit connection Analog power supply input Reference voltage input I/O port P1 I/O port P2 I/O port P4 I/O port P5 I/O port P6 I/O port P7 I/O port P8 P4OUT CUT input P6OUT CUT input Input Input Input Input Output Input I/O I/O I/O I/O I/O I/O I/O Input Input Apply 5 V±0.5 V to Vcc, and 0 V to Vss. Connect this pin to V SS . Connect this pin to Vss. The microcomputer is reset when “L” level is applies to this pin. These are input and output pins of the internal clock generating circuit. Connect a ceramic resonator or quartz-crystal oscillator between pins X IN and XOUT . When an external clock is used, the clock source should be connected to pin XIN, and pin XOUT should be left open. When using the PLL frequency multiplier, connect this pin to the filter circuit. When not using the PLL frequency multiplier, this pin should be left open. Power supply input pins for the A-D and D-A converters. Connect AVcc to Vcc, and AVss to Vss externally. This is the reference voltage input pin for the A-D and D-A converters. Port P1 is an 8-bit I/O port. This port has an I/O direction register, and each pin can be programmed for input or output. These pins enter the input mode ar reset. These pins also function as I/O pins of UART0, 1. In addition to having the same functions as port P1, these pins function as I/O pins for timers A4 and A9. Also, they can be programmed to function as input pins for tim- ers B0 to B2. In addition to having the same functions as port P1, these pins function as I/O pins for timers A5 to A8. Also, they function as output pins for motor drive waveform. In addition to having the same functions as port P1, these pins function as input pins for INT 1 to INT3 and INT5 to INT7. Also, pins P55 to P57 function as input pins for tim- ers B0 to B2 and as input pins for position data in the three-phase waveform mode; and pins P5 2 and P53 function as trigger-input pins in the pulse output port mode. In addition to having the same functions as port P1, these pins function as I/O pins for timers A0 to A3. Also, they function as motor drive waveform output pins. In addition to having the same functions as port P1, these pins function as input pins for the A-D converter. Also, P77 functions as an output pin for the D-A converter. In addition to having the same functions as port P1, these pins function as input pins for the A-D converter. Also, these pins function as I/O pins for UART2, and pin P80 functions as an output pin for the D-A converter. This pin has the function to forcibly place port P4 pins in the input mode. Also, this pin functions as an input pin for INT0; and this pin is used to input a signal, which forcibly cuts off a motor drive waveform output. This pin has the function to forcibly place port P6 pins in the input mode. Also, this pin functions as an input pin for INT4; and this pin is used to input a signal, which forcibly cuts off a motor drive waveform output. FunctionsInput/ OutputNamePin

M37905F8CFP, M37905F8CSP PRELIMINAR Y Notice: This is not a final specification. Som e param etric lim its are subject to change. 16-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS PIN DESCRIPTION (FLASH MEMORY SERIAL I/O MODE) VCC , VSS MD0 MD1 RESET X IN XOUT AVcc, AVss V REF P10–P17 P20–P23, P27 P24 P25 P26 P4OUT CUT P6OUT CUT P40–P47 P55–P53, P55–P57 P60–P67 P70–P74 P80–P83 VCONT Pin Power supply input MD0 MD1 Reset input Clock input Clock output Analog supply input Reference voltage input Input port P1 Input port P2 SCLK input SDA I/O BUSY output P4OUT CUT input P6OUT CUT input Input port P4 Input port P5 Input port P6 Input port P7 Input port P8 Filter circuit connection Name Input Input Input Input Output Input Input Input Input I/O Output Input Input Input Input Input Input Input Input /Output Functions Apply 5 V ± 0.5 V to Vcc, and 0 V to Vss. Connect this pin to Vss. Connect this pin to Vss via a resistor of 10 kΩ to 100 kΩ . The reset input pin. Connect a ceramic oscillator between the X IN and XOUT pins, or input an external clock from the XIN pin with the XOUT pin left open. Connect AVcc to Vcc, and AVss to Vss. Input an arbitrary level within the range of VSS –VCC . (This is not used in the flash memory serial I/O mode.) Input “H ” or “L”, or leave them open. (This is not used in the flash memory serial I/O mode.) Input “H ” or “L”, or leave them open. (This is not used in the flash memory serial I/O mode.) This is an input pin for a serial clock. This is an I/O pin for serial data. Connect this pin to VCC via a resistor (about 1 kΩ ). This is an output pin for the BUSY signal. Input “H ”. Input “H ”. Input “H ” or “L”, or leave them open. (This is not used in the flash memory serial I/O mode.) Input “H ” or “L”, or leave them open. (This is not used in the flash memory serial I/O mode.) Input “H ” or “L”, or leave them open. (This is not used in the flash memory serial I/O mode.) Input “H ” or “L”, or leave them open. (This is not used in the flash memory serial I/O mode.) Input “H ” or “L”, or leave them open. (This is not used in the flash memory serial I/O mode.) Connect this pin to the filter circuit, or leave this pin open. (This is not used in the flash memory serial I/O mode.)

M37905F8CFP, M37905F8CSP PRELIMINAR Y Notice: This is not a final specification. Som e param etric lim its are subject to change. 16-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS BASIC FUNCTION BLOCKS Each of the M37905F8CFP and M37905F8CSP has the same func- tion as that of the M37905M4C-XXXFP except for the following. Therefore, for details except for the following, refer to the datasheet of the M37905M4C-XXXFP.

• Internal ROM: type (flash memory) and size
• RAM size MEMORY Figure 1 shows the memory map. Fig. 1 Memory map of M37905F8CFP, M37905F8CSP (Single-chip mode) Interrupt vector table 00000016 Bank 016 00FFFF 16 00000016 00040016 0000FF16 00FFFE 16 00FFB4 16 Internal RAM 3072 bytes Internal ROM

(See Figures 2 and 3.) 00010016 INT4 A-D conversion Reserved area Reserved area Address matching detect Reserved area INT5 INT6 INT7 Timer A5 UART1 transmit UART1 receive UART0 transmit UART0 receive Timer B2 Timer B1 Timer B0 Timer A4 Timer A3 Timer A2 Timer A1 Timer A0 Watchdog timer BRK instruction Zero divide INT3 INT2 INT1 INT0 Reserved area RESET DBC

M37905F8CFP, M37905F8CSP PRELIMINAR Y Notice: This is not a final specification. Som e param etric lim its are subject to change. 16-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS Fig. 2 Location of SFRs (1) 00000016 00000116 00000216 00000316 00000416 00000516 00000616 00000716 00000816 00000916 00000A16 00000B16 00000C 16 00000D 16 00000E16 00000F16 00001016 00001116 00001216 00001316 00001416 00001516 00001616 00001716 00001816 00001916 00001A16 00001B16 00001C 16 00001D 16 00001E16 00001F16 00002016 00002116 00002216 00002316 00002416 00002516 00002616 00002716 00002816 00002916 00002A16 00002B16 00002C 16 00002D 16 00002E16 00002F16 00003016 00003116 00003216 00003316 00003416 00003516 00003616 00003716 00003816 00003916 00003A16 00003B16 00003C 16 00003D 16 00003E16 00003F16 Port P2 register Reserved area (Note) Port P1 direction register Reserved area (Note) Port P1 register Reserved area (Note) Port P2 direction register Reserved area (Note) Port P4 register Port P5 register Port P4 direction register Port P5 direction register Port P6 register Port P7 register Port P6 direction register Port P7 direction register Port P8 register Port P8 direction register Reserved area (Note) Reserved area (Note) Reserved area (Note) Reserved area (Note) A-D control register 0 A-D control register 1 A-D register 0 A-D register 1 A-D register 2 A-D register 3 UART0 transmit/receive mode register UART0 band rate register (BRG0) UART0 transmit buffer register UART0 transmit/receive control register 0 UART0 transmit/receive control register 1 UART0 receive buffer register UART1 transmit/receive mode register UART1 baud rate register (BRG1) UART1 transmit buffer register UART1 transmit/receive control register 0 UART1 transmit/receive control register 1 UART1 receive buffer register Address (Hexadecimel notation) Address (Hexadecimel notation) 000040 00004116 00004216 00004316 00004416 00004516 00004616 00004716 00004816 00004916 00004A16 00004B16 00004C 16 00004D 16 00004E16 00004F16 00005016 00005116 00005216 00005316 00005416 00005516 00005616 00005716 00005816 00005916 00005A16 00005B16 00005C 16 00005D 16 00005E16 00005F16 00006016 00006116 00006216 00006316 00006416 00006516 00006616 00006716 00006816 00006916 00006A16 00006B16 00006C 16 00006D 16 00006E16 00006F16 00007016 00007116 00007216 00007316 00007416 00007516 00007616 00007716 00007816 00007916 00007A16 00007B16 00007C 16 00007D 16 00007E16 00007F16 Count start register 0 One-shot start register 0 Up-down register 0 Timer A clock division select register Timer A0 register Timer A1 register Timer A2 register Timer A3 register Timer A4 register Timer B0 register Timer B1 register Timer B2 register Timer A1 mode register Timer A0 mode register Timer A2 mode register Timer A3 mode register Timer A4 mode register Timer B0 mode register Timer B1 mode register Timer B2 mode register Processor mode register 0 Processor mode register 1 Watchdog timer register Particular function select register 0 Particular function select register 1 Debug control register 0 INT 3 interrupt control register A-D conversion interrupt control register UART0 transmit interrupt control register UART0 receive interrupt control register UART1 receive interrupt control register Timer A0 interrupt control register Timer A1 interrupt control register Timer A3 interrupt control register Timer A4 interrupt control register Timer B0 interrupt control register Timer B2 interrupt control register INT0 interrupt control register INT1 interrupt control register Watchdog timer frequency select register Debug control register 1 INT4 interrupt control register UART1 transmit interrupt control register Timer A2 interrupt control register Timer B1 interrupt control register INT2 interrupt control register Address comparison register 0 Address comparison register 1 Particular function select register 2 Reserved area (Note) Note: Do not write to this address. A-D register 4 A-D register 5 A-D register 6 A-D register 7 Count start register 1 One-shot start register 1 Reserved area (Note) Reserved area (Note)

M37905F8CFP, M37905F8CSP PRELIMINAR Y Notice: This is not a final specification. Som e param etric lim its are subject to change. 16-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS Fig. 3 Location of SFRs (2) Serial I/O pin control register 0000C0 16 0000C1 16 0000C2 16 0000C3 16 0000C4 16 0000C5 16 0000C6 16 0000C7 16 0000C8 16 0000C9 16 0000CA 16 0000CB 16 0000CC 16 0000CD 16 0000CE 16 0000CF 16 0000D0 16 0000D1 16 0000D2 16 0000D3 16 0000D4 16 0000D5 16 0000D6 16 0000D7 16 0000D8 16 0000D9 16 0000DA 16 0000DB 16 0000DC 16 0000DD 16 0000DE 16 0000DF 16 0000E016 0000E116 0000E216 0000E316 0000E416 0000E516 0000E616 0000E716 0000E816 0000E916 0000EA 16 0000EB 16 0000EC 16 0000ED 16 0000EE 16 0000EF 16 0000F016 0000F116 0000F216 0000F316 0000F416 0000F516 0000F616 0000F716 0000F816 0000F916 0000FA 16 0000FB 16 0000FC 16 0000FD 16 0000FE 16 0000FF16 Up-down register 1 Timer A5 register Timer A6 register Timer A7 register Timer A8 register Timer A9 register Timer A01 register Timer A11 register Timer A21 register Timer A5 mode register Timer A7 mode register Timer A8 mode register Timer A9 mode register Comparator function select register 0 Comparator function select register 1 Comparator result register 0 A-D register 8 A-D register 9 A-D register 10 A-D register 11 Reserved area (Note) Reserved area (Note) Reserved area (Note) Reserved area (Note) Reserved area (Note) Reserved area (Note) Reserved area (Note) UART2 transmit interrupt control register UART2 receive interrupt control register Timer A7 interrupt control register Timer A5 interrupt control register Timer A6 interrupt control register Timer A8 interrupt control register Timer A9 interrupt control register INT7 interrupt control register INT5 interrupt control register INT6 interrupt control register 0000A016 0000A116 0000A216 0000A316 0000A416 0000A516 0000A616 0000A716 0000A816 0000A916 0000AA 16 0000AB 16 0000AC 16 0000AD 16 0000AE 16 0000AF 16 0000B016 0000B116 0000B216 0000B316 0000B416 0000B516 0000B616 0000B716 0000B816 0000B916 0000BA 16 0000BB 16 0000BC 16 0000BD 16 0000BE 16 0000BF 16 Pulse output control register Pulse output data register 0 Pulse output data register 1 Waveform output mode register Three-phase output data register 0 Three-phase output data register 1 UART2 transmit/receive mode register UART2 band rate register (BRG2) UART2 transmit buffer register UART2 transmit/receive control register 0 UART2 transmit/receive control register 1 000080 00008116 00008216 00008316 00008416 00008516 00008616 00008716 00008816 00008916 00008A16 00008B16 00008C 16 00008D 16 00008E16 00008F16 00009016 00009116 00009216 00009316 00009416 00009516 00009616 00009716 00009816 00009916 00009A16 00009B16 00009C 16 00009D 16 00009E16 00009F16 Address (Hexadecimel notation) Address (Hexadecimel notation) Reserved area (Note) Reserved area (Note) Reserved area (Note) Reserved area (Note) Reserved area (Note) Reserved area (Note) Reserved area (Note) Reserved area (Note) Reserved area (Note) Reserved area (Note) Reserved area (Note) Reserved area (Note) Note: Do not write to this address. Reserved area (Note) Reserved area (Note) Reserved area (Note) D-A control register D-A register 0 D-A register 1 Flash memory control register Dead-time timer Position-data-retain function control register Port P2 pin function control register UART2 receive buffer register Reserved area (Note) Reserved area (Note) Clock control register 0 Reserved area (Note) Reserved area (Note) Reserved area (Note) Timer A6 mode register A-D control register 2 Comparator result register 1 Reserved area (Note) External interrupt input read-out register Reserved area (Note)

M37905F8CFP, M37905F8CSP 16-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS PRELIMINAR Y Notice: This is not a final specification. Som e param etric lim its are subject to change. FLASH MEMORY MODE These microcomputers contain the flash memory; and single-power- supply reprogramming is available to this. These microcomputers have the following three modes, enabling reading/programming/era- sure for the flash memory:

• Flash memory parallel I/O mode and Flash memory serial I/O mode, where the flash memory is handled by using an external pro- grammer.
• CPU reprogramming mode, where the flash memory is handled by the central processing unit (CPU). As shown in Figure 4, the flash memory is divided into several blocks, and erasure per block is possible. Fig. 4 M37905F8CFP, M37905F8CSP: block configuration of internal flash memory This internal flash memory has the boot ROM area storing the repro- gramming control software for reprogramming in the CPU repro- gramming mode and flash memory serial I/O mode, as well as the user ROM area storing a certain control software for the normal op- eration in the microcomputer mode. Although our reprogramming control firmware for the flash memory serial I/O mode has been stored into this boot ROM area on ship- ment, the user-original reprogramming control software which is more appropriate for the user’s system is reprogrammable into this area, instead. Note that the reprogramming for the boot ROM area is enabled only in the flash memory parallel I/O mode.

28 Kbytes

16 Kbytes

Notice: This is not a final specification. Table 1. Software commands (flash memory parallel I/O mode the flash memory parallel I/O mode. area if the user uses the flash memory serial I/O mode. the reserved area for the programmer. lel I/O mode, do not program to this area.

M37905F8CFP, M37905F8CSP 16-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS PRELIMINAR Y Notice: This is not a final specification. Som e param etric lim its are subject to change. Flash Memory Serial I/O Mode In the flash memory serial I/O mode, addresses, data, and software commands, which are required to read/program/erase the internal flash memory, are serially input and output with a fewer pins and the dedicated serial programmer. In this mode, being different from the flash memory parallel I/O mode, the CPU controls reprogramming of the flash memory (using the CPU reprogramming mode), serial input of the reprogramming data, etc. The reprogramming control firmware for the flash memory serial I/O mode has been stored in the boot ROM area on shipment of the product from us. Note that, then, the flash memory serial I/O mode will become unavailable if the boot ROM area has been repro- grammed in the flash memory parallel I/O mode. Note that, also, this reprogramming control firmware for the flash memory serial I/O mode is subject to change. Figures 5 and 6 show the pin connections in the flash memory serial I/O mode. The three pins, SCLK, SDA, and BUSY, are used to input and output serial data. The SCLK pin is the input pin of external transfer clocks. The SDA pin is the I/O pin of transmit and receive data, and its output acts as the N-channel open-drain output. To the SDA pin, connect an exter- nal pullup resistor (about 1 kΩ ). The BUSY pin is the output pin of the BUSY flag (CMOS output) and goes “H ” during BUSY periods owing to a certain operation, such as transmit, receive, erase, program- ming, etc. Transmit and receive data are serially transferred 8 bits at a time. In the flash memory serial I/O mode, only the user ROM area can be reprogrammed; the boot ROM area is not accessible. Addresses FF90 16 to FF9F16 are the reserved area for the serial programmer. Therefore, when the user uses the flash memory serial I/O mode, do not program to this area.

M37905F8CFP, M37905F8CSP MITSUBISHI MICROCOMPUTERS PRELIMINAR Y Notice: This is not a final specification. Som e param etric lim its are subject to change. Fig. 5 Pin connection of M37905F8CFP in flash memory serial I/O mode (outline: 64P6N-A) Outline 64P6N-A 3/AN 2/AN 1/AN 0/AN 7/TA3 IN /RTP1 6/TA3 OU T/RTP1 5/TA2 IN /U/RTP1 4/TA2 OUT /V/ RT P1 3/TA1 IN /W/ RT P0 7/INT 7/TB 2IN /ID U 6/INT 6/TB1 IN /IDV 5/INT 5/TB 0IN /ID W OUT CU T/INT 2/TA1 OUT /U/ RT P0 1/TA0 IN /V/RT 0/TA 0OUT /W/RT 3/TxD 6/RxD 7/TxD 0/TA4 OUT 1/TA4 IN 2/TA9 OUT 4(/ TB 0 IN 5(/ TB 1IN 6(/ TB 2IN MD 0/TA5 OU T/RTP2 1/TA5 IN /RT P2 3/TA9 IN 5/CTS 1/CLK 4/CTS 1/RTS P74/AN4 P75/AN5 P76/AN6 P77/AN7/DA0 P82/AN10/RxD2 P83/AN11/TxD2 Vss AVss VR EF AVcc Vcc P12/RxD0 P81/AN9/CT S2/CLK2 P80/AN8/CT S2/RTS2/DA1 P10/CTS0/RTS0 P11/CTS0/CLK0 MD 0 XIN VC O N T XO UT Vss P47/TA8IN/RTP33 P46/TA8O UT/RTP32 P45/TA7IN/RTP31 P44/TA7O UT/RTP30 P43/TA6IN/RTP23 P42/TA6O UT/RTP22 RE SE T P53/INT3/RTPTR G 0 P52/INT2/RTPTR G 1 P51/INT1 P4 OUTC UT/INT0 (Note 1) BUSYSCLK (Note 3) (Note 1) V CC (Note 3) SD A MD1V SS (Note 2) RE SET 33343536373839404142434445464748 151413121110987654321 16 Notes 1: Allocation of pins TB0IN to TB2IN can be switched by software. 2: Connected to the oscillation circuit. 3: Recommended to be connected with VCC via a resistor. : Connected to a serial programmer.

M37905F8CFP, M37905F8CSP 16-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS PRELIMINAR Y Notice: This is not a final specification. Som e param etric lim its are subject to change. Fig. 6 Pin connection of M37905F8CSP in flash memory serial I/O mode (outline: 64P4B) VRE F P82/AN10/RXD 2 P83/AN11/TXD 2 P12/RXD 0 P13/TXD 0 P16/RXD 1 P17/TXD 1 P20/TA4OUT P21/TA4IN P22/TA9OUT P23/TA9IN P24(/ TB 0IN) P25(/ TB 1IN) P26(/ TB 2IN) P27 AVss P81/AN9/CTS2/CLK2 P80/AN8/CTS2/RTS2/DA1 P77/AN7/DA0 P72/AN2 P71/AN1 P70/AN0 RE SE T XIN XOUT VCO NT Vss P75/AN5 P74/AN4 P73/AN3 P76/AN6 Vcc P40/TA5OUT /RTP20 P41/TA5IN/RTP21 P42/TA6OUT /RTP22 P43/TA6IN/RTP23 P44/TA7OUT /RTP30 P45/TA7IN/RTP31 P46/TA8OUT /RTP32 P47/TA8IN/RTP33 P67/TA3IN/RTP13 P65/TA2IN/U/RTP11 P64/TA2OUT /V/RTP10 P63/TA1IN/W/RTP0 3 P62/TA1OUT /U/RTP02 P61/TA0IN/V/RTP01 P60/TA0OUT /W/RTP0 0 P66/TA3OUT /RTP12 P52/INT2/RTPTRG1 P55/INT5/TB0IN/IDW P53/INT3/RTPTRG0 P57/INT7/TB2IN/IDU P56/INT6/TB1IN/IDV P51/INT1 P4 OUTCU T/INT0 AVcc MD0 MD1 Vss P10/CTS0/RTS0 P11/CTS0/CLK0 P14/CTS1/RTS1 P15/CTS1/CLK1 (Note 2) (Note 1) BUSY SCLK (Note 3) (Note 1) VCC VSS RE SE T (Note 3) SDA MD1 P6 OUTCU T/INT4 Notes 1: Allocation of pins TB0IN to TB2IN can be switched by software. 2: Connected to the oscillation circuit. 3: Recommended to be connected with VCC via a resistor. : Connected to a serial programmer. Outline 64P4B

M37905F8CFP, M37905F8CSP MITSUBISHI MICROCOMPUTERS PRELIMINAR Y Notice: This is not a final specification. Som e param etric lim its are subject to change. CPU Reprogramming Mode The CPU reprogramming mode is used to perform the operations for the internal flash memory (reading, programming, erasing) under control of the CPU. In this mode, only the user ROM area can be reprogrammed; the boot ROM area cannot be reprogrammed. The user-original reprogramming control software for the CPU repro- gramming mode can be stored in either the user ROM area or the boot ROM area. Because the CPU cannot read out the flash memory in the CPU re- programming mode, the above software must be transferred to the internal RAM in advance to be executed. Boot Mode The user-original reprogramming control software for the CPU repro- gramming mode must be stored into the user ROM area or the boot ROM area in the flash memory parallel I/O mode in advance. (If this program has been stored into the boot ROM area, the flash memory serial I/O mode will become unavailable). Note that addresses of the boot ROM area depend on the accessing ways to the boot ROM area, When accessing in the flash memory parallel I/O mode, these addresses will be shifted to 0000 16 to 1FFF16. On the other hand, when accessing with the CPU, these ad- dresses will be shifted to E00016 to FFFF16. Reset removal with both of the MD0 and MD1 pins held “L” invokes the normal microcomputer mode, and the CPU operates using the control software stored in the user ROM area. In this case, the boot ROM area is not accessible. Removing reset with the MD0 pin held “L” and the MD1 pin “H”, the CPU starts its operation using the reprogramming control software stored in the boot ROM area. This mode is called the boot mode. The reprogramming control software in the boot ROM area can also re- program the user ROM area. After reset removal, be sure not to change the status at pins MD0 and MD1. Fig. 7 Bit configuration of flash memory control register Flash memory control register RY/BY status bit 0: Busy (Programming or erasing is active.) 1: Ready CPU reprogramming mode select bit (Note 2) 0: Normal mode (Software commands are ignored.) 1: CPU reprogramming mode (Software commands are acceptable.) Flash memory reset bit (Note 3) 0: Normal operation 1: Reset User ROM area select bit (Note 4) (Valid only in the boot mode.) 0: Boot ROM area access 1: User ROM area access Notes 1: The contents of the flash memory control register after reset is removed are “XX000001 ”. 2: To set “1”, writing of “0” to bit 1 and subsequent writing of “1” to bit 1 are necessary. Writing to bit 1 must be performed by the user-original reprogramming control software in the internal RAM. 3: This bit is valid only when bit 1 = “1”. Before setting this bit to “0”, be sure to confirm that bit 0 = “1” after setting this bit to “1” (reset). This bit 3 must be controlled with bit 1 = “1”. 4: Writing to bit 5 must be performed by the user-original reprogramming control software in the internal RAM. 765432 1

0 Address

M37905F8CFP, M37905F8CSP MITSUBISHI MICROCOMPUTERS PRELIMINAR Y Notice: This is not a final specification. Som e param etric lim its are subject to change. Fig. 8 CPU reprogramming mode set/termination flowchart Software Commands Table 2 lists the software commands. By writing a software command after the CPU reprogramming mode select bit has been set to “1”, erasing, programming, etc. can be specified. Note that, at software commands’ input, the high-order byte (D 8–D 15) is ignored. (Except for the write data at the 2nd cycle of a programming command.) Software commands are explained as below. Read Array Command (FF 16) By writing command code “FF16” at the 1st bus cycle, the microcom- puter enters the read array mode. If an address to be read is input in the next or the following bus cycles, the contents at the specified ad- dress are output to the data bus (D 0 to D15) in a unit of 16 bits. The read array mode is maintained until writing of another software command. Read Status Register Command (7016) Writing command code “7016” at the 1st bus cycle outputs the con- tents of the status register to the data bus (D0-D7) by a read at the 2nd bus cycle. The status register is explained later. Clear Status Register Command (5016) This command clears two status bits (SR.4, 5) each of which is set to “1” to indicate that the operation has been terminated by an error. To clear these bits, write command code “50 16” at the 1st bus cycle. Programming Command (40 16) This command facilitates programming of 1 word (2 bytes) at a time. To initiate programming, write command code “4016” at the 1st bus cycle; when write data is written in a unit of 16 bits at the 2nd bus cycle, the address is specified at the same time. Upon completion of data writing, automatic programming (data programming and verifi- cation) operation is started. The completion of the automatic programming operation is con- firmed by a read of the flash memory control register. The RY/BY sta- tus bit of the flash memory control register goes “0” during the automatic programming operation; and also, it goes “1” after the end of it. Before execution of the next command, be sure to confirm that the RY/BY status bit is set to “1” (READY). During the automatic pro- gramming operation, writing of commands and access to the flash memory must not be performed. When programming continuously, the programming command can be executed with the read status register mode kept if there is no programming error. Simultaneously with start of the automatic pro- gramming, the read status register mode is automatically active. In this case, the read status register mode is retained until the next read array command (FF 16) is written or until the reset is performed by using the flash memory reset bit. Reading out the status register after the automatic programming op- eration is completed reports the result of it. For details, refer to the section on the status register. Figure 9 shows an example of the programming flowchart. Additional programming to any word that has already been pro- grammed is prohibited. Completed Start Read array command is executed, or reset is performed by setting the flash memory reset bit. (Writing of “1” → Writing of “0”) (Note 2) Single-chip mode, Memory expansion mode, or Boot mode The processor mode register 1 is set (Note 1). Flag I is set to “1”. Operations such as erasing, programming are executed by using software commands. Jump to the above software in the internal RAM. (The operations shown below will be executed by the above software in this RAM.) The user-original reprogramming control software for the CPU reprogramming mode is transferred to the internal RAM. (Only in the boot mode.) Writing of “0” to user ROM area select bit (Note 3). Writing of “0” to the CPU reprogramming mode select bit. (Only in the boot mode.) The user ROM area select bit is set to “1”. Writing of “1” to the CPU reprogramming mode select bit. (Writing of “0” → Writing of “1”) Notes 1: The processor mode register 1’s bit 7 (address 5F16, the internal ROM bus cycle select bit) must be “0” (bus cycle = 3φ). 2: To terminate the CPU reprogramming mode after the erase and programming operations have been completed, be sure to execute the read array command or perform the flash memory reset operation. 3: This bit may remain “1”. However, if this bit is “1”, the user ROM area access is specified.

Notice: This is not a final specification. Table 2. Software commands (CPU reprogramming mode) Notes 1: At software commands’ input, the high-order byte of data (D8–D 15) is ignored. 4: WA = Write Address, WD = Write Data (16 bits). 5: Block address: the maximum address of each block must be input. Note that address A0 = “0”. Figure 10 shows an example of the block erase flowchart.

M37905F8CFP, M37905F8CSP MITSUBISHI MICROCOMPUTERS PRELIMINAR Y Notice: This is not a final specification. Som e param etric lim its are subject to change. Fig. 9 Programming flowchart Fig. 10 Block erase flowchart Start Write 4016 Write, Address, Data Flash memory control register Read Full status check Programming Completed NO YES RY/BY Status Bit = 1? Write 2016 Write D016, Flash memory control register Read Full status check Block erase Completed NO YES Block address Start RY/BY Status Bit = 1? Erase All Block Command (2016/2016) Writing command code “2016” at the 1st bus cycle and writing com- mand code “2016” at the subsequent 2nd bus cycle initiate the con- tinuous block erase (chip erase) operations for all the blocks. The completion of the chip erase operation, as well as of the block erase operation, is confirmed by a read of the flash memory control register. The result of the automatic erase operation is also reported by a read of the status register. During the automatic erase operation (when the RY/BY status bit = “0”), writing of commands and access to the flash memory must not be performed. Status Register The status register is used to indicate whether the programming/ erase operation has been completed normally or terminated by an error. By writing the read status register command (7016), the con- tents of the status register can be read out; by writing the clear sta- tus register command (50 16), the contents of the status register can be cleared. Table 3 lists the definition of each bit of the status register. The status register outputs “8016” after reset is removed. The status of each bit is described below.

Notice: This is not a final specification. tus register command (5016) is written. This bit reports the status of the automatic programming operation. taken if an error has occurred. Table 3. Bit definition of status register

M37905F8CFP, M37905F8CSP MITSUBISHI MICROCOMPUTERS PRELIMINAR Y Notice: This is not a final specification. Som e param etric lim its are subject to change. Fig. 11 Full status check flowchart and actions to be taken if an error has ocurred Symbol Parameter Limits UnitMin. Typ. Max. VCC power source current (at read) VCC power source current (at write) VCC power source current (at programming) VCC power source current (at erasing) Limits of VIH, VIL, VOH , VOL , IIH, and IIL for each pin are the same as those in the microcomputer mode. Note: f(fsys) indicates the system clcok (fsys) frequency. mA mA mA mA Parameter 256-byte programming time Block erase time Erase all block time Limits UnitMin. Typ. Max. 0.6 0.6 ✕ n 8 ✕ n ms s s n = Number of blocks to be erased Icc1 Icc2 Icc3 Icc4 The limits of parameters other than the above are same as those in the microcomputer mode. Note: f(fsys) indicates the system clock (fsys) frequency. Status Register Read SR.4 = 1 NO Command Sequence Error YES SR.5 = 0? YES Block Erase Error NO SR.4 = 0? YES Programming Error NO End (Block erase, Programming) and SR.5 = 1 ➀ Execute the clear status register command (5016) to clear the status register. ➁ Confirm whether the command has correctly been input or not; and then, start the operation again. Perform the block erase operation again. If an error occurs even after the above operation is performed, the block cannot be used. Perform the programming operation again. If an error occurs even after the above operation is performed, the word cannot be used. Note: Under the condition that any of SR.5 and SR.4 = 1 , none of the programming, block erase, and erase all block commands can be accepted. Before execution of these commands, execute the clear status register command (50 16) in advance.

M37905F8CFP, M37905F8CSP PRELIMINAR Y Notice: This is not a final specification. Som e param etric lim its are subject to change. 16-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS Unit V V V V V V mA mA mA mA mA mA MHz MHz Max. 5.5 Vcc 0.2 V CC –10 Parameter Power source voltage Analog power source voltage Power source voltage Analog power source voltage High-level Input voltageP10–P17, P20–P27, P40–P47, P51–P53, P55–P57, P60–P67, P70–P77, P80–P83, P4OUTCUT , P6OUTCUT , XIN, RESET, MD0, MD1 Low-level Input voltageP10–P17, P20–P27, P40–P47, P51–P53, P55–P57, P60–P67, P70–P77, P80–P83, P4OUTCUT , P6OUTCUT , XIN, RESET, MD0, MD1 High-level peak output current P10–P17, P20–P27, P55–P57, P60–P67, P70–P77 High-level average output current P10–P17, P20–P27, P55–P57, P60–P67, P70–P77 Low-level peak output current P10–P17, P20–P27, P51–P53, P55–P57, P70–P77 Low-level peak output current P40–P47, P60–P67 Low-level average output current P10–P17, P20–P27, P51–P53, P55–P57, P70–P77 Low-level average output current P40–P47, P60–P67 External clock input frequency (Note 1) System clock frequency Symbol VCC AV CC VSS AV SS VIH VIL IOH(peak) IOH(avg) IOL(peak) IOL(peak) IOL(avg) IOL(avg) f(XIN) f(fsys) Parameter Power source voltage Analog power source voltage Input voltage P1 0–P17, P20–P27, P40–P47, P51–P53, P55–P57, P60–P67, P70–P77, P80–P83, P4OUTCUT , P6OUTCUT , VCONT , VREF , XIN, RESET, MD0, MD1 Output voltage P10–P17, P20–P27, P40–P47, P51–P53, P55–P57, P60–P67, P70–P77, P80–P83, XOUT Power dissipation Operating ambient temperature Storage temperature Symbol VCC AV CC VI VO Pd Topr Tstg ABSOLUTE MAXIMUM RATINGS RECOMMENDED OPERATING CONDITIONS (Vcc = 5 V, Ta = –20 to 85 °C, unless otherwise noted) Notes 1: When using the PLL frequency multiplier, be sure that f(fsys) = 20 MHz or less. 2: Average output current is the average value of an interval of 100 ms. 3: The sum of IOL(peak) must be 110 mA or less, the sum of IOH(peak) must be 80 mA or less. Unit V V V V mW Ratings –0.3 to 6.5 –0.3 to 6.5 –0.3 to V CC +0.3 –0.3 to VCC +0.3 300 –20 to 85 –40 to 150 Limits Min. 4.5

0.8 Vcc

Typ. 5.0 VCC

M37905F8CFP, M37905F8CSP PRELIMINAR Y Notice: This is not a final specification. Som e param etric lim its are subject to change. 16-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS Unit V V V V V µA µA V mA µA f(fsys) = 20 MHz. CPU is active. Ta = 25 °C when clock is inactive. Ta = 85 °C when clock is inactive. Test conditions IOH = –10 mA IOL = 10 mA VI = 5.0 V VI = 0 V When clock is stoped. Parameter High-level output voltageP10–P17, P20–P27, P40–P47, P51–P53, P55–P57, P60–P67, P70–P77, P80–P83 Low-level output voltageP10–P17, P20–P27, P40–P47, P51–P53, P55–P57, P60–P67, P70–P77, P80–P83 Hysteresis TA0 IN–TA9IN, TA0OUT –TA9OUT , TB0 IN–TB2 IN, INT0–INT7, CTS0, CTS1, CTS 2, CLK0, CLK1, CLK2, RxD0, RxD1, RxD 2, RTPTRG0 , RTPTRG1 , P4OUTCUT , P6OUT CUT Hysteresis RESET Hysteresis XIN High-level input currentP10–P17, P20–P27, P40–P47, P51–P53, P55–P57, P60–P67, P70–P77, P80–P83, P4OUTCUT , P6OUT CUT , XIN, RESET, MD0, MD1 Low-level input currentP10–P17, P20–P27, P40–P47, P51–P53, P55–P57, P60–P67, P70–P77, P80–P83, P4OUTCUT , P6OUT CUT , XIN, RESET, MD0, MD1 RAM hold voltage Power source current Symbol VOH VOL VT+ — VT – VT+ — VT – VT+ — VT – IIH IIL VRAM ICC DC ELECTRICAL CHARACTERISTICS (Vcc = 5 V, Vss = 0 V, Ta = –20 to 85 °C, f(fsys) = 20 MHz) Min. 0.4 0.5 0.1 Limits Typ. Max. 1.5 0.3 Output-only pins are open, and the other pins are con- nected to Vss or Vcc. An external square-waveform clock is input. (Pin X OUT is open.) The PLL frequency multiplier is inac- tive.

M37905F8CFP, M37905F8CSP PRELIMINAR Y Notice: This is not a final specification. Som e param etric lim its are subject to change. 16-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS Resolution Absolute accuracy Ladder resistance Conversion time Reference voltage Analog input voltage R LADDER tCONV VREF VIA VREF = VCC VREF = VCC VREF = VCC f(fsys) ≤ 20 MHz Max. A-D CONVERTER CHARACTERISTICS (VCC = AVCC = 5 V ± 0.5 V, VSS = AVSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted) UnitParameterSymbol Test conditions Limits Min. 10-bit resolution mode 8-bit resolution mode Comparater 10-bit resolution mode 8-bit resolution mode Comparater 5.9 2.45 (Note) 0.7 (Note) 2.7 ± 3 ± 2 ± 40 VCC VREF Bits V LSB LSB mV kΩ µs V V Note: This is applied when A-D conversion freguency (φAD ) = f1 (φ). D-A CONVERTER CHARACTERISTICS (VCC = 5 V, VSS = AVSS = 0 V, VREF = 5 V, Ta = –20 to 85 °C, unless otherwise noted) UnitParameterSymbol Limits Typ.Min. Max.Test conditions Resolution Absolute accuracy Set time Output resistance Reference power source input current t su R O IVREF (Note) 2 3.5 ± 1.0 4.5 3.2 Bits µs kΩ mA Note: The test conditions are as follows:

• One D-A converter is used.
• The D-A register value of the unused D-A converter is “0016.”
• The reference power source input current for the ladder resistance of the A-D converter is excluded. µsRESET input low-level pulse widthtw(RESETL) Symbol Parameter Min. Limits Unit RESET INPUT Reset input timing requirements (VCC = 5 V ± 0.5 V, VSS = 0V, Ta = –20 to 85 °C, unless otherwise noted) Max.Typ. RESET input tw(RESETL) A-D converter Comparator 256

1 VREF

Typ.

M37905F8CFP, M37905F8CSP PRELIMINAR Y Notice: This is not a final specification. Som e param etric lim its are subject to change. 16-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS tc(TA) tw(TAH) tw(TAL) f(fsys) ≤ 20 MHz f(fsys) ≤ 20 MHz f(fsys) ≤ 20 MHz PERIPHERAL DEVICE INPUT/OUTPUT TIMING (VCC = 5 V±0.5 V, VSS = 0 V, Ta = –20 to 85 °C, f(fsys) = 20 MHz unless otherwise noted) ∗ For limits depending on f(fsys), their calculation formulas are shown below. Also, the values at f(fsys) = 20 MHz are shown in ( ). Timer A input (Up-down input and Count input in event counter mode) tc(UP) tw(UPH) tw(UPL) tsu(UP-TIN) th(TIN-UP) Symbol TAiOUT input cycle time TAiOUT input high-level pulse width TAiOUT input low-level pulse width TAiOUT input setup time TAiOUT input hold time Parameter Limits Min. 2000 1000 1000 400 400 Max. ns ns ns ns ns Unit Timer A input (External trigger input in pulse width modulation mode) tw(TAH) tw(TAL) Symbol TAiIN input high-level pulse width TAiIN input low-level pulse width Parameter Min. Limits Max. ns ns Unit Limits Symbol Parameter Min. Max. Unit 8 × 109 f(fsys) (400)TAiIN input cycle time TAiIN input high-level pulse width TAiIN input low-level pulse width ns ns ns Timer A input (External trigger input in one-shot pulse mode) Limits Symbol Parameter Min. Max. Unit 16 × 109 f(fsys) 8 × 109 f(fsys) 8 × 109 f(fsys) (800) (400) (400) t c(TA) tw(TAH) tw(TAL) TAiIN input cycle time TAiIN input high-level pulse width TAiIN input low-level pulse width ns ns ns Timer A input (Gating input in timer mode) Note :The TAiIN input cycle time requires 4 or more cycles of a count source. The TAiIN input high-level pulse width and the TAiIN input low-level pulse width respectively require 2 or more cycles of a count source. The limits in this table are applied when the count source = f2 at f(fsys) ≤ 20 MHz. Timer A input (Count input in event counter mode) tc(TA) tw(TAH) tw(TAL) Symbol TAiIN input cycle time TAiIN input high-level pulse width TAiIN input low-level pulse width Parameter Min. Limits Max. ns ns ns Unit f(f sys) ≤ 20 MHz

M37905F8CFP, M37905F8CSP PRELIMINAR Y Notice: This is not a final specification. Som e param etric lim its are subject to change. 16-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS tc(TA) tsu(TAjIN-TAjOUT) tsu(TAjOUT-TAjIN) Symbol Parameter Min. 800 200 200 Limits Max. ns ns ns Unit Timer A input (Two-phase pulse input in event counter mode) TAjIN input cycle time TAjIN input setup time TAjOUT input setup time tc(TA) tw(TAH) tw(TAL) tc(UP) tw(UPH) tw(UPL) th(TIN-UP) tsu(UP-TIN) tsu(TAjIN-TAjOUT ) tsu(TAjOUT -TAjIN) tsu(TAjIN-TAjOUT ) tsu(TAjOUT -TAjIN) tc(TA)

• Gating input in timer mode
• Count input in event counter mode
• External trigger input in one-shot pulse mode
• External trigger input in pulse width modulation mode TAiIN input TAiOUT input (Up-down input) TAiOUT input (Up-down input)
• Up-down and Count input in event counter mode TAiIN input (When count by falling) TAiIN input (When count by rising) TAjIN input TAjOUT input
• Two-phase pulse input in event counter mode Test conditions
• VCC = 5 V ± 0.5 V, Ta = –20 to 85 °C
• Input timing voltage : VIL = 1.0 V, VIH = 4.0 V

M37905F8CFP, M37905F8CSP PRELIMINAR Y Notice: This is not a final specification. Som e param etric lim its are subject to change. 16-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS f(fsys) ≤ 20 MHz f(fsys) ≤ 20 MHz f(fsys) ≤ 20 MHz f(fsys) ≤ 20 MHz f(fsys) ≤ 20 MHz f(fsys) ≤ 20 MHz tc(TB) tw(TBH) tw(TBL) tc(TB) tw(TBH) tw(TBL) Timer B input (Count input in event counter mode) Symbol TBiIN input cycle time (one edge count) TBiIN input high-level pulse width (one edge count) TBiIN input low-level pulse width (one edge count) TBiIN input cycle time (both edge count) TBiIN input high-level pulse width (both edge count) TBiIN input low-level pulse width (both edge count) Parameter Limits Min. 160 Max. ns ns ns ns ns ns Unit Limits Symbol Parameter Min. Max. Unit 16 × 109 f(fsys) 8 × 109 f(fsys) 8 × 109 f(fsys) (800) (400) (400) t c(TB) tw(TBH) tw(TBL) TBiIN input cycle time TBiIN input high-level pulse width TBiIN input low-level pulse width ns ns ns Timer B input (Pulse period measurement mode) Note: The TBiIN input cycle time requires 4 or more cycles of a count source. The TBiIN input high-level pulse width and the TBiIN input low-level pulse width respectively require 2 or more cycles of a count source. The limits in this table are applied when the count source = f2 at f(fsys) ≤ 20 MHz. Limits Symbol Parameter Min. Max. Unit 16 × 109 f(fsys) 8 × 109 f(fsys) 8 × 109 f(fsys) (800) (400) (400) t c(TB) tw(TBH) tw(TBL) TBiIN input cycle time TBiIN input high-level pulse width TBiIN input low-level pulse width ns ns ns Timer B input (Pulse width measurement mode) Note: The TBiIN input cycle time requires 4 or more cycles of a count source. The TBiIN input high-level pulse width and the TBiIN input low-level pulse width respectively require 2 or more cycles of a count source. The limits in this table are applied when the count source = f2 at f(fsys) ≤ 20 MHz. tc(CK) tw(CKH) tw(CKL) td(C-Q) th(C-Q) tsu(D-C) th(C-D) Serial I/O Symbol CLK i input cycle time CLK i input high-level pulse width CLK i input low-level pulse width TXD i output delay time TXD i hold time R XD i input setup time R XD i input hold time Parameter Limits Min. 200 100 100 Max. ns ns ns ns ns ns ns Unit

M37905F8CFP, M37905F8CSP PRELIMINAR Y Notice: This is not a final specification. Som e param etric lim its are subject to change. 16-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS tw(INH) tw(INL) Symbol INTi input high-level pulse width INTi input low-level pulse width Parameter Min. 250 250 Limits Max. ns ns Unit External interrupt (INTi) input tc(TB) tw(TBH) tw(TBL) tsu(D-C) tc(CK) tw(CKH) tw(CKL) tw(INL) tw(INH) td(C-Q) th(C-D) th(C-Q) TBiIN input INTi input CLK i input TxD i output RxD i input Test conditions

• Vcc = 5 V ± 0.5 V, Ta = –20 to 85 °C
• Input timing voltage : VIL = 1.0 V, VIH = 4.0 V
• Output timing voltage : VOL = 0.8 V, VOH = 2.0 V, CL = 50 pF

M37905F8CFP, M37905F8CSP PRELIMINAR Y Notice: This is not a final specification. Som e param etric lim its are subject to change. 16-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS tc tw(half) tw(H) tw(L) tr tf Max. 0.55 tc Min. 0.45 tc 0.5 tc – 8 0.5 tc – 8 External clock input cycle time External clock input pulse width with half input-voltage External clock input high-level pulse width External clock input low-level pulse width External clock input rise time External clock input fall time Limits External clock input Symbol Parameter ns ns ns ns ns ns Unit External clock input tr tf tw(L) tw(H) tw(half) XIN tc Test conditions

• Vcc = 5 V ± 0.5 V, Ta = –20 to 85 °C
• Input timing voltage : VIL = 1.0 V, VIH = 4.0 V (tw(H), tw(L), tr, tf)
• Output timing voltage : 2.5 V (tc, tw(half)) Timing Requirements (VCC = 5 V±0.5 V , VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)

M37905F8CFP, M37905F8CSP PRELIMINAR Y Notice: This is not a final specification. Som e param etric lim its are subject to change. 16-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS PACKAGE OUTLINE QFP64-P-1414-0.80 1.11 Weight(g) JEDEC CodeEIAJ Package Code Lead Material Alloy 42 64P6N-A Plastic 64pin 14✕ 14mm body QFP Symbol Min Nom Max A b c D E H E L y Dimension in Millimeters H D A1 0.20.1 0.5 ––I2 1.3 ––M D 14.6 ––M E 14.6 10°0° 0.1 1.4 0.80.60.4 17.116.816.5 17.116.816.5 0.8 14.214.013.8 14.214.013.8 0.20.150.13 0.450.350.3 2.8 3.05 e e e E c H E 64 49 H D D M D M E A F A1 A2 L y Recommended Mount Pad Detail F x –– 0.2 b x M 64 33 321 E ce1 A2A1 bb1 b2e L A SEATING PLANE D SDIP64-P-750-1.78 Weight(g) – 7.9 JEDEC CodeEIAJ Package Code Lead Material Alloy 42/Cu Alloy 64P4B Plastic 64pin 750mil SDIP Symbol Min Nom Max A b c E D L Dimension in Millimeters A1 0.38 –– – 3.8 – 0.4 0.5 0.59 0.9 1.0 1.3 0.65 0.75 1.05 0.2 0.25 0.32 56.2 56.4 56.6 16.85 17.0 17.15 – 1.778 – – 19.05 – 2.8 –– 0° – 15° –– 5.08 e MMP

M37905F8CFP, M37905F8CSP PRELIMINAR Y Notice: This is not a final specification. Som e param etric lim its are subject to change. 16-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS Notes regarding these materials

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• Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for further details on these materials or the products contained therein. © 2001 MITSUBISHI ELECTRIC CORP. New publication, effective May., 2001. Specifications subject to change without notice. Keep safety first in your circuit designs!
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REVISION HISTORY M37905F8CFP, M37905F8CSP DATASHEET Rev. Date Description Page Summary (1/1) 1.0 5/28/01 — First Edition