M37902FCCHP

M37902FGCGP MITSUBISHI | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 143

Technical content

M37902FCCHP, M37902FGCHP, M37902FJCHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS

DESCRIPTION

These are single-chip microcomputers designed with high-perfor- mance CMOS silicon gate technology, including the internal flash memory. These microcomputers support the 7900 Series instruction set, which are enhanced and expanded instruction set and are up- per-compatible with the 7700/7751 Series instruction set. The CPU of these microcomputers is a 16-bit parallel processor that can also be switched to perform 8-bit parallel processing. Also, the bus interface unit of these microcomputers enhances the memory access efficiency to execute instructions fast. Therefore, these mi- crocomputers are suitable for office, business, and industrial equip- ment controller that require high-speed processing of large data. For the internal flash memory, single-power-supply programming and erasure, using a PROM programmer or the control by the cen- tral processing unit (CPU), is supported. Also, each of these micro- computers has the memory area dedicated for storing a certain software which controls programming and erasure (reprogramming control software). Therefore, on these microcomputers, the program can easily be changed even after they are mounted on the board. DISTINCTIVE FEATURES <Microcomputer mode>

• Memory [M37902FCCHP] [M37902FGCHP] [M37902FJCHP] [All of the above computers]
• Instruction execution time
• Real-time output ....4 bits × 2 channels, or 6 bits × 1 channel + 2 bits × 1 channel
• 12-bit watchdog timer <Flash memory mode> (Data protection per block is enabled.)
• Programming/Erase control by software command APPLICATION Control devices for personal computer peripheral equipment such as CD-ROM drives, DVD-ROM drives, hard disk drives, high density FDD, printers

M37902FCCHP, M37902FGCHP, M37902FJCHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS M37902FxCHP PIN CONFIGURATION (TOP VIEW) Outline 100P6Q-A P64/INT2 ↔ P63/INT1 ↔ P62/INT0 ↔ P61/TA4IN ↔ P60/TA4OUT ↔ P55/TA2IN/RTP11/KI1 ↔ P54/TA2OUT /RTP10/KI0 ↔ P53/TA1IN/RTP03 ↔ P52/TA1OUT /RTP02 ↔ P51/TA0IN/RTP01 ↔ P50/TA0OUT /RTP00 ↔ P47/CS3 ↔ P46/CS2 ↔ P45/CS1 ↔ P44/CS0 ↔ P43/HOLD ↔ P40/ALE ↔ 100 P42/HLDA ↔ P41/φ1 ↔ P65/TB0IN ↔ P66/TB1IN ↔ P67/TB2IN ↔ P70/AN0 ↔ ↔ P30/RDY ↔ P31/RD ↔ P32/BLW ↔ P33/BHW ← BYTE VCONT ← RESET ← MD0 VSS ↔ P25/D13 ↔ P24/D12 ↔ P26/D14 ← XIN → XOUT VCC ↔ P27/D15 ↔ P23/D11 ↔ P22/D10 ↔ P21/D9 ↔ P20/D8 ↔ P17/D7/LA7 ↔ P16/D6/LA6 ↔ P15/D5/LA5 ↔ P10/D0/LA0 ↔ P11/D1/LA1 ↔ P12/D2/LA2 VSS ↔ P105/A5 ↔ P104/A4 ↔ P107/A7 ↔ P106/A6 ↔ P110/A8 ↔ P112/A10 ↔ P111/A9 ↔ P113/A11 ↔ P115/A13 ↔ P114/A12 ↔ P116/A14 ↔ P00/A16 ↔ P117/A15 ↔ P01/A17 ↔ P02/A18 ↔ P04/A20 ↔ P03/A19 ↔ P05/A21 ↔ P07/A23 ← MD1 ↔ P06/A22 ↔ P14/D4/LA4 ↔ P13/D3/LA3 P100/A0 ↔ P87/TXD 1 ↔ P86/RXD 1 ↔ P85/CTS1/CLK1 ↔ P84/CTS1/RTS1/INT4 ↔ P83/TXD 0 ↔ P103/A3 ↔ P102/A2 ↔ P101/A1 ↔ P82/RXD 0 ↔ VCC AV CC VREF → AV SS VSS P77/AN7/ADTRG /DA1/(INT2) ↔ P76/AN6/DA0 ↔ P75/AN5/(INT4) ↔ P74/AN4/(INT3) ↔ P73/AN3 ↔ P72/AN2 ↔ P71/AN1 ↔ P80/CTS0/RTS0/DA2/INT3 ↔ NMI → P81/CTS0/CLK0 ↔ M37902FCCHP M37902FGCHP M37902FJCHP P57/TA3IN/RTP13/KI3 ↔ P56/TA3OUT /RTP12/KI2 ↔

M37902FCCHP, M37902FGCHP, M37902FJCHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS BLOCK DIAGRAM Data bank Register DT (8) Program Counter PC (16) Incrementer/Decrementer (24) Program Bank Register PG (8) Input Buffer Register IB (16) Direct Page Register DPR0 (16) Stack Pointer S (16) Index Register Y (16) Index Register X (16) Arithmetic Logic Unit (16) Accumulator B (16) Accumulator A (16) Instruction register (8) Central Processing Unit (CPU) Incrementer (24) Program Address Register PA (24) Data Address Register DA (24) Bus Interface Unit(BIU) RESET MD1 Reference voltage input V REF (0V)AV SS AVcc Vcc External data bus width select input BYTE Clock Generating Circuit Clock input X IN V CONT X OUT Data Buffer DQ0 (8) Instruction Queue Buffer Q0 (8) Data Bus (Odd) Address Bus A-D converter (10) UART1 (9)UART0 (9) Watchdog timerTimer TB1 (16)Timer TB2 (16)Timer TB0 (16) D-A 1 converter (8) D-A 2 converter (8) Timer TA1 (16)Timer TA2 (16)Timer TA3 (16)Timer TA4 (16)Timer TA0 (16) RAM(Note) P8(8) Input/Output port P8 P7(8) Input/Output port P7 Input/Output port P4P4(8) P10(8) Input/Output port P10 P6(8) Input/Output port P6 P5(8) Input/Output port P5 P11(8) Input/Output port P11 P1(8) Input/Output port P1 P2(8) Input/Output port P2 P3(4) Input/Output port P3 P0(8) Input/Output port P0 MD0 (0V)Vss Processor Status Register PS (11) NMI Flash memory (Note) D-A 0 converter (8) Data Bus (Even) Data Buffer DQ1 (8) Data Buffer DQ2 (8) Data Buffer DQ3 (8) Instruction Queue Buffer Q1 (8) Instruction Queue Buffer Q2 (8) Instruction Queue Buffer Q3 (8) Instruction Queue Buffer Q4 (8) Instruction Queue Buffer Q5 (8) Instruction Queue Buffer Q6 (8) Instruction Queue Buffer Q7 (8) Instruction Queue Buffer Q8 (8) Instruction Queue Buffer Q9 (8) Direct Page Register DPR1 (16) Direct Page Register DPR2 (16) Direct Page Register DPR3 (16) Clock output Reset input Note: Flash memory RAM M37902FCCHP

120 Kbytes 4096 bytes

248 Kbytes 6144 bytes

498 Kbytes 12288 bytes

M37902FCCHP, M37902FGCHP, M37902FJCHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS 203 38 ns (the fastest instruction at f(fsys) = 26 MHz) 26 MHz (Max.) 26 MHz (Max.) (Note) (Note)

16 Kbytes

8-bit ✕ 10 4-bit ✕ 1 16-bit ✕ 5 16-bit ✕ 3 (UART or Clock synchronous serial I/O) ✕ 2 10-bit successive approximation method ✕ 1 (8 channels) 8-bit ✕ 3 12-bit ✕ 1 Chip select area ✕ 4 (CS 0–CS 3). A bus cycle type and bus width can be set for each chip select area. 4 bits ✕ 2 channels; or 6 bits ✕ 1 channel + 2 bits ✕ 1 channel 5 external types, 13 internal types. Each interrupt can be set to a priority level within the range of 0–7 by software. 1 external type, 3 internal types. Built-in (externally connected to a ceramic resonator or quartz crystal resonator). The following multiplication methods are available: double, triple, and quadruple. 5 V±0.5 V 150 mW (at f(f sys) = 26 MHz, Typ., PLL frequency multiplier stopped) 5 V 5 mA Up to 16 Mbytes. Note that bank FF 16 is a reserved area. –20 to 85 °C CMOS high-performance silicon gate process 100-pin plastic molded QFP FUNCTIONS (Microcomputer mode) FunctionsParameter Number of basic machine instructions Instruction execution time External clock input frequency f(X IN) System clock frequency f(fsys) Memory size Programmable input/output ports Multi-functional timers Serial I/O A-D converter D-A converter Watchdog timer Chip-select wait control Real-time output Interrupts Clock generating circuit PLL frequency multiplier Input/Output withstand voltage Output current Flash memory (User ROM area) RAM Flash memory (Boot ROM area) P0–P2, P4–P8, P10, P11 TA0–TA4 TB0 –TB2 UART0 and UART1 Power supply voltage Power dissipation Ports’ input/output characteristics Memory expansion Operating ambient temperature range Device structure Package Maskable interrups Non-maskable interrups Flash memory M37902FCCHP 120 Kbytes (User ROM area) M37902FGCHP 248 Kbytes M37902FJCHP 498 Kbytes RAM M37902FCCHP 4096 bytes M37902FGCHP 6144 bytes M37902FJCHP 12288 bytes Note:

M37902FCCHP, M37902FGCHP, M37902FJCHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS User ROM area Boot ROM area Flash memory parallel I/O mode Flash memory serial I/O mode Flash memory CPU reprogramming mode Flash memory parallel I/O mode Flash memory serial I/O mode Flash memory CPU reprogramming mode Power supply voltage Programming/Erase voltage Flash memory mode Block division for erasure Programming method Erase method Programming/Erase control Data protection method Number of commands Maximum number of reprograms 5 V±0.5 V (in the flash memory parallel I/O mode, 3.3 V±0.3 V) 5 V±0.5 V (in the flash memory parallel I/O mode, 3.3 V±0.3 V) 3 modes: parallel I/O, serial I/O, and CPU reprogramming modes (Note 1) 1 block (16 Kbytes ✕ 1) (Note 2) Programmed per page (in a unit of 256 Kbytes) User ROM area + Boot ROM area User ROM area User ROM area Total erase/Block erase User ROM area + Boot ROM area User ROM area User ROM area Programming/Erase control by software commands Protected per block, by using a lock bit. 8 commands 100 FUNCTIONS (Flash memory mode) FunctionsParameter 2: On shipment, our reprogramming control firmware for the flash memory serial I/O mode has been stored into the boot ROM area. Note that the boot ROM area can be erased/programmed only in the flash memory parallel I/O mode. User ROM area M37902FCCHP 5 blocks (8 Kbytes ✕ 3, 32 Kbytes ✕ 1, 64 Kbytes ✕ 1), total 120 Kbytes M37902FGCHP 7 blocks (8 Kbytes ✕ 3, 32 Kbytes ✕ 1, 64 Kbytes ✕ 3), total 248 Kbytes M37902FJCHP 11 blocks (2 Kbytes ✕ 1, 8 Kbytes ✕ 2, 32 Kbytes ✕ 1, 64 Kbytes ✕ 7), total 498 Kbytes Notes 1:

M37902FCCHP, M37902FGCHP, M37902FJCHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS Vcc, Vss MD0 MD1 RESET X IN XOUT BYTE VCONT AVcc, AVss VREF P00–P07 P10–P17 P20–P27 P30–P33 P40–P47 Power supply input MD0 MD1 Reset input Clock input Clock output External data bus width select input Filter circuit connection Analog power supply input Reference voltage input I/O port P0 I/O port P1 I/O port P2 I/O port P3 I/O port P4 Input Input Input Input Output Input Input I/O I/O I/O I/O I/O Apply 5 V±0.5 V to Vcc, and 0 V to Vss. This pin controls the processor mode. Connect this pin to V SS for the single-chip mode or memory expansion mode, and VCC for the microprocessor mode. Connect this pin to Vss. The microcomputer is reset when “L” level is applied to this pin. These are input and output pins of the internal clock generating circuit. Connect a ceramic or quartz- crystal resonator between the X IN and XOUT pins. When an external clock is used, the clock source should be connected to the XIN pin, and the XOUT pin should be left open. This pin determines whether the external data bus has an 8-bit width or 16-bit width for the memory expansion mode or microprocessor mode. The width is 16 bits when “L” signal is input, and 8 bits when “H ” signal is input. When BYTE = Vss level, by the register setting, the external data bus for each of areas CS 1 to CS3 can have a width of 8 bits. When using the PLL frequency multiplier, connect this pin to the filter circuit. When not using, this pin should be left open. Power supply input pins for the A-D converter and the D-A converter. Connect AVcc to Vcc, and AVss to Vss externally. This is the reference voltage input pin for the A-D converter and the D-A converter. I In single-chip mode Port P0 is an 8-bit I/O port. This port has an I/O direction register, and each pin can be programmed for input or output. These pins enter the input mode at reset. I In memory expansion and microprocessor modes Address (A 16–A23) is output. These pins also function as I/O port pins according to the register setting. I In single-chip mode These pins have the same functions as port P0. I In memory expansion and microprocessor modes The low-order 8 bits of data (D0–D 7) are input/output. When the external data bus has an 8-bit width, address (LA0–LA7) output and data (D0–D 7) input/output can be performed with the time-sharing method, according to the register setting. I In single-chip mode or When 8-bit external data bus is used in memory expansion mode and microprocessor mode These pins have the same functions as port P0. I When the 16-bit external data bus is used in memory expansion or microproce- ssor mode The high-order 8 bits of data (D 8–D 15) are input or output. I In single-chip mode These pins have the same functions as port P0. I In memory expansion mode P30 functions as an I/O port pin; and P31, P32, and P33 function as the output pins of RD, BLW, BHW, respectively. P30 also functions as an output pin of RDY according to the register setting. When the external data bus has a width of 8 bits, the BHW pin functions as an I/O port pin (P3 3). I In microprocessor mode P30 functions as an input pin of RDY; and P31,P32, P33 function as the output pins of RD, BLW, BHW, respectively. P30 also functions as an I/O port pin accord- ing to the register setting. When the external data bus has a width of 8 bits, the BHW pin functions as an I/O port pin (P3 3). I In single-chip mode These pins have the same functions as port P0. I In memory expansion mode P40–P47 function as I/O port pins. According to the register setting, these pins function as output pins or input pins of ALE, φ1, HLDA, HOLD, CS0–CS 3, respec- tively. I In microprocessor mode P40–P44 function as output or input pins of ALE, φ1, HLDA, HOLD, CS0, and P45–P47 as I/O port pins, respectively. According to the register setting, P40–P43 also function as I/O port pins, and P45–P47 as output pins of CS1–CS 3. PIN DESCRIPTION (MICROCOMPUTER MODE) FunctionsInput/ OutputNamePin

M37902FCCHP, M37902FGCHP, M37902FJCHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS I/O I/O I/O I/O I/O I/O Input FunctionsInput/ OutputNamePin P50–P57 P60–P67 P70–P77 P80–P87 P100–P107 P110–P117 NMI In addition to having the same functions as port P0 in the single-chip mode, these pins also function as I/O pins for timers A0–A3, output pins for the real-time output, and input pins for the key-input interrupt. In addition to having the same functions as port P0 in the single-chip mode, these pins also function as I/O pins for timer A4, input pins for external interrupt inputs____ ____ INT0–INT2, and input pins for timers B0–B2. In addition to having the same functions as port P0 in the single-chip mode, these pins also function as input pins for the A-D converter, output pins for the D-A converter, and input pins for INT 2, INT3, and INT4. In addition to having the same functions as port P0 in the single-chip mode, these pins also function as I/O pins for UART0, UART1, output pins for D-A converter, and input pins for INT 3 and INT4. I In single-chip mode These pins have the same functions as port P0. I In memory expansion and microprocessor modes Address (A0–A7) is output. I In single-chip mode These pins have the same functions as port P0. I In memory expansion and microprocessor modes Address (A8–A15) is output. Also, these pins function as I/O port pins according to the register setting. This pin is for a non-maskable interrupt. I/O port P5 I/O port P6 I/O port P7 I/O port P8 I/O port P10 I/O port P11 Non-maskable interrupt

M37902FCCHP, M37902FGCHP, M37902FJCHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS PIN DESCRIPTION (FLASH MEMORY SERIAL I/O MODE) VCC , VSS MD0 MD1 RESET X IN XOUT BYTE V CONT AVcc, AVss V REF P00–P07 P10–P17 P20–P27 P30–P33 P40, P44– P47 P41 P42 P43 P50–P57 P60–P67 P70–P77 P80–P87 P100–P107 P110–P117 NMI Pin Power supply input MD0 MD1 Reset input Clock input Clock output BYTE Filter circuit connection Analog supply input Reference voltage input Input port P0 Input port P1 Input port P2 Input port P3 Input port P4 SCLK input SDA I/O BUSY output Input port P5 Input port P6 Input port P7 Input port P8 Input port P10 Input port P11 Non-maskable interrupt Name Input Input Input Input Output Input Input Input Input Input Input Input Input I/O Output Input Input Input Input Input Input Input Input /Output Functions Apply 5 V ± 0.5 V to Vcc, and 0 V to Vss. Connect this pin to Vss. Connect this pin to Vss via a resistor of 10 kΩ to 100 kΩ . The reset input pin. Connect a ceramic resonator between the X IN and XOUT pins, or input an external clock from the XIN pin with the XOUT pin left open. Connect this pin to Vcc or Vss. (This is not used in the flash memory serial I/O mode.) Connect this pin to the filter circuit, or leave this pin open. (This is not used in the flash memory serial I/O mode.) Connect AVcc to Vcc, and AVss to Vss. Input an arbitrary level within the range of VSS –VCC . (This is not used in the flash memory serial I/O mode.) Input “H ” or “L”, or leave them open. (This is not used in the flash memory serial I/O mode.) Input “H ” or “L”, or leave them open. (This is not used in the flash memory serial I/O mode.) Input “H ” or “L”, or leave them open. (This is not used in the flash memory serial I/O mode.) Input “H ” or “L”, or leave them open. (This is not used in the flash memory serial I/O mode.) Input “H ” or “L”, or leave them open. (This is not used in the flash memory serial I/O mode.) This is an input pin for a serial clock. This is an I/O pin for serial data. Connect this pin to VCC via a resistor (about 1 kΩ ). This is an output pin for the BUSY signal. Input “H ” or “L”, or leave them open. (This is not used in the flash memory serial I/O mode.) Input “H ” or “L”, or leave them open. (This is not used in the flash memory serial I/O mode.) Input “H ” or “L”, or leave them open. (This is not used in the flash memory serial I/O mode.) Input “H ” or “L”, or leave them open. (This is not used in the flash memory serial I/O mode.) Input “H ” or “L”, or leave them open. (This is not used in the flash memory serial I/O mode.) Input “H ” or “L”, or leave them open. (This is not used in the flash memory serial I/O mode.) Input “H ”, or leave this pin open.

M37902FCCHP, M37902FGCHP, M37902FJCHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS BASIC FUNCTION BLOCKS These microcomputers contain the following devices on the single chip: the flash memory, RAM, CPU, bus interface unit, and periph- eral devices such as the interrupt control circuit, timers, serial I/O, A-D converter, D-A converter, I/O ports, clock generating circuit, etc. MEMORY Figures 1 to 3 show the memory maps. The address space is 16 Mbytes from addresses 0 16 to FFFFFF16. The address space is di- vided into 64-Kbyte units called banks. The banks are numbered from 0 16 to FF16. Bank FF16 is a reserved area for the development support tool. Therefore, do not use bank FF16. Internal flash memory and internal RAM are assigned as shown in Figures 1 to 3. Addresses FFC0 16 to FFFF16 contain the RESET and the interrupt vector addresses, and the interrupt vectors are stored there. For details, refer to the section on interrupts. Assigned to addresses 0 16 to FF16 are peripheral devices such as I/O ports, A-D converter, D-A converter, UART, timers, interrupt con- trol registers, etc. Figures 7 and 8 show the location of SFRs. For the flash memory in the boot ROM area, refer to the section on the flash memory mode. Fig. 1 Memory map of M37902FCCHP (Single-chip mode) /;/; /;/; /;/; INT4 A-D conversion Reserved area Reserved area Address matching detect Reserved area Reserved area Reserved area Reserved area Reserved area UART1 transmit UART1 receive UART0 transmit UART0 receive Timer B2 Timer B1 Timer B0 Interrupt vector table Timer A4 Timer A3 Timer A2 Timer A1 Timer A0 Watchdog timer BRK instruction Zero divide INT3 INT2 INT1 INT0 NMI RESET DBC 00000016 Bank 016 FFFFFF 16 FE0000 16 00FFFF 16 01000016 01FFFF 16 Bank FE16 00000016 00080016 0000FF16 00FFFE 16 00FFC0 16 Internal RAM 4096 bytes Internal flash memory

120 Kbytes

(User ROM area) Peripheral devices control registers 001FFF 16 00200016 FEFFFF 16 FF000016 0017FF16 00180016 00FFFF 16 00FFC0 16 Bank 116 Bank FF Reserved area for development support tool

M37902FCCHP, M37902FGCHP, M37902FJCHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS Fig. 3 Memory map of M37902FJCHP (Single-chip mode) /;/; /;/; /;/; Reserved area for development support tool INT4 A-D conversion Reserved area Reserved area Address matching detect Reserved area Reserved area Reserved area Reserved area Reserved area UART1 transmit UART1 receive UART0 transmit UART0 receive Timer B2 Timer B1 Timer B0 Interrupt vector table Timer A4 Timer A3 Timer A2 Timer A1 Timer A0 Watchdog timer BRK instruction Zero divide INT3 INT2 INT1 INT0 NMI RESET DBC 00000016 Bank 016 FFFFFF 16 FE0000 16 00FFFF 16 02000016 02FFFF 16 Bank FE16 00000016 00080016 0000FF16 00FFFE 16 00FFC0 16 Internal RAM 12288 bytes Internal flash memory

498 Kbytes

(User ROM area) Peripheral devices control registers 0037FF16 00380016 FEFFFF 16 FF000016 00FFFF 16 00FFC0 16 Bank 216 01000016 01FFFF 16 Bank 116 03000016 Bank 316 03FFFF 16 05000016 05FFFF 16 Bank 516 04000016 04FFFF 16 Bank 416 06000016 Bank 616 06FFFF 16 07000016 07FFFF 16 Bank 716 Bank FF16 Fig. 2 Memory map of M37902FGCHP (Single-chip mode) /;/; /;/; /;/; INT4 A-D conversion Reserved area Reserved area Address matching detect Reserved area Reserved area Reserved area Reserved area Reserved area UART1 transmit UART1 receive UART0 transmit UART0 receive Timer B2 Timer B1 Timer B0 Interrupt vector table Timer A4 Timer A3 Timer A2 Timer A1 Timer A0 Watchdog timer BRK instruction Zero divide INT3 INT2 INT1 INT0 NMI RESET DBC 00000016 Bank 016 FFFFFF 16 FE0000 16 00FFFF 16 01000016 01FFFF 16 Bank FE16 00000016 00080016 0000FF16 00FFFE 16 00FFC0 16 Internal RAM 6144 bytes Internal flash memory

248 Kbytes

(User ROM area) Peripheral devices control registers 001FFF 16 00200016 FEFFFF 16 FF000016 00FFFF 16 00FFC0 16 Bank 116 Bank FF 02000016 02FFFF 16 Bank 216 03000016 03FFFF 16 Bank 316 Reserved area for development support tool

M37902FCCHP, M37902FGCHP, M37902FJCHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS Fig. 7 Location of SFRs (1) 00000016 00000116 00000216 00000316 00000416 00000516 00000616 00000716 00000816 00000916 00000A16 00000B16 00000C 16 00000D 16 00000E16 00000F16 00001016 00001116 00001216 00001316 00001416 00001516 00001616 00001716 00001816 00001916 00001A16 00001B16 00001C 16 00001D 16 00001E16 00001F16 00002016 00002116 00002216 00002316 00002416 00002516 00002616 00002716 00002816 00002916 00002A16 00002B16 00002C 16 00002D 16 00002E16 00002F16 00003016 00003116 00003216 00003316 00003416 00003516 00003616 00003716 00003816 00003916 00003A16 00003B16 00003C 16 00003D 16 00003E16 00003F16 Port P2 register Port P3 register Port P1 direction register Port P0 direction register Port P1 register Port P0 register Port P2 direction register Port P3 direction register Port P4 register Port P5 register Port P4 direction register Port P5 direction register Port P6 register Port P7 register Port P6 direction register Port P7 direction register Port P8 register Port P8 direction register Port P10 register Port P11 register Port P10 direction register Port P11 direction register A-D control register 0 A-D control register 1 A-D register 0 A-D register 1 A-D register 2 A-D register 3 A-D register 4 A-D register 5 A-D register 6 A-D register 7 UART0 transmit/receive mode register UART0 baud rate register (BRG0) UART0 transmit buffer register UART0 transmit/receive control register 1 UART0 receive buffer register UART1 transmit/receive mode register UART1 baud rate register (BRG1) UART1 transmit buffer register UART1 transmit/receive control register 0 UART1 transmit/receive control register 1 UART1 receive buffer register Address (Hexadecimal notation) 000040 00004116 00004216 00004316 00004416 00004516 00004616 00004716 00004816 00004916 00004A16 00004B16 00004C 16 00004D 16 00004E16 00004F16 00005016 00005116 00005216 00005316 00005416 00005516 00005616 00005716 00005816 00005916 00005A16 00005B16 00005C 16 00005D 16 00005E16 00005F16 00006016 00006116 00006216 00006316 00006416 00006516 00006616 00006716 00006816 00006916 00006A16 00006B16 00006C 16 00006D 16 00006E16 00006F16 00007016 00007116 00007216 00007316 00007416 00007516 00007616 00007716 00007816 00007916 00007A16 00007B16 00007C 16 00007D 16 00007E16 00007F16 Address (Hexadecimal notation) Count start register One-shot start register Timer A clock division select register Timer A0 register Timer A1 register Timer A2 register Timer A3 register Timer A4 register Timer B0 register Timer B1 register Timer B2 register Timer A1 mode register Timer A0 mode register Timer A2 mode register Timer A3 mode register Timer A4 mode register Timer B0 mode register Timer B1 mode register Timer B2 mode register Processor mode register 1 Watchdog timer register Particular function select register 0 Particular function select register 1 Debug control register 0 INT 3 interrupt control register UART0 transmit interrupt control register UART1 receive interrupt control register Timer A0 interrupt control register Timer A1 interrupt control register Timer A3 interrupt control register Timer A4 interrupt control register Timer B0 interrupt control register Timer B2 interrupt control register INT 1 interrupt control register Watchdog timer frequency select register Debug control register 1 INT4 interrupt control register UART1 transmit interrupt control register Timer A2 interrupt control register Timer B1 interrupt control register INT 2 interrupt control register Address comparison register 0 Address comparison register 1 Particular function select register 2 Reserved area (Note) Note: Do not write to this address. UART0 transmit/receive control register 0 Up-down register Processor mode register 0 A-D conversion interrupt control register UART0 receive interrupt control register INT0 interrupt control register Reserved area (Note) Reserved area (Note)

M37902FCCHP, M37902FGCHP, M37902FJCHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS Fig. 8 Location of SFRs (2) 0000C0 16 0000C1 16 0000C2 16 0000C3 16 0000C4 16 0000C5 16 0000C6 16 0000C7 16 0000C8 16 0000C9 16 0000CA 16 0000CB 16 0000CC 16 0000CD 16 0000CE 16 0000CF 16 0000D0 16 0000D1 16 0000D2 16 0000D3 16 0000D4 16 0000D5 16 0000D6 16 0000D7 16 0000D8 16 0000D9 16 0000DA 16 0000DB 16 0000DC 16 0000DD 16 0000DE 16 0000DF 16 0000E016 0000E116 0000E216 0000E316 0000E416 0000E516 0000E616 0000E716 0000E816 0000E916 0000EA 16 0000EB 16 0000EC 16 0000ED 16 0000EE 16 0000EF 16 0000F016 0000F116 0000F216 0000F316 0000F416 0000F516 0000F616 0000F716 0000F816 0000F916 0000FA 16 0000FB 16 0000FC 16 0000FD 16 0000FE 16 0000FF16 0000A016 0000A116 0000A216 0000A316 0000A416 0000A516 0000A616 0000A716 0000A816 0000A916 0000AA 16 0000AB 16 0000AC 16 0000AD 16 0000AE 16 0000AF 16 0000B016 0000B116 0000B216 0000B316 0000B416 0000B516 0000B616 0000B716 0000B816 0000B916 0000BA 16 0000BB 16 0000BC 16 0000BD 16 0000BE 16 0000BF 16 Real-time output control register Pulse output data register 0 Pulse output data register 1 Serial I/O pin control register 000080 00008116 00008216 00008316 00008416 00008516 00008616 00008716 00008816 00008916 00008A16 00008B16 00008C 16 00008D 16 00008E16 00008F16 00009016 00009116 00009216 00009316 00009416 00009516 00009616 00009716 00009816 00009916 00009A16 00009B16 00009C 16 00009D 16 00009E16 00009F16 Address (Hexadecimal notation) CS 0 control register L CS 0 control register H CS 1 control register L CS 1 control register H CS 2 control register L CS 2 control register H CS 3 control register L CS 3 control register H Area CS 0 start address register Area CS 1 start address register Area CS 2 start address register Area CS 3 start address register Reserved area (Note) Reserved area (Note) Port function control register External interrupt input control register External interrupt input read-out register D-A control register D-A register 0 D-A register 1 D-A register 2 Flash memory control register Note: Do not write to this address. Clock control register Reserved area (Note) Reserved area (Note) Reserved area (Note) Address (Hexadecimal notation) Reserved area (Note) Reserved area (Note)

M37902FCCHP, M37902FGCHP, M37902FJCHP MITSUBISHI MICROCOMPUTERS SHINGLE-CHIP 16-BIT CMOS MICROCOMPUTER CENTRAL PROCESSING UNIT (CPU) The CPU has 13 registers and is shown in Figure 9. Each of these registers is described below. ACCUMULATOR A (A) Accumulator A is the main register of the microcomputer. It consists of 16 bits and the low-order 8 bits can be used separately. Data length flag m determines whether the register is used as 16-bit reg- ister or as 8-bit register. It is used as a 16-bit register when flag m is “0” and as an 8-bit register when flag m is “1”. Flag m is a part of the processor status register (PS) which is described later. Data operations such as calculations, data transfer, input/output, etc., are executed mainly through accumulator A. ACCUMULATOR B (B) Accumulator B has the same functions as accumulator A, but the use of accumulator B requires more instruction bytes and execution cycles than accumulator A. ACCUMULATOR E Accumulator E is a 32-bit register and consists of accumulator A (low-order 16 bits) and accumulator B (high-order 16 bits). It is used for 32-bit data processing. INDEX REGISTER X (X) Index register X consists of 16 bits and the low-order 8 bits can be used separately. Index register length flag x determines whether the register is used as 16-bit register or as 8-bit register. It is used as a 16-bit register when flag x is “0” and as an 8-bit register when flag x is “1”. Flag x is a part of the processor status register (PS) which is described later. In index addressing modes in which register X is used as the index register, the contents of this address are added to obtain the real ad- dress. Index register X functions as a pointer register which indicates an address of data table in instructions MVP , MVN, RMPA (Repeat MultiPly and Accumulate). INDEX REGISTER Y (Y) Index register Y consists of 16 bits and the low-order 8 bits can be used separately. The index register length flag x determines whether the register is used as 16-bit register or as 8-bit register. It is used as a 16-bit register when flag x is “0” and as an 8-bit register when flag x is “1”. Flag x is a part of the processor status register (PS) which is described later. In index addressing modes in which register Y is used as the index register, the contents of this address are added to obtain the real ad- dress. Index register Y functions as a pointer register which indicates an address of data table in instructions MVP , MVN, RMPA (Repeat MultiPly and Accumulate). 1 570 1 570 15 7 0 1 570 15 0 15 0 15 0 15 7 0 00000 IPL2 IPL1 IPL0 NVmxD I ZC DPR0 to DPR3 PC S YH YL XH XL BH BL AH AL Accumulator AAccumulator B Index register X Index register Y Stack pointer S Program counter PC Direct page registers DPR0 to DPR3 Processor status register PS Carry flag Zero flag Interrupt disable flag Decimal mode flag Index register length flag Data length flag Overflow flag Negative flag Processor interrupt priority level IPL PG Program bank register PG Data bank register DTDT 15 7 0 15 7 0 AH ALBH BL Accumulator E 31 0 Fig. 9 Register structure

M37902FCCHP, M37902FGCHP, M37902FJCHP MITSUBISHI MICROCOMPUTERS SHINGLE-CHIP 16-BIT CMOS MICROCOMPUTER STACK POINTER (S) Stack pointer (S) is a 16-bit register. It is used during a subroutine call or interrupts. It is also used during stack, stack pointer relative, or stack pointer relative indirect indexed Y addressing mode. PROGRAM COUNTER (PC) Program counter (PC) is a 16-bit counter that indicates the low-order 16 bits of the next program memory address to be executed. There is a bus interface unit between the program memory and the CPU, so that the program memory is accessed through bus interface unit. This is described later. PROGRAM BANK REGISTER (PG) Program bank register is an 8-bit register that indicates the high-or- der 8 bits of the next program memory address to be executed. When a carry occurs by incrementing the contents of the program counter, the contents of the program bank register (PG) is increased by 1. Also, when a carry or borrow occurs after adding or subtracting the offset value to or from the contents of the program counter (PC) using the branch instruction, the contents of the program bank regis- ter (PG) is increased or decreased by 1, so that programs can be written without worrying about bank boundaries. DATA BANK REGISTER (DT) Data bank register (DT) is an 8-bit register. With some addressing modes, the data bank register (DT) is used to specify a part of the memory address. The contents of data bank register (DT) is used as the high-order 8 bits of a 24-bit address. Addressing modes that use the data bank register (DT) are direct indirect, direct indexed X indi- rect, direct indirect indexed Y , absolute, absolute bit, absolute in- dexed X, absolute indexed Y, absolute bit relative, and stack pointer relative indirect indexed Y. DIRECT PAGE REGISTERS 0 to 3 (DPR0 to DPR3) The direct page register is a 16-bit register. An addressing mode of which name includes ‘direct’ generates an address of data to be ac- cessed, regarding the contents of this register as the base address. The 7900 Series has been expanded direct page registers up to 4 (DPR0 to DPR3), in comparison to the 7700 Series which has the single direct page register. Accordingly, the 7900 Series’s direct ad- dressing method which uses direct page registers differs from that of the 7700 Series. However, the conventional direct addressing method, using only DPR0, is still be selectable, in order to make use of the 7700 Series software property. For more details, refer to the section on the direct page. PROCESSOR STATUS REGISTER (PS) Processor status register (PS) is an 11-bit register. It consists of flags to indicate the result of operation and CPU interrupt levels. Branch operations can be performed by testing the flags C, Z, V, and The details of each bit of the processor status register are described below. 1. Carry flag (C) The carry flag contains the carry or borrow generated by the ALU af- ter an arithmetic operation. This flag is also affected by shift and ro- tate instructions. This flag can be set and reset directly with the SEC and CLC instructions or with the SEP and CLP instructions. 2. Zero flag (Z) The zero flag is set if the result of an arithmetic operation or data transfer is zero and reset if it is not. This flag can be set and reset directly with the SEP and CLP instructions. 3. Interrupt disable flag (I) When the interrupt disable flag is set to “1”, all interrupts except ___ watchdog timer, NMI, and software interrupt are disabled. This flag is set to “1” automatically when an interrupt is accepted. It can be set and reset directly with the SEI and CLI instructions or SEP and CLP instructions. 4. Decimal mode flag (D) The decimal mode flag determines whether addition and subtraction are performed as binary or decimal. Binary arithmetic is performed when this flag is “0”. If it is “1”, decimal arithmetic is performed with each word treated as 2- or 4- digit decimal. Arithmetic operation is performed using four digits when data length flag m is “0” and with two digits when it is “1”. Decimal adjust is automatically performed. (Decimal operation is possible only with the ADC and SBC instruc- tions.) This flag can be set and reset with the SEP and CLP instruc- tions.

M37902FCCHP, M37902FGCHP, M37902FJCHP MITSUBISHI MICROCOMPUTERS SHINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 5. Index register length flag (x) The index register length flag determines whether index register X and index register Y are used as 16-bit registers or as 8-bit registers. The registers are used as 16-bit registers when flag x is “0” and as 8- bit registers when it is “1”. This flag can be set and reset with the SEP and CLP instructions. 6. Data length flag (m) The data length flag determines whether the data length is 16-bit or 8-bit. The data length is 16 bits when flag m is “0” and 8 bits when it is “1”. This flag can be set and reset with the SEM and CLM instruc- tions or with the SEP and CLP instructions. 7. Overflow flag (V) The overflow flag is valid when addition or subtraction is performed with a word treated as a signed binary number. If data length flag m is “0”, the overflow flag is set when the result of addition or subtrac- tion is outside the range between –32768 and +32767. If data length flag m is “1”, the overflow flag is set when the result of addition or subtraction is outside the range between –128 and +127. It is reset in all other cases. The overflow flag can also be set and reset directly with the SEP, and CLV or CLP instructions. Additionally, the overflow flag is set when a result of unsigned/signed division exceeds the length of the register where the result is to be stored; the flag is also set when the addition result is outside range of –2147483648 to +2147483647 in the RMPA operation. 8. Negative flag (N) The negative flag is set when the result of arithmetic operation or data transfer is negative (If data length flag m is “0”, data’s bit 15 is “1”. If data length flag m is “1”, data’s bit 7 is “1”.) It is reset in all other cases. It can also be set and reset with the SEP and CLP instruc- tions. 9. Processor interrupt priority level (IPL) The processor interrupt priority level (IPL) consists of 3 bits and de- termines the priority of processor interrupts from level 0 to level 7. Interrupt is enabled when the interrupt priority of the device request- ing interrupt (set using the interrupt control register) is higher than the processor interrupt priority. When an interrupt is enabled, the cur- rent processor interrupt priority level is saved in a stack and the pro- cessor interrupt priority level is replaced by the interrupt priority level of the device requesting the interrupt. Refer to the section on inter- rupts for more details. Note: Fix bits 11 to 15 of the processor status register (PS) to “0”.

M37902FCCHP, M37902FGCHP, M37902FJCHP MITSUBISHI MICROCOMPUTERS SHINGLE-CHIP 16-BIT CMOS MICROCOMPUTER BANK In order to effectively use the integrated hardware on the chip, this CPU core uses an address generating method with a 24-bit address split into high-order 8 bits and low-order 16 bits. In other words, the

64 Kbytes specified by the low-order 16 bits are one unit (referred to

as “bank”), and the address space is divided into 256 banks (0 16 to FF16) specified by the high-order 8 bits. In the program area on the address space, the bank is specified by the program bank register (PG), and the address in the bank is specified by the program counter (PC). As for each bank boundary, when an overflow has occurred in PC, the contents of PG are incremented by 1. When a borrow has oc- curred in PC, the contents of PG are decremented by 1. Under the normal conditions, therefore, programming without concern for the bank boundaries is possible. Furthermore, as for the data area on the address space, the bank is specified by the data bank register (DT), and the address in the bank is specified by the operation result by using the various addressing modes (Note). Note: Some addressing modes directly specify a bank. DIRECT PAGE The internal memory and control registers for internal peripheral de- vices, etc. are assigned to bank 016 (addresses 016 to FFFF16). The direct page and direct addressing modes have been provided for the effective access to bank 016. In the 7900 Series, two types of direct addressing modes are available: the conventional direct addressing mode which uses only DPR0, as in the 7700 Series, and the ex- panded direct addressing mode, which uses up to 4 direct page reg- isters as selected by the user. The addressing mode is selected according to the contents of bit 1 of the processor mode register 1. This bit 1 is cleared to “0” at reset. (In other words, the conventional direct addressing mode is selected.) However, once this bit 1 has been set to “1” by software, this bit cannot be cleared to “0” again, except by reset. That is to say, when one of these two direct address- ing modes has been selected just after reset, the selected address- ing mode cannot be switched to another one while the program is running. I Conventional direct addressing mode The direct page area consists of 256-byte space. Its bank address is “00 16”, and the base address of its low-order 16-bit address is speci- fied by the contents of the direct page register 0 (DPR0). In this con- ventional direct addressing modes, a value (1 byte) just after an instruction code is regarded as an offset value for the DPR0 con- tents, and the CPU accesses each address in the direct page area. I Expanded direct addressing mode The direct page area consists of four 64-byte spaces. Their bank address is “00 16”, and the four base addresses of their low-order 16- bit addresses are respectively specified by the contents of four direct page registers. In this expanded direct addressing mode, a value (1 byte) just after an instruction code is regarded as follows:

• High-order 2 bits: regarded as a selection field for DPR0 to DPR3.
• Low-order 6 bits: regarded as an offset value for the selected direct page register. Then, the CPU accesses each address in each direct page area: Refer to “7900 Series Software Manual” for details concerning the various addressing modes which use the direct page area. Instruction Set The CPU core of the 7900 Series has an expanded instruction set based on the existing 7700/7751 Series’ CPU core. In addition, its source code (mnemonic) has the complete upper compatibility with the 7700 Series instruction set. For details concerning addressing modes and instruction set, refer to “7900 Series Software Manual”.

M37902FCCHP, M37902FGCHP, M37902FJCHP MITSUBISHI MICROCOMPUTERS SHINGLE-CHIP 16-BIT CMOS MICROCOMPUTER BUS INTERFACE UNIT Data transfer between the central processing unit (CPU) and inter- nal memory, internal peripheral devices, or external areas is always performed via the bus interface unit (BIU), which is located between the CPU and the internal buses. Figure 10 shows the BIU and the bus structure. The CPU and BIU are connected by a dedicated bus, and any transfer between the CPU and BIU is controlled by this dedicated bus. On the other hand, data transfer between the BIU and internal pe- ripheral devices uses the following internal common buses: 32-bit code bus, 16-bit data bus, 24-bit address bus, and control signals. The bus control method where the code bus and the data bus sepa- rate out (hereafter, this method is referred to as the separate code/ Fig. 10 BIU and bus structure Internal code bus (CB0 to CB31) Central Processing Unit (CPU) SFR : Special Function Register ❈ The CPU bus, internal bus, and external bus separate out independently. External devices Internal control signal CPU bus Internal buses Internal data bus (DB0 to DB15) Internal memory Internal peripheral devices (SFR) External bus A0 to A23 D 0 to D7 (LA0 to LA7) D 8 to D15 Control signal Bus Interface Unit (BIU) Bus conversion circuit Internal address bus (AD0 to AD23) HOLD Hold request HLDA M37902 data bus method) is employed in order to improve data transfer ca- pabilities. As a result, the internal memory is connected to both the code bus and the data bus, and registers of all other internal periph- eral devices are connected only to the data bus. Each width of external buses are as follows: a 24-bit address bus, 16-bit data bus. The external data bus transfers instruction codes and data. When the code or data access occurs for the external, the external access is performed via the bus conversion circuit. For details of the connection with the external devices, refer to the section on the processor modes and chip select wait controller de- scribed later.

the functions of each register. Table 1. Functions of each register Indicates a storage address for an instruction to be next taken into an instruction queue buffer. Temporarily stores an instruction which has been taken from a memory. Consists of 10 bytes. Indicates an address where data will be next read from or written to. peripheral devices, and external areas by the CPU. Consists of 32 bits.

the branch destination address. for instructions to be prefetched are categorized as listed in Table 2. passes it to the data buffer, and then, transfers it to the CPU. then, writes it into the specified address.

• Whether the address area locates in the internal area or the ex- ternal area.
• When the address area locates in the external area ➀ Whether the external bus width = 16 bits or 8 bits: (a) When the external bus width = 16 bits: whether the start address for access locates at a 4- byte boundary or at an 8-byte boundary. (b) When the external bus width = 8 bits: whether the start address for access locates at an even address, a 4-byte boundary or at the 8-byte bound ary. ➁ Whether the prefetch operation is generated by a branch, or not. ➂ Number of waits ➃ Whether the burst ROM access is specified or not.

Table 2. Store addresses for instructions to be prefetched

• Whether the address area locates in the internal area or the ex- ternal area.
• Length of data to be transferred: byte, word, double word
• When the address area locates in the external area: ➀ Whether the external bus width = 16 bits or 8 bits: ➁ Number of waits The BIU controls the bus cycle depending on the above conditions. Figures 12 to 16 show the bus cycle waveform examples for instruc- tion prefetch and data access. X: 0 or 1

M37902FCCHP, M37902FGCHP, M37902FJCHP MITSUBISHI MICROCOMPUTERS SHINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Access to internal area Access to external area When address locates at 4-byte boundary or when branched:double consecutive access When branched or at instruction prefetch When external data bus width = 16 bits When external data bus width = 8 bits φBIU Internal address busInternal code busCB 0 to CB Code A 0 to A D 0 to D D 8 to D ALE RD BLW BHW D 0 to D D 0 to D D 8 to D D 8 to D Address Address + 2 When address of instruction to be prefetched locates at 8-byte boundary:quadruple consecutive access A 0 to A D 0 to D D 8 to D ALE RD BLW BHW D 0 to D D 0 to D D 0 to D D 0 to D D 8 to D D 8 to D D 8 to D D 8 to D Address Address + 2 Address + 4 Address + 6 When address is even address or when branched:double consecutive access φ1 A 0 to A D 0 to D ALE RD BLW BHW D 0 to D D 0 to D Address Address + 1 When address of instruction to be prefetched locates at 4-byte boundary or 8-byte boundary: quadruple consecutive access φ1 A 0 to A D 0 to D ALE RD BLW BHW D 0 to D D 0 to D D 0 to D D 0 to D Address Address + 1 Address + 2 Address + 3 Address Fig. 12 Bus cycle waveform example for instruction prefetch

M37902FCCHP, M37902FGCHP, M37902FJCHP MITSUBISHI MICROCOMPUTERS SHINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Access to internal area 8-bit data read 8-bit data written 16-bit data read 16-bit data written Access starting from even address Access starting from odd address φBIU Internal address bus Internal data bus DB 0 to DB7 DB 8 to DB15 D 0 to D7 Address φBIU Internal address bus Internal data bus DB 0 to DB7 DB 8 to DB15 φBIU Internal address bus Internal data bus DB 0 to DB7 DB 8 to DB15 D 0 to D7 Address φBIU Internal address bus Internal data bus DB 0 to DB7 DB 8 to DB15 Address φBIU Internal address bus Internal data bus DB 0 to DB7 DB 8 to DB15 D 0 to D7 Address A0 to A23 D 0 to D7 D 8 to D15 D 0 to D7 Address D 8 to D15 φBIU Internal address bus Internal data bus DB 0 to DB7 DB 8 to DB15 D 8 to D15 D 0 to D7 D 8 to D15 D 8 to D15 A0 to A23 D 0 to D7 D 8 to D15 Address Address + 1 D 8 to D15 D 0 to D7 D 8 to D15 Invalid Invalid Invalid Invalid Address Address + 1 Address 32-bit data read 32-bit data written φBIU Internal address bus Internal data bus DB 0 to DB7 DB 8 to DB15 Address Address + 2 D 8 to D15 D 0 to D7D 0 to D7 D 8 to D15 φBIU Internal address bus Internal data bus DB 0 to DB7 DB 8 to DB15 Address Address + 1 Address + 3 D 8 to D15 D 0 to D7 D 8 to D15 D 0 to D7 φBIU Internal data bus DB 0 to DB7 DB 8 to DB15 D 8 to D15 D 0 to D7 D 8 to D15 D 0 to D7 φBIU Internal address bus Internal data bus DB 0 to DB7 DB 8 to DB15 D 8 to D15 D 0 to D7D 0 to D7 D 8 to D15 Invalid Invalid Address Address + 2 Address Address + 1 Address + 3Internal address bus Fig. 13 Bus cycle waveform example for data access (access to internal area)

M37902FCCHP, M37902FGCHP, M37902FJCHP MITSUBISHI MICROCOMPUTERS SHINGLE-CHIP 16-BIT CMOS MICROCOMPUTER External data bus width = 16 bits 8-bit data read 8-bit data written 16-bit data read 16-bit data written Access starting from even address Access starting from odd address A0 to A23 D 0 to D7 D 8 to D15 ALE RD BLW BHW D 0 to D7 Address A0 to A23 D 0 to D7 D 8 to D15 ALE RD BLW BHW Address A0 to A23 D 0 to D7 D 8 to D15 ALE RD BLW BHW D 0 to D7 Address A0 to A23 D 0 to D7 D 8 to D15 ALE RD BLW BHW Address A0 to A23 D 0 to D7 D 8 to D15 ALE RD BLW BHW D 7 to D0 Address A0 to A23 D 0 to D7 D 8 to D15 ALE RD BLW BHW D 0 to D7 Address D 8 to D15 A0 to A23 D 0 to D7 D 8 to D15 ALE RD BLW BHW Address Address + 1 D 8 to D15 D 0 to D7 D 8 to D15 D 8 to D15 A0 to A23 D 0 to D7 D 8 to D15 ALE RD BLW BHW Address Address + 1 D 8 to D15 D 0 to D7 D 8 to D15 Invalid Invalid Invalid Invalid Fig. 14 Bus cycle waveform example for data access (access to external area) (1)

M37902FCCHP, M37902FGCHP, M37902FJCHP MITSUBISHI MICROCOMPUTERS SHINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Fig. 15 Bus cycle waveform example for data access (access to external area) (2) External data bus width = 16 bits 32-bit data read 32-bit data written Access starting from even address Access starting from odd address A0 to A23 D 0 to D7 D 8 to D15 ALE RD BLW BHW Address Address + 2 D 8 to D15 D 0 to D7D 0 to D7 D 8 to D15 A0 to A23 D 0 to D7 D 8 to D15 ALE RD BLW BHW Address Address + 1 Address + 3 D 8 to D15 D 0 to D7 D 8 to D15 D 0 to D7 A0 to A23 D 0 to D7 D 8 to D15 ALE RD BLW BHW Address Address + 1 Address + 3 D 8 to D15 D 0 to D7 D 8 to D15 D 0 to D7 A0 to A23 D 0 to D7 D 8 to D15 ALE RD BLW BHW Address Address + 2 D 8 to D15 D 0 to D7D 0 to D7 D 8 to D15 Invalid Invalid

M37902FCCHP, M37902FGCHP, M37902FJCHP MITSUBISHI MICROCOMPUTERS SHINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Fig. 16 Bus cycle waveform example for data access (access to external area) (3) Note: When the voltage level at pin BYTE = “L”, functions as pins D8 to D15 are valid. However, when 8-bit width is selected as the external bus width by the chip select wait controller, the functions as pins D8 to D15 and BHW become invalid. (D8 to D15 = floating, BHW = “H ” output.) When the voltage level at pin BYTE = “H ”, these pins function as programmable I/O port (P2, P33) pins. External data bus width = 8 bits 32/16/ 8-bit data read 32/16/ 8-bit data written Access starting from even or odd address A0 to A23 D 0 to D7 D 8 to D15 (Note) (Note) ALE RD BLW BHW Address Address + 1 Address + 2 Address + 3 D 0 to D7 D 0 to D7 D 0 to D7D 0 to D7 A0 to A23 D 0 to D7 D 8 to D15 (Note) (Note) ALE RD BLW BHW Address Address + 1 Address + 2 Address + 3 D 0 to D7 D 0 to D7 D 0 to D7D 0 to D7 8-bit data access 16-bit data access 32-bit data access 8-bit data access 16-bit data access 32-bit data access

M37902FCCHP, M37902FGCHP, M37902FJCHP MITSUBISHI MICROCOMPUTERS SHINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Fig. 18 Bus cycle types at access to external area 1 0 0 1 0 0 Bus cycle select bit 1 = 0Bus cycle select bit 0 RD BLW,BHW RD BLW,BHW External address bus External data bus CS i RD BLW,BHW ALE Address 1 bus cycle = 2φ External address bus External data bus CS i ALE Address 1 bus cycle = 3φ External address bus External data bus CS i ALE Address 1 bus cycle = 4φ External address bus External data bus CS i ALE Address 1 bus cycle = 4φ Data Data Data Data RD BLW,BHW 1 1 Bus cycle select bit 1 = 1 RD BLW,BHW 1 bus cycle = 5φ External address bus External data bus CS i ALE Address RD BLW,BHW 1 bus cycle = 6φ External address bus External data bus CS i ALE Address 4φ2φ RD BLW,BHW 1 bus cycle = 6φ External address bus External data bus CS i ALE Address 3φ3φ RD BLW,BHW 1 bus cycle = 7φ External address bus External data bus CS i ALE Address 4φ3φ Data Data Data Data Bus cycle 1φ + 1φ ❈ Bus cycle 1φ + 2φ ❈ Bus cycle 1φ + 3φ ❈ Bus cycle 2φ + 2φ Bus cycle 2φ + 3φ Bus cycle 2φ + 4φ Bus cycle 3φ + 3φ Bus cycle 3φ + 4φ Notes 1: The bus cycle type is determined by the following bits:

• Areas out of area CSi : external bus cycle select bit 0 (bits 2 and 3 at address 5E16) external bus cycle select bit 1 (bit 0 at address 5F16)
• Area CSi : area CS i bus cycle select bit 0 (bits 0 and 1 at addresses 8016, 8216, 8416, 8616) area CSi bus cycle select bit 1 (bit 3 at addresses 8116, 8316, 8516, 8716) 2: ❈ indicates the bus cycle, where the burst ROM access specification is enabled.

M37902FCCHP, M37902FGCHP, M37902FJCHP MITSUBISHI MICROCOMPUTERS SHINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Fig. 19 Waveform example when recovery cycle is inserted At instruction prefetch At double consecutive access At quadruple consecutive access Recovery cycle = 1 cycle of φ1 Recovery cycle = 2 cycles of φ1 A0 to A23 ALE RD Address Address + 2 A0 to A23 ALE RD Address Address + 2 Address + 4 A0 to A23 ALE RD Address Address + 2 Instruction prefetch Recovery cycle Next access cycle Instruction prefetch Recovery cycle Next access cycle ❈ When address locates at 4-byte boundary, or when branched. ❈❈❈ Address + 6 Instruction prefetch Recovery cycle Next access cycle A0 to A23 ALE RD Address Address + 2 Address + 4 Address + 6 Instruction prefetch Recovery cycle Next access cycle ❈❈ When address locates at 8-byte boundary. At data access A0 to A23 ALE RD, Address Access cycle Recovery cycle Next access cycle BLW, BHW A0 to A23 ALE RD, Address Access cycle Recovery cycle Next access cycle BLW, BHW Notes 1: The recovery cycle insert is specified by the recovery cycle insert select bit and the recovery-cycle-insert-number select bit (bits 4 and 6 at address 5F16). Recovery cycle insertion is valid only at access to area CSi. 2: The above is applied when 1 bus cycle = 2φ. G Recovery cycle A recovery cycle which is equivalent to 1 or 2 cycles of φ1 can be in- ___ serted after each area CSi’s access cycle. Whether the recovery cycle is inserted or not is determined by the recovery cycle insert ___ select bit of each CSi control register L (bit 6 at addresses 8016, 8216, 8416, 8616). Also, the number of the recovery cycles is selected by the recovery-cycle-insert-number select bit of the processor mode register 1 (bit 6 at address 5F 16). Figure 19 shows a waveform ex- ample when a recovery cycle is inserted.

M37902FCCHP, M37902FGCHP, M37902FJCHP MITSUBISHI MICROCOMPUTERS SHINGLE-CHIP 16-BIT CMOS MICROCOMPUTER G Burst ROM access When ROM supporting the burst ROM access has been allocated to ___ area CSi, the burst ROM access can be specified. The burst ROM ___ access is specified by each burst ROM access select bit of the CSi control register L (bit 5 at addresses 8016, 8216, 8416, 8616). The burst ROM access is valid only when the external data bus width = 16 bits with an instruction prefetched. In the other cases, the normal access is performed regardless of the contents of the burst ROM ac- cess select bit. The burst ROM access can be specified only in the case of ❈ in Figure 18. Figure 20 shows a waveform example at burst ROM access. When an instruction is prefetched from the burst ROM, 8 bytes are fetched starting from an 8-byte boundary (the low-order 3 bits of ad- dress, A 2, A1, A0 = “000”) in waveform (a). When branched, regard- less of the 8-byte boundary of the branch destination address, access starting from the 4-byte boundary (the low-order 2 bits of ad- dress, A 1, A0 = “00”) is performed in waveform (b). Once the 8-byte boundary has been selected, instructions will be prefetched in wave- form (a) until a branch. Fig. 20 Waveform example at burst ROM access Note: The above is applied when 1 bus cycle = 2φ. (b) External address bus RD External data bus Data (Instruction) External data bus Data (Instruction) Data (Instruction) Data (Instruction) Address Address (a) External address bus (A0 to A23) RD External data bus (D0 to D7) Data (Instruction) External data bus Data (Instruction) Data (Instruction) Data (Instruction) Address Address Address Address Data (Instruction) Data (Instruction) Data (Instruction) Data (Instruction) (D8 to D15) (A0 to A23) (D0 to D7) (D8 to D15) At quadruple consecutive accessAt double consecutive access Note: The above is applied when 1 bus cycle = 2φ. Notes 1: The burst ROM access is selected by the burst ROM access select bit (bit 5 at addresses 8016, 8216, 8416, 8616). 2: The burst ROM access can be selected only in the case of ❈ in Figure 18.

M37902FCCHP, M37902FGCHP, M37902FJCHP MITSUBISHI MICROCOMPUTERS SHINGLE-CHIP 16-BIT CMOS MICROCOMPUTER G Address output selection As shown in Figure 21, the unnecessary state change of address output pins (A0 to A23) can be avoided, without outputting an address at access to the internal area. When the address output select bit of the particular function select register 1 (bit 4 at address 63 16) is set to “1”, an address is output only at access to the external area. Also, at access to the internal area, the address at the preceding access to the external area is re- tained. The address output start timing in this case is the half cycle of φ 1 later than that at the normal access (when the address output select bit = “0”). For the bit structure of the particular function select register 1, refer to the section on the standby function. Also, at the normal access, an address is output at both of the ac- cess to the internal and external areas. Fig. 21 Waveform example depending on address output function selection Access to external area RD, BLW,BHW A0 to A23 RD, BLW,BHW A0 to A23 Access to external area Address output select bit = 0 Address output select bit = 1 (Address waveform changes only when external access is generated.) Access to internal area Address Address Address Address Unde- fined Unde- fined

M37902FCCHP, M37902FGCHP, M37902FJCHP MITSUBISHI MICROCOMPUTERS SHINGLE-CHIP 16-BIT CMOS MICROCOMPUTER G Area multiplication ___ When area CS 2’s external data bus width = 8 bits with the multi- ___ plexed bus select bit of the CS2 control register H (bit 5 at address 8516) = “1”, the external bus type can be changed to the multiplexed ___ bus type only at access to area CS2. In this case, the low-order 8 bits of an address (LA0 to LA7) are output, and the low-order 8 bits of data (D0 to D7) are input/output with the time-sharing method, re- spectively. Figure 22 shows a waveform example of area multiplication for each bus cycle. Do not select the area multiplication function for a bus cycle not shown in Figure 22. Fig. 22 Waveform example of area multiplication for each bus cycle D 0 to D7 1 1 1 0 1 1 Multiplexed bus select bit = 1 Bus cycle select bit 0 RD, BLW 1 bus cycle = 6φ CS i ALE 3φ3φ RD, BLW 1 bus cycle = 7φ CS i ALE 4φ3φ D 0 to D7 D 0 to D7 D 0 to D7 External address bus Address External address bus Address Bus cycle 2φ + 2φ Bus cycle 3φ + 3φ Bus cycle 3φ + 4φ RD, BLW At write, LA0/D0 to LA7/D7 CS i ALE D 0 to D7 1 bus cycle = 4φ D 0 to D7 External address bus Address Area CS2 bus cycle select bit 0 At read, LA0/D0 to LA7/D7 At write, LA0/D0 to LA7/D7 At read, LA0/D0 to LA7/D7 At write, LA0/D0 to LA7/D7 At read, LA0/D0 to LA7/D7 LA0 to LA7 LA0 to LA7 LA0 to LA7 LA0 to LA7 LA0 to LA7 LA0 to LA7 Notes 1: The number of bus cycles is determined by the following bits:

• Area CS2 bus cycle select bit 0 (bits 0 and 1 at address 8416)
• Area CS2 bus cycle select bit 1 (bit 3 at address 8516) Area multiplication is specified by the multiplexed bus select bit (bit 5 at address 8516). 2: Do not select the area multiplication function for a bus cycle not shown in Figure 22. 2φ 2φ

M37902FCCHP, M37902FGCHP, M37902FJCHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS PROCESSOR MODES Any of the three processor modes (single-chip mode, memory ex- pansion mode, microprocessor mode) can be selected with the fol- lowing:

• Processor mode bits of the processor mode register 0 (bits 1 and 0 at address 5E 16; Figure 24)
• Voltage level applied to pin MD0 Table 3 lists the selection method of a processor mode. The memory map which the CPU can access depends on the se- lected processor mode. Figure 23 shows the memory maps in three processor modes. Also, the functions of ports P0 to P4, P10, P11 depend on the se- lected processor mode. For details, see Tables 5 and 6. Figures 24 to 26 show the bit configurations of the processor mode registers 0, 1, and port function control register. In the single-chip mode, ports P0 to P4, P10, P11 function as I/O ports. (While the internal peripheral devices are used, these ports function as these devices’ I/O pins.) In this mode, only the internal area (SFRs, internal RAM, internal ROM) is accessible. In the memory expansion and microprocessor modes, external de- vices assigned in the external memory area can be connected via buses. Therefore, ports P0 to P4, P10, P11 function as I/O pins for the address bus, data bus, bus control signals. (Some port functions are selectable.) Table 4 lists each bus control signal’s function. In the memory expansion mode, all of the internal area (SFRs, inter- nal RAM, internal ROM) and external area are accessible. In the mi- croprocessor mode, the internal area except for the internal ROM (in other words, SFRs and internal RAM) and the external area are ac- cessible. Note that, when the external devices are located to an area where the internal area and external area overlap, only the internal area can be read/written; the external area cannot be read/written. Single-chip mode SFR area Unused area Unused area Internal RAM area Internal ROM area Memory expansion mode SFR area Internal RAM area Internal ROM area Reserved area (Note) Microprocessor mode SFR area Internal RAM area Reserved area (Note) 016 FF16 FEFFFF 16 FF000016 FFFFFF 16 External area : Access to this area enables the access to the devices which are connected with the external. Note: Do not access this area (bank FF16). SFR area : Internal peripheral devices’ control registers are allocated here. Fig. 23 Memory maps in three processor modes

M37902FCCHP , M37902FGCHP, M37902FJCHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS Signal RD BLW BHW ALE RDY HOLD HDLA CS 0–CS 3 BYTE VSS VCC MD0 Processor mode bits After reset is removed, the single-chip mode is selected. By chang- ing the processor mode bits’ contents by software, the memory ex- pansion mode or microprocessor mode can be selected. (Note 1) Processor mode After reset is removed, the microprocessor mode is selected.(Note 2) Single-chip mode Memory expansion mode Microprocessor mode Microprocessor mode Table 3. Selection method of processor mode Table 4. Each bus control signal’s function Read signal. Outputs “L” at read from the external area. Write signal. Outputs “L” at write to the external area. period just before signals RD, BLW, BHW become “L”. This is used to latch an address in an external circuit. voltage is applied to this pin. quest to terminate the hold state. Hold acknowledge signal. Outputs “L” in the hold state. when Vcc, 8-bit width will be selected. pending on the external data bus width, see Table 5.

• While ALE = “H”, be sure to open a latch, so the address will pass it.
• While ALE = “L”, be sure to hold the address. Acceptance and termination of a hold request is performed at completion of the bus cycle while the BIU operates. In the hold state, A 0–A23, D0–D 15, RD, BLW, BHW, ALE, CS 0–CS 3 enter the floating state. At termination of the hold state, simultaneously with the timing when HLDA becomes “H” level, the above floating state is terminated. Then, bus access will be restarted 1 cycle of φ1 after. In the hold state, also, the CPU operates with access to the internal area. If the CPU accesses the external area, in the hold state, the CPU stops its operation. For details, refer to the section on the chip select wait con- troller. When BYTE = Vss level, by the register setting, each chip select area (CS 1 to CS3) can have the 8-bit data bus, inde- pendently. For details, refer to the section on the chip select wait con- troller. Notes 1: Processor mode bits = bits 0 and 1 of the processor mode register 0 (address 5E16) 2: While the Vcc level voltage is applied to pin MD0, the processor mode bits are fixed to “10”.

even address) is input/output. even/odd address) is input/output. odd address) is input/output. Low-order address (A0 to A7) is output. even address) is input/output. even/odd address) is input/output. odd address) is input/output. Ready signal RDY is input (Note 6). Table 5. Relationship between processor modes, memory area, and port function (1)

Notes 1: For details of the processor mode setting, see Table 3. 2: Processor mode bits = bits 0 and 1 of the processor mode register 0 (address 5E16). switch select bits of the port function control register (bits 2 to 0 at address 9216).

• Output of address LA0 to LA7
• Input/Output of data D0 to D7 5: When one of areas CS1/CS2/CS3 is accessed under the following conditions, pins D8 to D15 enter the floating state, and pin BHW outputs “H ” level. (They do not become I/O port pins.)
• Pin BYTE is at Vss level.
• One of bit 2s at addresses 8216, 8416, 8616 (the external data bus width select bit of the CS1/CS2/CS3 control register L) is set to “1” (external data bus width = 8 bits). 6: In the memory expansion mode, by the corresponding select bits of the processor mode register 0 and 1 (addresses 5E 16, 5F16), port pins P30, P40 to P43 can operate as pins for RDY input, ALE output, φ1 output, HLDA output, HOLD input, respectively. In the microprocessor mode, by the above select bits, the above pins (RDY, ALE, φ1, HLDA, HOLD) can operate as port pins P30, P40 to P43, respec- tively. In the single-chip mode, port pin P41 can operate as the φ1 output pin by the above select bits. 7: In the memory expansion mode, port pin P44 can operate as the CS0 output pin by the CS0 output select bit of the CS0 control register L (bit 7 at address 8016). 8: In the memory expansion and microprocessor modes, port pins P45 to P47 can operate as the CS1/CS2/CS3 output pins by the CSi output select bits (i = 1 to 3) (bit 7s at addresses 8216, 8416, 8616).

Table 6. Relationship between processor modes, memory area, and port function (2) Clock φ1 is output (Note 6). Clock φ1 is output (Note 6). Chip select signal CS0 is output.

M37902FCCHP, M37902FGCHP, M37902FJCHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS Fig. 24 Bit configuration of processor mode register 0 Notes 1: While VSS level voltage is applied to pin MD0, this bit’s state is cleared to “0” at reset. While VCC level voltage is applied to pin MD0, on the other hand, this bit’s state is set to “1” at reset. (Fixed to “1”.) 2: These bits are valid to the external area except for chip select area (area CSi). The bus cycle of area CSi is selected by the corresponding area CSi bus cycle select bits 0, 1. 3: While VSS level voltage is applied to pin MD0, this bit’s state is cleared to “0” at reset. While VCC level voltage is applied to pin MD0, on the other hand, this bit’s state is set to “1” at reset. 76543210 Processor mode register 0 Processor mode bits (Note 1) 0 0 : Single-chip mode 0 1 : Memory expansion mode 1 0 : Microprocessor mode 1 1 : Do not select. Interrupt priority detection time select bits 0 0 : 7 cycles of f sys 0 1 : 4 cycles of fsys 1 0 : 2 cycles of fsys 1 1 : Do not select. Software reset bit By a write of “1” to this bit, the microcomputer will be reset, and then, restarted. External bus cycle select bit 0 (Note 2) See Figure 18. Clock φ1 output select bit (Note 3) 0 : φ1 output is disabled. (P41 functions as an programmable I/O port pin.) 1 : φ1 output is enabled. (P41 functions as the clock φ1 output pin.) Address 5E16

M37902FCCHP , M37902FGCHP, M37902FJCHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS Fig. 25 Bit configuration of processor mode register 1 Notes 1: This bit is valid to the external area except for chip select areas (area CSi), and the bus cycle of area CSi is independent of this bit’s contents. The bus cycle of area CSi is selected by the corresponding area CSi bus cycle select bits 0, 1 (bits 0, 1 at addresses 8016, 8216, 8416, 8616; bit 3 at addresses 8116, 8316, 8516, 8716). 2: After reset, this bit’s contents can be switched only once. During the software execution, be sure not to switch this bit’s contents. 3: In the single-chip mode, these bits’ functions are disabled regardless of these bits’ contents. 4: While VSS level voltage is applied to pin MD0, each of these bits is “0” at reset. While VCC level voltage is applied to pin MD0, on the other hand, each of these bits is “1” at reset. 5: In the memory expansion or microprocessor mode, if this bit’s contents is switched from “1” to “0”, this bit will be cleared to “0”. After this clearance, this bit cannot return to “1”. If it is necessary to set this bit to “1”, be sure to reset the microcomputer. 6: The program which switches this bit’s contents must be assigned to the internal area. 7: In the microprocessor mode, this bit is invalid. When the internal flash memory is reprogrammed in the CPU reprogramming mode, be sure to clear this bit to “0”. 76543210 Processor mode register 1 External bus cycle select bit 1 (Note 1) See Figure 18. RDY input select bit (Notes 3 to 5) 0 : RDY input is disabled. (P30 functions as a programmable I/O port pin.) 1 : RDY input is enabled. (P30 functions as pin RDY.) ALE output select bit (Notes 3 and 4) 0 : ALE output is disabled. (P40 functions as a programmable I/O port pin.) 1 : ALE output is enabled. (P40 functions as pin ALE.) Direct page register switch bit (Note 2) 0 : Only DPR0 is used. 1 : DPR0 to DPR3 are used. Recovery cycle insert select bit (Notes 3 and 4) 0 : No recovery cycle is inserted at access to the external area. 1 : Recovery cycle is inserted at access to the external area. Address HOLD input, HLDA output select bit (Notes 3 to 5) 0 : HOLD input and HLDA output are disabled. (P43 and P42 function as programmable I/O port pins.) 1 : HOLD input and HLDA output are enabled. (P43 and P42 function as pins HOLD and HLDA, respectively.) Recovery-cycle-insert number select bit (Note 6) 0 : 1 cycle 1 : 2 cycles Internal ROM bus cycle select bit (Note 7) 0 : 3φ 1 : 2φ

M37902FCCHP, M37902FGCHP, M37902FJCHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS Fig. 26 Bit configuration of port function control register Notes 1: For the M37902FxM (power source voltage = 3.3 V±0.3 V), VIH = 0.5VCC . 2: When MD1 = VCC and MD0 = VCC (flash memory parallel I/O mode), pins P44 to P47 and NMI are not pulled up, regardless of these bits’ contents. 3: When MD1 = VSS and MD0 = VCC (microprocessor mode), pin CS0 (P44) is not pulled up, regardless of the bit’s contents. 76543210 Port function control register Port P0 input level select bit 0 : VIH = 0.7VCC , VIL = 0.2VCC 1 : VIH = 0.43VCC (Note 1), VIL = 0.16VCC Address/Port switch select bits 000 : A0 to A23 (16 Mbytes) 001 : A0 to A21, P06, P07 (4 Mbytes) 010 : A0 to A19, P04 to P07 (1 Mbytes) 011 : A0 to A17, P02 to P07 (256 Kbytes) 100 : A0 to A15, P00 to P07 (64 Kbytes) 101 : Do not select. 110 : A 0 to A11, P00 to P07, P114 to P117 (4 Kbytes) 111 : A0 to A7, P00 to P07, P110 to P117 (256 bytes) Pins P44–P47 pullup select bit (Notes 2 and 3) 0 : Pins P44–P47 are pulled up. 1 : Pins P44–P47 are not pulled up. Address 9216 Pin NMI pullup select bit (Note 2) 0 : Pin NMI is pulled up. 1 : Pin NMI is not pulled up. Fix these bits to “0”. 0 0 At reset 0016

• 1φ + 1φ
• 1φ + 2φ
• 1φ + 3φ
• 2φ + 2φ
• 2φ + 3φ
• 2φ + 4φ
• 3φ + 3φ
• 3φ + 4φ (Selected by bits 2, 3 at address 16 and bit 0 at address 5F16.) Determined by pin BYTE’s level Valid (Selected by bit 2 at address 16.) Not available. Available. Not available. Available. CS Banks 216 to FE16

128 Kbytes,

256 Kbytes,

512 Kbytes,

1 Mbytes,

2 Mbytes,

4 Mbytes,

• 1φ + 1φ
• 1φ + 2φ
• 1φ + 3φ
• 2φ + 2φ
• 2φ + 3φ
• 2φ + 4φ
• 3φ + 3φ
• 3φ + 4φ (Selected by bits 0, 1 at address 16 and bit 3 at address 8716.) When BYTE = VSS level, 8-bit width or 16-bit width can be selected arbitrary (Note 1). (Selected by bit 2 at address 86 16.) Valid (Selected by bit 2 at address 16 and bit 3 at address 8616.) Available. Available. Not available. Available. Bus cycle:
• 1φ + 1φ
• 1φ + 2φ
• 1φ + 3φ
• 2φ + 2φ
• 2φ + 3φ
• 2φ + 4φ
• 3φ + 3φ
• 3φ + 4φ (Selected by bits 0, 1 at addresses 16, 8416 and bit 3 at addresses 8316, 8516.) When BYTE = VSS level, 8-bit width or 16-bit width can be selected arbitrary (Note 1). (Selected by bit 2 at addresses 82 16, 8416.) Valid (Selected by bit 2 at address 5F16 and bit 3 at addresses 8216, 8416.) Available. Available. CS 1: Not available. CS 2: Available. (Note 4) Available. Space where start address can be set Block size Bus cycle External data bus width RDY control Burst ROM access (Notes 2, 3) Recovery cycle insertion Area multiplexed bus access (Note 3) Address output selection (Note 5) Bus cycle:
• 1φ + 1φ
• 1φ + 2φ
• 1φ + 3φ
• 2φ + 2φ
• 2φ + 3φ
• 2φ + 4φ
• 3φ + 3φ
• 3φ + 4φ (Selected by bits 0, 1 at address 16 and bit 3 at address 8116.) Determined by pin BYTE’s level. Valid (Selected by bit 2 at address 5F16 and bit 3 at address 8016.) Available. Available. Not available. Available. CS Mode 0 Banks 216 to FE16

4 Kbytes

Table 7. Function of areas CS0 to CS3 Notes 1: When BYTE = Vcc level, the external data bus width is fixed to 8 bits. 2: Burst ROM access is valid only when the external data bus width is 16 bits at instruction prefetch. 3: Burst ROM access and area multiplexed bus access cannot be used at the same time. 4: Valid only when area CS2 is accessed with the 8-bit external data bus width. 5: Selected by the address output select bit (bit 4 at address 6316). The address output selection for each area is not available.

M37902FCCHP , M37902FGCHP, M37902FJCHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS Fig. 28 Bit configuration of CS0/CS1/CS2/CS3 control register Ls 76543210 CS 0 control register L External data bus width select bit (Note 1) 0 : 16-bit width 1 : 8-bit width RDY control bit (Note 2) 0 : RDY control is valid. 1 : RDY control is invalid. Area CS 0 bus cycle select bit 0 See Figure 18. Address 8016 At reset 4216 Burst ROM access select bit (Note 3) 0 : Normal access 1 : Burst ROM access Recovery cycle insert select bit 0 : No recovery cycle is inserted at access to area CS0. 1 : Recovery cycle is inserted at access to area CS0. CS 0 output select bit (Notes 4, 5) 0 : CS0 output is disabled. (P44 functions as a programmble I/O port pin.) 1 : CS0 output is enabled. (P44 functions as pin CS0.) Notes 1: While VSS level voltage is applied to pin BYTE, this bit’s state is cleared to “0” at reset. While VCC level voltage is applied to pin BYTE, on the other hand, this bit’s state is set to “1” at reset. 2: This bit is valid when the RDY input select bit (bit 2 at address 5F16) = “1”. 3: While VCC level voltage is applied to pin BYTE, the normal access is selected regardless of this bit’s contents. 4: In the single-chip mode, this bit’s contents are invalid. (CS0 output is disabled.) 5: While VSS level voltage is applied to pin MD0, this bit’s state is cleared to “0” at reset. While VCC level voltage is applied to pin MD0, on the other hand, this bit’s state is set to “1” at reset. (Fixed to “1”.)

76543210 CS 1 control register L

External data bus width select bit 0 : 16-bit width 1 : 8-bit width (Note 1) RDY control bit (Note 2) 0 : RDY control is valid. 1 : RDY control is invalid. Area CS j bus cycle select bit 0 (j = 1 to 3) See Figure 18. “0” at reading. Address 8216 8416 8616 At reset 4216 4216 4216 Burst ROM access select bit (Note 3) 0 : Normal access 1 : Burst ROM access Recovery cycle insert select bit 0 : No recovery cycle is inserted at access to area CSj. 1 : Recovery cycle is inserted at access to area CSj. CS j output select bit (j = 1 to 3) (Note 4) 0 : CSj output is disabled. (P45 to P47 function as programmable I/O port pins.) 1 : CSj output is enabled. (P45 to P47 function as pin CSj.) Notes 1: While VCC level voltage is applied to pin BYTE, this bit is fixed to “1” (8-bit width). 2: This bit is valid when the RDY input select bit (bit 2 at address 5F16) = “1”. 3: When only the external data bus width select bit (bit 2) = “1” or while VCC level voltage is applied to pin BYTE, the normal access is selected regardless of this bit’s contents. 4: In the single-chip mode, this bit’s contents are invalid. (CS0 output is disabled.) “0” at read.

M37902FCCHP, M37902FGCHP, M37902FJCHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS Fig. 29 Bit configuration of CS0/CS1/CS2/CS3 control register Hs Area CS3 bus cycle select bit 1 See Figure 18. Area CS1 bus cycle select bit 1 See Figure 18. Area CS0 bus cycle select bit 1 See Figure 18. 76543210 CS 0 control register H Area CS0 block size select bit When mode 0 is selected 0 0 0 : 0 byte (Area CS0 is invalid.) 0 0 1 : 128 Kbytes 0 1 0 : 256 Kbytes 0 1 1 : 512 Kbytes 1 0 0 : 1 Mbytes 1 0 1 : 2 Mbytes 1 1 0 : 4 Mbytes 1 1 1 : 8 Mbytes Address At reset 8116 At reset 0016 76543210 CS 1 control register H Area CS1 block size select bit Address 8316 When mode 0 is selected 0 0 0 : 0 byte (Area CS1 is invalid.) 0 0 1 : 128 Kbytes 0 1 0 : 256 Kbytes 0 1 1 : 512 Kbytes 1 0 0 : 1 Mbytes 1 0 1 : 2 Mbytes 1 1 0 : 4 Mbytes 1 1 1 : 8 Mbytes When mode 1 is selected 0 0 0 : 0 byte (Area CS 1 is invalid.) 0 0 1 : Do not select. 0 1 0 : Do not select. 0 1 1 : Do not select. 1 0 0 : 4 Kbytes 1 0 1 : 8 Kbytes 1 1 0 : Do not select. 1 1 1 : Do not select. When mode 1 is selected 0 0 0 : 0 byte (Area CS 0 is invalid.) 0 0 1 : 128 Kbytes 0 1 0 : 256 Kbytes 0 1 1 : 512 Kbytes 1 0 0 : 1 Mbytes 1 0 1 : 2 Mbytes 1 1 0 : 4 Mbytes 1 1 1 : 8 Mbytes Must be fixed to “0”. 76543210 CS 3 control register H Area CS3 block size select bit 0 0 0 : 0 byte (Area CS3 is invalid.) 0 0 1 : 128 Kbytes 0 1 0 : 256 Kbytes 0 1 1 : 512 Kbytes 1 0 0 : 1 Mbytes 1 0 1 : 2 Mbytes 1 1 0 : 4 Mbytes 1 1 1 : 8 Mbytes Address Area CS1 setting mode select bit 0 : Mode 0 (A block can be set to 16-Mbyte space in a unit of 128 Kbytes.) 1 : Mode 1 (A block can be set to bank 0 in a unit of 4 Kbytes.) Area CS0 setting mode select bit 0 : Mode 0 (A block can be set to 16-Mbyte space.) 1 : Mode 1 (Area CS 0 start address can be set to bank 0.) “0” at read. “0” at read. “0” at read. At reset 0016 At reset 0016 76543210 CS 2 control register H Area CS2 block size select bit Address 8516 When mode 0 is selected 0 0 0 : 0 byte (Area CS2 is invalid.) 0 0 1 : 128 Kbytes 0 1 0 : 256 Kbytes 0 1 1 : 512 Kbytes 1 0 0 : 1 Mbytes 1 0 1 : 2 Mbytes 1 1 0 : 4 Mbytes 1 1 1 : 8 Mbytes When mode 1 is selected 0 0 0 : 0 byte (Area CS 2 is invalid.) 0 0 1 : Do not select. 0 1 0 : Do not select. 0 1 1 : Do not select. 1 0 0 : 4 Kbytes 1 0 1 : 8 Kbytes 1 1 0 : Do not select. 1 1 1 : Do not select. Multiplexed bus select bit 0 : Separated bus (D0 to D7 are input/output.) 1 : Multiplexed bus (When the CS2 external data bus width = 8 bits with area CS2 accessed, LA0/D0 to LA7/D7 are input/output.) Area CS2 setting mode select bit 0 : Mode 0 (A block can be set to 16-Mbyte space in a unit of 128 Kbytes.) 1 : Mode 1 (A block can be set to bank 0 in a unit of 4 Kbytes.) Area CS2 bus cycle select bit 1 See Figure 18. “0” at read.

M37902FCCHP , M37902FGCHP, M37902FJCHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS 76543210 Area CS0 start address register When mode 0 is selected, these bits determine A16 to A23 of the area CS0 start address. When mode 1 is selected, these bits determine A8 to A15 of the area CS0 start address. Any of the following values can be set to these bits: “1016”, “2016”, “4016”, and “8016”. (Bits 0 to 3 are always “0” at read.) Address 8A16 At reset 1016 At reset 0016 0016 At reset 0016 76543210 Area CS1 start address register Area CS2 start address register When mode 0 is selected, these bits determine A16 to A23 of the area CS1/CS2 start address. When mode 1 is selected, these bits determine A8 to A15 of the area CS1/CS2 start address. (Bit 0 is always “0” at read.) Address 8C 16 8E16 76543210 Area CS3 start address register These bits determine A16 to A23 of the area CS3 start address. (Bit 0 is always “0” at read.) Address 9016 Note: Do not set a value other than “1016”, “2016”, “4016”, and “8016”. See Figure 31. Note: The start address setting depends on the block size, which has been selected by the area CS1/CS2 block size select bits (bits 0 to 2 at address 8316, bits 0 to 2 at address 8516). See Figures 32 and 33. Note: The start address setting depends on the block size, which has been selected by the area CS3 block size select bits (bits 0 to 2 at address 8716). See Figure 33. “0” at read. “0” at read. “0” at read. Fig. 30 Bit configuration of area CS0/CS1/CS2/CS3 start address registers

M37902FCCHP, M37902FGCHP, M37902FJCHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS Fig. 31 Area CS0 (mode 1) 128Kbytes 512Kbytes 2Mbytes 1M bytes 4Mbytes 8Mbytes 128K bytes 512Kbytes 2Mbytes 256K bytes 1Mbytes 4Mbytes 8Mbytes 1000 1FFFF 7FFFF FFFFF 128K bytes 512Kbytes 2Mbytes Start address : 1000 Value to be set to area CS0 start address register = “1016 Block size 2000 Start address : 2000 Value to be set to area CS0 start address register = “2016 4000 Start address : 4000 Value to be set to area CS0 start address register = “4016 8000 128Kbytes Start address : 8000 Value to be set to area CS0 start address register = “8016 Area CS 0 cannot be assigned here. Note: When an area where area CS 0 and the internal area overlap is accessed, the internal area will be accessed. In this case, pin CS 0 outputs “H” level. 3FFFF 256Kbytes 1FFFFF 1M bytes 4Mbytes 8Mbytes 512K bytes 2Mbytes 256K bytes 1Mbytes 4Mbytes 8Mbytes 3FFFFF 7FFFFF Block size Block size Block size 256K bytes

M37902FCCHP , M37902FGCHP, M37902FJCHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS Fig. 32 Area CS1/CS2 (mode 1) 016 100016 200016 ( FFFF16) Block size : 4 Kbytes Addresses which can be start address (Address FFFF 16 is not included; Note 1) 300016 400016 500016 600016 700016 800016 016 200016 (FFFF16) Block size : 8 Kbytes Addresses which can be start address (Address FFFF 16 is not included; Note 1) 400016 600016

8 Kbytes

Notes 1: Only A8 to A15 of one of these addresses can be set to the area CS1/CS2 start address register. Do not set another address not shown here. 2: When an area where area CS 1/CS2 and the internal area overlap is accessed, the internal area will be accessed. In this case, pin CS 1/CS2 outputs “H ” level.

M37902FCCHP, M37902FGCHP, M37902FJCHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS Fig. 33 Area CS0/CS1/CS2 (mode 0) and area CS3 Notes 1: Only A to A of one of these addresses can be set to the area CS 0/CS 1/CS 2/CS 3 start address register. Do not set another address not shown here. When an area where area CS 0/CS 1/CS 2/CS 3 and the internal area overlap is accessed, the internal area will be accessed. In this case, pin CS 0/CS 1/CS 2/CS 3 outputs “H” level. /;/;/; Block size : 128 Kbytes Addresses which can be start address(Addresses 0 and FF0000 to FFFFFF are not included; Note 1 : Area CS 0/CS 1/CS 2/CS 3 cannot be assigned here. 20000 40000 60000 80000 A0000 C0000 E0000 100000 F60000 F80000 FA0000 FC0000 FE0000 ( FF0000 ( FFFFFF 120000 /;/;/; Block size : 256 Kbytes Addresses which can be start address(Addresses 0 and FF0000 to FFFFFF are not included; Note 1 40000 80000 C0000 100000 F80000 FC0000 ( FF0000 ( FFFFFF /;/;/; Block size : 512 Kbytes Addresses which can be start address(Addresses 0 and FF0000 to FFFFFF are not included; Note 1 80000 100000 F80000 ( FF0000 ( FFFFFF /;/;/; Block size : 1 Mbytes Addresses which can be start address(Addresses 0 and FF0000 to FFFFFF are not included; Note 1 100000 200000 300000 400000 500000 600000 700000 800000 B00000 C00000 D00000 E00000 F00000 ( FF0000 ( FFFFFF 900000 A00000 /;/;/; Block size : 2 Mbytes Addresses which can be start address(Addresses 0 and FF0000 to FFFFFF are not included; Note 1 200000 400000 600000 800000 C00000 E00000 ( FF0000 ( FFFFFF A00000 /;/;/; Block size : 4 Mbytes Addresses which can be start address(Addresses 0 and FF0000 to FFFFFF are not included; Note 1 400000 800000 C00000 ( FF0000 ( FFFFFF /;/;/;Block size : 8 Mbytes Addresses which can be start address(Addresses 0 and FF0000 to FFFFFF are not included; Note 1 800000 ( FF0000 ( FFFFFF : Reserved area. Do not access this area.

DBC and BRK instruction are interrupts used only for debugging. Therefore, do not use these interrupts. 35 shows the bit configuration of the interrupt control register. bits other than watchdog timer and NMI can be cleared by software. interrupt input can be selected with the polarity select bit. ure 40.), pin position of INT2 to INT4 can be changed. rupt. For details, refer to the section on the key input interrupt. out, the status of pins INT0 to INT4 and NMI can directly be read. Timer and UART interrupts are described in the respective section. justed by software as shown in Figure 36. Table 8. Interrupt sources and interrupt vector addresses the status of pin INT3 cannot be read out.

M37902FCCHP, M37902FGCHP, M37902FJCHP MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Fig. 35 Bit configuration of interrupt control register 76543210 Interrupt priority level select bits (Note 1) Interrupt request bit 0 : No interrupt requested 1 : Interrupt requested 76543210 Interrupt priority level select bits (Notes 1, 2) Interrupt request bit 0 : No interrupt requested 1 : Interrupt requested Polarity select bit 0 : Interrupt request bit is set to “1” at “H ” level when level sense is selected; this bit is set to “1” at falling edge when edge sense is selected. 1 : Interrupt request bit is set to “1” at “L” level when level sense is selected; this bit is set to “1” at rising edge when edge sense is selected. Level/Edge select bit 0 : Edge sense 1 : Level sense Interrupt control register bit configuration for A-D converter, UART0, UART1, timer A0 to timer A4, and timer B0 to timer B2. Interrupt control register bit configuration for INT 0– INT2 76543210 Interrupt priority level select bits Interrupt request bit (Note 1) 0 : No interrupt requested 1 : Interrupt requested Polarity select bit 0 : Interrupt request bit is set to “1” at falling edge. 1 : Interrupt request bit is set to “1” at rising edge. Interrupt control register bit configuration for INT 3 and INT4 Notes 1: Use the MOVM (MOVMB) instruction or the STA (STAB, STAD) instruction for writing to this bit. 2: Interrupt request bits of INT0 to INT2 are invalid when the level sense is selected.

Other interrupts previously mentioned are A-D converter, UART, etc. orities are the same, the one above has priority. interrupt disable flag I to “0” and enable further interrupts. processor interrupt level (IPL) is set as shown in Table 10. Table 9. Addresses of interrupt control registers Priority can be changed by software inside ➃ .

Table 10. Value loaded in processor interrupt level (IPL) during an interrupt Table 11. Relationship between interrupt priority detection time select Note: This pulse resides when 2 cycles of fsys is selected.

M37902FCCHP, M37902FGCHP, M37902FJCHP MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Key Input Interrupt The INT3 interrupt can function as the key input interrupt by setting bits 1 to 3 of the external interrupt input control register (address 16). The key input interrupt uses inputs KI0 to KI3. Figure 39 shows the block diagram of the INT3/key input interrupt input circuit, and Figure 40 shows the bit configuration of the external interrupt input control register. When bit 0 of the external interrupt input control register (key input interrupt select bit)= “0”, a signal from pin INT 3 is connected to the INT3 interrupt control circuit, and INT3 external interrupt is normally performed. When bit 0 = “1”, signals from pins KI0 to KI3, which cor- respond to ports P54 to P57 pins, are inverted, and then, the logical sum of these signals is connected to the INT3 interrupt control regis- ter. In this case, the external interrupt which uses pins KI0 to KI3 is performed. Bits 2 and 3 of the external interrupt input control register are the key input interrupt pin select bits. By setting these bits, the combination of key input interrupt pins can be selected. The interrupt vector ad- dresses and interrupt control register of the key input interrupt are common to those of the INT 3 interrupt. Additionally, pullup resistors (transistors) can be added to pins KI0 to KI4 by setting as follows:

• Set bit 1 of the external interrupt input control register to “1”.
• Next, select the key input interrupt pins by bits 2 and 3 of the exter- nal interrupt input control register.
• Then, clear the contents of the port direction register which corre- sponds to the selected pins to “0”. Pullup transistor Pullup transistor Pullup transistor P54/KI0 Port P56 direction register Key input interrupt pin pullup select bit P56/KI2 KI2 enable signal (Note) INT3 interrupt request INT3 interrupt control register Key input interrupt pin pullup select bit P57/KI3 Port P57 direction register KI3 enable signal (Note) P57/KI3 Interrupt control circuit Note: KIi enable signal (i = 0 to 3) means a signal which becomes “1” when the key input interrupt select bit = “1” and pin KIi is selected by the key input interrupt pin select bits.
• Port P5j direction register : bit j (j = 4 to 7) at address D16
• INT3 interrupt control register : address 6E16
• Key input interrupt select bit : bit 0 at address 9416
• Key input interrupt pin pullup select bit : bit 1 at address 9416
• Pin INT3 select bit : bit 5 at address 94 16 P74/(INT3) P80/INT3 Pin INT3 select bit Key input interrupt select bit Port P55 direction register Key input interrupt pin pullup select bit P55/KI1 KI1 enable signal (Note) Port P54 direction register Key input interrupt pin pullup select bit KI0 enable signal (Note) Pullup transistor Fig. 39 Block diagram of INT3/key input interrupt input circuit

M37902FCCHP, M37902FGCHP, M37902FJCHP MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Fig. 40 Bit configuration of external interrupt input control register 76543210 External interrupt input control register Key input interrupt select bit 0: INT3 interrupt 1: Key input interrupt Pin INT2 select bit 0: Allocate pin INT2 to P64. 1: Allocate pin INT2 to P77 (Note 2). Key input interrupt pin select bits (Note 1) 0 0: Pins KI0 to KI3 0 1: Pins KI0 to KI2 1 0: Pins KI0 and KI1 1 1: Pin KI0 Address 9416 At reset 0016 Key input interrupt pin pullup select bit 0: Pins KI 0 to KI3 are not pulled up. 1: Pins KI0 to KI3 are pulled up. Pin INT3 select bit (Note 3) 0: Allocate pin INT3 to P80. 1: Allocate pin INT3 to P74. Pin INT4 select bit 0: Allocate pin INT4 to P84. 1: Allocate pin INT4 to P75 (Note 4). Fix this bit to “0”. Notes 1: When using pin KIi, do not select timer A’s output pins and pulse output pins which are multiplexed with pin KIi. 2: When pin INT2 is allocated to P77, do not use pin AN7/ADTRG . Additionally, clear the D-A1 output enable bit (bit 1 at address 9616) to “0” (output disabled). 3: When pin INT3 is allocated to P80, clear the D-A2 output enable bit (bit 2 at address 9616) to “0” (output disabled). When pin INT3 is allocated to P74, do not use pin AN4. 4: When pin INT4 is allocated to P75, do not use pin AN5.

start bit is “0”, “L” is output from TAiOUT pin. 4 is “0”, TAiIN can be used as a normal port pin. can be used to measure the pulse width of the TAiIN input signal. more cycles of the timer count source. same data is also written to the reload register and the counter. 1 0 : Count only while TAiIN input is “L”. 1 1 : Count only while TAiIN input is “H ”. 0 : Always “0” in timer mode. Note: When using pins TA2OUT and TA3OUT as pulse output pins, do not select pins KI0 and KI2. Because they are key input interrupt pins and are multiplexed with pins TA2OUT and TA3OUT . Table 12. Relationship between timer A clock division select bits, timer A clock division select bits.

M37902FCCHP, M37902FGCHP, M37902FJCHP MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Fig. 44 Bit configuration of count start register Fig. 45 Count waveform when gate function is available 76543210 Timer A0 count start bit Timer A1 count start bit Timer A2 count start bit Timer A3 count start bit Timer A4 count start bit Timer B0 count start bit Timer B1 count start bit Timer B2 count start bit Count start register (Stop at “0”, Start at “1”) Address Selected clock source fi TAiIN Bit 4 Bit 3 Timer mode register Bit 4 Bit 3 Timer mode register

M37902FCCHP, M37902FGCHP, M37902FJCHP MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER (2) Event counter mode [01] Figure 46 shows the bit configuration of the timer Ai mode register during event counter mode. In event counter mode, bit 0 of the timer Ai mode register must be “1” and bits 1 and 5 must be “0”. The input signal from the TAi IN pin is counted when the count start bit shown in Figure 44 is “1” and counting is stopped when it is “0”. Count is performed at the fall of the input signal when bit 3 is “0” and at the rise of the signal when it is “1”. In event counter mode, whether to increment or decrement the count can be selected with the up-down bit or the input signal from the TAi OUT pin. When bit 4 of the timer Ai mode register is “0”, the up-down bit is used to determine whether to increment or decrement the count (decrement when the bit is “0” and increment when it is “1”). Figure 47 shows the bit configuration of the up-down register. When bit 4 of the timer Ai mode register is “1”, the input signal from the TAi OUT pin is used to determine whether to increment or decre- ment the count. However, note that bit 2 must be “0” if bit 4 is “1.” It is because if bit 2 is “1”, TAiOUT pin becomes an output pin to output pulses. The count is decremented when the input signal from the TAi OUT pin is “L” and incremented when it is “H ”. Determine the level of the input signal from the TAiOUT pin before a valid edge is input to the TAiIN pin. An interrupt request signal is generated and the interrupt request bit in the timer Ai interrupt control register is set when the counter reaches 0000 16 (decrement count) or FFFF16 (increment count). At the same time, the contents of the reload register is transferred to the counter and the count is continued. When bit 2 is “1,” each time the counter reaches 000016 (decrement count) or FFFF16(increment count), the waveform’s polarity is re- versed and is output from TAiOUT pin. If bit 2 is “0”, TAiOUT pin can be used as a normal port pin. However, if bit 4 is “1” and the TAiOUT pin is used as an output pin, the output from the pin changes the count direction. Therefore, bit 4 must be “0” unless the output from the TAiOUT pin is to be used to se- lect the count direction. Fig. 46 Bit configuration of timer Ai mode register during event counter mode Fig. 47 Bit configuration of up-down register 76543210 100×× 0 1 : Always “01” in event counter mode 0 : No pulse output 1 : Pulse output 0 : Count at the falling edge of input signal 1 : Count at the rising edge of input signal 0 : Increment or decrement according to up/down bit 1 : Increment or decrement according to TAi OUT pin input signal level 0 : Always “0” in event counter mode × × : Not used in event counter mode Timer A0 mode register Timer A1 mode register Timer A2 mode register Timer A3 mode register Timer A4 mode register Addresses 5716 5816 5916 5A16 Note: When using pins TA2OUT and TA3OUT as pulse output pins, do not select pins KI0 and KI2. Because they are key input interrupt pins and are multiplexed with pins TA2OUT and TA3OUT . Timer A0 up-down bit Timer A1 up-down bit Timer A2 up-down bit Timer A3 up-down bit Timer A4 up-down bit Timer A2 two-phase pulse signal processing select bit 0 : Two-phase pulse signal processing disabled 1 : Two-phase pulse signal processing mode Timer A3 two-phase pulse signal processing select bit 0 : Two-phase pulse signal processing disabled 1 : Two-phase pulse signal processing mode Timer A4 two-phase pulse signal processing select bit 0 : Two-phase pulse signal processing disabled 1 : Two-phase pulse signal processing mode Up-down register

76543210 Address

M37902FCCHP, M37902FGCHP, M37902FJCHP MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER nored. (See Figure 50.) Note that bits 5, 6, and 7 of the up-down reg- ister (address 4416) are the two-phase pulse signal processing se- lect bits for timers A2, A3 and A4 respectively. Each timer operates in normal event counter mode when the corresponding bit is “0” and performs two-phase pulse signal processing when it is “1”. Count is started by setting the count start bit to “1”. Data write and read are performed in the same way as for normal event counter mode. Note that the direction register of the input port must be set to input mode because two kinds of pulse signals, described above, are input. Also, there can be no pulse output in this mode. Data write and data read are performed in the same way as for timer mode. That is, when data is written to timer Ai halted, it is also writ- ten to the reload register and the counter. When data is written to timer Ai which is busy, the data is written to the reload register, but not to the counter. The counter is reloaded with new data from the reload register at the next reload time. The counter can be read at any time. In event counter mode, whether to increment or decrement the counter can also be determined by supplying two kinds of pulses of which phases differ by 90° to timer A2, A3, or A4. There are two types of two-phase pulse processing operations. One uses timers A2 and A3, and the other uses timer A4. In both processing operations, two pulses described above are input to the TA jOUT (j = 2 to 4) pin and TAjIN pin respectively. When timers A2 and A3 are used, as shown in Figure 48, the count is incremented when a rising edge is input to the TAk IN pin after the level of TAkOUT (k=2, 3) pin changes from “L” to “H ”, and when the falling edge is input, the count is decremented. For timer A4, as shown in Figure 49, when a phase-related pulse with a rising edge input to the TA4 IN pin is input after the level of TA4OUT pin changes from “L” to “H ”, the count is incremented at the respective rising edge and falling edge of the TA4OUT pin and TA4IN pin. When a phase-related pulse with a falling edge input to the TA4OUT pin is input after the level of TA4IN pin changes from “H ” to “L”, the count is decremented at the respective rising edge and falling edge of the TA4 IN pin and TA4OUT pin. When performing this two-phase pulse signal processing, timer Aj mode register bit 0 and bit 4 must be set to “1” and bits 1, 2, 3, and 5 must be “0”. Bits 6 and 7 are ig- Fig. 50 Bit configuration of timer Aj mode register when performing two-phase pulse signal processing in event counter mode Fig. 48 Two-phase pulse processing operation of timers A2 and A3 Fig. 49 Two-phase pulse processing operation of timer A4 76543210 100010×× 0 1 : Always “01” in event counter mode 0 1 0 0 : Always “0100” when processing two-phase pulse signal × × : Not used in event counter mode Timer A2 mode register Timer A3 mode register Timer A4 mode register Addresses 5916 5A16 TAkOUT TAkIN (k = 2, 3) Increment- count Increment- count Increment- count Decrement- count Decrement- count Decrement- count TA4 OUT TA4 IN Decrement-count at each edgeIncrement-count at each edge Decrement-count at each edgeIncrement-count at each edge

M37902FCCHP, M37902FGCHP, M37902FJCHP MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Fig. 53 Pulse output example when external rising edge is selected Fig. 54 Example when trigger is re-issued during pulse output Selected clock source fi TAiIN (rising edge) TAiOUT Example when the contents of the reload register is 000316 Selected clock source fi TAiIN (rising edge) TAiOUT Example when the contents of the reload register is 000416

M37902FCCHP, M37902FGCHP, M37902FJCHP MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER (4) Pulse width modulation mode [11] Figure 55 shows the bit configuration of the timer Ai mode register during pulse width modulation mode. In pulse width modulation mode, bits 0, 1, and 2 must be set to “1”. Bit 5 is used to determine whether to perform 16-bit length pulse width modulator or 8-bit length pulse width modulator. 16-bit length pulse width modulator is selected when bit 5 is “0” and 8-bit length pulse width modulator is selected when it is “1”. The 16-bit length pulse width modulator is described first. The pulse width modulator can be started with a software trigger or with an input signal from a TAi IN pin (external trigger). The software trigger mode is selected when bit 4 is “0”. Pulse width modulator is started and a pulse is output from TAiOUT when the count start bit is set to “1”. The external trigger mode is selected when bit 4 is “1”. Pulse width modulation starts when a trigger signal is input from the TAi IN pin when the count start bit is “1”. Whether to trigger at the fall or rise of the trigger signal is determined by bit 3. The trigger is at the fall of the trigger signal when bit 3 is “0” and at the rise when it is “1”. When data is written to timer Ai with the pulse width modulator halted, it is written to the reload register and the counter. Then when the count start bit is set to “1” and a software trigger or an external trigger is issued to start modulation, the waveform shown in Figure 56 is output continuously. Once modulation is started, triggers are not accepted. If the value in the reload register is m, the duration “H ” of pulse is × m and the output pulse period is × (2 16 –1). An interrupt request signal is generated and the interrupt request bit in the timer Ai interrupt control register is set at each fall of the output pulse. The width of the output pulse is changed by updating timer data. The update can be performed at any time. The output pulse width is changed at the rise of the pulse after data is written to the timer. The contents of the reload register are transferred to the counter just before the rise of the next pulse so that the pulse width is changed from the next output pulse. Undefined data is read when timer Ai is read. The 8-bit length pulse width modulator is described next. The 8-bit length pulse width modulator is selected when the timer Ai mode register bit 5 is “1”. The reload register and the counter are both divided into 8-bit halves. selected clock frequency selected clock frequency The low-order 8 bits function as a prescaler and the high-order 8 bits function as the 8-bit length pulse width modulator. The prescaler counts the clock selected by bits 6, 7, and the contents of the timer A clock division select register. (See Table 12.) A pulse is generated when the counter reaches 0000 16 as shown in Figure 57. At the same time, the contents of the reload register is transferred to the counter and count is continued. Fig. 55 Bit configuration of timer Ai mode register during pulse width modulation mode 76543210 111 1 1 : Always “11” in pulse width modulation mode 1 : Always “1” in pulse width modulation mode 0 × : Software trigger 1 0 : Trigger at the falling of TAi IN input 1 1 : Trigger at the rising of TAiIN input 0 : 16-bit pulse width modulator 1 : 8-bit pulse width modulator Clock source select bits (See Table 12.) Timer A0 mode register Timer A1 mode register Timer A2 mode register Timer A3 mode register Timer A4 mode register Addresses 5716 5816 5916 5A16

M37902FCCHP, M37902FGCHP, M37902FJCHP MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER high-order 8 bits of the reload register are m, the duration “H ” of pulse is And the output pulse period is selected clock frequency Therefore, if the low-order 8 bits of the reload register are n, the pe- riod of the generated pulse is × (n+1). The high-order 8 bits function as an 8-bit length pulse width modula- tor using this pulse as input. The operation is the same as for 16-bit length pulse width modulator except that the length is 8 bits. If the selected clock frequency selected clock frequency Fig. 56 16-bit length pulse width modulator output pulse example Fig. 57 8-bit length pulse width modulator output pulse example Selected clock source fi TAiIN (rising edge) TAiOUT 1/fi × (216 – 1) 1/fi × (m) This trigger is not accepted Example when the contents of the reload register is 000316 Selected clock source fi TAiIN (falling edge) Prescaler output (when n = 2) 8-bit length pulse width modulator output (when m = 2) 8 – 1) 1/fi × (n + 1) × (n+1) × m. × (n+1) × (28–1).

M37902FCCHP , M37902FGCHP, M37902FJCHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS When timer Bi is read, the contents of the reload register is read. Note that in this mode, the interval between the fall of the TBiIN pin input signal to the next rise or from the rise to the next fall must be at least two cycles of the timer count source. Timer Bi overflow flag which is bit 5 of timer Bi mode register is set to “1” when the timer Bi counter reaches 0000 16, which indicates that a pulse width or pulse period is longer than that which can be mea- sured by a 16-bit length. This flag is cleared by writing data to the corresponding timer Bi mode register. This flag is set to “1”at reset. Fig. 62 Pulse period measurement mode operation (example of measuring the interval between the falling edge to next falling one) Fig. 63 Pulse width measurement mode operation Selected clock source fi TBiIN Reload register ← Counter Counter ← 0 Count start bit Interrupt request signal Selected clock source fi TBiIN Reload register ← Counter Counter ← 0 Count start bit Interrupt request signal

M37902FCCHP, M37902FGCHP, M37902FJCHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS Serial I/O mode select bits 0 0 0 : Serial I/O is invalid. (Port P8 functions as a programmable I/O port.) 0 0 1 : Clock synchronous 1 0 0 : 7-bit UART 1 0 1 : 8-bit UART 1 1 0 : 9-bit UART Internal/External clock select bit 0 : Internal clock 1 : External clock Stop bit length select bit (Valid in UART mode.) 0 : 1 stop bit 1 : 2 stop bits Odd/Even parity select bit (Valid in UART mode with the parity enable bit = “1”.) (Note) 0 : Odd parity 1 : Even parity Parity enable bit (Valid in UART mode) (Note) 0 : No parity 1 : With parity Sleep select bit (Valid in UART mode) (Note) 0 : No sleep 1 : Sleep

76543210 UART 0 Transmit/Receive mode register

UART 1 Transmit/Receive mode register Addresses 3816 Note: In the clock synchronous serial I/O mode, bits 4 to 6 are invalid. (Each of them may be “0” or “1”.) Furthermore, fix bit 7 to “0”. SERIAL I/O PORTS Two independent serial I/O ports are provided. Figure 64 shows a block diagram of the serial I/O ports. Bits 0 to 2 of the UARTi(i = 0,1) transmit/receive mode register shown in Figure 65 are used to determine whether to use port P8 as a programmable I/O port, clock synchronous serial I/O port, or asyn- chronous (UART) serial I/O port which uses start and stop bits. Figures 66 and 67 show the block diagrams of the receiver/transmit- ter . Figure 68 shows the bit configuration of the UARTi transmit/receive control register. Each communication method is described below. Fig. 65 Bit configuration of UARTi transmit/receive mode register Fig. 64 Block diagram of serial I/O port UARTi receive register TXD i R XD i Receive control circuit Transmit control circuit UARTi transmit register 1/16 divider 1/2 divider 1/(n + 1) divider 1/16 divider Transfer clock Transfer clock UARTi transmit buffer register UART Clock synchronous Clock synchronous Clock synchronous (when internal clock selected) BRG count source select bits f16 f64 f512 Clock synchronous (Internal clock) UART D 7 D 6 D 5 D 4 D 3 D 2 D 1 UARTi receive buffer registerD 0 D 7D 8 D 6 D 5 D 4 D 3 D 2 D 1 D 0 0D 8000000 BRGi UART0 (Addresses 3316, 3216) UART1 (Addresses 3B16, 3A16) UART0 (Addresses 3716, 3616) UART1 (Addresses 3F16, 3E16) CTS i/RTSi Clock synchronous (External clock) n = a value set into the UARTi baud rate register (BRGi) CLK i CTS i CTS i/CLKi Data bus (even) Data bus (odd) Bit converter Data bus (odd) Data bus (even) Bit converter

M37902FCCHP, M37902FGCHP, M37902FJCHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS Data bus (odd) Data bus (even) D 0D 1D 2D 3D 4D 5D 6D 7D 8 SP SP PAR No parity UARTi receive register R XD i UARTi receive buffer register 9-bit UART 7-bit UART7-bit UART 8-bit UART Synchronous UART 8-bit UART 9-bit UART Synchronous Synchronous Parity2SP 1SP 0000000 SP : Stop bit PAR : Parity bit Fig. 66 Block diagram of receiver Fig. 67 Block diagram of transmitter D 0D 1D 2D 3D 4D 5D 6D 7D 8 SP PAR TXD i 2SP SP 1SP UART Data bus (odd) Data bus (even) No parity 7-bit UART 9-bit UART Synchronous 7-bit UART 8-bit UART 9-bit UART Synchronous 8-bit UART Synchronous Parity SP : Stop bit PAR : Parity bit UARTi transmit register UARTi receive transmit register

M37902FCCHP, M37902FGCHP, M37902FJCHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS Fig. 68 Bit configuration of UARTi transmit/receive control register /LSB MSB TX EPTY 76543210 R/C CS 1 CS 0 BRG count source select bits 00 : f2 01 : f16 10 : f64 11 : f512 CTS/RTS function select bit (Note 1) 0 : CTS function is selected. 1 : RTS function is selected. Transmit register empty flag 0 : Data is present in the transmit register. (Transmission is in progress.) 1 : No data is present in the transmit register. (Transmission is completed.) CTS/RTS enable bit 0 : CTS, RTS function is enabled. 1 : CTS, RTS function is disabled. UARTi receive interrupt mode select bit 0 : Reception interrupt 1 : Reception error interrupt CLK polarity select bit (This bit is used in the clock synchronous serial I/O mode.) (Note 2) 0 : At the falling edge of a transfer clock, transmit data is output; at the rising edge, receive data is input. When not in transfer, pin CLK’s level is “H ”. 1 : At the rising edge of a transfer clock, transmit data is output; at the falling edge, receive data is input. When not in transfer, pin CLK’s level is “L”. Transfer format select bit (This bit is used in the clock synchronous serial I/O mode.) (Note 2) 0 : LSB (Least Significant Bit) first 1 : MSB (Most Significant Bit) first 76543210 RERIOERFERPERSUM TI TE Transmit enable bit Transmit buffer empty flag Receive enable bit Receive complete flag Overrun error flag Framing error flag (Note 3) Parity error flag (Note 3) Error sum flag (Note 3) UART0 transmit/receive control register 0 UART1 transmit/receive control register 0 Address 3C 16 UART0 transmit/receive control register 1 UART1 transmit/receive control register 1 Address 3D 16 CPL Notes 1: Valid when the CTS/RTS enable bit (bit 4) = “0”. 2: Fix these bits to “0” in UART mode or when serial I/O is invalid. 3: Valid in UART mode.

M37902FCCHP, M37902FGCHP, M37902FJCHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS CLOCK SYNCHRONOUS SERIAL COMMUNI- CATION A case where communication is performed between two clock syn- chronous serial I/O ports as shown in Figure 69 will be described. (The transmission side will be denoted by subscript j and the receiv- ing side will be denoted by subscript k.) Bit 0 of the UARTj transmit/receive mode register and UARTk trans- mit/receive mode register must be set to “1” and bits 1 and 2 must be “0”. The length of the transmission data is fixed at 8 bits. Bit 3 of the UARTj transmit/receive mode register of the clock send- ing side is cleared to “0” to select the internal clock. Bit 3 of the UARTk transmit/receive mode register of the clock receiving side is set to “1” to select the external clock. Bits 4, 5 and 6 are ignored in clock synchronous mode. Bit 7 must always be “0”. The clock source is selected by bit 0 (CS 0) and bit 1 (CS1) of the clock-sending-side UARTj transmit/receive control register 0. As shown in Figure 64, the selected clock is divided by (n+1), then by 2, is passed through a transmission control circuit, and is output as transmission clock CLKj. Therefore, when the selected clock is fi, Bit Rate = f i/ {(n + 1) × 2} On the clock receiving side, the CS0 and CS1 bits of the UARTk transmit/receive control register 0 are ignored because an external clock is selected. Both of UART0 and UART1 can use CTS and RTS functions. Bit 4 of the UARTi transmit/receive control register 0 is used to de- termine whether to use CTS or RTS signal. Bit 4 must be “0” when CTS or RTS signal is used. Bit 4 must be “1” when CTS and RTS sig- nals are not used. When CTS and RTS signals are not used, CTS/ RTS pin can be used as a normal port pin. When using pin CTS/RTS, :

• If bit 2 of the UARTi transmit/receive control register 0 is cleared to “0”, CTS input is selected.
• If bit 2 is set to “1”, RTS output is selected. The case using CTS and RTS signals are explained below. As shown in Figure 76, bits 2 and 3 of the serial I/O pin control register can determine whether port pins P8 3 and P87 are used as pins TxDi or as port pins. When bits 2 and 3 are “0”, P83 and P87 function as pins TxDi; when bits 2 and 3 are “1”, P83 and P87 function as port pins. Therefore, in the input-only system where pins TxDi are not used, pins TxDi can function as port pins. Fig. 69 Clock synchronous serial communication UARTj transmit register TxDj RxDj CLKj CTSj UARTj transmit buffer register UARTj receive buffer register UARTj receive register UARTj Transmit/Receive mode register UARTj Transmit/Receive control register 0 UARTj Transmit/Receive control register 1 00 0 0TX EPTY CS 1 CS 0 RERIOERFERPER CPL CPL SUM TI TE UARTk transmit register UARTk transmit buffer register UARTk receive buffer register UARTk receive register UARTk Transmit/Receive mode register UARTk Transmit/Receive control register 0 UARTk Transmit/Receive control register 1 01 1 0 1TX EPTY MSB /LSB RERIOERFERPERSUM TI TE TxDk RxDk CLKk RTSk MSB /LSB

M37902FCCHP, M37902FGCHP, M37902FJCHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS Transmission Transmission is started when bit 0 (TEj flag: transmit enable bit) of UARTj transmit/receive control register 1 is “1”, bit 1 (TIj flag) of one is “0”, and CTSj input is “L”. The TIj flag indicates whether the trans- mit buffer register is empty or not. It is cleared to “0” when data is written in the transmit buffer register ; it is set to “1” when the con- tents of the transmit buffer register is transferred to the transmit reg- ister and the transmit buffer register becomes empty. When all of the transmit conditions are satisfied, the transmit data in the transmit buffer register are transferred to the transmit register, and transmission starts. As shown in Figure 70, data is output from T XDj pin each time when transmission clock CLKj changes from “H ” to “L”. (In the clock synchronous serial I/O mode, the polarity of a transfer clock can be changed. For details, refer to the section on the selection of the transfer clock polarity.) The data is output from the least significant bit. When the transmit register becomes empty after the contents has been transmitted, data is transferred automatically from the transmit buffer register to the transmit register if the next transmission start condition is satisfied. The next transmission is performed succeedingly. Once transmission has started, the TEj flag, TIj flag, and CTSj signals are ignored until data transmission completes. Therefore, transmission is not interrupt when CTSj input is changed to “H ” during transmission. The transmission start condition indicated by TEj flag, TIj flag, and CTSj is checked while the TEND j signal (shown in Figure 70) is “H ”. Therefore, data can be transmitted continuously if the next transmis- sion data is written in the transmit buffer register and TIj flag is cleared to “0” before theT END j signal goes “H ”. Bit 3 (TXEPTYj flag) of UARTj transmit/receive control register 0 changes to “1” at the next cycle just after the TEND j signal goes “H ” and changes to “0” when transmission starts. Therefore, this flag can be used to determine whether data transmission has completed. When the TIj flag changes from “0” to “1”, the interrupt request bit in the UARTj transmit interrupt control register is set to “1”. Receive When bit 2 of the UARTk transmit/receive control register 1 is set to “1”, reception becomes enabled. In this case, when the CLKk signal is input, the receive operation starts simultaneously with this signal. The RTSk output is “H ” when the REK flag is “0”. When the REK flag is set to “1”, the RTSk output becomes “L”. This informs the transmit- ter side that reception becomes enabled. When the receive opera- tion starts, the RTSk output automatically becomes “H ”. When the receive operation starts, the receiver takes data from pin RxDk each time when the transmit clock (CLKj) turns from “L” to “H ”. Simultaneously with reception, the contents of the receiver register is shifted bit by bit. (Note that, in the clock synchronous serial communication, the polar- ity of a transfer clock can be inverted. For details, refer to the section on the polarity of the transfer clock.) When an 8-bit data is received, the contents of the receive register is transferred to the receive buffer register and bit 3 (RIk flag) of UARTk transmit/receive control regis- ter 1 is set to “1”. In other words, the setting “1” to the RIk flag indi- cates that the receive buffer register contains the received data. At this time, if the low-order byte of the UARTk receive buffer register is read out, the RTSk output turns back to “L”. This indicates that the next data reception becomes enabled. Bit 4 (OERk flag) of UARTk transmit/receive control register 1 is set to “1” when the next data is transferred from the receive register to the receive buffer register while RIk flag is “1”, and indicates that the next data was transferred to the receive register before the contents of the receive buffer regis- ter was read. (In other words, this indicates that an overrun error has occurred.) RIk flag is automatically cleared to “0” when the low-order byte of the receive buffer register is read or when the REk flag is cleared to “0”. The OERk flag is cleared when the REk flag is cleared. Bit 5 (FERk flag), bit 6 (PERk flag), and bit 7 (SUMk flag) are ignored in clock synchronous mode. As shown in Figure 64, with clock synchronous serial communica- tion, data cannot be received unless the transmitter is operating be- cause the receive clock is created from the transmission clock. Therefore, the transmitter must be operating even when there is no need to sent data from UARTk to UARTj.

M37902FCCHP, M37902FGCHP, M37902FJCHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS Transmission clock TE j 1/fi × (n + 1) × 2 1/fi × (n + 1) × 2 TIj CTS j Write in transmit buffer register D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7 D 1 D 2 D 3 D 4 D 5 D 6 D 7 D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7D 0 Transmit register ← Transmit buffer register Stopped because TEj = “0” CLK j TENDj TXD j TXEPTY j Fig. 70 Clock synchronous serial I/O timing Interrupt request at completion of reception When the RIk flag changes from “0” to “1”, in other words, when the receive operation is completed, the interrupt request bit of the UARTk receive interrupt control register can be set to “1”. The timing when this interrupt request bit is to be set to “1” can be selected from the following:

• Each reception
• When an error occurs at reception If bit 5 of the UARTk transmit/receive control register 0 (UART re- ceive interrupt mode select bit) is cleared to “0”, the interrupt request bit is set to “1” at each reception. If bit 5 is set to “1”, the interrupt re- quest bit is set to “1” only when an error occurs. (In the clock syn- chronous serial communication, only when an overrun error occurs, the interrupt request bit is set to “1”.) Polarity of transfer clock In the clock synchronous serial communication, by bit 6 of the UARTj transmit/receive control register 0 (CPL), the polarity of a transfer clock can be selected. As shown in Figure 71, when bit 6 = “0”, the polarity is as follows:
• In transmission, transmit data is output at the falling edge of CLKj.
• In reception, receive data is input at the rising edge of CLKk.
• When not in transfer, CLKi is at “H ” level. When bit 6 = “1”, the polarity is as follows:
• In transmission, transmit data is output at the rising edge of CLKj.
• In reception, receive data is input at the rising edge of CLKk.
• When not in transfer, CLKi is at “L” level.

M37902FCCHP, M37902FGCHP, M37902FJCHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS Fig. 71 Polarity of transfer clock I CLK polarity select bit = 0 CLK i TxD i RxD i D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7 D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7 ❇ Transmit data is output to pin TxDi at the falling edge of transfer clock, and receive data is input from pin RxDi at the rising edge of transfer clock. When not in transfer, pin CLKi’s level is “H ”. I CLK polarity select bit = 1 CLK i TxD i RxD i D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7 D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7 ❇ Transmit data is output to pin TxDi at the rising edge of transfer clock, and receive data is input from pin RxDi at the falling edge of transfer clock. When not in transfer, pin CLKi’s level is “L”.

M37902FCCHP, M37902FGCHP, M37902FJCHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS Selection of transfer format In clock synchronous serial communication, transfer format can be selected by bit 7 of the transmit/receive control register 0. When bit 7 is “0”, transfer format is LSB first. When bit 7 is “1”, transfer format is MSB first. This function is realized by changing connection relation between the transmit buffer register and the receive buffer register when writ- ing transmit data to the transmit buffer register or reading receive data from the receive buffer register. Accordingly, the transmitter’s operation is the same in both transfer formats. Figure 72 shows the connection relation. Fig. 72 Connection relation between transmit buffer register, receive buffer register, and data bus Bit 7 in transmit/receive control register 0 Write to transmit buffer register Read from receive buffer register (LSB first) (MSB first) Transmit buffer register DB 7 Data bus D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 DB 6 DB 5 DB 4 DB 3 DB 2 DB 1 DB 0 Transmit buffer register DB 7 Data bus D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 DB 6 DB 5 DB 4 DB 3 DB 2 DB 1 DB 0 Receive buffer register DB 7 Data bus D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 DB 6 DB 5 DB 4 DB 3 DB 2 DB 1 DB 0 Receive buffer register DB 7 Data bus D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 DB 6 DB 5 DB 4 DB 3 DB 2 DB 1 DB 0 Precautions for clock synchronous serial communication When using pin CTS0/RTS0, be sure to clear the D-A2 output enable bit (bit 2 at address 9616) to “0” (output disabled). Also, in the clock synchronous serial communication, the separate function for CTSi/ RTSi cannot be selected. Furthermore, when an internal clock is se- lected, RTS output is undefined. Therefore, do not use the RTS func- tion. Before transmit operation is performed, be sure to clear bits 2 and 3 of the serial I/O pin control register (address AC 16) to “00”.

M37902FCCHP, M37902FGCHP, M37902FJCHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS Fig. 73 Transmit timing example when 8-bit asynchronous communication with parity and 1 stop bit selected Fig. 74 Transmit timing example when 9-bit asynchronous communication with no parity and 2 stop bits selected ASYNCHRONOUS SERIAL COMMUNICATION Asynchronous serial communication can be performed using 7-, 8-, or 9-bit length data. The operation is the same for all data lengths. The following is the description for 8-bit asynchronous communication. With 8-bit asynchronous communication, bit 0 of UARTi transmit/re- ceive mode register is “1”, bit 1 is “0”, and bit 2 is “1”. Bit 3 is used to select an internal clock or an external clock. If bit 3 is “0”, an internal clock is selected and if bit 3 is “1”, then external clock is selected. If an internal clock is selected, bit 0 (CS 0) and bit 1 (CS1) of UARTi transmit/receive control register 0 are used to select the clock source. When an internal clock is selected for asynchronous serial communication, the CLKi pin can be used as a normal I/O pin. The selected internal or external clock is divided by (n+1), then by 16, and is passed through a control circuit to create the UART trans- mission clock or UART receive clock. Therefore, the transmission speed can be changed by changing the contents (n) of the bit rate generator. If the selected clock is an inter- nal clock Pfi or an external clock f EXT , Bit Rate = (fi or fEXT ) / {(n+1)×16} Bit 4 is the stop bit length select bit to select 1 stop bit or 2 stop bits. Bit 5 is a select bit of odd parity or even parity. In the odd parity mode, the parity bit is adjusted so that the sum of 1s in the data and parity bit is always odd. In the even parity mode, the parity bit is adjusted so that the sum of the 1s in the data and parity bit is always even. Bit 6 is the parity bit select bit which indicates whether to add parity bit or not. Bits 4 to 6 must be set or reset according to the data format used in the communicating devices. Bit 7 is the sleep select bit. The sleep mode is described later. Figure 76 shows the bit configuration of the serial I/O pin control reg- ister. By bits 0 and 1 of the serial I/O pin control register (CTSi/RTSi separate select bits), the function of the CTS/RTS pin can be sepa- rated into two functions, and each function can be assigned to two different pins. When bits 0 and 1 = “11”, the above separation is per- formed. When bits 0 and 1 = “00”, no separation is performed. Table 13 lists the selection methods of the CTS/RTS function. (1/fi or 1/fEXT ) × (n + 1) × 16 Written in transmit buffer register Transmission clock TE i TIi CTS i TENDi TXD i TXEPTY i D 0 D 1ST Start bit Parity bit Stop bit D 2 D 3 D 4 D 5 D 6 D 7 PS P S T D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7 PS P S T D 0 D 1 Transmit register ← Transmit buffer register Stopped because TEi = “0” (1/fi or 1/fEXT ) × (n + 1) × 16 Written in transmit buffer register Transmission clock TE i TIi TENDi TXD i TXEPTY i D 0 D 1ST D 2 D 3 D 4 D 5 D 6 D 7 D 8 SPSP ST D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7 D 8 SP SP ST D 0 D 2D 1 Transmit register ← Transmit buffer register Stopped because TEi = “0”Start bit Stop bit Stop bit

M37902FCCHP, M37902FGCHP, M37902FJCHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS Once transmission has started, the TEi flag, TIi flag, and CTSi signal are ignored until data transmission is completed. Therefore, transmission does not stop until it completes event if, dur- ing transmission, the TEi flag is cleared to “0” or CTSi input is set to “1”. The transmission start condition indicated by TEi flag, TIi flag, and CTSi is checked while the TEND i signal shown in Figure 73 is “H ”. Therefore, data can be transmitted continuously if the next transmis- sion data is written in the transmit buffer register and TIi flag is cleared to “0” before the T END i signal goes “H ”. Bit 3 (TXEPTYi flag) of UARTi transmit/receive control register 0 changes to “1” at the next cycle just after the TEND i signal goes “H ” and changes to “0” when transmission starts. Therefore, this flag can be used to determine whether data transmission is completed. When the TIi flag changes from “0” to “1”, the interrupt request bit of the UARTi transmit interrupt control register is set to “1”. Transmission Transmission is started when bit 0 (TEi flag transmit enable flag) of UARTi transmit/receive control register 1 is “1”, bit 1 (TIi flag) is “0”, and CTSi input (in other words, transmit enable signal input from re- ceiver) is “L.” The TIi flag indicates whether the transmit buffer is empty or not. It is cleared to “0” when data is written in the transmit buffer; it is set to “1” when the contents of the transmit buffer register is transferred to the transmit register. When all of the transmission conditions are satisfied, transmit data is transferred to the transmit register, and transmit operation starts. As shown in Figures 73 and 74, data is output from the T XDi pin with the stop bit or parity bit specified by bits 4 to 6 of UARTi transmit/re- ceive mode register. The data is output from the least significant bit. When the transmit register becomes empty after the contents has been transmitted, data is transferred automatically from the transmit buffer register to the transmit register if the next transmit start condi- tion is satisfied. Then, the next transmission is performed succeedingly. Fig. 75 Receive timing example when 8-bit asynchronous communication with no parity and 1 stop bit selected Start bit Stop bit Start bit D 0 D 1 D 7 Check to be “L” level Starting at the falling edge of start bit Data fetched fi or fEXT RE i R XD i Receive clock RIi RTS i

Table 13. Selection methods of CTS/RTS function Notes 1: When using the CTS0/RTS0 pin, be sure to clear the D-A2 output enable bit (bit 2 at address 9616) to “0”. 2: When using the CTS function, be sure to clear the corresponding bit of the port P8 direction register to “0”. cannot be separated. Also, when CTSi and RTSi are separated in UART mode, be sure to select an internal clock. 0 : CTS0/RTS0 are used together. 1 : CTS0/RTS0 are separated. 0 : CTS1/RTS1 are used together. 1 : CTS1/RTS1 are separated. bit arrives and the data is received. receive operation starts, the RTSi output automatically becomes “H ”. the contents of the receive buffer register has been read. Bit 6 (PERi flag) is set to “1” when a parity error occurs. determine whether there is an error. the receive buffer register.

M37902FCCHP, M37902FGCHP, M37902FJCHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS The FERi, PERi, and SUMi flags are cleared to “0” when reading the low-order byte of the receive buffer register or when writing “0” to the REi flag. The OERi flag is cleared to “0” when writing “0” to the REi flag. Interrupt request at completion of reception When the RIk flag changes from “0” to “1”, in other words, when the receive operation is completed, the interrupt request bit of the UARTk receive interrupt control register can be set to “1”. The timing when this interrupt request bit is to be set to “1” can be selected from the following:

• Each reception
• When an error occurs at reception If bit 5 of the UARTk transmit/receive control register 0 (UART re- ceive interrupt mode select bit) is cleared to “0”, the interrupt request bit is set to “1” at each reception. If bit 5 is set to “1”, the interrupt request bit is set to “1” only when an error occurs. (In the clock asyn- chronous serial communication, when an overrun error, framing er- ror, or parity error occurs, the interrupt request bit is set to “1”.) Sleep mode The sleep mode is used to communicate only between certain micro- computers when multiple microcomputers are connected through serial I/O. The microcomputer enters the sleep mode when bit 7 of UARTi transmit/receive mode register is set to “1.” The operation of the sleep mode for an 8-bit asynchronous commu- nication is described below. When sleep mode is selected, the contents of the receive register is not transferred to the receive buffer register if bit 7 (bit 6 if 7-bit asyn- chronous communication and bit 8 if 9-bit asynchronous communi- cation) of the received data is “0”. Also the RIi, OERi, FERi, PERi, and the SUMi flags are unchanged. Therefore, the interrupt request bit of the UARTi receive interrupt control register is also unchanged. Normal receive operation takes place when bit 7 of the received data is “1”. The following is an example of how the sleep mode can be used. The main microcomputer first sends data: bit 7 is “1” and bits 0 to 6 are set to the address of the subordinate microcomputer to be com- municated with. Then all subordinate microcomputers receive this data. Each subordinate microcomputer checks the received data, clears the sleep bit to “0” if bits 0 to 6 are its own address and sets the sleep bit to “1” if not. Next, the main microcomputer sends data with bit 7 cleared. Then the microcomputer which cleared the sleep bit will receive the data, but the microcomputers which set the sleep bit to “1” will not. In this way, the main microcomputer is able to com- municate only with the designated microcomputer. Precautions for clock asynchronous (UART) serial communication When using pin CTS0/RTS0, be sure to clear the D-A2 output enable bit (bit 2 at address 9616) to “0” (output disabled). Also, when CTSi and RTSi are separated, pin CLKi cannot be used. Therefore, when CTSi and RTSi are separated in UART mode, be sure to select an internal clock. Before transmit operation is performed, be sure to clear bits 2 and 3 of the serial I/O pin control register (address AC 16) to “00”.

M37902FCCHP, M37902FGCHP, M37902FJCHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS A-D CONVERTER The A-D converter is a 10-bit successive approximation converter. Figure 77 shows the block diagram of the A-D converter, Figure 78 shows the bit configuration of the A-D control register 0 (address 1E16), and Figure 79 shows the bit configuration of the A-D control register 1 (address 1F16). A-D conversion accuracy Bit 3 of A-D control register 1 is used to select whether to regard the conversion result as 10-bit or as 8-bit data. The conversion result is regarded as 10-bit data when bit 3 is “1” and as 8-bit data when bit 3 is “0”. When the conversion result is used as 10-bit data, the low-order 8 bits of the conversion result is stored in the even address of the cor- responding A-D register and the high-order 2 bits are stored in bits 0 and 1 at the odd address of the corresponding A-D register. Bits 2 to 7 of the A-D register odd address are “000000 2” when read. Fig. 77 Block diagram of A-D converter When the conversion result is used as 8-bit data, the conversion re- sult are stored in even address of the corresponding A-D register. In this case, the value at the A-D register’s odd address is “0016” when read. A-D conversion frequency An operation clock (φAD ) of an A-D converter can be selected with bit 7 of the A-D control register 0 and bit 4 of the A-D control register 1. When bit 4 of the A-D control register 1 is “0”, φAD becomes f2/4 when bit 7 of the A-D control register 0 is “0”, φAD becomes f2/2 when bit 7 of the A-D control register 0 is “1”. When bit 4 of the A-D control register 1 is “1”, φAD becomes f2 when bit 7 of the A-D control register 0 is “0”, φAD becomes f1 when bit 7 of the A-D control register 0 is “1”. Note that φAD = f1 (in other words, the fastest speed) can be selected only in the 8-bit mode. φAD during A-D conversion must be 250 kHz or more because the comparator uses a capacity coupling amplifier. Comparator Resistor ladder network Selector AN 0 AN 1 AN 2 AN 3 AN 4 AN 5 AN 6 AN 7/ADTRG Vref Successive approximation register A-D register 0 A-D register 1 A-D register 2 A-D register 3 Data bus (odd) A-D control register 1 A-D control register 0 φAD A-D conversion frequency (φAD ) select bit 1,0 (1,1) A-D conversion frequency selection (1,0) (0,1) (0,0) Data bus (even) AV SS VREF VREF connection select bit A-D register 4 A-D register 5 A-D register 6 A-D register 7 Decoder

M37902FCCHP, M37902FGCHP, M37902FJCHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS Trigger A-D conversion can be started by an internal trigger or by an exter- nal trigger. An internal trigger is selected when bit 5 of A-D control register 0 is “0” and an external trigger is selected when it is “1”. When trigger is selected, A-D conversion is started when bit 6 (A-D conversion start bit) is set to “1.” When an external trigger is selected, the polarity of a trigger input can be selected by bit 5 of the A-D control register 1. When bit 5 = “0”, a falling edge is selected, and when bit 5 = “1”, a rising edge is selected. A-D conversion starts when the A-D conversion start bit is “1” and the AD TRG input changes from “H ” to “L” (or “L” to “H.”) In this case, the pins that can be used for A-D conversion are AN0 to AN6 because the AD TRG pin is multiplexed with an analog voltage input pin, AN7. If an Fig. 78 Bit configuration of A-D control register 0 external trigger is selected, even when the A-D conversion is com- pleted, the A-D conversion start bit keeps “1”. Also, a retrigger can be available even when A-D conversion is in progress. VREF connection Whether to connect the reference voltage input (VREF ) with the resis- tor ladder network or not depends on bit 6 of the A-D control register 1. The VREF pin is connected when bit 6 is “0” and is disconnected when bit 6 is “1” (High impedance state). When A-D conversion is not performed, current from the VREF pin to the resistor ladder network can be cut off by disconnecting resistor ladder network from the V REF pin. Before starting A-D conversion, wait for 1 µs or more after clearing bit 6 to “0”. A-D control register 0 Notes 1: Ignored in the single sweep and repeat sweep modes. (Each of these bits may be “0” or “1”.) 2: When using the AN4 pin, be sure to clear the INT3 pin select bit (bit 5 at address 9416) to “0”. 3: When using the AN5 pin, be sure to clear the INT4 pin select bit (bit 6 at address 9416) to “0”. 4: When using the AN6 pin, be sure to clear the D-A0 output enable bit (bit 0 at address 9616) to “0” (output disabled). 5: When using the AN7 pin, be sure to clear both of the INT2 pin select bit (bit 4 at address 9416) and the D-A1 output enable bit (bit 1 at address 9616) to “0”. 6: When using an external trigger, be sure to clear the INT2 pin select bit (bit 4 at address 9416) and D-A1 output enable bit (bit 1 at address 9616) to “0”. 7: For writing to this bit, use the MOVM (MOVMB) instruction, or the STA (STAB, STAD) instruction. 8: Rewriting to each bit of the A-D control register 0 (except for bit 6) must be performed while A-D conversion is stopped. Address 1E16 76543210 Analog input select bits (Note 1) (Valid in the one-shot and repeat modes.) 0 0 0 : Select AN 0 0 1 : Select AN1 0 1 0 : Select AN2 0 1 1 : Select AN3 1 0 0 : Select AN4 (Note 2) 1 0 1 : Select AN5 (Note 3) 1 1 0 : Select AN6 (Note 4) 1 1 1 : Select AN7 (Note 5) A-D operation mode select bits 0 0 : One-shot mode 0 1 : Repeat mode 1 0 : Single sweep mode 1 1 : Repeat sweep mode Trigger select bit 0 : Internal trigger 1 : External trigger due to AD TRG input (Note 6) A-D conversion start bit (Note 7) 0 : Stop A-D conversion 1 : Start A-D conversion A-D conversion frequency (φ AD ) select bit 0

M37902FCCHP, M37902FGCHP, M37902FJCHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS Fig. 79 Bit configuration of A-D control register 1 76543210 A-D sweep pin select bits (Note 1) (Valid in the single sweep mode and repeat sweep mode.) 0 0 : AN 0, AN1 0 1 : AN0–AN 3 1 0 : AN0–AN 5 1 1 : AN0–AN 7 Must be “0”. Resolution select bit 0: 8-bit mode 1: 10-bit mode A-D conversion frequency (φ AD ) select bit 1 External trigger polarity select bit (Valid when external trigger is selected.) 0: Falling edge of input signal to the AD TRG pin 1: Rising edge of input signal to the ADTRG pin VREF connection select bit (Note 6) 0 : VREF is connected. 1 : VREF is not connected. “0” at read. (2 pins) (4 pins) (6 pins) (Notes 2, 3) (8 pins) (Notes 2 to 5) A-D control register 1 Address A-D conversion frequency (φAD ) select bit Bit 1 Bit 0 φAD f2/4 f2/2 11 f1 (Selectable only in 8-bit mode) Notes 1: Ignored in the one-shot and repeat modes. (Each of these bits may be “0” or “1”.) 2: When using the AN4 pin, be sure to clear the INT3 pin select bit (bit 5 at address 9416) to “0”. 3: When using the AN5 pin, be sure to clear the INT4 pin select bit (bit 6 at address 9416) to “0”. 4: When using the AN6 pin, be sure to clear the D-A0 output enable bit (bit 0 at address 9616) to “0” (output disabled). 5: When using the AN7 pin, be sure to clear both of the INT2 pin select bit (bit 4 at address 9416) and the D-A1 output enable bit (bit 1 at address 9616) to “0”. When an external trigger is selected, the AN7 pin cannot be used as an analog input pin. 6: Once this bit is cleared from “1” to “0”, it is necessary to wait for 1 µs or more before the A-D or D-A conversion starts. 7: Rewriting to each bit of the A-D control register 1 must be performed while A-D conversion is stopped.

M37902FCCHP, M37902FGCHP, M37902FJCHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS Operation mode The operation mode is selected by bits 3 and 4 of A-D control regis- ter 0. The available operation modes are one-shot, repeat, single sweep, and repeat sweep. Analog input port pins are multiplexed with port P7 pins. Therefore, bits which correspond to pins for A-D conversion must be “0” (input mode). (1) One-shot mode One-shot mode is selected when bits 3 and 4 of A-D control register 0 are “0” is “0”. The A-D conversion pins are selected with bits 0 to 2 of A-D control register 0. A-D conversion can be started by a soft- ware trigger or by an external trigger. When an internal trigger is selected, A-D conversion is started when bit 6 (A-D conversion start bit) is set to “1.” When bit 3 of the A-D control register 1 is “1”, A-D conversion ends after 59 φ AD cycles, and the interrupt request bit of the A-D interrupt control register is set to “1.” At the same time, A-D control register 0 bit 6 (A-D conversion start bit) is cleared to “0” and A-D conversion stops. The result of A-D conversion is stored in the A-D register cor- responding to the selected pin. If an external trigger is selected, A-D conversion starts when the A-D conversion start bit is “1” and a valid edge is input to the AD TRG pin, This operation is the same as that for internal trigger except that the A-D conversion start bit is not cleared after A-D conversion and a retrigger can be available during A-D conversion. (2) Repeat mode Repeat mode is selected when bit 3 of A-D control register 0 is “1” and bit 4 is “0”. The operation of this mode is the same as the operation of one-shot mode except that when A-D conversion of the selected pin is com- plete and the result is stored in the A-D register, conversion does not stop, but is repeated. No interrupt request is generated in this mode. Furthermore, if an external trigger is selected, the A-D conversion start bit is not cleared. The contents of the A-D register can be read at any time. (3) Single sweep mode Single sweep mode is selected when bit 3 of A-D control register 0 is “0” and bit 4 is “1”. In the single sweep mode, the number of analog input pins to be swept can be selected. Analog input pins are selected by bits 1 and 0 of the A-D control register 1 (address 1F16). Two pins, four pins, six pins, or eight pins can be selected as analog input pins, depending on the contents of these bits. A-D conversion is performed only for selected input pins. After A-D conversion is performed for input of AN 0 pin, the conversion result is stored in A-D register 0, and in the same way, A-D conversion is per- formed for selected pins one after another. After A-D conversion is performed for all selected pins, the sweep is stopped. A-D conversion can be started with an internal trigger or with an ex- ternal trigger input. An internal trigger is selected when bit 5 of the A- D control register 0 (address 1E 16) is “0” and an external trigger is selected when it is “1”. When an internal trigger is selected, A-D conversion is started when A-D control register 0 bit 6. (A-D conversion start bit) is set to “1.” When A-D conversion of all selected pins end, the interrupt request bit of the A-D conversion interrupt control register is set to “1.” At the same time, A-D conversion start bit is cleared to “0” and A-D conver- sion stops. When an external trigger is selected, A-D conversion starts when the A-D conversion start bit is “1” and a valid edge is input to the AD TRG pin. In this case, the A-D conversion result which is stored in the A-D register 7 becomes invalid. The operation by external trigger is the same as that by an internal trigger except that the A-D conversion start bit is not cleared to “0” after A-D conversion and a retrigger can be available during A-D conversion. (4) Repeat sweep mode Repeat sweep mode is selected when bit 3 of A-D control register 0 is “1” and bit 4 is “1”. The difference from the single sweep mode is that A-D conversion does not stop after conversion for all selected pins, but repeats again from the AN 0 pin. The repeat is performed among the selected pins. Also, no interrupt request is generated. Furthermore, if an internal trigger is selected, the A-D convension start bit is not cleared. The A-D register can be read at any time. Precautions for A-D conversion interrupt function Clear the interrupt request bit of the A-D interrupt control register (bit 3 at address 7016) before using the A-D interrupt. It is because the interrupt request bit is undefined just after reset.

M37902FCCHP , M37902FGCHP, M37902FJCHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS D-A CONVERTER Three independent D-A converters are included in this microcom- puter, and each D-A converter adopts an 8-bit R-2R method. Figure 80 shows the block diagram of the D-A converter, Figure 81 shows the bit configuration of the A-D control register 1, and Figure 82 shows the bit configuration of the D-A control register. D-A conversion is performed by writing a value to the corresponding D-A register i. Whether to output the analog voltage or not is deter- mined by bits 0 to 2 of the D-A control register. When any of bits 0 to 2 = “1”, the corresponding pin (D-A 0 to D-A2) outputs the analog volt- age. This analog voltage (V) is determined according to value n. (“n” = decimal number. This has been set in the D-A register.) V = V REF ✕ n/256 (n = 0 to 255) VREF : Reference voltage The contents of the corresponding D-A output enable bit and D-A register are cleared to “0” at reset. Whether to connect the reference voltage input (V REF ) with the ladder network or not depends on bit 6 of the A-D control register 1. Pin VREF is connected with the ladder network when bit 6 = “0” and is disconnected when bit 6 = “1” (high impedance state). When not performing the A-D or D-A conversion, current from pin V REF to the ladder network can be cut off by discon- necting ladder network from pin VREF . Before starting A-D or D-A conversion, be sure to clear bit 6 to “0”, and then, insert a waiting time of 1 µs or more. An external buffer is necessary when connecting a low impedance load with the D-A converter. It is because that a D-A output pin doesn’t include a buffer. Pin D-Ai is multiplexed with I/O port pins, analog input pins, serial I/O pins, and external interrupt input pins. When a D-A i output enable bit = “1” (in other words, output is enabled.), however, the corre- sponding pin cannot function as another I/O pin, which is multiplexed Fig. 80 Block diagram of D-A converter Fig. 81 Bit configuration of A-D control register 1 Note: When bit 6 has been cleared to “0” from “1”, insert a waiting time of 1 µs or more, and then, start the D-A or A-D conversion. Not used for D-A converter. VREF connection select bit (Note) 0: Connected. 1: Disconnected. A-D control register 1 Address 16✕✕ 76543210 AV SS VREF R-2R ladder network D-A register i (i = 0 to 2) (Addresses 98 16 to 9A16) Pin D-Ai D-Ai output enable bit VREF connection select bit Data bus Fig. 82 Bit configuration of D-A control register D-A0 output enable bit (Note) 0: Output is disabled. 1: Output is enabled. D-A1 output enable bit (Note) 0: Output is disabled. 1: Output is enabled. D-A2 output enable bit (Note) 0: Output is disabled. 1: Output is enabled. 76543210 D-A control register Address Note: Pin D-Ai is multiplexed with I/O port pins, analog input pins, serial I/O pins, and external interrupt input pins. When a D-Ai output enable bit = “1” (in other words, output is enabled.), however, the corresponding pin cannot function as another I/O pin, which is multiplexed with pin D-Ai. with pin D-Ai. Also, when not using the D-A converter, be sure to clear the contents of the corresponding D-A output enable bit and D-A register to “0”.

M37902FCCHP, M37902FGCHP, M37902FJCHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS REAL-TIME OUTPUT The real-time output function enables to change the output level of several pins simultaneously with a specified timer’s counting. Whether to use the real-time output function is decided by the wave- form output select bits of the 8-bit real-time output control register (bits 0 and 1 at address A0 16). (See Figure 83.) Also, the real-time output controlled by the pulse output mode select bit of the real-time output control register (bit 2 at address A0 16) and is used in one of the following ways:

• 4 bits ✕ 2 channels
• 6 bits ✕ 1 channel + 2 bits ✕ 1 channels (1) Pulse mode 0 When the pulse output mode select bit is cleared to “0”, the micro- computer enters pulse output port is controlled by 2 groups of 4 bits. Figures 84 and 85 show the bit configuration of the pulse output data register 0/1 (address A2 16/A416) and real-time output structure in pulse mode 0, respectively. When the waveform output select bits are set to “01” (bit 1 = “0” and bit 0 = “1”), RTP03 to RTP00 become pulse output port pins, in other words, RTP0 is selected. When the waveform output select bits are set to “10” (bit 1 = “1” and bit 0 = “0”), RTP1 3 to RTP10 become pulse output port pins, in other words, RTP1 is selected. When the waveform output select bits are set to “11” (bit 1 = “1” and bit 0 = “1”), two groups consisting of RTP13 to RTP10 and RTP03 to RTP0 0 become pulse output port pins, in other words, RTP1 and RTP0 are selected. When the waveform output select bits are set to “00” (bit 1 = bit 0 = “0”), port P5 pins become normal programmable I/O port pins. The contents of the pulse output data register 1 (high-order 4 bits at address A4 16), which corresponds to RTP13 to RTP10, is output to these ports each time when the contents of timer A1 counter be- comes “0000 16”. The contents of the pulse output data register 0 Fig. 83 Bit configuration real-time output control register Fig. 84 Bit configuration of pulse output data register Real-time output register A016 Waveform output select bits 00 : Programmable I/O port 01 : RTP0 selected When pulse mode 0 is selected: RTP0 When pulse mode 1 is selected: RTP0 1, RTP00 10 : RTP1 selected When pulse mode 0 is selected: RTP1 When pulse mode 1 is selected: RTP1, RTP0 3, RTP02 11 : RTP1 and RTP0 selected When pulse mode 0 is selected: RTP1 and RTP0 When pulse mode 1 is selected: RTP1, RTP0 3, RTP0 2 and RTP01, RTP0 0 Pulse output mode select bit 0 : Pulse mode 0 1 : Pulse mode 1 “0” at read.

Note 1: Used only in pulse mode 0 2: Used only in pulse mode 1 Pulse output data register 0 RTP0 0 pulse output data bit RTP0 1 pulse output data bit RTP0 2 pulse output data bit (Note 1) RTP0 3 pulse output data bit (Note 1) A216 Pulse output data register 1 RTP0 2 pulse output data bit (Note 2) RTP0 3 pulse output data bit (Note 2) RTP1 0 pulse output data bit RTP1 1 pulse output data bit RTP1 2 pulse output data bit RTP1 3 pulse output data bit (low-order 4 bits at address A216), which corresponds to RTP03 to RTP0 0, is output to these ports each time when the contents of timer A0 counter becomes “000016”. When “0” is written to a specified bit of the pulse output data register, a low-level signal is output to a pulse output port if the counter con- tents of the timer which corresponds to the bit becomes “000016”: when “1” is written to the bit, a high-level signal is output to a pulse output port which corresponds to the bit at the same timing.

M37902FCCHP , M37902FGCHP, M37902FJCHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS Fig. 85 Real-time output structure in pulse mode 0 (2) Pulse mode 1 When the pulse output mode select bit is set to “1”, the microcom- puter enters pulse mode 1, and a pulse output port pins are sepa- rately controlled (6 bits and 2 bits). Figures 86 shows the real-time output structure in pulse mode 1. When the waveform output select bits are set to “01” (bit 1 = “0” and bit 0 = “1”), RTP1 3 to RTP10, RTP03, and RTP02 become program- mable I/O port pins. Simultaneously, RTP01 and RTP00 become pulse output port pins. When the waveform output select bits are set to “10” (bit 1 = “1” and bit 0 = “0”), RTP1 3 to RTP10, RTP03, and RTP02 become pulse out- put port pins. At this time, RTP01 and RTP00 become programmable I/O port pins. When the waveform output select bits are set to “11” (bit 1 = bit 0 = T DQ DQ DQ DQ T DQ DQ DQD 6 D 5 D 4 D 3 D 2 D 1 D 0 Timer A0 Timer A2 P53/RTP03 P52/RTP02 P51/RTP01 P50/RTP00 Port P5i latch Waveform output select bit (Address A016) bit 1 Pulse output data register 0 (Address A216) Pulse output data register 1 (Address A416) Data bus (Even) Pulse output mode select bit (Address A0 16) 0 D 7 T T T DQ T T T a a a a a a a a Waveform output select bit (Address A016) bit 0 P57/RTP13 P56/RTP12 P55/RTP11 P54/RTP10 Port P5i direction register “1” “0”(i = 7 to 0) a (Address D16) (Address B16) “1”), pulse output port pins are divided into two groups; one consists of RTP13 to RTP10, RTP03, RTP02 and the other consists of RTP01 and RTP00. When the waveform output select bits are set to “00” (bit 1 = bit 0 = “0”), port P5 pins become normal programmable I/O port pins. RTP1 3 to RTP10, RTP03, and RTP02 are controlled by timer A2. Also, RTP01 and RTP00 are controlled by timer A0. The contents of the pulse output data register 1 (high-order 6 bits at address A416), which corresponds to RTP13 to RTP10, RTP03, and RTP0 2, are output to this port each time when the contents of timer A2 counter becomes “000016”. The contents of the pulse output data register 0 (low-order 2 bits at address A216), which corresponds to RTP0 1 and RTP00, are output to this port each time when the con- tents of timer A0 counter become “000016”.

M37902FCCHP, M37902FGCHP, M37902FJCHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS Fig. 86 Real-time output structure in pulse mode 1 Table 14 lists the port P5/RTP pin output when all of the port P5 di- rection registers are set to the output mode. Precautions for real-time output function After reset, the port P5 direction register is set to the input mode, and port P5i (i = 0 to 7) pins function as normal I/O port pins. When using these pins as real-time output port pins, set the corresponding bits of the port P5 direction register to the output mode. Additionally, by reading the real-time output port’s value from the port P5 register, output level of pins can be read out. Real-time output control register (Address A016) Store address for port P5/RTP pin output data bit bit bit bit bit bit bit bit bit bit bit Table 14 Port P5/RTP pin output DQ DQ DQ DQ T DQ DQ DQD 6 D 5 D 4 D 3 D 2 D 1 D 0 Timer A0 Timer A2 P53/RTP03 P52/RTP02 P51/RTP01 P50/RTP00 Port P5i latch Waveform output select bit (Address A016) bit 1 Pulse output data register 0 (Address A216) Pulse output data register 1 (Address A416) Data bus (Even) Pulse output mode select bit (Address A0 16) 1 D 7 T T T DQ T T a a a a a a a a Waveform output select bit (Address A016) bit 0 P57/RTP13 P56/RTP12 P55/RTP11 P54/RTP10 Port P5i direction register “1” “0”(i = 7 to 0) a T T (Address D16) (Address B16) Address 0B16: Port P5 Address A216: Pulse output data register 0 Address A416: Pulse output data register 1

M37902FCCHP , M37902FGCHP, M37902FJCHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS Watchdog timer frequency select bit “FFF 16” is set. Writing to watchdog timer register STP instruction Watchdog timer interrupt request Wf32 Wf512 Watchdog timer Wait mode Access to external area HLDA

• Watchdog timer register: address 6016
• Watchdog timer frequency select register: bit 0 at address 6116
• Watchdog timer clock source select bits at STP state termination: bits 6, 7 at address 6116 ❈ When the most significant bit of the watchdog timer becomes “0”, this signal will be generated. Note: During the stop mode and until the stop mode is terminated, setting for disabling the watchdog timer is ignored. RESET Disables watchdog timer (Note). fX16 fX32 fX64 fX128 Watchdog timer clock source select bits at STP state termination Stop mode Divided f(XIN) WATCHDOG TIMER The watchdog timer is used to detect unexpected execution se- quence caused by software runaway and others. Figure 87 shows the block diagram of the watchdog timer. The watchdog timer consists of a 12-bit binary counter. The watchdog timer counts clock Wf 32, which is obtained by dividing the peripheral devices’ clock f2 by 16; or clock Wf512, which is ob- tained by doing it by 256. Bit 0 of the watchdog timer frequency se- lect register (watchdog timer frequency select bit) shown in Figure 88 selects which clock is to be counted. Wf 512 is selected when this bit 0 is “0”, and Wf32 is selected when bit 0 is “1”. Bit 0 is cleared to “0” after reset. FFF 16 is set in the watchdog timer when “L” level voltage is applied to pin RESET, STP instruction is executed, data is written to the watchdog timer register (address 60 16), or the most significant bit of the watchdog timer becomes “0”. After FFF16 is set in the watchdog timer, when the watchdog timer counts Wf32 or Wf512 by 2048 counts, the most significant bit of watchdog timer becomes “0”, the watchdog timer interrupt request bit is set to “1”, and FFF16 is set again in the watchdog timer. In program coding, make sure that data is written in the watchdog timer before the most significant bit of the watchdog timer becomes “0”. If this routine is not executed owing to unexpected program ex- ecution or others, the most significant bit of the watchdog timer be- Fig. 87 Block diagram of watchdog timer Fig. 88 Bit configuration of watchdog timer frequency select register 76543210 Watchdog timer frequency select register Watchdog timer frequency select bit 0 : Wf512 1 : Wf32 Watchdog timer clock source select bits at STP state termination 0 0 : fX 0 1 : fX16 1 0 : fX128 1 1 : fX64

comes “0” and an interrupt is generated. The microcomputer can generate a reset pulse by writing “1” to bit 6 (software reset bit) of processor mode register 0 in an interrupt rou- tine and can be restarted. The watchdog timer can also be used to return from the STP state, where a clock has stopped its operation owing to the STP instruction execution. For details, refer to the sections on the clock generating circuit and standby function. The watchdog timer stops its operation in the following cases, and at this time, input to the watchdog timer is disabled:

• When the external area is accessed in the hold state
• In the wait mode
• In the stop mode

M37902FCCHP, M37902FGCHP, M37902FJCHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS How to disable watchdog timer When not using the watchdog timer, it can be disabled. When the watchdog timer is disabled, it’s operation stops and no watchdog timer interrupt has been generated. Setting for disabling the watchdog timer is possible by writing “79 16” and “5016” to the particular function select register 2 (address 6416) sequentially with the following instructions:

• MOVMB/STAB instruction, or
• MOVM/STA instruction (m = 1) If any method other than above has been adopted in order to access (in other words, read/write) the particular function select register 2, the watchdog timer will not be disabled until reset operation is per- formed. (Also, reset is the only one method to remove the setting for disabling the watchdog timer.) Moreover, this setting for disabling the watchdog timer is ignored at return from the STP mode, and the watchdog timer operates. (For details, refer to the section on the standby function.)

M37902FCCHP , M37902FGCHP, M37902FJCHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS INPUT/OUTPUT PINS Ports P0 to P8, P10, P11 all have the direction register, and each bit can be programmed for input or output. A pin becomes an output pin when the corresponding bit of direction register is “1”, and an input pin when it is “0”. When a pin is programmed for output, the data is written to its port latch and it is output to the output pin. When a pin is programmed for output, the contents of the port latch is read instead of the value of the pin. Accordingly, a previously output value can be read correctly even when the output “H ” voltage is lowered or the output “L” voltage is raised owing to an external load, etc. A pin programmed as an input pin is in the flooting state, and the value input to the pin can be read. When a pin is programmed as an input pin, the data is written only in the port latch and the pin remains floating. Each of Figures 89 and 90 shows the block diagram for each port pin and pin NMI. Figure 91 shows the bit configuration of the port func- tion control register. Bit 3 of the port function control register serves as the port P0 input level select bit, which selects the V IH/VIL level under the condition that port P0 is used as an input port. Bit 4 of the port function control register serves as the P4 4–P4 7 pullup connection select bit. This bit determines whether port pins P4 4–P4 7, which are multiplexed with chip select pins, are to be pulled up or not. At reset, this bit 4 = “0” and P4–P47 are pulled up. The pullup function is valid only when the corresponding port is used an input port. Bit 7 of the port function control register serves as the NMI pullup connection select bit. At reset, this bit 7 = “0” and pin NMI is pulled up. The pullup function is valid only when the corresponding port is used as an input port. When using port pins P5 4–P57 as the key input interrupt input pins (KI0 to KI3), the pullup function can be selected, also. For details, refer to the section on interrupts. When using a port pin as an internal peripheral device’s input pin, clear the corresponding port direction register’s bit to “0”. When us- ing a port pin as an internal peripheral device’s output pin, the port direction register’s bit may be “0” or “1”. In the memory expansion or microprocessor mode, port pins of P0 to P4, P10, P11 become I/O pins, and the their functions as I/O port pins are invalid. Note that, however, some port pins can function as port pins by the special setting. For details, refer to the section on the processor modes. Fig. 91 Bit configuration of port function control register Notes 1: For the M37902FxM (power source voltage = 3.3 V±0.3 V), VIH = 0.5VCC . 2: When MD1 = VCC and MD0 = VCC (flash memory parallel I/O mode), pins P44 to P47 and NMI are not pulled up, regardless of these bits’ contents. 3: When MD1 = VSS and MD0 = VCC (microprocessor mode), pin CS0 (P44) is not pulled up, regardless of the bit’s contents. 76543210 Port function control register Port P0 input level select bit 0 : VIH = 0.7VCC , VIL = 0.2VCC 1 : VIH = 0.43VCC (Note 1), VIL = 0.16VCC Address/Port switch bits 000 : A0 to A23 (16 Mbytes) 001 : A0 to A21, P06, P07 (4 Mbytes) 010 : A0 to A19, P04 to P07 (1 Mbytes) 011 : A0 to A17, P02 to P07 (256 Kbytes) 100 : A0 to A15, P00 to P07 (64 Kbytes) 101 : Do not select. 110 : A 0 to A11, P00 to P07, P114 to P117 (4 Kbytes) 111 : A0 to A7, P00 to P07, P110 to P117 (256 bytes) Pins P44–P47 pullup connection select bit (Notes 2 and 3) 0 : Pins P44–P47 are pulled up. 1 : Pins P44–P47 are not pulled up. Address 9216 Pin NMI pullup connection select bit (Note 2) 0 : Pin NMI is pulled up. 1 : Pin NMI is not pulled up. Fix these bits to “0”. 0 0 At reset 0016

M37902FCCHP, M37902FGCHP, M37902FJCHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS Fig. 89 Block diagram for each port pin and pin NMI (1) [Inside dotted-line not included] P00 to P07, P10 to P17, P20 to P27, P31 to P33, P100 to P107, P110 to P117 [Inside dotted-line included] 0/RDY, P43/HOLD, P6 1/TA4IN, P6 2/INT0, P63/INT1, P64/INT2, P6 5/TB0IN, P66/TB1IN, P67 /TB2IN, P8 2/RXD 0, P86/RXD 1 [Shaded area not included] 1/TA0IN/RTP01, P5 3/TA1IN/RTP03 [Shaded area included] 5/TA2IN/RTP11/KI1, P57/TA3IN/RTP13/KI3 [Inside dotted-line not included] 0/ALE, P41/φ1, P42/HLDA, P83/TXD 0, P87/TXD 1 [Inside dotted-line included] 0/TA4OUT [Shaded area included] 4/CS0, P45/CS1, P46/CS2, P47 /CS3 [Shaded area not included] 0/TA0OUT /RTP00, P5 2/TA1OUT /RTP02 [Shaded area included] 4/TA2OUT /RTP10/KI0, P5 6/TA3OUT /RTP12/KI2 Data bus Port latch Direction register Data bus Port latch Direction register Pullup selection Pullup transistor Data bus Port latch Direction register Latch T Q CKTimer underflow signal Pullup selection Pullup transistor Data bus Port latch Direction register Latch T Q CKTimer underflow signal Pullup selection Pullup transistor Output(Internal peripheral devices) Output (Internal peripheral devices)

M37902FCCHP , M37902FGCHP, M37902FJCHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS P81/CTS0/CLK0, P84/CTS1/RTS1/INT4, P85/CTS1/CLK1 [Inside dotted-line not included] 0/AN0, P71/AN1, P72/AN2, P73/AN3 [Inside dotted-line included] 4/AN4/(INT3), P75/AN5/(INT4) P80/CTS0/RTS0/DA2/INT3 [Inside dotted-line not included] 6/AN6/DA0 [Inside dotted-line included] 7/AN7/ADTRG /DA1/(INT2) Analog input Analog output Enable D-A output Analog output Enable D-A output Analog input NMI Pullup selection Data bus Port latch Direction register Data bus Port latch Direction register Data bus Port latch Direction register Data bus Port latch Direction register Pullup transistor Output (Internal peripheral devices) Output (Internal peripheral devices) Fig. 90 Block diagram for each port pin and pin NMI (2)

M37902FCCHP, M37902FGCHP, M37902FJCHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS Fig. 93 Microcomputer internal register’s status at reset (2) (8016)··· Address CS 0 control register L (8116)···CS 0 control register H (8216)···CS 1 control register L (8316)···CS 1 control register H (8C 16)···Area CS1 start address register (8416)···CS 2 control register L (8516)···CS 2 control register H (8616)···CS 3 control register L (8716)···CS 3 control register H (8A16)···Area CS0 start address register (8E16)···Area CS2 start address register (9016)···Area CS3 start address register Notes 1: The contents of the other registers and RAM are undefined at reset and must be initialized by software. 2: While Vss level voltage is applied to pin MD0, this bit is “0”. While Vcc level voltage is applied to pin MD0, on the other hand, this bit is “1”. 3: While Vss level voltage is applied to pin BYTE, these bits are “0”. While Vcc level voltage is applied to pin BYTE, on the other hand, these bits are “1”. (9216)···Port function control register (9416)···External interrupt input control register (9616)···D-A control register Address 010 (Note 3) 10 01001 0 01001 0 01001 0 00010 000 00000 000 00000 000 00000 000 000 01 001 000 000 000 000 0000 0000 000 0016 0016 Program bank register PG Contents at address FFFF16Program counter PCH Contents at address FFFE16Program counter PCL 000016Direct page registers DPR0 to DPR3 Data bank register DT FFF 16Stack pointer (9816)···D-A register 0 (9916)···D-A register 1 (9A16)···D-A register 2 (A016)···Real-time output control register (AC 16)···Serial I/O pin control register (BC 16)···Clock control register 000 0000 00000 111 (9E16)···Flash memory control register 000 001 00000 0000 0016 0016 0016 Processor status register PS 1??000??000 (Note 3) (Note 3) (Note 3) (Note 2) RESET CIRCUIT While the power source voltage satisfies the recommended operat- ing condition, reset state is removed if pin RESET’s level returns from the stabilized “L” level to the “H ” level. As a result, program ex- ecution starts from the reset vector address. This reset vector ad- dress is expressed as shown below:

• A23 to A16 = 0016
• A15 to A8 = Contents at address FFFF16
• A7 to A0 = Contents at address FFFE16 Figures 92 and 93 show the microcomputer internal register’s status at reset, and Figure 94 shows an operation example of the reset cir- cuit. Apply “L” level voltage to pin RESET for a period (2 µs or more) under the following conditions:
• Pin Vcc’s level satisfies the recommended operating condition.
• Oscillator’s operation has been stabilized. Fig. 94 Operation example of reset circuit (Note that proper evalua- tion is necessary in the system development stage.) VCC RESET Power on VCC level 0.2VCC level Oscillation stabilized 2 µs XIN

M37902FCCHP , M37902FGCHP, M37902FJCHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS Fig. 92 Microcomputer internal register’s status at reset (1) (0416)··· Address 0016 (0516)··· (0816)··· (0916)··· 0016 (0C 16)··· (0D 16)··· 0016 (1016)··· (1116)··· (1416)··· (5616)··· 0016 (5716)··· 0016 (5816)··· 0016 (5916)··· 0016 (5A16)··· 0016 (1816)··· 0016 (1916)··· 0016 Notes 1: The contents of the other registers and RAM are undefined at reset and must be initialized by software. 2: While Vss level voltage is applied to pin MD0, these bits are “0”. While Vcc level voltage is applied to pin MD0, on the other hand, these bits are “1”. 3: At power-on reset, these bits are clear to “0”. At hardware or software reset, on the other hand, these bits retain the value just before reset. 0000 011(1F16)··· 100 000(3416)··· 100 000(3C 16)··· 00000 010(3516)··· 00 000(4216)··· 00(4516)··· (3016)··· 0016 (3816)··· 0016 (4416)··· (4016)··· 0016 00?0 000(5B16)··· 1000(Note 2) 0 (Note 2) 0(5E16)··· (5F16)··· (6016)··· Address (Note 3) 000 0 0000 FFF 16 (6116)··· (6216)··· (6316)··· (6616)··· (6716)··· (6E16)··· (6F16)··· 0000 ?000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 (72 16)··· (7316)··· (7416)··· (7716)··· (7816)··· (7916)··· (7A16)··· 000 000 (7C 16)··· 000 (7E16)··· (7016)··· (7116)··· (7516)··· (7616)··· 000 000 (7D 16)··· (7B16)··· (7F16)··· 000 0016 (Note 2)000 0 (Note 3) 0000 0016 0016 (Note 3)(Note 3) 00?0 000(5C 16)··· 00?0 000(5D 16)··· 0016 0016 0016 Port P0 direction register Port P1 direction register Port P2 direction register Port P3 direction register Port P4 direction register Port P5 direction register Port P6 direction register Port P7 direction register Port P8 direction register Timer A0 mode register Timer A1 mode register Timer A2 mode register Timer A3 mode register Timer A4 mode register A-D control register 0 A-D control register 1 UART 0 Transmit/Receive control register 0 UART 1 Transmit/Receive control register 0 UART 0 Transmit/Receive control register 1 UART 1 Transmit/Receive control register 1 One-shot start register Timer A clock frequency select register Port P10 direction register Port P10 direction register UART 0 Transmit/Receive mode register UART 1 Transmit/Receive mode register Up-down register Count start register Timer B0 mode register Timer B1 mode register Timer B2 mode register Processor mode register 0 Processor mode register 1 Watchdog timer Watchdog timer frequency select register Debug control register 1 Debug control register 0 Particular function select register 1 Particular function select register 0 INT2 interrupt control register INT3 interrupt control register INT4 interrupt control register UART 0 receive interrupt control register UART 1 transmit interrupt control register UART 1 receive interrupt control register Timer A2 interrupt control register Timer A3 interrupt control register Timer A4 interrupt control register Timer B0 interrupt control register Timer B2 interrupt control register INT 1 interrupt control register A-D conversion interrupt control register UART 0 transmit interrupt control register Timer A0 interrupt control register Timer A1 interrupt control register INT0 interrupt control register Timer B1 interrupt control register

M37902FCCHP, M37902FGCHP, M37902FJCHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS OSCILLATION CIRCUIT An oscillation circuit locates between pins XIN and XOUT , and Figure 95 shows a circuit example with a oscillator (an external ceramic resonator or quartz crystal oscillator). The constants such as capaci- tance etc. depend on a oscillator. Therefore, for these constants, adopt the oscillator manufacturer’s recommended values. Figure 96 shows a circuit example with an external clock source. When an external clock is input, be sure to leave pin X OUT open. Also, in this case, when the external clock input select bit (bit 1 of the particular function select register 0; See Figure 100.) is set to “1”, the oscillation circuit stops it’s operation, and the current dissipation is reduced. Moreover, this bit has another function, which selects the return condition from the stop mode. For details, refer to the section on the standby function. On the other hand, the PLL (Phase Locked Loop) frequency multi- plier (hereafter, referred as PLL circuit.) is included, also. This PLL circuit uses an clock input from pin X IN and generates a multiplied clock. When using the PLL circuit, be sure to connect pin VCONT with an external filter circuit. (See Figure 97.) When not using the PLL cir- cuit, be sure to leave pin V CONT open. When not using the PLL circuit, be sure to clear the PLL circuit op- eration enable bit (bit 1 of the clock control register; See Figure 99.), so that the PLL circuit will stop it’s operation. Fig. 95 Circuit example with external ceramic resonator or quartz crystal oscillator Fig. 96 Circuit example with external clock source Fig. 97 Circuit example with pin VCONT and PLL circuit XIN R f XOUT R d C IN C OUT M37902 M37902 XIN XOUT Left open. External clock source Vcc Vss M37902 VCONT 1 KΩ 0.1 µF 220 pF Note: Make the wiring length as short as possible, and shield it with the GND line which surrounds this circuit. Also, for the clock supply to pin X IN, see Figures 95 and 96.

Figure 98 shows the block diagram of the clock generating circuit. valid, regardless of this bit 1’s status. multiplication ratio select bits are allowed to be changed only once. the PLL circuit operation enable bit =“0”. quency. At reset, these bits become “0, 0”. Table 15. f Table 16. Internal peripheral devices’ operation clock frequency Note: The PLL multiplication ratio must be set so that the frequency of the PLL output clock (fPLL) must be in the range from 10 MHz to 26 MHz. Note: When selecting the peripheral devices’ clock select bits 1, 0 = “012”, be sure that system clock fsys does not exceed 13 MHz.

M37902FCCHP, M37902FGCHP, M37902FJCHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS Fig. 98 Block diagram of clock generating circuit f2 f64 f512 f4096 Q RS STP instruction φ BIU (Clock for BIU)φ CPU (Clock for CPU) CPU wait request Reset

• Watchdog timer frequency select bit : bit 0 at address 61
• Watchdog timer clock source select bit at stop state termination : bits 6, 7 at address 61
• External clock input select bit : bit 1 at address 62
• System clock stop select bit at WIT : bit 3 at address 63
• PLL circuit operation enable bit : bit 1 at address BC
• PLL multiplication ratio select bits : bits 2, 3 at address BC
• System clock select bit : bit 5 at address BC
• Peripheral device ’s clock select bit 0, 1 : bits 6, 7 at address BC Watchdog timer Wf 32 Wf 512 f16f1 Peripheral device ’s clocks Watchdog timer frequency select bit X IN X OUT System clock stop select bi at WIT Access to external area HLDA Watchdog timer clock source select bit at stop state termination φ Wait mode Wait mode System clock frequency select bit PLL frequency multiplier fPLL V CONT Wait mode External clock input select bit Q RS STP instructionInterrupt request Q RS WIT instructionInterrupt request Wait mode PLL circuit operation enable bit PLL multiplication ratio select bits fX IN f/n fX fX fX fX 128 fX fX fX fX 128 Peripheral device ’s clock select bit 0 Peripheral device ’s clock select bit 1 BIU : Bus interface UnitCPU : Central Processing Unit❈ : Signal generated when the watchdog timer ’s most significant bit becomes “0”. fsys System clock frequency select bit Operating clock for serial I/O, timer BA-D conversion frequency (φAD ) clock source Operating clock for timer A External clock input select bit Interrupt request

M37902FCCHP, M37902FGCHP, M37902FJCHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS Fig. 100 Bit configuration of particular function select register 0 Fig. 99 Bit configuration of clock control register 76543210 Clock control register Fix this bit to “1”. PLL circuit operation enable bit (Note 1) 0: PLL frequency multiplier is stopped, and pin VCONT is invalid (floating state). 1: PLL frequency multiplier is operating, and pin VCONT is valid. PLL multiplication ratio select bits (Note 2) 00: Do not select. 01: Double 10: Triple 11: Quadruple Fix this bit to “0”. System clock select bit (Note 3) 0: fX IN 1: fPLL Peripheral device’s clock select bits 1, 0 See Table 16. Address BC 1610 At reset 0716 Notes 1: When not using the PLL frequency multiplier, clear this bit to “0”. In the stop mode or in the flash memory parallel I/O mode, the PLL circuit stops it’s operation regardless of this bit’s contents; at this time, pin VCONT is invalid. 2: When rewriting this bit, be sure to clear bit 5 to “0” simultaneously. Also, after this bit is rewritten, insert a waiting time of 2 ms, and then set bit 5 to “1”. 3: When the PLL circuit operation enable bit (bit 1) has been cleared to “0”, this bit will also be cleared to “0”. Also, bit 1 = “0”, nothing can be written to this bit. (Fixed to be “0”.) 76543210 Particular function select register 0 External clock input select bit (Note) 0: Oscillation circuit is active. (Oscillator is connected.) Watchdog timer is used at stop mode termination. 1: Oscillation circuit is inactive. (External clock is input.) When the system clock select bit = “0”, watchdog timer is not used at stop mode termination. When the system clock select bit = “1”, watchdog timer is used at stop mode termination. Fix this bit to “0”. STP instruction invalidity select bit (Note) 0: STP instruction is valid. 1: STP instruction is invalid. Note: Address 160 0 0 Writing to these bits requires the following procedure:

• Write “5516” to this register. (The bit status does not change only by this writing.)
• Succeedingly, write “0” or “1” to each bit. Also, use the MOVM (MOVMB) instruction or STA (STAB, STAD) instruction

tem clock in the case that the CPU needs not be operating. of an interrupt request or reset. or WIT instruction will be executed. cleared to “0” by software at termination of the STP or the WIT mode. section on the power saving function. watchdog timer’s clock source. 1 to f4096, Wf32 and Wf512, are stopped. clocks f1 to f4096, Wf32 and Wf512 are also supplied. the operation-stabilizing time for these circuits has passed. eration restart of the oscillation circuit and PLL circuit. Timers A, B, Serial I/O, A-D converter: Operation is enabled. Notes 1: When the external clock input select bit = “1”, the oscillation circuit stops. Also, clock input from pin XIN is available. 2: When the PLL operation enable bit = “0”, the PLL circuit stops. Table 17. Microcomputer’s operation in STP and WIT modes

M37902FCCHP, M37902FGCHP, M37902FJCHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS Fig. 101 Bit configuration of particular function select register 1 Fig. 102 Bit configuration of watchdog timer frequency select register 76543210 Particular function select register 1 STP-instruction-execution status bit (Note 1) 0: Normal operation. 1: STP instruction has been executed. WIT-instruction-execution status bit (Note 1) 0: Normal operation. 1: WIT instruction has been executed. Standby state select bit 0: External bus 1: Programmable I/O port System clock stop select bit at WIT (Note 2) 0: In wait mode, system clock f sys is active. 1: In wait mode, system clock fsys is stopped. Address output select bit 0: Address changes depending on bus access. 1: Address changes only at access to external address. Timer B2 clock source select bit In event counter mode: 0: Clock input from pin TB2 IN is counted. 1: fX32 (f(XIN)/32) is counted. Address 6316 Notes 1: At power-on reset, this bit becomes “0”. At hardware reset or software reset, this bit retains the value just before reset. Even when “1” is written, the bit status will not change. 2: Setting this bit to “1” must be performed just before execution of the WIT instruction. Also, after the wait state is terminated, this bit must be cleared to “0” immediately. 76543210 Watchdog timer frequency select register Watchdog timer frequency select bit 0 : Select Wf512 1 : Select Wf32 Watchdog timer clock source select bits at STP termination 0 0 : fX32 0 1 : fX16 1 0 : fX128 1 1 : fX64 down with one of the above divide clocks, fX16 to fX128, after the os- cillation circuit and PLL circuit have been restarted their operations owing to an interrupt. The most significant bit of the watchdog timer reaching “0”, supply of φBIU and φCPU restarts. On the other hand, when the external clock input select bit = “1 ” and the system clock select bit = “0”, supply of φBIU and φCPU will restart immediately after the oscillation circuit has been restarted their op- erations owing to an interrupt. (In actual fact, after the selected one of the above divide clocks, fX 16 to fX128, has been changed from “H ” to “L”, this supply will restart.)

M37902FCCHP, M37902FGCHP, M37902FJCHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS WIT mode When the WIT instruction is executed with the system clock stop se- lect bit at WIT (bit 3 of the particular function select register 1 in Fig- ure 101) being “0”, φBIU, φCPU , and divide clocks Wf32 and Wf512 are stopped in the “L“ state. However, the oscillation circuit, PLL circuit, input clock fXIN, system clock fsys, φ1, and peripheral devices’ clock f1 to f4096 remain operating. Therefore, BIU and CPU are stopped, whereas timers A and B, serial I/O, and the A-D converter, which use the peripheral devices’ clocks f 1 to f4096, are still operating. Note that the watchdog timer is stopped. On the other hand, when the WIT instruction is executed with the system clock stop select bit at WIT being “1”, the oscillation circuit, PLL circuit, and input clock fX IN are operating, while system clock fsys, φBIU, φCPU , and peripheral devices’ clocks stop operating. As a result, the A-D converter and watchdog timer, which use peripheral devices’ clocks f 1 to f4096, Wf32 and Wf512, are stopped. At this time, timers A and B operate only in the event counter mode, and serial I/O communication is active only while an external clock is selected. If the internal peripheral devices are not used in the WIT mode, the latter is better because the current dissipation is more saved. Note that the system clock stop select bit at WIT is to be set to “1” immedi- ately before execution of the WIT instruction and cleared to “0” im- mediately after the WIT mode is terminated. The WIT state is terminated by acceptance of an interrupt request, and then, supply of φBIU and φCPU will restart. Since the oscillation circuit, PLL circuit, and clock input fXIN are operating in the WIT mode, an interrupt processing can be executed just after the WIT mode termination.

control signals become valid. Table 18. Correspondence between external buses, bus control sig- standby state select bit’s contents. For details, refer to the section on the standby function.

• the external clock input select bit (bit 1 of the particular function select register 0) = “1”.
• the oscillation driver between pins X IN and XOUT stops its operation. At this time, the output level at pin XOUT is fixed to “H ”. When not us- ing a PLL output clock, also, the supply of φBIU and φCPU restarts their operations just after the microcomputers returns from the stop mode, owing to an interrupt request occurrence. Therefore, an in- struction can be executed just after the termination of the stop mode. For details, refer to the section on the clock generating circuit and standby function. (4) Disconnection from pin VREF When not using the A-D converter and D-A converter, by setting the V REF connection select bit (bit 6 of the A-D control register 1) to “1”, the resistor ladder network of the A-D converter will be disconnected from the reference voltage input pin (V REF ). In this case, no current flows from pin VREF to the resistor ladder network, and the power dis- sipation can be saved. Note that, after the VREF connection select bit changes from “1” (VREF disconnected) to “0” (VREF connected), be sure that a waiting time of 1 µs of more has passed before the A-D conversion starts. For details, refer to the sections on the A-D con- verter and D-A converter. (5) Address output selection In the memory expansion mode or microprocessor mode, when the address output select bit (bit 4 of the particular function select regis- ter 1) becomes “1”, the unnecessary change of address pins’ state will be avoided, without output of an address at access to the inter- nal area. For details, refer to the section on the BIU.

M37902FCCHP, M37902FGCHP, M37902FJCHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS Fig 103. Block diagram of debug function Address compare register 0 Address compare register 1 Debug control register 0 Matching • Compare register Matching • Compare register Address matching detect circuit Debug control register 1 Internal data bus (DB0 to DB 15) CPU bus (Address) Address matching detection interrupt DEBUG FUNCTION When the CPU fetches an instruction code, an interrupt request will be generated if a selected condition is satisfied, as a resultant of comparison between a specified address and the start address where the instruction code is stored (the contents of PG and PC). The decision whether this condition is satisfied or not is called ad- dress matching detection, and the interrupt generated by this detec- tion is called an address matching detection interrupt. (For interrupt vector addresses, refer to the section on interrupts.) In the address matching detection, a non-maskable interrupt routine is proceeded without execution of the original instruction which has been allocated to the target address. The debug function provides the following two modes:

• the address matching detection mode, which is used to avoid the area where program exists or modify a program.
• the out-of-address-area detection mode, which is used to detect a program runaway. Figures 103 shows the block diagram of the debug function. Figures 104 and 105 show the bit configurations of the debug control regis- ters 0, 1, and address compare registers 0,1, respectively. The detect condition select bits of the debug control register 0 can select one condition between the following 4 conditions. When the selected address condition is satisfied, an address matching detec- tion interrupt request will be generated: (1) Address matching detection 0 The contents of PG and PC match with the address which has been set in the address compare register 0. (2) Address matching detection 1 The contents of PG and PC match with the address which has been set in the address compare register 1. (3) Address matching detection 2 The contents of PG and PC match with the address which has been set in either of the address compare register 0 or address compare register 1. (4) Out-of-address-area detection The contents of PG and PC are less than the address which has been set in the address compare register 0 or larger than the ad- dress which has been set in the address compare register 1. By setting the detect enable bit of the debug control register 0 to “1”, an address matching detection interrupt request will be generated if any one of the above address conditions is satisfied. Clearing the detect enable bit to “0” generates no interrupt request even if any of the above address conditions is satisfied. The address compare register access enable bit of the debug con- trol register 1 must be set to “1” by the instruction just before the ac- cess operation (read/write). Then, this bit must be cleared to “0” (disabled) by the next instruction. While this bit = “0”, the address compare registers 0, 1 cannot be accessed. The address-matching-detection 2 decision bit of the debug control register 1 decides, whether the address which has been set in the address compare register 0 or 1 matches with the contents of PG, PC, when the address matching detection 2 is selected. The con- tents of this bit is invalid when address matching detection 0 or 1 is selected. In order to use the debug function to avoid the area where program exists or modify a program, perform the necessary processing within an address matching interrupt routine. As a result, the contents of PG, PC, PS at acceptance of an address matching detection inter- rupt request (i.e. the address at which an address matching detec- tion condition is satisfied) have been pushed on to the stack. If a return destination address after the interrupt processing is to be al- tered, rewrite the contents of the stack, and then return by the RTI instruction. To use the debug function to detect a program runaway, set an ad- dress area where no program exists into the address compare regis- ters 0 and 1 by using the out-of-address-area detection. When the CPU fetches instruction codes from this address area and executes them, an address matching detection interrupt request will be gener- ated. The above debug function cannot be evaluated by a debugger, so that the debug function must not be used while a debugger is run- ning.

M37902FCCHP, M37902FGCHP, M37902FJCHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS 100 Fig. 104 Bit configuration of debug control register 0, 1 Fig. 105 Bit configuration of address compare register 0, 1 76543210 Debug control register 0 Detect condition select bits (Note 1) 000: Do not select. 001: Address matching detection 0 010: Address matching detection 1 011: Address matching detection 2 100: Do not select. 101: Out-of-address-area detection 110: Do not select. 111: Do not select Fix this bit to “0” (Note 1). Detect enable bit (Note 1) 0: Detection disabled. 1: Detection enabled. Fix this bit to “0” (Note 1). “1” at read. Address 76543210 Debug control register 1 Fix this bit to “0” (Note 1). “0” at read (Note 1). Address compare register access enable bit (Note 2) 0: Disabled 1: Enabled Fix this bit to “1” when using the debug function. Fix this bit to “0” (Note 1). While debugger is not used, “0” at read. While debugger is used, “1” at read. Address-matching-detection 2 decision bit ❈ Valid when address matching detection 2 is selected. 0: Matches with the contents of the address compare register 0. 1: Matches with the contents of the address compare register 1. “0” at read. Address 000 010 Notes 1: At power-on reset, these bits = “0”; at hardware reset or software reset, these bits retain the value just before reset. 2: Set this bit to “1” with the instruction just before the address compare register 0, 1 (addresses 6816 to 6D16) is accessed. And then, clear this bit to “0” with the instruction just after the access.

0 Address compare register 0

Address compare register 1 The address to be detected (in other words, the start address of instruction) is set here. Address 6816, 6916, 6A16 6B16, 6C16, 6D16 (23) (8)(15)(16) 0707

M37902FCCHP, M37902FGCHP, M37902FJCHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS Notes 1: In the flash memory mode, the read/programming/erase operation cannot be performed for areas except for the internal flash memory area. 2: The boot ROM area can be reprogrammed only in the flash memory parallel I/O mode. When the boot ROM area is read out by the CPU, these addresses are shifted to addresses 00C00016–00FFFF 16 (byte addresses). 3: The reserved area for the serial programmer is assigned to addresses FFB016–FFBF 16 (byte addresses). When the flash memory serial I/O mode is used, do not program to this area. Boot ROM areaUser ROM area

32 Kbytes

2 Kbytes

Byte Addresses Word Addresses

64 Kbytes

These microcomputers contain the DINOR (DIvided bit line NOR)- type flash memory; and single-power-supply reprogramming is avail- able to this. These microcomputers have the following three modes, enabling reading/programming/erasure for the flash memory:

• Flash memory parallel I/O mode and Flash memory serial I/O mode, where the flash memory is handled by using an external pro- grammer.
• CPU reprogramming mode, where the flash memory is handled by the central processing unit (CPU). As shown in Figures 106 to 108, the flash memory is divided into several blocks, and erasure per block is possible. Each of these blocks is provided with a lock bit, which determines the validity of erasure/program execution. Therefore, data protection per Fig 106. M37902FJCHP: block configuration of internal flash memory block is possible. This internal flash memory has the boot ROM area storing the repro- gramming control software for reprogramming in the CPU repro- gramming mode and flash memory serial I/O mode, as well as the user ROM area storing a certain control software for the normal op- eration in the microcomputer mode. Although our reprogramming control firmware for the flash memory serial I/O mode has been stored into this boot ROM area on ship- ment, the user-original reprogramming control software which is more appropriate for the user’s system is reprogrammable into this area, instead. Note that the reprogramming for the boot ROM area is enabled only in the flash memory parallel I/O mode.

M37902FCCHP, M37902FGCHP, M37902FJCHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS 102 Fig 108. M37902FGCHP: block configuration of internal flash memory Notes 1: In the flash memory mode, the read/programming/erase operation cannot be performed for areas except for the internal flash memory area. 2: The boot ROM area can be reprogrammed only in the flash memory parallel I/O mode. When the boot ROM area is read out by the CPU, these addresses are shifted to addresses 00C00016–00FFFF 16 (byte addresses). 3: The reserved area for the serial programmer is assigned to addresses FFB016–FFBF 16 (byte addresses). When the flash memory serial I/O mode is used, do not program to this area. Boot ROM areaUser ROM area Byte Addresses Word Addresses Fig 107. M37902FCCHP: block configuration of internal flash memory Boot ROM areaUser ROM area Byte Addresses Word Addresses Notes 1: In the flash memory mode, the read/programming/erase operation cannot be performed for areas except for the internal flash memory area. 2: The boot ROM area can be reprogrammed only in the flash memory parallel I/O mode. When the boot ROM area is read out by the CPU, these addresses are shifted to addresses 00C00016–00FFFF 16 (byte addresses). 3: The reserved area for the serial programmer is assigned to addresses FFB016–FFBF 16 (byte addresses). When the flash memory serial I/O mode is used, do not program to this area.

from erasing/programming (in other words, block lock). Table 19. Software commands (flash memory parallel I/O mode) address assigned in the range of 0016— FF16 (byte addresses). the flash memory parallel I/O mode. address out of this area is prohibited). area if the user uses the flash memory serial I/O mode. I/O mode, do not program to this area. 16— FFFF 16 (byte addresses).

M37902FCCHP, M37902FGCHP, M37902FJCHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS 104 Flash Memory Serial I/O Mode In the flash memory serial I/O mode, addresses, data, and software commands, which are required to read/program/erase the internal flash memory, are serially input and output with a fewer pins and the dedicated serial programmer. In this mode, being different from the flash memory parallel I/O mode, the CPU controls reprogramming of the flash memory (using the CPU reprogramming mode), serial input of the reprogramming data, etc. The reprogramming control firmware for the flash memory serial I/O mode has been stored in the boot ROM area on shipment of the product from us. Note that, then, the flash memory serial I/O mode will become unavailable if the boot ROM area has been repro- grammed in the flash memory parallel I/O mode. Note that, also, this reprogramming control firmware for the flash memory serial I/O mode is subject to change. Figure 112 shows the pin connection in the flash memory serial I/O mode. The three pins, SCLK, SDA, and BUSY, are used to input and output serial data. The SCLK pin is the input pin of external transfer clocks. The SDA pin is the I/O pin of transmit and receive data, and its output acts as the N-channel open-drain output. To the SDA pin, connect an exter- nal pullup resistor (about 1 kΩ ). The BUSY pin is the output pin of the BUSY flag (CMOS output) and goes “H ” during BUSY periods owing to a certain operation, such as transmit, receive, erase, program- ming, etc. Transmit and receive data are serially transferred 8 bits at a time. In the flash memory serial I/O mode, only the user ROM area can be reprogrammed; the boot ROM area is not accessible. Addresses FFB0 16 to FFBF16 are the reserved area for the serial programmer. Therefore, when the user uses the flash memory serial I/O mode, do not program to this area.

M37902FCCHP, M37902FGCHP, M37902FJCHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS Fig.112 Pin connection of M37902FxCHP in flash memory serial I/O mode Output 100P6Q-A 1/φ1 0/ALE 2/HLDAP4 5/CS 0/TA4 OUT 1/TA4 IN 2/INT 3/INT 4/INT 5/TB0 IN 6/TB1 IN 0/TA0 OUT /RTP0 1/TA0 IN /RTP0 2/TA1 OUT /RTP0 3/TA1 IN /RTP0 4/TA2 OUT /RTP1 0/KI 5/TA2 IN /RTP1 1/KI 6/TA3 OUT /RTP1 2/KI 7/TA3 IN /RTP1 3/KI 6/CS 4/CS 3/HOLDP4 7/CS 7/TB2 IN 0/AN 100 59 58 57 56 55 54 53 52 51 74 73 72 71 70 69 68 67 66 64 63 62 61 606575 M37902FCCHP M37902FGCHP M37902FJCHP VCC VSS RESET 2524232221321 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 SCLKBUSYSDA MD1 VCC VSS XOUT XIN VCONT RESET MD0 P13/D3/LA3 P14/D4/LA4 P15/D5/LA5 P25/D13 P24/D12 P23/D11 P20/D8 P17/D7/LA7 P22/D10 P21/D9 P16/D6/LA6 P27/D15 P26/D14 P33/BHW P31/RD P32/BLW P30/RDY BYTE V SS MD1P10 4/A P10 5/A P10 6/A P10 7/A P11 0/A P11 1/A P11 2/A P11 3/A P11 4/A P11 5/A P11 6/A P11 7/A 0/A 1/A 2/A 3/A 4/A 5/A 7/A 6/A 0/D 0/LA 1/D 1/LA 2/D 2/LA P103/A3 P101/A1 P102/A2 P87/TXD 1 P100/A0 P81/CTS0/CLK0 P82/RXD 0 P83/TXD 0 VSS AV SS VREF VCC AV CC P73/AN3 P72/AN2 P71/AN1 P84/CTS1/RTS1/INT4 P85/CTS1/CLK1 P86/RXD 1 P74/AN4/(INT3) P75/AN5/(INT4) P76/AN6/DA0 P77/AN7/ADTRG /DA1/(INT2) P80/CTS0/RTS0/DA2/INT3 NMI ✼ : Connect to the ceramic oscillation circuit.

M37902FCCHP , M37902FGCHP, M37902FJCHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS 106 CPU Reprogramming Mode The CPU reprogramming mode is used to perform the operations for the internal flash memory (reading, programming, erasing) under control of the CPU. In this mode, only the user ROM area can be reprogrammed; the boot ROM area cannot be reprogrammed. The user-original reprogramming control software for the CPU repro- gramming mode can be stored in either the user ROM area or the boot ROM area. Because the CPU cannot read out the flash memory in the CPU reprogramming mode, the above software must be trans- ferred to the internal RAM in advance to be executed. Boot Mode The user-original reprogramming control software for the CPU re- programming mode must be stored into the user ROM area or the boot ROM area in the flash memory parallel I/O mode in advance. (If this program has been stored into the boot ROM area, the flash memory serial I/O mode will become unavailable). Note that addresses of the boot ROM area depend on the accessing ways to the boot ROM area, When accessing in the flash memory parallel I/O mode, these addresses will be shifted to 0000 16 to 3FFF 16 (byte address). On the other hand, when accessing with the CPU, these addresses will be shifted to C00016 to FFFF16 (byte address). Reset removal with both of the MD0 and MD1 pins held “L” invokes the normal microcomputer mode, and the CPU operates using the control software stored in the user ROM area. In this case, the boot ROM area is not accessible. Removing reset with the MD0 pin held “L” and the MD1 pin “H”, the CPU starts its operation using the reprogramming control software stored in the boot ROM area. This mode is called the boot mode. The reprogramming control software in the boot ROM area can also re- program the user ROM area. After reset removal, be sure not to change the status at pins MD0 and MD1. Fig. 114 Bit configuration of flash memory control register Flash memory control register RY/BY status bit 0: Busy (Programming or erasing is active.) 1: Ready CPU reprogramming mode select bit (Note 2) 0: Normal mode (Software commands are ignored.) 1: CPU reprogramming mode (Software commands are acceptable.) Lock bit invalidity select bit (Note 3) 0: Block lock by lock bit data is valid. 1: Block lock by lock bit data is invalid. Flash memory reset bit (Note 4) 0: Normal operation 1: Reset Must be “0”. User ROM area select bit (Note 5) (Valid only in the boot mode.) 0: Boot ROM area access 1: User ROM area access Address 765432 10 Notes 1: The contents of the flash memory control register after reset is removed are “XX000001 2”. 2: To set “1”, writing of “0” to bit 1 and subsequent writing of “1” to bit 1 are necessary. Writing to bit 1 must be performed by the user-original reprogramming control software in the internal RAM. 3: To set “1”, writing of “0” to bit 2 and subsequent writing of “1” to bit 2 are necessary while bit 1 = “1”. 4: Valid only when bit 1 = “1”. Set bit 3 to “1” (reset), and then clear to “0”. This bit 3 must be controlled with bit 1 = “1”. 5: Writing to bit 5 must be performed by the user-original reprogramming control software in the internal RAM.

M37902FCCHP , M37902FGCHP, M37902FJCHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS 108 Fig. 115 CPU reprogramming mode set/termination flowchart Software Commands Table 20 lists the software commands. By writing a software command after the CPU reprogramming select bit has been set to “1”, erasing, programming, etc. can be specified. Note that, at software commands’ input, the high-order byte (D D 15) is ignored. (Except for the write data at the 2nd cycle of a page programming command.) Software commands are explained as below. Read Array Command (FF 16) By writing command code “FF16” at the 1st bus cycle, the microcom- puter enters the read array mode. If an address to be read is input in the next or the following bus cycles, the contents at the specified ad- dress are output to the data bus (D0 to D15) in a unit of 16 bits. The read array mode is maintained until writing of another software command. Read Status Register Command (7016) Writing command code “7016” at the 1st bus cycle outputs the con- tents of the status register to the data bus (D0-D7) by a read at the 2nd bus cycle. The status register is explained later. Clear Status Register Command (5016) This command clears three status bits (SR.3–5) each of which is set to “1” to indicate that the operation has been terminated by an error. To clear these bits, write command code “50 16” at the 1st bus cycle. Page Programming Command (41 16) Page programming facilitates quick programming of 128 words (a page = 256 bytes) at a time. To initiate page programming, write command code “41 16” at the 1st bus cycle; then, program a series of data, in a unit of 16 bits, sequentially from the 2nd to the 129th bus cycle. It is necessary, at this time, to increment address A0–A7 from "0016" to “FE16” by +2. (Programmed to even addresses.) Upon completion of data loading, automatic programming (data pro- gramming and verification) operation is started. The completion of the automatic programming operation is recog- nized by a read of the status register or a read of the flash memory control register. As the automatic programming operation starts, the microcomputer enters the read status register mode automatically to allow reading out the contents of the status register. Bit 7 of the sta- tus register (SR.7) is cleared to “0” simultaneously with the start of the automatic programming operation; and also, bit 7 returns to “1” by the end of it. Until writing of the read array command (FF 16), writ- ing of the read lock bit status command (7116), or performing the re- set operation with the flash memory reset bit, this read status register mode is maintained. In continuous programming, if there is no pro- gramming error, page programming commands can be executed with the read status register mode kept. Completed Start Read array command is executed, or reset is performed by setting the flash memory reset bit. (Writing of “1” → Writing of “0”) (Note 2) Single-chip mode, Memory expansion mode, or Boot mode The processor mode register 1 is set (Note 1). Flag I is set to “1”. Operations such as erasing, programming are executed by using software commands. (If necessary, the lock bit invalidity select bit is set.) Jump to the above software in the internal RAM. (The operations shown below will be executed by the above software in this RAM.) The user-original reprogramming control software for the CPU reprogramming mode is transferred to the internal RAM. (Only in the boot mode.) Writing of “0” to user ROM area select bit (Note 3). Writing of “0” to the CPU reprogramming mode select bit. (Only in the boot mode.) The user ROM area select bit is set to “1”. Writing of “1” to the CPU reprogramming mode select bit. (Writing of “0” → Writing of “1”) Notes 1: The processor mode register 1’s bit 7 (address 5F16, the internal ROM bus cycle select bit) must be “0” (bus cycle = 3φ). 2: To terminate the CPU reprogramming mode after the erase and programming operations have been completed, be sure to execute the read array command or perform the flash memory reset operation. 3: This bit may remain “1”. However, if this bit is “1”, the user ROM area access is specified.

M37902FCCHP, M37902FGCHP, M37902FJCHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 110 Fig. 116 Page programming flowchart Fig. 117 Block erase flowchart Fig. 119 Read lock bit status flowchart Fig. 118 Lock bit programming flowchart n = FE16 Start Write 4116 n = 0 Write Addressn, Datan SR.7 = 1? Status Register Read Full status check Page programming completed n = n + 2 NO YES NO YES Write 2016 Write D016 Status Register Read SR.7 = 1? Full Status Check Block Erase Completed NO YES Block Address Start SR.7 = 1? Write 7716 Write D016 NO YES SR.4 = 0? NO Lock Bit Programming Completed Block Address Lock Bit Programming Error YES Start Block: unlocked Write 7116 D 6 = 0? Block: locked NO YES Block Address Start

Table 21. Bit definition of status register cleared to “0” (BUSY), however, set to “1” upon completion of them.

• the system power is turned on.
• reset is removed.
• the clear status register command (50 16) is executed. Programming Status Bit (SR.4) This bit reports the status of the automatic programming operation. This bit is set to “1” if a programming error occurs and returns to “0” if one of the following conditions is satisfied:
• the system power is turned on.
• reset is removed.
• the clear status register command (50 16) is executed. Block Status After Programming Bit (SR.3) This bit is set to “1”, upon completion of the page programming op- eration, if the excessive programming (Note) occurs. That is, the sta- tus register becomes “80 16” when the programming operation is terminated normally, “9016” when the programming operation is failed, and “8816” when the excessive programming occurs. Under the condition that any of SR.5, SR.4 and SR.3 = “1”, none of the page programming, block erase, erase all unlocked block, and lock bit programming commands can be accepted. To execute these commands, in advance, execute the clear status register command (50 16) to clear the status register. Both of SR.4 and SR.5 are set to “1” under the following conditions (Command Sequence Error): (1) when data other than “D0 16” and “FF16” is written to the data in the 2nd bus cycle of the lock bit programming command (7716/ D0 16) (2) when data other than “D016” and “FF16” is written to the data in the 2nd bus cycle of the block erase command (2016/D016) (3) when data other than “D016” and “FF16” is written to the data in the 2nd bus cycle of the erase all unlocked block command (A7 16/D016) Note that, writing of “FF16” forces the microcomputer into the read array mode. Simultaneously with this, the command written in the 1st bus cycle will be canceled. Note: The excessive programming means the status that memory cells are too depleted, so data cannot be read out correctly. Full Status Check The full status check reports the results of the erase or programming operation. Figure 120 shows the full status check flowchart and actions to be taken if an error has occurred.

M37902FCCHP , M37902FGCHP, M37902FJCHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Fig. 120 Full status check flowchart and actions to be taken if an error has ocurred Status Register Read SR.4 = 1 NO Command Sequence Error YES SR.5 = 0? YES Block Erase Error NO SR.4 = 0? YES Programming Error (Page, Lock bit) NO SR.3 = 0? YES Programming Error (Block) NO End (Block erase, Programming) and SR.5 = 1 Execute the clear status register command (5016) to clear the status register. After verifying the command to be correctly input, start the operation again. Examine whether a lock is active or not by executing the read lock bit status command (7116). After removing the lock, perform block erase again. If the same error still occurs, this page cannot be used. Examine whether a lock is active or not by executing the read lock bit status command (7116). After removing the lock, perform programming again. If the same error still occurs, this page cannot be used. After erasing the block where an error has occured, perform programming again. If the same error still occurs, this block cannot be used. Note: Under the condition that any of SR.5, SR.4 and SR.3 = “1”, none of the page programming, block erase, erase all unlocked block, and lock bit programming commands can be accepted. To execute these commands, in advance, execute the clear status register command (50 16). The limits of parameters other than the above are same as those in the microcomputer mode. Note: f(fsys) indicates the system clock (fsys) frequency. Symbol Parameter Limits Unit Icc1 Icc2 Icc3 Icc4 Min. Typ. Max. VCC power source current (at read) VCC power source current (at write) VCC power source current (at programming) VCC power source current (at erasing) 30 48 Limits of VIH, VIL, VOH , VOL , IIH, and IIL for each pin are the same as those in the microcomputer mode. Note: f(fsys) indicates the system clcok (fsys) frequency. mA mA mA mA Parameter Page programming time Block erase time Erase all unlocked block time Lock bit programming time Limits UnitMin. Typ. Max. 50 ✕ n 120 600 600 ✕ n 120 ms ms ms ms n = Number of blocks to be erased

M37902FCCHP, M37902FGCHP, M37902FJCHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS 114 Unit V V V V V V V V V V V V V V V V V V mA mA mA mA MHz MHz Max. 5.5 Vcc V CC Vcc Vcc Vcc Vcc Vcc 0.2 V CC

0.2 VCC

0.16 VCC

–10 Parameter Power source voltage Analog power source voltage Power source voltage Analog power source voltage High-level input voltage X IN, RESET, BYTE, MD0, MD1 High-level input voltage P10–P17, P20–P27, P30–P33, P40–P47, P50–P57, P60–P67, P70–P77, P80–P87, P100–P107, P110–P117 High-level input voltage P00–P07 (When the port P0 input level select bit = “0”) High-level input voltage P00–P07 (When the port P0 input level select bit = “1”) High-level input voltage D0–D 7, D8–D 15 High-level input voltage RDY, HOLD, TA0IN–TA4IN, TA0OUT –TA4OUT , TB0 IN–TB2 IN, KI0–KI3, INT0–INT4, NMI, ADTRG , CTS0, CTS 1, CLK0, CLK1, RxD0, RxD1 High-level input voltage SCLK, SDA (Note 1) Low-level input voltage XIN, RESET, BYTE, MD0, MD1 Low-level input voltage P10–P17, P20–P27, P30–P33, P40–P47, P50–P57, P60–P67, P70–P77, P80–P87, P100–P107, P110–P117 Low-level input voltage P00–P07 (When the port P0 input level select bit = “0”) Low-level input voltage P00–P07 (When the port P0 input level select bit = “1”) Low-level input voltage D0–D 7, D8–D 15 Low-level input voltage RDY, HOLD, TA0IN–TA4IN, TA0OUT –TA4OUT , TB0 IN–TB2 IN, KI0–KI3, INT0–INT4, NMI, ADTRG , CTS0, CTS 1, CLK0, CLK1, RxD0, RxD1 Low-level input voltage SCLK, SDA (Note 1) High-level peak output current P00–P07, P10–P17, P20–P27, P30–P33, P40–P47, P50–P57, P60–P67, P70–P77, P80–P87, P100–P107, P110–P117 High-level average output current P00–P07, P10–P17, P20–P27, P30–P33, P40–P47, P50–P57, P60–P67, P70–P77, P80–P87, P100–P107, P110–P117 Low-level peak output current P00–P07, P10–P17, P20–P27, P30–P33, P40–P47, P50–P57, P60–P67, P70–P77, P80–P87, P100–P107, P110–P117 Low-level average output current P00–P07, P10–P17, P20–P27, P30–P33, P40–P47, P50–P57, P60–P67, P70–P77, P80–P87, P100–P107, P110–P117 External clock input frequency (Note 2) System clock frequency Symbol VCC AV CC VSS AV SS VIH VIH VIH VIH VIH VIH VIH VIH VIL VIL VIL VIL VIL VIL IOH(peak) IOH(avg) IOL(peak) IOL(avg) f(XIN) f(fsys) Parameter Power source voltage Analog power source voltage Input voltage P0 0–P07, P10–P17, P20–P27, P30–P33, P40–P47, P50–P57, P60–P67, P70–P77, P80–P87, P100–P107, P110–P117, VREF , XIN, RESET, BYTE, MD0, MD1, NMI, VCONT Output voltage P00–P07, P10–P17, P20–P27, P30–P33, P40–P47, P50–P57, P60–P67, P70–P77, P80–P87, P100–P107, P110–P117, XOUT Power dissipation Operating ambient temperature Storage temerature Symbol V CC AV CC VI VO Pd Topr Tstg ABSOLUTE MAXIMUM RATINGS RECOMMENDED OPERATING CONDITIONS (Vcc = 5 V, Ta = –20 to 85 °C, unless otherwise noted) Notes 1: Pins SCLK and SDA are used only in the flash memory serial I/O mode. 2: When using the PLL frequency multiplier, be sure that f(fsys) = 26 MHz or less. 3: Average output current is the average value of an interval of 100 ms. 4: The sum of IOL(peak) for ports P0–P2, P8, P10, and P11 must be 80 mA or less, the sum of IOH(peak) for ports P0–P2, P8, P10, and P11 must be 80 mA or less, the sum of IOL(peak) for ports P3–P7 must be 80 mA or less, the sum of IOH(peak) for ports P3–P7 must be 80 mA or less. Unit V V V V mW Ratings –0.3 to 6.5 –0.3 to 6.5 –0.3 to V CC +0.3 –0.3 to VCC +0.3 400 –20 to 85 –40 to 150 Limits Min. 4.5

0.8 Vcc

0.7 VCC

0.43 Vcc

Typ. 5.0 V CC

M37902FCCHP , M37902FGCHP, M37902FJCHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS Unit V V V V V V V V V µA µA µA mA V mA µA f(fsys) = 26 MHz. CPU operates. Ta = 25 °C when clock is stopped. Ta = 85 °C when clock is stopped. Test conditions IOH = –10 mA IOH = –400 µA IOH = –10 mA IOH = –400 µA IOL = 10 mA IOL = 2 mA IOL = 10 mA IOL = 2 mA VI = 5.0 V VI = 0 V VI = 0 V, No pullup transistor VI = 0 V, Pullup transistor used When clock is stoped. Parameter High-level output voltage P00–P07, P10–P17, P20–P27, P30, P40–P47, P50–P57, P60–P67, P70–P77, P80–P87, P100–P107, P110–P117 High-level output voltage P00–P07, P10–P17, P20–P27, P40, P42, P44–P47, P100–P107, P110–P117 High-level output voltage P31–P33 Low-level output voltage P00–P07, P10–P17, P20–P27, P30, P40–P47, P50–P57, P60–P67, P70–P77, P80–P87, P100–P107, P110–P117 Low-level output voltage P00–P07, P10–P17, P20–P27, P40, P42, P44–P47, P100–P107, P110–P117 Low-level output voltage P31–P33 Hysteresis RDY, HOLD, TA0IN–TA4IN, TA0OUT –TA4OUT , TB0IN–TB2 IN, KI0–KI3, INT0–INT4, NMI, ADTRG , CTS 0, CTS1, CLK0, CLK1, RxD0, RxD1 Hysteresis RESET Hysteresis XIN High-level input currentP00–P07, P10–P17, P20–P27, P30–P33, P40–P47, P50–P57, P60–P67, P70–P77, P80–P87, P100–P107, P110–P117, XIN, RESET, BYTE, MD0, MD1, NMI Low-level input currentP00–P07, P10–P17, P20–P27, P30–P33, P40–P43, P50–P53, P60–P67, P70–P77, P80–P87, P100–P107, P110–P117, XIN, RESET, BYTE, MD0, MD1 Low-level input currentP44–P47, P54–P57, NMI RAM hold voltage Power source current Symbol VOH VOH VOH VOL VOL VOL VT+ — VT – VT+ — VT – VT+ — VT – IIH IIL IIL VRAM ICC DC ELECTRICAL CHARACTERISTICS (Vcc = 5 V, Vss = 0 V, Ta = –20 to 85 °C, f(fsys) = 26 MHz (Note)) Min. 4.7 3.4 4.8 0.2 0.5 0.1 –0.4 Limits Typ. –0.7 Max. 0.45 1.6 0.4 0.7 1.5 0.3 –1.1 Output-only pins are open, and the other pins are con- nected to Vss or Vcc. An external square-waveform clock is input. (Pin X OUT is open.) The PLL frequency multiplier stops its operation.

M37902FCCHP, M37902FGCHP, M37902FJCHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS 116 Resolution Absolute accuracy Ladder resistance Conversion time Reference voltage Analog input voltage R LADDER tCONV VREF VIA VREF = VCC VREF = VCC VREF = VCC f(fsys) ≤ 26 MHz Max. A-D CONVERTER CHARACTERISTICS (VCC = AVCC = 5 V ± 0.5 V, VSS = AVSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted) UnitParameterSymbol Test conditions Limits Min. 10-bit resolution mode 8-bit resolution mode 10-bit resolution mode 8-bit resolution mode 4.54 1.89 (Note) 2.7 ± 3 ± 2 VCC VREF Bits LSB LSB kΩ µs V V Note: This is applied when A-D conversion freguency (φAD ) = f1. D-A CONVERTER CHARACTERISTICS (VCC = 5 V, VSS = AVSS = 0 V, VREF = 5 V, Ta = –20 to 85 °C, unless otherwise noted) UnitParameterSymbol Limits Typ.Min. Max.Test conditions Resolution Absolute accuracy Set time Output resistance Reference power source input current t su R O IVREF (Note) 1 2.5 ± 1.0 3.2 Bits µs kΩ mA Note: The test conditions are as follows:

• One D-A converter is used.
• The D-A register value of the unused D-A converter is “00 16.”
• The reference power source input current for the ladder resistance of the A-D converter is excluded. µsRESET input low-level pulse widthtw(RESETL) Symbol Parameter Min. Limits Unit RESET INPUT Reset input timing requirements (VCC = 5 V ± 0.5 V, VSS = 0V, Ta = –20 to 85 °C, unless otherwise noted) Max.Typ. RESET input tw(RESETL)

M37902FCCHP , M37902FGCHP, M37902FJCHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS tc(TA) tw(TAH) tw(TAL) f(fsys) ≤ 26 MHz f(fsys) ≤ 26 MHz f(fsys) ≤ 26 MHz PERIPHERAL DEVICE INPUT/OUTPUT TIMING (VCC = 5 V±0.5 V, VSS = 0 V, Ta = –20 to 85 °C, f(fsys) = 26 MHz unless otherwise noted) ∗ For limits depending on f(fsys), their calculation formulas are shown below. Also, the values at f(fsys) = 26 MHz are shown in ( ). Timer A input (Up-down input and Count input in event counter mode) tc(UP) tw(UPH) tw(UPL) tsu(UP-TIN) th(TIN-UP) Symbol TAiOUT input cycle time TAiOUT input high-level pulse width TAiOUT input low-level pulse width TAiOUT input setup time TAiOUT input hold time Parameter Limits Min. 2000 1000 1000 400 400 Max. ns ns ns ns ns Unit Timer A input (External trigger input in pulse width modulation mode) tw(TAH) tw(TAL) Symbol TAiIN input high-level pulse width TAiIN input low-level pulse width Parameter Min. Limits Max. ns ns Unit Limits Symbol Parameter Min. Max. Unit 8 × 109 f(fsys) (307)TAiIN input cycle time TAiIN input high-level pulse width TAiIN input low-level pulse width ns ns ns Timer A input (External trigger input in one-shot pulse mode) Limits Symbol Parameter Min. Max. Unit 16 × 109 f(fsys) 8 × 109 f(fsys) 8 × 109 f(fsys) (615) (307) (307) t c(TA) tw(TAH) tw(TAL) TAiIN input cycle time TAiIN input high-level pulse width TAiIN input low-level pulse width ns ns ns Timer A input (Gating input in timer mode) Note :The TAiIN input cycle time requires 4 or more cycles of a count source. The TAiIN input high-level pulse width and the TAiIN input low-level pulse width respectively require 2 or more cycles of a count source. The limits in this table are applied when the count source = f2 at f(fsys) ≤ 26 MHz. Timer A input (Count input in event counter mode) tc(TA) tw(TAH) tw(TAL) Symbol TAiIN input cycle time TAiIN input high-level pulse width TAiIN input low-level pulse width Parameter Min. Limits Max. ns ns ns Unit f(f sys) ≤ 26 MHz

M37902FCCHP, M37902FGCHP, M37902FJCHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS 118 tc(TA) tsu(TAjIN-TAjOUT) tsu(TAjOUT-TAjIN) Symbol Parameter Min. 800 200 200 Limits Max. ns ns ns Unit Timer A input (Two-phase pulse input in event counter mode) TAiIN input cycle time TAjIN input setup time TAjOUT input setup time TAiIN input TAiOUT input (Up-down input) TAiOUT input (Up-down input) TAiIN input (When count by falling) TAiIN input (When count by rising) TAjIN input TAjOUT input Test conditions

• VCC = 5 V±0.5 V, Ta = –20 to 85 °C
• Input timing voltage : VIL = 0.8 V, VIH = 2.15 V
• Up-down and Count input in event counter mode
• Two-phase pulse input in event counter mode
• Gating input in timer mode
• Count input in event counter mode
• External trigger input in one-shot pulse mode
• External trigger input in pulse width modulation mode tc (TA) tw(TAH) tw(TAL) tc(UP) tw(UPH) tw(UPL) th(TIN-UP) tsu(TAjIN-TAjOUT ) tsu(TAjIN-TAjOUT ) tsu(TAjOUT -TAjIN) tsu(TAjOUT -TAjIN) tc(TA) tsu(UP-TIN)

M37902FCCHP , M37902FGCHP, M37902FJCHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS f(fsys) ≤ 26 MHz f(fsys) ≤ 26 MHz f(fsys) ≤ 26 MHz f(fsys) ≤ 26 MHz f(fsys) ≤ 26 MHz f(fsys) ≤ 26 MHz tc(TB) tw(TBH) tw(TBL) tc(TB) tw(TBH) tw(TBL) Timer B input (Count input in event counter mode) Symbol TBiIN input cycle time (one edge count) TBiIN input high-level pulse width (one edge count) TBiIN input low-level pulse width (one edge count) TBiIN input cycle time (both edge count) TBiIN input high-level pulse width (both edge count) TBiIN input low-level pulse width (both edge count) Parameter Limits Min. 160 Max. ns ns ns ns ns ns Unit Limits Symbol Parameter Min. Max. Unit 16 × 109 f(fsys) 8 × 109 f(fsys) 8 × 109 f(fsys) (615) (307) (307) t c(TB) tw(TBH) tw(TBL) TBiIN input cycle time TBiIN input high-level pulse width TBiIN input low-level pulse width ns ns ns Timer B input (Pulse period measurement mode) Note: The TBiIN input cycle time requires 4 or more cycles of a count source. The TBiIN input high-level pulse width and the TBiIN input low-level pulse width respectively require 2 or more cycles of a count source. The limits in this table are applied when the count source = f2 at f(fsys) ≤ 26 MHz. Limits Symbol Parameter Min. Max. Unit 16 × 109 f(fsys) 8 × 109 f(fsys) 8 × 109 f(fsys) (615) (307) (307) t c(TB) tw(TBH) tw(TBL) TBiIN input cycle time TBiIN input high-level pulse width TBiIN input low-level pulse width ns ns ns Timer B input (Pulse width measurement mode) Note: The TBiIN input cycle time requires 4 or more cycles of a count source. The TBiIN input high-level pulse width and the TBiIN input low-level pulse width respectively require 2 or more cycles of a count source. The limits in this table are applied when the count source = f2 at f(fsys) ≤ 26 MHz. tc(AD) tw(ADL) Symbol AD TRG input cycle time (minimum allowable trigger) AD TRG input low-level pulse width Parameter Min. 1000 125 Limits Max. ns ns Unit A-D trigger input

M37902FCCHP, M37902FGCHP, M37902FJCHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS 120 tc(CK) tw(CKH) tw(CKL) td(C-Q) th(C-Q) tsu(D-C) th(C-D) Serial I/O Symbol CLK i input cycle time CLK i input high-level pulse width CLK i input low-level pulse width TXD i output delay time TXD i hold time R XD i input setup time R XD i input hold time Parameter Limits Min. 200 100 100 Max. ns ns ns ns ns ns ns Unit tw(INH) tw(INL) Symbol INTi input/NMI input/KIi input high-level pulse width INTi input/NMI input/KIi input low-level pulse width Parameter Min. 250 250 Limits Max. ns ns Unit External interrupt (INTi) input, NMI input, Key input interrupt (KIi) input tc(TB) tw(TBH) tw(TBL) tc(CK) tw(CKH) tw(CKL) th(C - Q) td(C - Q) tsu(D - C) tw(INH) tw(INL) th(C - D) tc(AD) tw(ADL) TBiIN input INTi input, AD TRG input CLKi input TxDi output RxDi input NMI input, KIi input Test conditions

• Vcc = 5 V ± 0.5 V, Ta = –20 to 85 °C
• Input timing voltage : VIL = 0.8 V, VIH = 2.15 V
• Output timing voltage : VOL = 0.8 V, VOH = 2.0 V, CL = 50 pF

M37902FCCHP , M37902FGCHP, M37902FJCHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS td(φ1-HLDAL) td(RDH-HLDAL) td(BXWH-HLDAL) tpxz(HLDAL-RDZ) tpxz(HLDAL-BXWZ) tpxz(HLDAL-CSiZ) tpxz(HLDAL-ALEZ) tpxz(HLDAL-AZ) tpzx(HLDAL-RDZ) tpzx(HLDAL-BXWZ) tpzx(HLDAL-CSiZ) tpzx(HLDAL-ALEZ) tpzx(HLDAL-AZ) READY, HOLD TIMING Timing requirements(VCC = 5 V±0.5 V, VSS = 0 V, Ta = –20 to 85 °C, f(fsys) = 26 MHz, unless otherwise noted) tsu(RDY-φ1) tsu(HOLD-φ1) th(φ1-RDY) th(φ1-HOLD) Symbol RDY input setup time HOLD input setup time RDY input hold time HOLD input hold time Parameter Limits Min. Max. ns ns ns ns Unit Switching characteristics (VCC = 5 V±0.5 V, VSS = 0 V, Ta = –20 to 85 °C, f(fsys) = 26 MHz, unless otherwise noted) Symbol HLDA output delay time HLDA low-level output delay time after read HLDA low-level output delay time after write Floating start delay time Floating start delay time Floating start delay time Floating start delay time Floating start delay time Floating release delay time Floating release delay time Floating release delay time Floating release delay time Floating release delay time Parameter Min. tc –15 (Note) tc –15 (Note) –15 –15 –15 –15 –15 Limits Max. ns ns ns ns ns ns ns ns ns ns ns ns ns Unit Note: tc = 1/f(fsys).

M37902FCCHP, M37902FGCHP, M37902FJCHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS 122 RDY input tsu (RDY-φ1) RD, BLW, BHW : Wait inserted by software (The above is applied when bus cycle = 1φ + 2φ) : Wait inserted by ready function RDY input th (φ1-RDY) Test conditions

• VCC = 5 V ± 0.5 V, Ta= –20 to 85 °C
• RDY input, HOLD input : VIL = 0.8V, VIH = 2.15 V
• HLDA output : V OL = 0.8V, VOH = 2.0 V, CL = 50 pF HOLD input tsu (HOLD-φ1) td (φ1-HLDAL) tpxz (HLDAL-RDZ) tpxz (HLDAL-BXWZ) tpxz (HLDAL-CSiZ) tpxz (HLDAL-AZ) th (φ1-HOLD) td (φ1-HLDAL) tpzx (HLDAL-RDZ) tpzx (HLDAL-BXWZ) tpzx (HLDAL-CSiZ) tpzx (HLDAL-ALEZ) tpzx (HLDAL-AZ) Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z HOLD input HLDA output RD BLW BHW CS i A0–A23 output td (RDH-HLDAL) td (BXWH-HLDAL) tpxz (HLDAL-ALEZ) ALE

M37902FCCHP , M37902FGCHP, M37902FJCHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS tc(in) tw(half) tw(H) tw(L) tr tf ta(A-D) ta(A-D) ta(CSiL-D) ta(RDL-D) tsu(D-RDL) th(RDH-D) ta(BA-D) th(BA-D) ta(LA-D) Max. 0.55 tc (W H + WL) tc-45 (W H + W L-0.5) tc-35 (W H + W L-0.5) tc-35 W L ✕ tc-30 W L ✕ tc-35 Min. 0.45 tc 0.5 tc – 6 0.5 tc – 6 (W H + WL-0.5)tc-35 (Note) External clock input cycle time External clock input pulse width with half input-volage External clock input high-level pulse width External clock input low-level pulse width External clock input rise time External clock input fall time Address access time (the address output select bit = 0) Address access time (the address output select bit = 1) Chip select access time Read access time Read data setup time Data input hold time after read Address access time at burst ROM access Data hold time after address at burst ROM access Address access time (the multiplexed bus select bit = 1) 1φ +1φ 1φ +2φ 1φ +3φ 2φ +2φ Limits External bus timing For limits depending on f(fsys), their calculation formulas are shown below. Symbol Parameter ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit External clock input tr tf tw(L) tw(H) tw(half) XIN tc(in) Test conditions

• Vcc = 5 V ± 0.5 V, Ta = –20 to 85 °C
• Input timing voltage : VIL = 1.0 V, VIH = 4.0 V (tw(H), tw(L), tr, tf)
• Output timing voltage : 2.5 V (tc(in), tw(half)) Bus cycle W H W L Bus cycle W H W L 2φ +3φ 2φ +4φ 3φ +3φ 3φ +4φ tc = 1/f(fsys). Timing Requirements (VCC = 5 V±0.5 V, VSS = 0 V, Ta = –20 to 85 °C, f(XIN) = 26 MHz, unless otherwise noted) Note: This is independent of the address output select bit’s contents.

M37902FCCHP, M37902FGCHP, M37902FJCHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS 124 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Bus cycle = 2φ + 2φ Bus cycle = 3φ + 3φ, 3φ + 4φ t d(φ1-RDL) td(φ1-RDH) td(φ1-BXWL) td(φ1-BXWH) td(φ1L-CSiL) td(φ1L-CSiH) td(φ1H-A) td(φ1L-A) tw(ALEH) td(A-ALEL) tw(RDL) tw(RDH) td(RDH-BXWH) td(A-RDH) td(A-RDH) th(RDH-A) th(RDH-A) td(RDH-ALEL) td(ALEL-RDH) td(CSiL-RDH) td(CSiL-RDL) th(RDH-CSiL) td(RDH-D) tw(BXWL) tw(BXWH) td(BXWH-RDH) td(A-BXWH) td(A-BXWH) th(BXWH-A) th(BXWH-A) td(BXWH-ALEL) td(ALEL-BXWH) td(CSiL-BXWH) td(CSiL-BXWL) th(BXWH-CSiL) td(D-BXWL) th(BXWH-D) tpxz(BXWH-DZ) Parameter Switching characteristics (VCC = 5 V±0.5 V, VSS = 0 V, Ta = –20 to 85 °C, f(fsys) = 26 MHz, unless otherwise noted) Max. 0.5tc + 10 Min. –18 –18 –18 –18 –20 –22 –20 0.5tc-19 tc-20 1.5tc-20 tc-30 1.5tc-30 2tc-30 0.5tc-19 tc-20 1.5tc-20 W L ✕ tc-15 W H ✕ tc-15 tc-15 W H ✕ tc-30 (W H -0.5)tc-19 0.5tc-10 0.5tc-19 tc-15 (W H -0.5)tc-19 (W H + WL-0.5)tc-20 0.5tc-14 tc-15 W L ✕ tc-15 W H ✕ tc-15 tc-15 W H ✕ tc-30 (W H -0.5)tc-19 0.5tc-10 0.5tc-19 tc-15 (W H -0.5)tc-19 (W H + WL-0.5)tc-20 0.5tc-14 W L ✕ tc-20 0.5tc-10 Read low-level output delay time Read high-level output delay time Write low-level output delay time Write high-level output delay time Chip select low-level output delay time Chip select high-level output delay time Address output delay time (the address output select bit = 0) Address output delay time (the address output select bit = 1) ALE pulse width ALE completion delay time after address stabilization (when the address output select bit = 0) ALE completion delay time after address stabilization (when the address output select bit = 1) Read output pulse width Read output high-level width (Note 1) Write disable valid time after read (Note 2) Address valid time before read (when the address output select bit = 0) Address valid time before read (when the address output select bit = 1) Address hold time after read (when the address output select bit = 0) (Note 2) Address hold time after read (when the address output select bit = 1) (Note 2) ALE completion delay time after read start Read disable valid time after ALE completion Chip select valid time before read Chip select output valid time before read completion Chip select hold time after read Next write cycle data output delay time after read (Note 2) Write output pulse width Write output high-level width (Note 1) Read disable valid time after write (Note 2) Address valid time before write (when the address output select bit = 0) Address valid time before write (when the address output select bit = 1) Address hold time after write (when the address output select bit = 0) (Note 2) Address hold time after write (when the address output select bit = 1) (Note 2) ALE completion delay time after write start Write disable valid time after ALE completion Chip select valid time before write Chip select output valid time before write completion Chip select hold time after write Data output valid time before write completion Data hold time after write (Note 3) Floating start delay time after write (Note 3) Limits Symbol Unit Bus cycle = 1φ + 1φ, 1φ + 2φ, 1φ + 3φ Bus cycle = 2φ + 2φ Bus cycle = 2φ + 3φ, 2φ + 4φ, 3φ + 3φ, 3φ + 4φ Bus cycle = 1φ + 1φ, 1φ + 2φ, 1φ + 3φ Bus cycle = 2φ + 2φ Bus cycle = 2φ + 3φ, 2φ + 4φ, 3φ + 3φ, 3φ + 4φ Bus cycle = 2φ + 2φ Bus cycle = 2φ + 3φ, 2φ + 4φ, 3φ + 3φ, 3φ + 4φ Notes 1: When the bus cycle just before this parameter is for the area where the recovery cycle insertion is selected, this parameter is extended by tc (ns: one recovery cycle is inserted.) or by 2tc (ns: two recovery cycles are inserted.). 2: When accessing the area where the recovery cycle insertion is selected, this parameter is extended by tc (ns: one recovery cycle is inserted.) or by 2tc (ns: two recovery cycles are inserted.). 3: This parameter is extended by tc (ns) when both of the following conditions are satisfied:

• When accessing the area where the recovery cycle insertion is selected.
• When two recovery cycles are inserted. Bus cycle = 1φ + 1φ, 1φ + 2φ, 1φ + 3φ Bus cycle = 2φ + 2φ Bus cycle = 2φ + 3φ, 2φ + 4φ, 3φ + 3φ, 3φ + 4φ

M37902FCCHP , M37902FGCHP, M37902FJCHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS td(LA-RDH) td(LA-ALEL) th(ALEL-LA) tpxz(RDH-LAZ) td(LA-BXWH) tpzx(RDH-DZ) Address valid time before read ALE completion delay time after address stabilization Address hold time after ALE completion Floating start delay time Address valid time before write Floating release delay time Bus cycle = 2φ + 2φ Bus cycle = 3φ + 3φ, 3φ + 4φ Bus cycle = 2φ + 2φ Bus cycle = 3φ + 3φ, 3φ + 4φ Switching characteristics (V CC = 5 V±0.5 V, VSS = 0 V, Ta = –20 to 85 °C, f(fsys) = 26 MHz, unless otherwise noted) Parameter Max. Min. (WH-0.5)tc-19 (Note) tc-20 (Note) 1.5tc-20 (Note) 0.5tc-19 tc-15 (WH-0.5)tc-19 (Note) 0.5tc-19 (Note) Limits Symbol ns ns ns ns ns ns ns ns Unit Note: This is independent of the address output select bit’s contents.

M37902FCCHP, M37902FGCHP, M37902FJCHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS 126 Bus cycle th(RDH-D) th(RDH-A) tw(RDL) ta(CSiL-D) ta(RDL-D) ta(A-D) td(CSiL-RDL) tsu(D-RDL) tw(ALEH) td(RDH-ALEL) tc td(A-ALEL) tw(RDH) td(RDH-D) td(φ1-RDL) th(RDH-A) td(A-RDH) td(CSiL-RDH) ta(A-D) td(A-ALEL) td(φ1H-A) td(φ1L-A) td(φ1L-CSiL) td(φ1L-CSiH) td(φ1-RDH) th(RDH-CSiL) td(RDH-BXWH) td(A-RDH) CS i RD ALE fsys BLW BHW <At read> Normal access: bus cycle = 1φ + 1φ, 1φ + 2φ, 1φ+ 3φ, 2φ + 3φ, or 2φ + 4φ A0–A23 (when the address output select bit = 0) A0–A23 (when the address output select bit = 1) D 0–D 7, D8–D 15 Test conditions

• VCC = 5 V ±0.5 V, Ta = –20 to 85 °C
• Input timing voltage : VIL=0.8 V, VIH=2.15 V
• Output timing voltage: VOL =0.8 V, VOH =2.0 V, CL=15 pF (CSi)
• Output timing voltage: VOL =0.8 V, VOH =2.0 V, CL=50 pF (except for CSi)

M37902FCCHP , M37902FGCHP, M37902FJCHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS th(BXWH-A) td(CSiL-BXWL) tw(BXWL) td(BXWH-ALEL) td(D-BXWL) th(BXWH-D) tpxz(BXWH-DZ) Bus cycle td(φ1-BXWL) th(BXWH-A) td(A-BXWH) td(CSiL-BXWH) tc td(A-ALEL) tw(ALEH) td(φ1H-A) td(φ1L-CSiL) td(φ1L-CSiH) td(BXWH-RDH) td(φ1-BXWH) th(BXWH-CSiL) td(A-ALEL) tw(BXWH) td(A-BXWH) td(φ1L-A) CS i RD ALE BLW BHW fsys <At write> Normal access: bus cycle = 1φ + 1φ, 1φ + 2φ, 1φ + 3φ, 2φ + 3φ, or 2φ + 4φ A0–A23 (when the address output select bit = 0) A0–A23 (when the address output select bit = 1) D 0–D 7, D8–D 15 Test conditions

• VCC = 5 V ±0.5 V, Ta = –20 to 85 °C
• Input timing voltage : VIL=0.8 V, VIH=2.15 V
• Output timing voltage: VOL =0.8 V, VOH =2.0 V, CL=15 pF (CSi)
• Output timing voltage: VOL =0.8 V, VOH =2.0 V, CL=50 pF (except for CSi)

M37902FCCHP, M37902FGCHP, M37902FJCHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS 128 td(A-RDH) Bus cycle td(CSiL-RDL) td(A-ALEL) th(RDH-D) th(RDH-A) tw(RDL) ta(CSiL-D) ta(RDL-D) ta(A-D) tsu(D-RDL) tw(ALEH) tc tw(RDH) td(RDH-D) td(ALEL-RDH) td(φ1-RDL) td(φ1-RDH) th(RDH-D) ta(LA-D) ta(RDL-D) td(LA-RDH) tsu(D-RDL) tpzx(RDH-DZ) td(LA-ALEL) th(ALEL-LA) tpxz(RDH-LAZ) th(RDH-A)td(A-RDH) td(CSiL-RDH) ta(A-D) Address Input data Address td(φ1H-A) td(φ1L-CSiL) td(φ1L-CSiH) td(RDH-BXWH) th(RDH-CSiL) td(A-ALEL) td(φ1L-A) CS i RD ALE BLW BHW fsys Note: Valid only when area CS2 is accessed with the external data bus width = 8 bits. <At read> Normal access: bus cycle = 2φ + 2φ, 3φ + 3φ, 3φ + 4φ A0–A23 (when the address output select bit = 0) D 0–D 7, D8–D 15 (when the multiplexed bus select bit = 0) LA0/D0–LA7/D7 (when the multiplexed bus select bit = 1, Note) A0–A23 (when the address output select bit = 1) Test conditions

• VCC = 5 V ±0.5 V, Ta = –20 to 85 °C
• Input timing voltage : VIL=0.8 V, VIH=2.15 V
• Output timing voltage: VOL =0.8 V, VOH =2.0 V, CL=15 pF (CSi)
• Output timing voltage: VOL =0.8 V, VOH =2.0 V, CL=50 pF (except for CSi)

M37902FCCHP , M37902FGCHP, M37902FJCHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS td(CSiL-BXWL) th(BXWH-A)td(A-BXWH) tw(ALEH) tw(BXWL) td(D-BXWL) th(BXWH-D) tpxz(BXWH-DZ) td(A-ALEL) tw(BXWH) td(ALEL-BXWH) Bus cycle td(φ1-BXWL) th(BXWH-D) tpxz(BXWH-DZ) td(D-BXWL) th(ALEL-LA)td(LA-ALEL) td(LA-BXWH) tc th(BXWH-A)td(A-BXWH) td(CSiL-BXWH) Address Output data td(φ1-BXWH)td(φ1H-A) td(φ1L-CSiL) td(φ1L-CSiH) td(A-ALEL) th(BXWH-CSiL) td(BXWH-RDH) td(φ1L-A) CS i RD ALE BLW BHW fsys Note: Valid only when area CS2 is accessed with the external data bus width = 8 bits. <At write> Normal access: bus cycle = 2φ + 2φ, 3φ + 3φ, 3φ + 4φ A0–A23 (when the address output select bit = 0) D 0–D 7, D8–D 15 (when the multiplexed bus select bit = 0) LA0/D0–LA7/D7 (when the multiplexed bus select bit = 1, Note) A0–A23 (when the address output select bit = 1) Test conditions

• VCC = 5 V ±0.5 V, Ta = –20 to 85 °C
• Input timing voltage : VIL=0.8 V, VIH=2.15 V
• Output timing voltage: VOL =0.8 V, VOH =2.0 V, CL=15 pF (CSi)
• Output timing voltage: VOL =0.8 V, VOH =2.0 V, CL=50 pF (except for CSi)

M37902FCCHP, M37902FGCHP, M37902FJCHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS 130 th(BA-D) td(RDH-BXWH) BLWBHW RD ta(RDL-D) td(A-RDH) CS i th(RDH-A) ta(CSiL-D) ta(A-D) ta(BA-D) th(BA-D) th(BA-D) th(RDH-D) ta(BA-D) ta(BA-D) th(RDH-CSiL) td(CSiL-RDH) td(A-ALEL) tw(ALEH) ALE td(RDH-ALEL) tw(RDH) td(A-RDH) th(RDH-A) ta(A-D) Burst ROM access: bus cycle = 1 φ + 1 φ, 1 φ + 2 φ, 1 φ + 3 φ, 2 φ + 3 φ, 2 φ + 4 φ D 0–D 7, D 8–D Test conditions • V CC = 5 V ±0.5 V, Ta = –20 to 85

• Input timing voltage : V IL =0.8 V, V IH =2.15 V
• Output timing voltage: V OL =0.8 V, V OH =2.0 V, C L=15 pF (CS
• Output timing voltage: V OL =0.8 V, V OH =2.0 V, C L=50 pF (except for CS A 0–A (when the address output select bit = 0) A 0–A (when the address output select bit = 1) td(A-ALEL)

M37902FCCHP , M37902FGCHP, M37902FJCHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS Notes regarding these materials

• These materials are intended as a reference to assist our customers in the selection of the Mitsubishi semiconductor product best suited to the customer’s application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Mitsubishi Electric Corporation or a third party.
• Mitsubishi Electric Corporation assumes no responsibility for any damage, or infringement of any third-party’s rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials.
• All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by Mitsubishi Electric Corporation without notice due to product improvements or other reasons. It is therefore recommended that customers contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for the latest product information before purchasing a product listed herein. The information described here may contain technical inaccuracies or typographical errors. Mitsubishi Electric Corporation assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. Please also pay attention to information published by Mitsubishi Electric Corporation by various means, including the Mitsubishi Semiconductor home page (http://www.mitsubishichips.com).
• When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. Mitsubishi Electric Corporation assumes no responsibility for any damage, liability or other loss resulting from the information contained herein.
• Mitsubishi Electric Corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use.
• The prior written approval of Mitsubishi Electric Corporation is necessary to reprint or reproduce in whole or in part these materials.
• If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited.
• Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for further details on these materials or the products contained therein. © 2000 MITSUBISHI ELECTRIC CORP. New publication, effective Jun., 2000. Specifications subject to change without notice. Keep safety first in your circuit designs!
• Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non-flammable material or (iii) prevention against any malfunction or mishap. PACKAGE OUTLINE LQFP100-P-1414-0.50 Weight(g) JEDEC CodeEIAJ Package Code Lead Material Cu Alloy 100P6Q-A Plastic 100pin 14✕ 14mm body LQFP 0.1 0.2 Symbol Min Nom Max A b c D E H E L y Dimension in Millimeters H D 0.225 ––I2 1.0 ––M D 14.4 ––M E 14.4 10°0° 0.1 1.0 0.70.50.3 16.216.015.8 16.216.015.8 0.5 14.114.013.9 14.114.013.9 0.1750.1250.105 0.280.180.13 1.4 1.7 e e e E c H E 5026 H D D M D M E A F b A A L y Recommended Mount Pad Detail F 100

Rev. Rev. No. date

1.0 First Edition 990305

2.0 Refer to Corrections and Supplementary Explanation for “M37902FxC Datasheet (REV.A)”.990625

3.0 The following are revised/added points in this edition: 990917

• Figure 26 in page 40; the bit’s name (bit 7) of the port function control register <Error> Pin NMI pullup connection select bit (Note 2) <Correction> Pin NMI pullup select bit (Note 2)
• Page 95; CLOCK GENERATING CIRCUIT , Right column, line 10 <Error> ••••• the PLL output clock (fPLL). (In other words, set bit 5 to “1”.) <Correction> ••••• the PLL output clock (fPLL). (In other words, set bit 5 to “1”.) Note that, after reset, the PLL multiplication ratio select bits are allowed to be changed only once.
• Table 15 in page 95; Note is revised. <Error> ••••• f(XIN) means the frequency of the input clock from pin XIN f(XIN). <Correction> ••••• f(XIN) means the frequency of the input clock from pin XIN f(XIN). After reset, the PLL multiplication ratio select bits are allowed to be changed only once.
• Page 120; RECOMMENDED OPERATING CONDITIONS <Error> f(fsys) External clock input frequency (Note 2) ••••••••••• <Correction> f(XIN) External clock input frequency (Note 2) •••••••••••

4.0 The following are revised/added points in this edition: 991008

• Page 83; D-A CONVERTER , Left column, line 15 <Error> The D-A output enable bit is cleared to “0” at reset. •••• <Correction> The contents of the corresponding D-A output enable bit and D-A register are
• Page 83; D-A CONVERTER , Right column, line 1 <Error> with pin D-Ai. <Correction> with pin D-Ai. Also, when not using the D-A converter, be sure to clear the contents of the corresponding D-A output enable bit and D-A register to “0”. 5.0 Refer to Corrections and Supplementary Explanation for “M37902FxC Datasheet (REV.B)”.000629 Notes 1: # represents the new information added in Rev.5.0. 2: The revised/added points informed in Rev.3.0 and Rev.4.0 are included in Corre- ctions and Supplementary Explanation for “M37902FxC Datasheet (REV.B)”. Revision History M37902FxCHP Datasheet (1/1) Revision Description

Corrections and Supplement ar y Explanation for M37902FxC Dat asheet (REV. B) NO.1 Page Erro r Correction (1/11) Page 3, B LO C K DIAGRA M No t Note: RAM 2048 bytes 4096 bytes 6144 bytes 6144 bytes 12288 bytes 12288 bytes M37902F8 C G P,M37902F8C H P M37902FC CGP ,M3790 C CHP M37902FECGP,M37902FECHP M37902FGCGP, M 37902FG C HP M37902FH CGP ,M3790 H CHP M37902FJC G P,M37902FJCH P Flash memory

60 Kbytes

184 Kbytes

370 Kbytes

Note: RAM 4096 bytes 6144 bytes 12288 bytes M37902F C C H P M37902FGCH P M37902FJC HP Flash memory # All pages, H eader PRELIMINARY Notice: This is not a final specification. Some parametric limits are subject to change. (Deleted) P63/ INT2 P64/INT2 Page 2, PIN CONFI GUR AT ION Page 105, Fig 112, Pi n conne ct i on of M3790 xC HP in f l ash m emory M37902F8 C G P , M37902F 8C HP , M37902FC CG P, M37902FC CHP M37902FE CGP, M 37902 FEC HP, M37902FGCGP, M37902FGCHP M37902F HCGP, M37902FH CHP M37902FJC G P M37902FJC HP M37902F C C HP , M37902FGC H P, M37902F JC HP Page 1, DISTI N CTI VE FEAT U RES M emory [M 379 02F8CG P , M37902F8C HP] Fl ash memor y (User R O M ar ea .... .... ... .... .... .60 Kbytes RA M ... .... .... .... ... .... .... .... ... .... .... .... .... ... .... .... .... .2048 bytes (Deleted) [M 379 02FCC G P , M37902FC C HP ] Fl ash memor y (User R O M ar ea .... .... ... .... ...120 Kbytes RA M ... .... .... .... ... .... .... .... ... .... .... .... .... ... .... .... .... .4096 bytes [M 379 02FCC HP] Fl ash memor y (User R O M ar ea .... .... ... .... ...120 Kbytes RA M ... .... .... .... ... .... .... .... ... .... .... .... .... ... .... .... .... .4096 bytes [M37902FECG P, M37902FEC HP] (Deleted) [M37902FGCG P, M37902FGC HP] [M37902F GC HP] [M37902FH CG P, M37902FHC HP] (Deleted) [M 379 02FJCG P, M37902FJC H P] Fl ash memor y (User R O M ar ea .... .... ... .... ...498 Kbytes RA M ... .... .... .... ... .... .... .... ... .... .... .... .... ... .... .... ...12288 byt e s [M 379 02FJC H P] Fl ash memor y (User R O M ar ea .... .... ... .... ...498 Kbytes RA M ... .... .... .... ... .... .... .... ... .... .... .... .... ... .... .... ...12288 byt e s Page 1, APPLI C AT ION C ontrol devices for personal computer peripheral equi p- ment such as CD-ROM drives, DV R O M dr i ves, hard disk drives, high density FDD printers Control devices for office equipment such as copi er s and f a csim i les Control devices for in dust rial eq uipment such as comm nication and measuring instrum ents C ontrol devices for personal computer peripheral equip- ment such as CD-ROM drives, DVD-ROM drives, hard disk drives, high density FDD , printers # M37902Fx C G P P IN C ONFI G URA TIO N (TOP V I E W) (Deleted) M37902F8 CHP M37902FCCHP M37902FECHP M37902FGCHP M37902FHCHP M37902FJCHP M37902F CC HP M37902FGCHP M37902FJCHP (Type) (Type) Pa ge 4, Ch ip-select wait control C hi p sel ect area ✕ 4 ( C S0–C S3) . A wai t number an d bus width can be set for each ch ip select ar ea. C hi p sel ect area ✕ 4 ( C S0–C S3) . A bus cycle type and bus width can be set for e ach ch ip select a r ea.

Corrections and Supplement ar y Explanation for M37902FxC Dat asheet (REV. B) NO.2 Page Erro r Correction (2/11) 00FFC0 16 Internal f l ash memory (User ROM area) FFFF 16 00200016 00FFC0 16 Internal f l ash memory (User ROM area) 00FFFF 16 00200016 Page 9, MEMORY, Line 2

• • •••• ••• . The addre ss spa ce i s 1 6 Mb yt es from address 016 to FFFF FF16. ••
• •••
• ••
• ••••••••. The address space is 16 Mbytes from Page 4, Parameter Pa ge 6, P40–P47 I I n mi croprocessor mode
• •••
• •. According to the register setting, P40–P44 also ••
• ••
• ••• I I n mi croprocessor mode
• •••
• •. According to the register setting, P40–P43 also ••
• ••
• ••• Operating temperature range •••••• Oper a t i ng a m bie nt tem p er ature r ange ••••• Page 4, No t Note: RAM 2048 bytes 4096 bytes 6144 bytes 6144 bytes 12288 bytes 12288 bytes M37902F8 C G P,M37902F8C H P M37902FC CGP ,M3790 C CHP M37902FECGP,M37902FECHP M37902FGCGP, M 37902FG C HP M37902FH CGP ,M3790 H CHP M37902FJC G P,M37902FJCH P Flash memory (User ROM area)

M37902F8 C G P,M37902F8C H P M37902FC CGP ,M3790 C CHP M37902FECGP,M37902FECHP M37902FGCGP, M 37902FG C HP M37902FH CGP ,M3790 H CHP M37902FJC G P,M37902FJCH P Note: RAM 4096 bytes 6144 bytes 12288 bytes M37902F CC H P M37902FGCHP M37902FJCHP Flash memory (User ROM area) Page 5, Notes 1: User R O M area M37902F8C G M 37902F8CH P 4 bl M37902FCCGP, M37902FCCHP 5 blocks •••••• M37902FECGP, M37 902FE C HP 6 bl M37902FGCGP, M37902 F GCH P 7 bl M37902FHCGP, M37902FHCHP 9 blocks •••••• M37902FJC G M 37902FJCHP 11 bl User R O M area M37902FC M37902FJCHP 11 blocks ••••• Page 9, Fig. 1 Fi g. 2. M emory map of M37902F CCG P and M37902FC CHP (Si ngle-chip m od Fig. 1. Memory map of M37902FCC HP (Single-chip mode) Memory map of M37902F8CG P and M37902F 8C HP (Single-chip mode) (Deleted)# Mem ory m ap of M 379 02FE C G P and M 37902 FE C HP (Singl chi p m ode) # (Deleted) Mem ory m ap of M 379 02FH C G P an d M37902F H C HP (Singl chi p m ode) (Deleted)

Corrections and Supplement ar y Explanation for M37902FxC Dat asheet (REV. B) NO.3 Page Erro r Correction (3/11) 00FF C0 16 Internal f l ash memory (User ROM area) FFFF 16 00380016 00FFC0 16 Internal f l ash memory (User ROM area) 00FFFF 16 00380016 00FF C0 16 Internal f l ash memory (User ROM area) 00FFFF 16 00380016 00FFC0 16 Internal f l ash memory (User ROM area) 00FFFF 16 00380016 Po r t 011 direct i on regi st er00001916 00001A16 Port P11 direction register00001916 00001A16 Page 11, Fig. 7 00000016 00000116 00000016 00000116 Reserved area (Note) Reserved area (Note)address 0016, 0116 address 1916 Fi g. 4. M emory map of M37902F G C G P and M37902FGCH P ( S ingle-chip mode) Fig. 2. Memory map of M37902FGC HP (Single-chip mode)Page 10, Fig. 2 Fi g. 6. M emory map of M37902F JCG P and M37902FJC HP (Singl chi p mode) Fig. 3. Memory map of M37902FJC HP (Single-chip mode)Page 10, Fig. 3 Page 12, Fig. 8 Serial I/O control r egi st e r0 000AC 16 000AD 16 Serial I/O pin control register0 000AC 16 000AD 16 address A616 address AC 16, AD16 Reserved a r ea (Note)0000A 616 0000A 716 (Deleted)

Corrections and Supplement ar y Explanation for M37902FxC Dat asheet (REV. B) NO.4 Page Erro r Correction (4/11) b31 b0 DB Data buff er b31 b0 D Q Data buff er Page 18, Fig. 11 Page 26, Fig. 18, Notes 1 N o t e s 1 : The number of bus cycles is determi- ned by the follow ing bits:

• •••
• ••
• ••• Notes 1: The bus cycle type is determined by the following bits: Page 31, R ight column Line 5
• • •••• ••. Therefore, ports P0 or P 4 , P10, P11 fun- ction as I/O pin s for the address bus, ••
• •••
• •••••••. Therefore, ports P0 to P4, P10, P11 fun- ction as I/O pins for the address bus, •••••••• Mode (Note 1) Pin MD0 Processor mode (Note 2) Page 33, Table 5 Mode (Note 1) Pin MD0 Processor mode bi t s (Note 2) Page 35, Fig. 24, Note N o t e s 1 : W h i l e VS While VC C ••••
• , bit 1 i s se t to “1” at reset. (Fixed to “1”.) Notes 1: While VSS •••••, this bit’s state is cleared to “0” at reset. While VCC •••••, this bit’s state is set to “1” at reset. (Fixed to “1”.) 3: While VSS •••••, bit 7 is cleared to “0”. While VCC •••••, bit 7 is set to “1” at reset. 3: While VSS •••••, this bit’s state is cleared to “0” at reset. While VCC •••••, this bit’s state is set to “1” at reset. 4 : W h i l e VS S •••••, these bits ar e cleared to “0”. Whil e VC on the ot h er hand, t h ese b its are set to “ 4: While VSS •••••, each of these bits is “0” at reset. While VCC •••••, on the other hand, each of these bits is “1” at reset. Data buff er Temporari t y stores data which has bee n • ••• ••• •, and external are as b y the BIU or which is to be writeen to internal me mory,
• ••
• ••• Temporarily stores data which has been ••••••••, and external areas by the BIU; or temporarily stores data which is to be written to internal # Page 18, Table 1 I nstruction queue buff er Temporarity stores an instruction which ••••••••. Temporarily stores an instruction which ••••••••. Processor mode regi st er 1 10243567 Recove ry-cycle-i nsert sel ect bi t
• ••• Int er nal RO M b us cycl e sel ect bit (Note 6)
• ••• Page 36, Fig. 25 Processor mode regi st er 1 10243567 Recove ry-cycle-i nsert sel ect bi t o te
• ••• Int er nal RO M b us cycl e sel ect bit (Note 7)
• ••• 2: A ft er r eset, t hi s b it’s cont en t s can be switched only once. During the software execution, be su r e not t o swi t ch this bit’s contents. 2: A ft er r eset, t hi s b it can be set only once. D ur i ng t he softwar e execu t i on, be sure not to change this bit. 5: In the memory expansion or microprocessor mode, if this bit’s contents is switched from “1” to “0”, this bit will be cleared to “0”. After this clearance, this bit cannot return to “1”. If it is necessary to set this bit to “1”, be sure to reset the microcomputer. 5: A ft er r eset, t he se bi t s can be set to “1” only once. Once t he se bi t s have been clea r ed to “ 0” f rom “1”, they cannot be set to “1” ag ain. (Fi xed t o “0”

Corrections and Supplement ar y Explanation for M37902FxC Dat asheet (REV. B) NO.5 Page Erro r Correction (5/11) Page 3 7 , Fig. 26, bit 4 Pins P44–P47 pullup connectio n sel ect bit Pins P44–P47 pullup sel ect bit • •• • Pin NMI pull up conn ect i on sel ect bi t o te Pin NMI pull up sel ect bi t (Note 2) Page 39, Table 7 A r ea m ultiplexe d bus address (Note 3) Area multiplexed bus access (Note 3) Page 40, Fig. 28, CS 0 control register Note # Notes 1: While VSS •••••, this bit is cleared to “0”. While VCC •••••, this bit is set to “1” at reset. Notes 1: While VSS •••••, this bit’s state is cleared to “0” at reset. While VCC •••••, this bit’s state is set to “1” at reset. 5: While VSS •••••, this bit is cleared to “0”. While VCC •••••, this bit is set to “1” at reset. (Fixed to “1”.) 5: While VSS •••••, this bit’s state is cleared to “0” at reset. While VCC •••••, this bit’s state is set to “1” at reset. (Fixed to “1”.) 7: In the microprocessor mode, this bit is invalid. When the internal flash memory is reprogrammed in the CPU reprogramming mode, be sure to clear this bit to “0”. 6: The program which switches this bit’s contents must be assigned to the internal area. Page 36, Fig. 25 6: In the m icroprocessor mode, t hi s b it i s i nvalid. Page 42, Fig. 30, Area CSx start address register (x = 0 to 3) Page 43, Fig. 31 256 K bytes 1FFF FF16 FFFFF 16 S tart address : 400016 1FFF FF16 FFFFF 16 Start address : 400016 Area C Sx start address register (x = 0 to 2) 01 01 Area C Sx start address register (x = 0 to 2) “0” at read. 2 2 Area C S3 start address register 01 01 These bi t s determ i ne ••••• Area C S3 start address register “0” at read. 2 2 These bits determine •••••

Corrections and Supplement ar y Explanation for M37902FxC Dat asheet (REV. B) NO.6 Page Erro r Correction (6/11) Page 44, Fig. 32 00016 (FFF FF16) 016 800016 Block size : 4 Kbytes E000016 (FFFFF16) 016 800016 Block size : 8 Kbytes Addresses w hich can be

• ••• A ddr ess FFF FF16 is not i nclud ed; Note 1) Addresses w hich can be
• ••• A ddr ess FFF FF16 is not i nclud ed; Note 1) 0016 F FFF 16) 016 800016 Block size : 4 Kbytes E00016 (FFFF16) 016 800016 Block size : 8 Kbytes Addresses w hich can be
• ••• (Address FFFF16 i s not i nclud ed; Note 1) Addresses w hich can be
• ••• (Address FFFF16 i s not i nclud ed; Note 1) Page 45, Fig. 33 Bl ock si ze

8 Mbyt

w hich can be

• ••• (Addresses 016 and FF00001 are not in cluded; N ote 016 Bl ock si ze

Addresses which can be ••••• (Addresses 016 and FF000016 to FFFFFF16 are not included; Note 1) 016 Page 45, Fig. 33, title Fig. 33 Area C S0/C S1/C S2 (mode 1) and area CS3 Fig. 33 Area C S0/C S1/C S2 (mode 0) and area CS3 Page 46, Left column, Line 2 Tabl e 8 sho ws t he interr u pt types and t h e •••••••• Table 8 shows the interrupt sources and the •••••••• Page 46, Table 8, title Tabl e 8. Inter rupt t ypes and the interr upt vector add r esses Tabl e 8. Inter rupt sour ces and interr up t vector add r esses Page 52, Left column, Line 5 To use these pins as timer input pins, the data direction To use these pins as timer input pins, the port direction Page 55, Fig. 46, bit 4 0 : Increment o r decr ement accor ding t o up/down flag 1 :

• •• 0 : Increment o r decr ement accor ding t o up/down bi t 1 :
• •• Page 62, (2) E vent cou nt er m od e [01] part i cular function sel ect register 1 (bit 7 at address 6316) ••
• •• part i cular function sel ect register 1 (bit 6 at address 6316) ••
• •• Page 64, Fig. 64 1/16 d ivi d e r 1/2 di vi d e r C l ock synch ronous C l ock synch ronous (External cl ock) Cl ock synchronous (Exte rnal cl ock) Transmit control circui t UAR T 1/16 divider 1/2 divider C lock synchronous C lock synchronous (Internal clock) Cl ock synchronous (Exte rnal cl ock) Transmit control circui t UART Page 59, Left column, Lines 14, 17, (Li ne 15) (Li ne 15)

Corrections and Supplement ar y Explanation for M37902FxC Dat asheet (REV. B) NO.7 Page Erro r Correction (7/11) Page 64, Fig. 65, bits to 0, bi t 5, bit 6 Serial I/O mode select bits 0 0 0 : Serial I/O mode is invalid. ••••••••• 21056 Even/O dd pari t y select bit ••• •• •• 0 : Parity enable sele ct bit • •• •• •• 0 : Serial I/O mode select bits 21056 O dd/Even parity select bit ••••••• Page 66, Fig. 68, UA RT0/1 tr an sm it/r e ceive co nt rol register bit 6 C LK polar ity sel ect bit • •• •• 0 : At the f al ling •• , receive data i s i nput. CPL C LK polarity select bit ••••• 0 : At the falling ••••, receive data is input. When not in transfer, pin CLK’s level is “H”. CPL Page 68, Left column, Last l ine read out the RTSk output turns back to “L”. •••••••read out the RTSk output turns back to “L”. ••••••• Page 70, Fig. 71 I C LK porarity se lect bi t = 1 I C LK porarity select bit = 0

• •••
• ••• I C LK porarity se lect bi t = 0 I C LK porarity select bit = 1
• •••
• ••• Page 74, Table 13 Pin P80/C TS0/RTS0 (Note 1) Functions C TS2 Pin P81/••• P81 or C LK0 Pin P80/C TS0/RTS0 (Note 1) Functions C TS0 Pin P81/••• P81 or C LK0 Page 77, Left column, Line 12 AD T Page 77, L e f t column, Line 14 AD T RG pin i s multipl exed with an a nalog voltage •••••• AD T RG pin i s multipl exed with an a nalog voltage •••••• Page 76, Fig. 77 Ladder n et w or k Resistor ladder network Page 77, R i g h t column, Lines 5 to 6 Page 77, R i g h t column, Line 10 the ladder net w or k can be cut off by disconnecting ladd er network • the r esi st or ladder net w or k can be cut o f f by disconnect- ing resistor la dder network •••
• ••• Page 80, L e f t column, Line 10

Corrections and Supplement ar y Explanation for M37902FxC Dat asheet (REV. B) NO.8 Page Erro r Correction (8/11) Page 81, Fig. 83, bits 1 and 0 Wave form out p ut select bits

• •• 11 : RTP1 and RTP0 sel ect e d Whe n pul se m ode i s sel ect ed: R TP 1 and RTP1
• •• Page 86, Fig. 91, bi t s 2 to 0 Address/Port switch select bits 210 0 1 Wave form out p ut select bits
• •• 11 : RTP1 and RTP0 sel ect e d Whe n pul se m ode i s sel ect ed: R TP 1 and RTP0
• •• Address/Port sw itch bi t s 0 0 0 :
• •• 210 Page 80, L e f t column, Line 15 The D-A output enable bit is cleared to “0” at reset .••••••• The contents of the corr espond ing D-A output enab le bit and D-A register are cleared t o “0” at r Page 80, R i g h t column, Line 1 wi t h pin D-Ai .w i t h pin D-Ai . Al so, wh en n ot using the D-A convert e r , be sur e to clear the content s of t he corresponding D-A output enable bit and D-A register to “ 0”. [I n side dott ed-li ne n ot incl uded] P40/ A LE, P41/φ1, P42/HLDA
• ••• Page 87, Fig. 89, 2nd diagram [I n side dott ed-li ne n ot incl uded] P40/ A LE, P41/φ1, P42/HLDA
• ••• Port l at ch O utput Port latch O ut put (Int ern al peripher al devices) Page 88, Fig. 90, 3rd di agram [Inside dotted-line not included] P77/AN7/ADTRG /DA1/(INT2) [Inside dotted-line included] 7/AN7/ADTRG /DA1/(INT2) Page 82, Right column, Lines 1 to 3 # When the waveform output select bits are set to “11” (bit 1 = bit 0 = “1”), RTP13 to RTP10 and RTP03 to RTP00 become pulse output port pins. When the waveform output select bits are set to “11” (bit 1 = bit 0 = “1”), pulse output port pins are divided into two groups; one consists of RTP1 3 to RTP10, RTP03, RTP02 and the other consists of RTP01 and RTP00. Page 90, Fig. 92, address 7016 0 00?A-D interrup t control register (7016) •• •• 000?A-D conversion interr u pt cont rol register 016)
• •• Page 89, Fig. 93, address 8116 0000CS 0 control regi st er H (8116) •• •• 0 0000CS 0 control regi st er H (8116) •• •• 1 Page 91, Left column, Line 17
• •••••• from pin XIN and output a m ultip lied clock. # ••••••• from pin XIN and generates a m ultiplied clock. Page 91, Left column, Lines 11, 12
• •••••• , the oscillatio n ci r cui t stops it’s o p e r a t i o n a n d r e s u - m e s t h e c u r r e n t d i s s i p a t i o n
• •••••• , the oscillatio n ci r cui t stops it’s o p e r a t i o n , a n d t h e c u r r e n t d i s s i p a t i o n i s r e d u c e d Page 92, Right column, Lines 4 to 5
• •••••• In t h is selection, be su r e that multipl ied f (XI N ) does not exceed 26 M
• •••
• •••••• T he P LL m ul t i plication ratio m ust be set so that the fr equ ency o f the PLL output cl ock ( fPLL) must be in the range f rom MHz to MHz. •• Page 92, Right column, Lines 10 to 11
• •••• the PLL output clock ( fPL L) . ( In other words, set bit 5 to “ 1”.)
• •••• the PLL output clock ( fPL L) . ( In other words, set bit 5 to “ 1”.) Note t h at , aft er r ese t , t h e P LL m ul t i plication ratio select bits ar e al lowed to be ch anged only once.

Corrections and Supplement ar y Explanation for M37902FxC Dat asheet (REV. B) NO.9 Page Erro r Correction (9/11) Page 92, Table 15, Note No t e: Be sur e that syst em clock fsys doe s not exceed 26 MHz. f (XI N ) m ean s the fr eque ncy of the input clock fr om pin XI N (f XIN) No t e: The PLL multipli cat i on r atio must be set so that the frequency of the PLL output clock ( fPLL) must be i n the range f rom

10 MHz to

MHz. f (XI N ) m eans the frequency of the input clock fr om pin XI N (f XIN) . After reset, the PLL multipli cation r atio sel ect bits are al lowed to be changed only once. Page 98, Right column, Line 8 Page 98, Right column, Line 10 the ladder net w or k of t he A - D converter wi ll ••••• the resistor ladder network of the A-D converter will ••••• pin VREF to the ladder network, and the power dissipation pin VREF to the resistor ladder network, and the power Page 96, Left column, Line 7

• •••• the oscil lation circuit a nd P LL circuit ha ve be en rest arted •••
• ••
• •••• the oscil lation circuit h as be en restar ted ••••••# M37902F8 C G P , M37902F 8C HP : block configuration of internal flash m emory (Deleted)# Fi g. 106. M 3 7902FJCG P , M37902FJC HP : b lock confi- guration of i nt ernal flash mem ory Fig. 106. M37902FJC HP : block configuration of inter- nal flash memory Page 101, Fig. 106 Fi g. 108. M 3 7902FCC G P , M37902F CC HP : block con- figuration of i nt ernal flash mem ory Fig. 107. M37902FCC HP : block configuration of inter- nal flash memory Page 102, Fig. 107 M37902FE CG P, M 37902 FE C HP : b lock conf i gurat i on of inter nal fla sh memor y (Deleted) Fig. 110. M37902FGCG P, M37902FGC HP : block con- figuration of internal flash memory Fig. 108. M37902FGC HP : block configuration of inter - nal flash memory Page 102, Fig. 108 M37902FH CG P, M37902F H C H P : bl ock config ur ation of inter nal fla sh memor y (Deleted)# Page 103, Right column, Lines 15 to 17 area if the user use s the flash m emory se r ial I/O mode. Note that, when the boot ROM area i s area if the user uses the flash memory serial I/O mode. Addresses FFB016 to FFBF16 are the reserved area for the serial programmer. Therefore, when the user uses the flash memory serial I/O mode, do not program to this area. Note that, when the boot ROM area is read ••••••••• Page 106, Right column, After line 13 progr am the u ser ROM area. program the user ROM area. After reset removal, be sure not to change the status at pins MD0 and MD1. # Pi n co nnection of M37902F xCG P in f l ash m emory serial I/ O mode (Deleted) Page 106, Fig. 114, Notes 4 # 4: V alid onl y ••••• clear to “0” . 4: Valid only ••••• clear to “0”. This bit 3 must be controll- ed with bit 1 = “1”. Page 107, Left column, Lines 16 to 20 # ••••• command consists o f 8-bit u nits must be w r i t ten only to an e ven ad dr ess; ther efore, any data writt e n to an odd address will b e i nvalid. The write stat e
• •••• command consisting of 8 bi t s must be written t o an even address; therefor e, any com mand written to an odd address will b e i nvalid. Sin ce the write data at the 2nd cycle of a p r ogramm ing command consists of 16 bits, this data m ust be writt en to even and odd addr e sses. The write stat e Page 107, Right column, After line 24 # request occu r rence. request occu r rence. In the C PU reprogr amming m od e, be sure no t to use the ST P and WIT instr uction

Corrections and Supplement ar y Explanation for M37902FxC Dat asheet (REV. B) NO.10 Page Erro r Correction (10/11) Page 108, Fig. 115 The C PU reprogramming mode select bit is set to “1”. (Writing of “0” → Writing of “1”) Writing of “1” to the C PU reprogramming mode select bit. (Writing of “0” → Writing of “1”) Page 108, Software C ommands 5) is ignored. (Li nes 6, 7) 5) is ignored. ( E xcept for the write data at the 2nd cycle of a page progr a m ming comm and.) (Li nes 6, 7) Page 109, Page programming Command (After line 20)

• •••••• , the sam e way as bit 7 of the st a t us register . Readi ng out (Li nes 4 to 7)
• •••••• , the sam e wayas bi t 7 of the status register. Before execution of the next com mand, be su r e to ver ify that bi t 7 of t he status r egi st er ( S R.7) or the RY /BY status bi t is set t o “1” (RE ADY . During t h e au t omatic progr amming operat i on, w r itin g of comm ands and access to the flash mem ory m ust not be perfor med. Readi ng out Page 109, Block Erase Command # (Li nes 20 to 2 3)
• ••••••, the same way as bit 7 of the status register. (Li nes 20 to 2 3)
• ••••••, the same way as bit 7 of the status register. Before execution of the next command, be sure to verify that bit 7 of the status register (SR.7) or the RY/BY status bit is set to “1” (READY). During the automatic erase operation, writing of commands and access to the flash memory must not be performed. Page 111, Erase All Unlocked Block Command # (Li nes 9 to 11 )
• •••••• is al so report e d by a read of the st a t us register. When the lock bit (Li nes 9 to 11 )
• •••••• is al so report e d by a read of the st a t us register. During the autom atic erase oper a t i on (when the RY B Y status bi t = “ 0” ) , writing of commands and access to the flash m e m ory m ust not be perfor med. When the lock bit Page 108, P age progr amming Co m mand (Li nes 4 to 7) (After line 20)
• •••••• mode is m ai nt a ined. I n continuou s program ming, if t h er e is no progr amming er ror, page program ming comm ands can be executed with the r ead status regi st er mode kept (Titll e) Pag e P r og r am C om mand (4116) (Titll e) Pag e P r og r amm i ng C om mand (4116) Page 111, Data Protect Function (Block Lock) # (Aft er li ne 20) lock bit is terminated. (Aft er li ne 20) lock bit is terminated. To perform erase or programming, be sure to do one of the following.
• By executing the read lock bit status command, verify that the lock of the target block is invalid.
• Set the lock bit invalidity select bit to “1” to invalidate the lock. When the block erase or programming is performed with the lock valid, the erase status bit (SR.5) and program- ming status bit (SR.4) are set to “1” (terminated by error). Page 114, AB SOLUT E MAX IM UM RA TINGS 300 Rating sSymbol Pd Power di sspat i on Parameter Uni t mW 400 Rating sSymbol Pd Power di sspat i on Parameter Uni t mW Topr O perating t em perature Topr O perating ambien t temperature

Corrections and Supplement ar y Explanation for M37902FxC Dat asheet (REV. B) NO.11 Page Erro r Correction (11/11) tw(harf Page 123, T iming Requ ir e m ents Page 114, RECOMMENDED OPERATING CONDITIONS # f(sys) System clcok f requency ••••••• • f( fsys) System clcok f requency ••••••• • f(fsys) External clcok input frequency (Note 2) •••••••• f(XIN) External clcok input frequency (Note 2) •••••••• Page 131, PA CKE GE OUT LI N E # 100P 6S-A packege outline (Deleted)