M37735S4LHP

M37735S4LHP RENESAS | Alldatasheet

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Regarding the change of names mentioned in the document, such as Mitsubishi Electric and Mitsubishi XX, to Renesas Technology Corp. The semiconductor operations of Hitachi and Mitsubishi Electric were transferred to Renesas Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.) Accordingly, although Mitsubishi Electric, Mitsubishi Electric Corporation, Mitsubishi Semiconductors, and other Mitsubishi brand names are mentioned in the document, these names have in fact all been changed to Renesas Technology Corp. Thank you for your understanding. Except for our corporate trademark, logo and corporate statement, no changes whatsoever have been made to the contents of the document, and these changes do not constitute any alteration to the contents of the document itself. Note : Mitsubishi Electric will continue the business operations of high frequency & optical devices and power devices. Renesas Technology Corp. Customer Support Dept. April 1, 2003 To all our customers

DESCRIPTION

The M37735S4LHP is a microcomputer using the 7700 Family core. This microcomputer has a CPU and a bus interface unit. The CPU is a 16-bit parallel processor that can be an 8-bit parallel processor, and the bus interface unit enhances the memory access efficiency to execute instructions fast. This microcomputer also includes a 32 kHz oscillation circuit, in addition to the RAM, multiple-function timers, serial I/O, A-D converter, and so on. Its strong points are the low power dissipation, the low supply voltage, and the small package.

FEATURES

l Instruction execution time l Low power dissipation (At 3 V supply voltage, 12 MHz frequency) l 12-bit watchdog timer l Programmable input/output (80P6D-A; 0.5 mm lead pitch) APPLICATION Control devices for general commercial equipment such as office automation, office equipment, and so on. Control devices for general industrial equipment such as communication equipment, and so on. New product PIN CONFIGURATION (TOP VIEW) P3 0/WEL P3 2/ALE P3 1 /WE H P3 3/HLDA XOUT RDE CNV SS R ESET HO LD 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 P8 6/RxD 1 P8 7/TxD 1 P0 0/CS 0 P01/CS 1 P0 2/CS 2 P0 3/CS 3 P0 4/CS 4 P0 5/RS MP P0 6/A P0 7/A 0/A 8/D 1/A 9/D 2/A 3/A 4/A 5/A 6/A 7/A 0/A 0/D 1/A 1/D 60 59 58 RDY P2 7/A7/D7 P4 2/ 1 BYT E XIN VSS P2 6/A6/D6 P2 5/A5/D5 P2 4/A4/D4 P2 3/A3/D3 P2 2/A2/D2 P6 6/T B1IN 5/T IN 4/IN 3/IN 2/IN P6 1/TA4 IN P6 0/TA4 OU T 7/T A3IN I3/R TP13 P5 6/TA3 OU T/K I2/RTP P5 5/TA2IN/KI1/RTP1 P5 4/TA2OUT /KI0/RTP1 P5 3/TA1IN/RTP0 P5 2/TA1OUT /RTP0 P5 1/TA0 IN/RTP0 P5 0 /TA0OUT /RTP0 Outline 80P6D-A P8 5/CLK 1 P8 4/CTS1/RTS1 P8 3/TXD 0 P8 2/RXD 0 /CLKS 0 P81 /CLK 0 P8 0/CTS0/RTS0/CLKS1 VCC AV CC VRE F AV SS VSS P7 6/AN 6 /XCO UT P75/AN 5/AD TRG /TXD 2 P74 /AN 4/RXD 2 P73/AN 3/CLK 2 P72/AN 2/CTS 2 P71/AN 1 P70/AN 0 P6 7/TB 2IN/ SU B M37735S4LHP P7 7/AN 7/XCIN 1 2 3 4 5

16-BIT CMOS MICROCOMPUTERNew productM37735S4LHP BLOCK DIAGRAM XIN XOUT RESET Reset input VREF P8(8) P7(8) P5(8) P6(8) P4(5) Address (18)/Data (16) CNVss BYTE UART1(9) UART0(9) AVSS (0V) AVCC (0V) VSS VCC A-D Converter(10) XCIN XCOUT XCIN XCOUT Clock input Clock output Reference voltage input External data bus width selection input Clock Generating Circuit Instruction Register(8) Arithmetic Logic Unit(16) Accumulator A(16) Accumulator B(16) Index Register X(16) Index Register Y(16) Stack Pointer S(16) Direct Page Register DPR(16) Input Butter Register IB(16) Data Bank Register DT(8) Program Bank Register PG(8) Incrementer/Decrementer(24) Data Address Register DA(24) Incrementer(24) Instruction Queue Buffer Q2(8) Instruction Queue Buffer Q1(8) Instruction Queue Buffer Q0(8) Data Buffer DBL(8) Data Buffer DBH (8) RAM 2048 bytes Timer TA3(16) Timer TA4(16) Timer TA2(16) Timer TA1(16) Timer TA0(16) Watchdog Timer Timer TB2(16) Timer TB1(16) Timer TB0(16) Address Bus Data Bus(Odd) Data Bus(Even) Input/Output port P8 Input/Output port P7 Input/Output port P6 Input/Output port P5 Input/Output port P4 Address bus/Data bus UART2(9 ) WELWEHALE HLDA HOLD RDY1 RDE RSMPCS 0 CS 1 CS 2 CS 3 CS 4 Processor Status Register PS(11) Program Counter PC(16) Program Address Register PA(24)

16-BIT CMOS MICROCOMPUTERNew product FUNCTIONS OF M37735S4LHP Input/Output ports Multi-function timers Interrupts Clock generating circuit Power dissipation Input/Output characteristic Parameter Functions Number of basic instructions 103 Instruction execution time 333 ns (the fastest instruction at external clock 12 MHz frequency) Memory size RAM 2048 bytes P5 – P8 8-bit 5 4 P4 5-bit 5 1 TA0, TA1, TA2, TA3, TA4 16-bit 5 5 TB0, TB1, TB2 16-bit 5 3 Serial I/O (UART or clock synchronous serial I/O) 5 3 A-D converter 10-bit 5 1 (8 channels) Watchdog timer 12-bit 5 1 3 external types, 16 internal types Each interrupt can be set to the priority level (0 – 7.) 2 circuits built-in (externally connected to a ceramic resonator or a quartz-crystal oscillator) Supply voltage 2.7 – 5.5 V 10.8 mW (at 3 V supply voltage, external clock 12 MHz frequency) 27 mW (at 5 V supply voltage, external clock 12 MHz frequency) Input/Output voltage 5 V Output current 5 mA Memory expansion Maximum 1 Mbytes Operating temperature range –40 to 85 °C Device structure CMOS high-performance silicon gate process Package 80-pin plastic molded fine-pitch QFP (80P6D-A; 0.5 mm lead pitch)

16-BIT CMOS MICROCOMPUTERNew product PIN DESCRIPTION Pin Name Input/Output Functions Vcc, Power source Apply 2.7 – 5.5 V to Vcc and 0 V to Vss. Vss CNVss CNVss input Input Connect to Vcc._____ RESET Reset input Input When “L” level is applied to this pin, the microcomputer enters the reset state. These are pins of main-clock generating circuit. Connect a ceramic resonator or a quartz-crystal oscillator between XIN and XOUT . When an external clock is used, the clock source should be connected to the XIN pin, and the XOUT pin should be left open.___ RDE Read enable output Output ___ When data/instruction read is performed, output level of RDE signal is “L”. BYTE Bus width Input This pin determines whether the external data bus has an 8-bit width or a 16-bit width. selection input The data bus has a 16-bit width when “L” signal is input and an 8-bit width when “H” signal is input. AVcc, Analog power Power source input pin for the A-D converter. Externally connect AVcc to Vcc and AVss to Vss. AVss source input VREF Reference Input This is reference voltage input pin for the A-D converter. voltage input___ P00/CS 0 – Chip selection Output When the specified external memory area is accessed, CS 0 – CS 4 signals are “L”.___ P04/CS 4 output____ P05/RSMP Ready sampling Output ___ The timing signal to be input to the RDY pin is output. output P06/A16, Address output Output An address (A 16, A17) is output. P07/A17 P10/A8/D8 – Address output I/O When the BYTE pin is set to “L” and external data bus has a 16-bit width, high-order data P17/A15/D15 /data (high (D8 – D15) is input/output or an address (A8 – A15) is output. When the BYTE pin is “H” and an -order) I/O external data bus has an 8-bit width, only address (A8 – A15) is output. P20/A0/D0 – Address output I/O Low-order data (D 0 – D7) is input/output or an address (A0 – A7) is output. P27/A7/D7 /data (low -order) I/O___ P30/WEL Write enable Output ___ When the BYTE pin is “L” and writing to an even address is performed, output level of WEL signal output is “L”. When the BYTE pin is “H” and writing to an even address or an odd address is performed,___ output level of WEL signal is “L”.___ P31/WEH Write enable Output ___ When the BYTE pin is “L” and writing to an odd address is performed, output level of WEH signal high output ___ is “L”. When the BYTE pin is “H”, WEH signal is always “H”. P32/ALE Address latch Output This is used to retrieve only the address from the multiplex signal which consists of address and enable output data.____ P33/HLDA Hold acknow- Output This outputs “L” level when the microcomputer enters hold state after a hold request is accepted. ledge output____ HOLD Hold request Input ____ This is an input pin for HOLD request signal. The microcomputer enters hold state while this RDY Ready input Input ___ This is an input pin for RDY signal. The microcomputer enters ready state while this signal is “L”. P42/ 1 Clock output Output This pin outputs the clock 1. P43 – P47 I/O port P4 I/O These pins become a 5-bit I/O port. An I/O direction register is available so that each pin can be programmed for input or output. These ports are in the input mode when reset. P50 – P57 I/O port P5 I/O In addition to having the same functions as port P4, these pins also function as I/O pins for timers__ __ A0 to A3 and input pins for key input interrupt input (KI0 – KI3). P60 – P67 I/O port P6 I/O In addition to having the same functions as port P4, these pins also function as I/O pins for timer___ ___ A4, input pins for external interrupt input (INT0 – INT2) and input pins for timers B0 to B2. P67 also functions as sub-clock SUB output pin. P70 – P77 I/O port P7 I/O In addition to having the same functions as port P4, these pins function as input pins for A-D converter. P72 to P75 also function as I/O pins for UART2. Additionally, P76 and P77 have the function as the output pin (XCOUT ) and the input pin (XCIN) of the sub-clock (32 kHz) oscillation circuit, respectively. When P76 and P77 are used as the XCOUT and XCIN pins, connect a resonator or an oscillator between the both. P80 – P87 I/O port P8 I/O In addition to having the same functions as port P4, these pins also function as I/O pins for UART 0 and UART 1. XIN Clock input Input XOUT Clock output Output

16-BIT CMOS MICROCOMPUTERNew product BASIC FUNCTION BLOCKS The M37735S4LHP has the same functions as the M37735MHBXXXFP except for the following: (1) The memory map is different. (2) The processor mode is different. (3) The reset circuit is different. (4) Pulse output port mode of timer A is available. (5) The function of ROM area modification is not available. Refer to the section on the M37735MHBXXXFP, except for above (1)–(5). MEMORY The memory map is shown in Figure 1. The address space has a capacity of 16 Mbytes and is allocated to addresses from 0 16 to FFFFFF 16. The address space is divided by 64-Kbyte unit called bank. The banks are numbered from 016 to FF16. However, banks 10 16–FF 16 of the M37735S4LHP cannot be accessed. Built-in RAM and control registers for internal peripheral devices are assigned to bank 0 16. Addresses FFD616 to FFFF16 are the RESET and interrupt vector addresses and contain the interrupt vectors. Use ROM for memory of this address. The 2048-byte area allocated to addresses from 80 16 to 87F16 is the built-in RAM. In addition to storing data, the RAM is used as stack during a subroutine call or interrupts. Peripheral devices such as I/O ports, A-D converter, serial I/O, timer, and interrupt control registers are allocated to addresses from 0 16 to 7F16. A 256-byte direct page area can be allocated anywhere in bank 016 by using the direct page register (DPR). In the direct page addressing mode, the memory in the direct page area can be accessed with two words. Hence program steps can be reduced. Fig. 1 Memory map A-D/UART2 trans./rece. Timer B2 Timer B1 Timer B0 Timer A4 Timer A3 Timer A2 Timer A1 Timer A0 INT2/Key input INT0 Watchdog timer DBC BRK instruction Zero divide RESET Internal peripheral devices control registers refer to Fig. 2 for detail information Interrupt vector table 00000016 00FFFF 16 01000016 01FFFF 16 Bank 016 Bank 116 FE0000 16 FEFFFF 16 FF000016 FFFFFF 16 Bank FF16 Bank FE16 00FFFF 16 00FFD6 16 00087F16 00000016 00007F16 00008016 Internal RAM 2048 bytes 00FFFE 16 00FFD6 16 00007F16 00000016 UART1 transmission UART1 receive UART0 transmission UART0 receive INT1 : Internal : External Note. Banks 1016–FF16 cannot be accessed in the M37735S4LHP.

16-BIT CMOS MICROCOMPUTERNew product Fig. 2 Location of internal peripheral devices and interrupt control registers UART 0 transmission interrupt control register UART 1 transmission interrupt control register INT2/Key input interrupt control register Port P1 direction register UART 0 transmit/receive mode register UART 0 baud rate register (BRG0) UART 0 transmit/receive control register 0 UART 0 transmit/receive control register 1 UART 0 transmission buffer register UART 1 transmit/receive control register 0 UART 1 transmit/receive mode register UART 1 baud rate register (BRG1) UART 1 transmit/receive control register 1 UART 0 receive buffer register UART 1 transmission buffer register UART 1 receive buffer register Port P0 register A-D register 0 A-D register 2 Port P1 register Port P0 direction register Port P2 register Port P3 register Port P4 register Port P5 register Port P6 register Port P7 register Port P8 register A-D control register 0 A-D control register 1 A-D register 1 A-D register 3 A-D register 4 A-D register 5 000000 000001 000002 000003 000005 000006 000007 000008 000009 000010 000011 000012 000013 000014 000015 000016 000017 000018 000019 00001A 00001B 00001C 00001D 00001E 00001F 000020 000021 000022 000023 000024 000025 000026 000027 000028 000029 00002A 00002B 00002C 00002D 00002E 00002F 000030 000031 000032 000033 000034 000035 000036 000037 000038 000039 00003A 00003B 00003C 00003D 00003E 00003F 00000B 00000C 00000D 00000E 00000F 00000A 000004 000040 000041 000042 000043 000045 000046 000047 000048 000049 000050 000051 000052 000053 000054 000055 000056 000057 000058 000059 00005A 00005B 00005C 00005D 00005E 00005F 000060 000061 000062 000063 000064 000065 000066 000067 000068 000069 00006A 00006B 00006C 00006D 00006E 00006F 000070 000071 000072 000073 000074 000075 000076 000077 000078 000079 00007A 00007B 00007C 00007D 00007E 00007F 00004B 00004C 00004D 00004E 00004F 00004A 000044 Address (Hexadecimal notation) Address (Hexadecimal notation) Timer A1 register Timer A4 register Timer A2 register Timer A3 register Timer B0 register Timer B1 register Timer B2 register Count start flag One-shot start flag Up-down flag Timer A0 register Timer A0 mode register Timer A1 mode register Timer A2 mode register Timer A4 mode register Timer B0 mode register Timer B1 mode register Timer B2 mode register Processor mode register 0 Watchdog timer register Watchdog timer frequency selection flag A-D/UART2 trans./rece. interrupt control register UART 0 receive interrupt control register UART 1 receive interrupt control register Timer A0 interrupt control register Timer A1 interrupt control register Timer A2 interrupt control register Timer A3 interrupt control register Timer A4 interrupt control register Timer B0 interrupt control register Timer B1 interrupt control register Timer B2 interrupt control register INT0 interrupt control register INT1 interrupt control register Processor mode register 1 Oscillation circuit control register 1 Serial transmit control register Port function control register Oscillation circuit control register 0 Timer A3 mode register Port P2 direction register Port P3 direction register Port P4 direction register Port P5 direction register Port P6 direction register Port P7 direction register Port P8 direction register Pulse output data register 1 Pulse output data register 0 A-D register 6 A-D register 7 Waveform output mode register UART2 transmit/receive mode register UART2 baud rate register (BRG2) UART2 transmission buffer register UART2 transmit/receive control register 0 UART2 transmit/receive control register 1 UART2 receive buffer register Reserved area (Note) Note. Writing to reserved area is disabled.

16-BIT CMOS MICROCOMPUTERNew product RTP1 0, RTP11, RTP12, and RTP13 are applied pulse width modulation by timer A3 by setting the pulse width modulation selection bit by timer A3 (bit 5) of the waveform output mode register to “1”. RTP0 0, RTP01, RTP02, and RTP03 are applied pulse width modulation by timer A1 by setting the pulse width modulation selection bit by timer A1 (bit 4) of the waveform output mode register to “1”. The contents of the pulse output data register 0 can be reversed and output to pulse output ports RTP0 0, RTP01, RTP02, and RTP03 by the polarity selection bit (bit 3) of the waveform output mode register. When the polarity selection bit is “0”, the contents of the pulse output data register 0 is output unchangeably, and when “1”, the contents of the pulse output data register 0 is reversed and output. When pulse width modulation is applied, likewise the polarity reverse to pulse width modulation can be selected by the polarity selection bit. Fig. 4 Waveform output mode register bit configuration Fig. 5 Timer A0, A2 mode register bit configuration in pulse output port mode Fig. 6 Pulse output data register bit configuration Weveform output selection bit 0 0 : Parallel port 0 1 : RTP1 selected 1 0 : RTP0 selected 1 1 : RTP1 and RTP0 selected Pulse width modulation selection bit by timer A3 0 : Not modulated 1 : Modulated Always “0” 765432 0 1 Weveform output mode register 6216 Address Polarity selection bit 0 : Positive polarity 1 : Negative polarity Pulse width modulation selection bit by timer A1 0 : Not modulated 1 : Modulated Always “100” in pulse output port mode Clock source selection bit 0 0 : Select f 0 1 : Select f16 1 0 : Select f64 1 1 : Select f512 765432 0 1 Timer A0 mode register 5616 Timer A2 mode register 5816 Address Not used in pulse output port mode Always “00” in pulse output port mode 0 0 X 1 0 0 RTP0 0 output data 765432 0 1 Address RTP0 1 output data RTP0 2 output data RTP0 3 output data Pulse output data register 0 1D16 RTP1 0 output data 765432 0 1 Pulse output data register 1 1C16 Address RTP1 1 output data RTP1 2 output data RTP1 3 output data

16-BIT CMOS MICROCOMPUTERNew product Fig. 7 Example of waveforms in pulse output port mode Output signal at each time when timer A2 becomes 000016 Example of pulse output port (RTP10 – RTP13) RTP1 3 (P57) RTP1 1 (P55) RTP1 0 (P54) RTP1 2 (P56) Output signal at each time when timer A2 becomes 0000 Example of pulse output port (RTP10 – RTP13) when pulse width modulation is applied by timer A3. RTP1 3 (P57) RTP1 1 (P55) RTP1 0 (P54) RTP1 2 (P56) Output signal at each time when timer A0 becomes 0000 Example of pulse output port (RTP00 – RTP03) when pulse width modulation is applied by timer A1 with polarity selection bit = “1”. RTP0 3 (P53) RTP0 1 (P51) RTP0 0 (P50) RTP0 2 (P52)

16-BIT CMOS MICROCOMPUTERNew product PROCESSOR MODE Only the microprocessor mode can be selected. ___ Figure 9 shows the functions of pins P00/CS 0 — P4 7 in the microprocessor mode. Figure 10 shows external memory area for the microprocessor mode. Access to the external memory is affected by the BYTE pin, the wait bit (bit 2 of the processor mode register 0 at address 5E 16), and the wait selection bit (bit 0 of the processor mode register 1 at address 16) .

• BYTE pin When accessing the external memory, the level of the BYTE pin is used to determine whether to use the data bus as 8-bit width or 16- bit width. The data bus has a width of 8 bits when level of the BYTE pin is “H”, and pins P2 0/A0/D0 — P27/A7/D7 are the data I/O pins. The data bus has a width of 16 bits when the level of the BYTE pin is “L”, and pins P2 0/A0/D0 — P27/A7/D7 and pins P10/A8/D8 — P17/A15/ D15 are the data I/O pins. When accessing the internal memory, the data bus always has a width of 16 bits regardless of the BYTE pin level. Not used Must be “10” (“10” after reset) Wait bit 0 : Wait 1 : No wait Software reset bit Reset occurs when this bit is set to “1” Interrupt priority detection time selection bit 0 0 : Internal clock 5 7 (cycle) 0 1 : Internal clock 5 4 (cycle) 1 0 : Internal clock 5 2 (cycle) Must be “0” 765432 0 1

0 Processor mode register 0

16Processor mode register 1 Wait selection bit 0 : Wait 0 1 : Wait 1 765432 0 1 Fig. 8 Processor mode register bit configuration

16-BIT CMOS MICROCOMPUTERNew product ___ Fig. 9 Functions of pins P00/CS 0 to P47 in microprocessor mode Note.The signal output disable selection bit (bit 6 of the oscillation circuit control register 0) can stop the 1 output in the microprocessor mode. In this mode, signals RDE , WEL , WEH can also be fixed to “H” when the internal memory area is accessed. P30/WEL P31/WEH P32/ALE P33/HLDA (Note) ALE WEH WEL HLDA (Note) P30/WEL, P31/WEH , P32/ALE, P33/HLDA HOLD RDY P42/ 1 P00/CS 0 to P04/CS 4 Address Data(odd) Address A8 – A15 Address Data(even) Address Data (odd,even) I/O Port PM 1 PM 0 Mode Microprocessor mode (Note) Pin RDE CS 0 to CS 4 RSMP , A16, A17 P10/A8/D8 to P17/A15/D15 BYTE = “L” BYTE = “H” BYTE = “L” BYTE = “H” HOLD , RDY , P42/ 1, Ports P43 to P47 RDE P10/A8/D8 to P17/A15 /D15 RSMP CS 0 — CS 4 RDY HOLD P05/RSMP P20/A0/D0 to P27/A7/D7 A8 to A15 P10/A8/D8 to P17/A15/D15 P20/A0/D0 to P27/A7/D7 A0 to A7 P20/A0/D0 to P27/A7/D7 A0 to A7 RDE, WEL, WEH RDE, WEL, WEH RDE, WEL, WEH RDE, WEL, WEH RDE, WEL, WEH RDE, WEL, WEH (Note) Address A16, A17 P06/A16 P07/A17 P43 to P47

16-BIT CMOS MICROCOMPUTERNew product Fig. 11 Relationship between wait bit, wait selection bit, and access time

• Wait bit As shown in Figure 11, when the external memory area is accessed with the wait bit (bit 2 of the processor mode register 0 at address 16) cleared to “0”, the access time can be extended compared with no wait (the wait bit is “1”). The access time is extended in two ways and this is selected with the wait selection bit (bit 0 of the processor mode register 1 at address 16). When this bit is “1”, the access time is 1.5 times compared to that for no wait. When this bit is “0”, the access time is twice compared to that for no wait. At reset, the wait bit and the wait selection bit are “0”. Access to internal memory area is always performed in the no wait mode regardless of the wait bit. The processor modes are described below. Fig. 10 External memory area for microprocessor mode (1) Microprocessor mode [10] The microcomputer enters the microprocessor mode after connecting the CNVss pin to Vcc and starting from reset. Pin RDE is the output pin for the read enable signal (RDE). ___ RDE is “L” during the data read term in the read cycle. When the ___ internal memory area is read, RDE can be fixed to “H” by setting the signal output disable selection bit (bit 6 of the oscillation circuit control register 0) to “1”. SFR RAM Microprocessor mode The shaded area is the external memory area. Note that banks 1016 to FF16 cannot be accessed. 0016 8016 87F16 FFFFFF 16 Internal clock Ai/Di RDE or WEL , WEH ALE Wait bit “1” (No wait) Ai/Di RDE or WEL , WEH ALE Wait bit “0” (Wait 1) Access time Access time Address Data Address Data Address Data Address Data Ai/Di RDE or WEL , WEH ALE Wait bit “0” (Wait 0) Access time Address Data Address

16-BIT CMOS MICROCOMPUTERNew product CS 0 to CS 4 are the chip select signals and are “L” when the address ____ shown in Table 2 is accessed. RSMP is the ready-sampling signal ___ which is output for the RDY input described later when the external ____ memory area is accessed. By inputting logical AND of RSMP and CS n (n = 0 to 4) to the RDY pin, read/write term for any address areas can be extended by 1 cycle of clock 1. In addition, the read/write term can also be extended by 2 cycles of clock 1 if the above function and wait 0/1 function specified with the wait bit are used together. Pins P1 0/A8/D8 — P17/A15/D15 have two functions depending on the level of the BYTE pin. When the BYTE pin level is “L”, pins P1 0/A8/D8 — P17/A15/D15 function as address (A8 to A15) output pins while RDE or WEL , WEH are “H” and as odd address data I/O pins while these signals are “L”. However, ___ if an internal memory is read, external data is ignored while RDE is “L”. When the BYTE pin level is “H”, pins P1 0/A8/D8 — P17/A15/D15 function as address (A8 to A15) output pins. Pins P20/A0/D0 — P27/A7/D7 have two functions depending on the level of the BYTE pin. When the BYTE pin level is “L”, pins P2 0/A0/D0 — P27/A7/D7 function as address (A0 to A7) output pins while RDE or WEL , WEH are “H” and as even address data I/O pins while these signals are “L”. However, ___ if an internal memory is read, external data is ignored while RDE is “L”. When the BYTE pin level is “H”, pins P2 0/A0/D0 — P27/A7/D7 function as address (A0 to A7) output pins while RDE or WEL , WEH are “H” and as even and odd address data I/O pins while these signals are “L”. However, if an internal memory is read, external data is ignored while ___ RDE is “L”. WEL , WEH are the write-enable low signal and the write-enable high signal, respectively. These signals are “L” during the data write term of the write cycle, but their operations differ depending on the BYTE pin level. ___ In the case the BYTE pin level is “L”, WEL is “L” when writing to ___ an even address, WEH is “L” when writing to an odd address, and both WEL and WEH are “L” when writing to even and odd addresses. In the case the BYTE pin level is “H”, regardless of address, only WEL is “L”, and WEH retains “H”. WEL and WEH can also be fixed to ___ “H” when the internal memory is accessed, same as RDE , by writing “1” to the signal output disable selection bit. ALE is an address latch enable signal used to latch the address signal from a multiplexed signal of address and data. The latch is transparent while ALE is “H” to let the address signal pass through and held while ALE is “L”. ____ HLDA is a hold acknowledge signal and is used to notify externally ____ when the microcomputer receives HOLD input and enters into hold state. ____ HOLD is a hold request signal. It is an input signal used to put the ____ microcomputer in hold state. HOLD input is accepted when the internal clock falls from “H” level to “L” level while the bus is not used. Pins P00/CS 0 — P31/WEH and RDE are floating while the microcomputer ____ stays in hold state. After HLDA signal changes to “L” level and one cycle of internal clock passed, these ports become floating. After ____ HLDA signal changes to “H” level and one cycle of internal clock passed, these ports are released from floating state. ___ RDY is a ready signal. If this signal goes “L”, the internal clock ___ stops at “L”. RDY is used when slow external memory is attached. P42/ 1 pin is an output pin for clock 1. The 1 output is ___ independent of RDY and does not stop even when internal clock ___ stops because of “L” input to the RDY pin.

Table 1. Relationship between CNVss pin input levels and processor

• MicroprocessorVcc 00 088016 to 00 7FFF16 00 800016 to

03 FFFF16

07 FFFF16

Table 2. Relationship between access addresses and chip-select signals CS 0 to CS 4 Table 3. Function of signal output disable selection bit CM6 (bit 6 of oscillation circuit control register 0) register, refer to Figures 64 and 11 in data sheet “M37735MHBXXXFP”, respectively. internal/external memory area is accessed. external memory area is accessed. function control register) must be set to “1”.

16-BIT CMOS MICROCOMPUTERNew product ADDRESSING MODES The M37735S4LHP has 28 powerful addressing modes.Refer to the MITSUBISHI SEMICONDUCTORS DATA BOOK SINGLE-CHIP 16- BIT MICROCOMPUTERS for the details of each addressing mode. MACHINE INSTRUCTION LIST The M37735S4LHP has 103 machine instructions. Refer to the MITSUBISHI SEMICONDUCTORS DATA BOOK SINGLE-CHIP 16- BIT MICROCOMPUTERS for details. Fig. 13 Example of a reset circuit VCCRESET RESET VCC 0 V 0 V 2.7 V 0.55 V Power on Note. In this case, stabilized clock is input from the external to the main-clock oscillation circuit. Perform careful evaluation at the system design level before using.

16-BIT CMOS MICROCOMPUTERNew product Symbol Parameter Conditions Ratings Unit Vcc Power source voltage –0.3 to +7 V AVcc Analog power source voltage –0.3 to +7 V VI Input voltage RESET , CNVss, BYTE –0.3 to +12 V Input voltageP10/A8/D8 – P17/A15/D15, P20/A0/D0 – P27/A7/D7, P80 – P87, VREF , XIN, HOLD , RDY Output voltage ___ P00/CS 0 – P07/A17, P10/A8/D8 – P17/A15/D15, P20/A0/D0 – P27/A7/D7, P30/WEL – P33/HLDA ,P42/ 1, P43 – P47, P50 – P57, P60 – P67, P70 – P77, P80 – P87,___ XOUT , RDE Pd Power dissipation Ta = 25 °C 200 mW Topr Operating temperature –40 to +85 °C Tstg Storage temperature –65 to +150 °C ABSOLUTE MAXIMUM RATINGS VI VO –0.3 to Vcc + 0.3 V –0.3 to Vcc + 0.3 V Limits Min. Typ. Max. f(XIN) : Operating 2.7 5.5 f(XIN) : Stopped, f(XCIN) = 32.768 kHz 2.7 5.5 AVcc Analog power source voltage Vcc V Vss Power source voltage 0V AVss Analog power source voltage 0 V High-level input voltage HOLD , RDY , P43 – P47, P50 – P57, P60 – P67, P70 – P77,_____ P80 – P87, XIN, RESET , CNVss, BYTE, XCIN (Note 3) High-level input voltage P10/A8/D8 – P17/A15/D15, P20/A0/D0 – P27/A7/D7____ ___ Low-level input voltage HOLD , RDY , P43 – P47, P50 – P57, P60 – P67, P70 – P77,_____ P80 – P87, XIN, RESET , CNVss, BYTE, XCIN (Note 3) Low-level input voltage P10/A8/D8 – P17/A15/D15, P20/A0/D0 – P27/A7/D7___ High-level peak output current P00/CS 0 – P07/A17, P10/A8/D8 – P17/A15/D15,___ ____ P20/A0/D0 – P27/A7/D7, P30/WEL – P33/HLDA , P42/ 1, P43 – P47, P50 – P57, P60 – P67, High-level average output current P00/CS 0 – P07/A17, P10/A8/D8 – P17/A15/D15,___ ____ P20/A0/D0 – P27/A7/D7, P30/WEL – P33/HLDA , P42/ 1, P43 – P47, P50 – P57, P60 – P67, Low-level peak output current P00/CS 0 – P07/A17, P10/A8/D8 – P17/A15/D15,___ ____ P20/A0/D0 – P27/A7/D7, P30/WEL – P33/HLDA , P42/ 1, P43, P54 – P57, P60 – P67, P70 – P77, P80 – P87 Low-level peak output current P44 – P47, P50 – P53___ Low-level average output current P00/CS 0 – P07/A17, P10/A8/D8 – P17/A15/D15,___ ____ P20/A0/D0 – P27/A7/D7, P30/WEL – P33/HLDA , P42/ 1, P43, P54 – P57,P60 – P67, P70 – P77, P80 – P87 IOL(avg) Low-level average output current P44 – P47, P50 – P53 12 mA f(XIN) Main-clock oscillation frequency (Note 4) 12 MHz f(XCIN) Sub-clock oscillation frequency 32.768 50 kHz Unit RECOMMENDED OPERATING CONDITIONS (Vcc = 2.7 – 5.5 V, Ta = –40 to +85 °C, unless otherwise noted) Notes 1. Average output current is the average value of a 100 ms interval. 2. The sum of IOL(peak) for ports P00/CS 0 – P07/A17, P10/A8/D8 – P17/A15/D15, P20/A0/D0 – P27/A7/D7, P30/WEL – P33/HLDA and P8 must be 80 mA or less, the sum of IOH(peak) for ports P00/CS 0 – P07/A17, P10/A8/D8 – P17/A15/D15, P20/A0/D0 – P27/A7/D7, P30/WEL – P33/ ____ HLDA and P8 must be 80 mA or less, the sum of IOL(peak) for ports P4, P5, P6, and P7 must be 100 mA or less, and the sum of IOH(peak) for ports P4, P5, P6, and P7 must be 80 mA or less. 3. Limits VIH and VIL for XCIN are applied when the sub clock external input selection bit = “1”. 4. The maximum value of f(XIN) = 6 MHz when the main clock division selection bit = “1”.

0.8 Vcc

0.5 Vcc

V V V V mA mA mA mA mA Parameter Symbol Vcc Power source voltage Vcc Vcc 0.2Vcc 0.16Vcc V –10 VIH VIH VIL VIL IOH(peak) IOH(avg) IOL(peak) IOL(peak) IOL(avg)

16-BIT CMOS MICROCOMPUTERNew product Limits Min. Typ. Max. VRAM V CC = 5 V, IOH = –10 mA V CC = 3 V, IOH = –1 mA V CC = 5 V, IOH = –400 A VCC = 5 V, IOH = –10 mA V CC = 5 V, IOH = –400 A VCC = 3 V, IOH = –1 mA VCC = 5 V, IOH = –10 mA V CC = 5 V, IOH = –400 A VCC = 3 V, IOH = –1 mA VCC = 5 V, IOL = 10 mA VCC = 3 V, IOL = 1 mA VCC = 5 V, IOL = 16 mA VCC = 3 V, IOL = 10 mA VCC = 5 V, IOL = 2 mA VCC = 5 V, IOL = 10 mA VCC = 5 V, IOL = 2 mA VCC = 3 V, IOL = 1 mA VCC = 5 V, IOL = 10 mA VCC = 5 V, IOL = 2 mA VCC = 3 V, IOL = 1 mA VCC = 5 V VCC = 3 V VCC = 5 V VCC = 3 V VCC = 5 V VCC = 3 V VCC = 5 V VCC = 3 V VCC = 5 V, VI = 5 V VCC = 3 V, VI = 3 V VCC = 5 V, VI = 0 V VCC = 3 V, VI = 0 V V I = 0 V, without a pull-up transistor V I = 0 V, with a pull-up transistor When clock is stopped. 0.2 0.1 0.1 0.06 0.1 0.06 Unit ELECTRICAL CHARACTERISTICS (Vcc = 5 V, Vss = 0 V, Ta = –40 to +85 °C, f(XIN) = 12 MHz, unless otherwise noted) Symbol Parameter Test conditions 2.5 4.7 3.1 4.8 2.6 3.4 4.8 2.6 0.4 0.5 1.8 1.5 1.9 0.43 0.4 0.45 1.6 0.4 0.4 0.5 0.4 0.4 0.26 0.4 0.26 A A V V V V V V V V V V V V V V OH VOH VOH VOL VOL VOL VOL VOL VT+ – VT– VT+ – VT– IIH IIL IIL VT+ – VT– VT+ – VT– 0.1 0.7 VOH –0.25 –0.08 –0.5 –0.18 A mA ___ High-level output voltage P00/CS 0 – P07/A17, P10/A8/D8 – P17/A15/D15,____ P20/A0/D0 – P27/A7/D7, P33/HLDA , P42/ 1, P43 – P47, P50 – P57, P60 – P67, P70 – P77, P80 – P87___ High-level output voltage P00/CS 0 – P07/A17, P10/A8/D8 – P17/A15/D15,____ P20/A0/D0 – P27/A7/D7, P33/HLDA , P42/ 1 High-level output voltage P30/WEL , P31/WEH , P32/ALE ___ High-level output voltage RDE ___ Low-level output voltage P00/CS 0 – P07/A17, P10/A8/D8 – P17/A15/D15,____ P20/A0/D0 – P27/A7/D7, P33/HLDA , P42/ 1, P43, P54 – P57, P60 – P67, P70 – P77, P80 – P87 Low-level output voltage P44 – P47, P50 – P53 ___ Low-level output voltage P00/CS 0 – P07/A17, P10/A8/D8 – P17/A15/D15,____ P20/A0/D0 – P27/A7/D7, P33/HLDA , P42/ 1 Low-level output voltage P30/WEL , P31/WEH , P32/ALE ___ Low-level output voltage RDE INT0 – INT2, AD TRG , CTS 0, CTS 1, CTS 2, CLK0,__ __ CLK 1, CLK2, KI0 – KI3 Hysteresis RESET Hysteresis XIN Hysteresis XCIN (When external clock is input) High-level input current P10/A8/D8 – P17/A15/D15, P20/A0/D0 – P27/A7/D7, P43 – P47, P80 – P87, XIN, RESET , CNVss, BYTE Low-level input current P10/A8/D8 – P17/A15/D15, P20/A0/D0 – P27/A7/D7, P43 – P47, P80 – P87, XIN, RESET , CNVss, BYTE Low-level input current P54 – P57, P62 – P64 RAM hold voltage –1.0 –0.35 V VCC = 5 V VCC = 3 V VCC = 5 V VCC = 3 V

16-BIT CMOS MICROCOMPUTERNew product VCC = 5 V, f(XIN) = 12 MHz (square waveform), (f(f2) = 6 MHz), f(XCIN) = 32.768 kHz, in operating (Note 1) VCC = 3 V, f(XIN) = 12 MHz (square waveform), (f(f2) = 6 MHz), f(XCIN) = 32.768 kHz, in operating (Note 1) V CC = 3 V, f(XIN) = 12 MHz (square waveform), (f(f2) = 0.75 MHz), f(XCIN) : Stopped, in operating VCC = 3 V, f(XIN) = 12 MHz (square waveform), f(XCIN) = 32.768 kHz, when a WIT instruction is executed (Note 2) VCC = 3 V, f(XIN) : Stopped, f(XCIN) = 32.768 kHz, in operating (Note 3) V CC = 3 V, f(XIN) : Stopped, f(XCIN) = 32.768 kHz, when a WIT instruction is executed (Note 4) Ta = 25 °C, when clock is stopped Ta = 85 °C, when clock is stopped mA mA mA A A A A A Max. 10.8 7.2 1.0 Limits Typ. 5.4 3.6 0.5 UnitMin. Test conditions Symbol Parameter ELECTRICAL CHARACTERISTICS (Vcc = 5 V, Vss = 0 V, Ta = –40 to +85 °C, unless otherwise noted) When external bus is in use, output pins are open, and other pins are V SS . Power source currentI CC Limits Min. Typ. Max. — Resolution V REF = VCC 10 Bits — Absolute accuracy V REF = VCC ± 3 LSB RLADDER Ladder resistance V REF = VCC 10 25 k Ω tCONV Conversion time 19.6 s VREF Reference voltage 2.7 V CC V VIA Analog input voltage 0 V REF V Symbol Parameter Test conditions Unit A–D CONVERTER CHARACTERISTICS (VCC = AVCC = 5 V, VSS = AVSS = 0 V, Ta = –40 to +85 °C, f(XIN) = 12 MHz, unless otherwise noted (Note)) Note. This applies when the main clock division selection bit = “0” and f(f2) = 6 MHz. Notes 1. This applies when the main clock external input selection bit = “1”, the main clock division selection bit = “0”, and the signal output stop bit = “1”. 2. This applies when the main clock external input selection bit = “1” and the system clock stop bit at wait state = “1”. 3. This applies when CPU and the clock timer are operating with the sub clock (32.768 kHz) selected as the system clock. 4. This applies when the XCOUT drivability selection bit = “0” and the system clock stop bit at wait state = “1”.

16-BIT CMOS MICROCOMPUTERNew product Limits Min. Max. tc External clock input cycle time (Note 1) 83 ns tw(H) External clock input high-level pulse width (Note 2) 33 ns tw(L) External clock input low-level pulse width (Note 2) 33 ns tr External clock rise time 15 ns tf External clock fall time 15 ns TIMING REQUIREMENTS (VCC = 2.7 – 5.5 V, VSS = 0 V, Ta = –40 to +85 °C, f(XIN) = 12 MHz, unless otherwise noted (Note 1)) Notes 1. This applies when the main clock division selection bit = “0” and f(f2) = 6 MHZ. 2. Input signal’s rise/fall time must be 100 ns or less, unless otherwise noted. External clock input UnitSymbol Parameter Notes 1. When the main clock division selection bit = “1”, the minimum value of tc = 166 ns. 2. When the main clock division selection bit = “1”, values of tw(H) / tc and tw(L) / tc must be set to values from 0.45 through 0.55. Microprocessor mode UnitSymbol Parameter Limits Min. Max. tsu(P4D–RDE) Port P4 input setup time 200 ns tsu(P5D–RDE) Port P5 input setup time 200 ns tsu(P6D–RDE) Port P6 input setup time 200 ns tsu(P7D–RDE) Port P7 input setup time 200 ns tsu(P8D–RDE) Port P8 input setup time 200 ns th(RDE–P4D) Port P4 input hold time 0n s th(RDE–P5D) Port P5 input hold time 0n s th(RDE–P6D) Port P6 input hold time 0n s th(RDE–P7D) Port P7 input hold time 0n s th(RDE–P8D) Port P8 input hold time 0n s tsu(D–RDE) Data input setup time 80 ns tsu(RDY– 1) ___ RDY input setup time 80 ns tsu(HOLD– 1) ____ HOLD input setup time 80 ns th(RDE–D) Data input hold time 0n s th( 1–RDY) ___ RDY input hold time 0n s th( 1–HOLD) ____ HOLD input hold time 0n s

16-BIT CMOS MICROCOMPUTERNew product Limits Min. Max. tc(TA) TAiIN input cycle time 250 ns tw(TAH) TAiIN input high-level pulse width 125 ns tw(TAL) TAiIN input low-level pulse width 125 ns UnitSymbol Parameter Timer A input (Count input in event counter mode) Limits Min. Max. tc(TA) TAiIN input cycle time (Note) 666 ns tw(TAH) TAiIN input high-level pulse width (Note) 333 ns tw(TAL) TAiIN input low-level pulse width (Note) 333 ns UnitSymbol Parameter Timer A input (Gating input in timer mode) Limits Min. Max. tc(TA) TAiIN input cycle time (Note) 333 ns tw(TAH) TAiIN input high-level pulse width 166 ns tw(TAL) TAiIN input low-level pulse width 166 ns UnitSymbol Parameter Timer A input (External trigger input in one-shot pulse mode) Limits Min. Max. tw(TAH) TAiIN input high-level pulse width 166 ns tw(TAL) TAiIN input low-level pulse width 166 ns UnitSymbol Parameter Timer A input (External trigger input in pulse width modulation mode) Limits Min. Max. tc(UP) TAiOUT input cycle time 3333 ns tw(UPH) TAiOUT input high-level pulse width 1666 ns tw(UPL) TAiOUT input low-level pulse width 1666 ns tsu(UP–TIN) TAiOUT input setup time 666 ns th(TIN–UP) TAiOUT input hold time 666 ns UnitSymbol Parameter Timer A input (Up-down input in event counter mode) Limits Min. Max. tc(TA) TAjIN input cycle time 2000 ns tsu(TAjIN–TAjOUT ) TAjIN input setup time 500 ns tsu(TAjOUT –TAjIN) TAjOUT input setup time 500 ns UnitSymbol Parameter Timer A input (Two-phase pulse input in event counter mode) Note. Limits change depending on f(XIN). Refer to “DATA FORMULAS”. Note. Limits change depending on f(XIN). Refer to “DATA FORMULAS”.

16-BIT CMOS MICROCOMPUTERNew product Limits Min. Max. tc(CK) CLK i input cycle time 333 ns tw(CKH) CLK i input high-level pulse width 166 ns tw(CKL) CLK i input low-level pulse width 166 ns td(C–Q) TXDi output delay time 100 ns th(C–Q) TXDi hold time 0n s tsu(D–C) RXD i input setup time 65 ns th(C–D) RXD i input hold time 75 ns Limits Min. Max. tc(TB) TBiIN input cycle time (one edge count) 250 ns tw(TBH) TBiIN input high-level pulse width (one edge count) 125 ns tw(TBL) TBiIN input low-level pulse width (one edge count) 125 ns tc(TB) TBiIN input cycle time (both edges count) 500 ns tw(TBH) TBiIN input high-level pulse width (both edges count) 250 ns tw(TBL) TBiIN input low-level pulse width (both edges count) 250 ns UnitSymbol Parameter Timer B input (Count input in event counter mode) Limits Min. Max. tc(TB) TBiIN input cycle time (Note) 666 ns tw(TBH) TBiIN input high-level pulse width (Note) 333 ns tw(TBL) TBiIN input low-level pulse width (Note) 333 ns UnitSymbol Parameter Timer B input (Pulse period measurement mode) Limits Min. Max. tc(TB) TBiIN input cycle time (Note) 666 ns tw(TBH) TBiIN input high-level pulse width (Note) 333 ns tw(TBL) TBiIN input low-level pulse width (Note) 333 ns UnitSymbol Parameter Timer B input (Pulse width measurement mode) UnitSymbol Parameter A-D trigger input UnitSymbol Parameter Serial I/O UnitSymbol Parameter External interrupt INTi input, key input interrupt KIi input Limits Min. Max. tw(INH) ___ INTi input high-level pulse width 250 ns tw(INL) ___ INTi input low-level pulse width 250 ns tw(KIL) KIi input low-level pulse width 250 ns Limits Min. Max. tc(AD) ____ AD TRG input cycle time (minimum allowable trigger) 1333 ns tw(ADL) ____ AD TRG input low-level pulse width 166 ns Note. Limits change depending on f(XIN). Refer to “DATA FORMULAS”. Note. Limits change depending on f(XIN). Refer to “DATA FORMULAS”.

16-BIT CMOS MICROCOMPUTERNew product DATA FORMULAS Timer A input (Gating input in timer mode) 8 5 109 2 • f(f2) 4 5 109 2 • f(f2) 4 5 109 2 • f(f2) Limits Min. Max.Symbol Parameter Unit tc(TA) TAiIN input cycle time tw(TAH) TAiIN input high-level pulse width tw (TAL ) TAi IN input low-level pulse width ns ns ns 8 5 109 2 • f(f2) Timer A input (External trigger input in one-shot pulse mode) Limits Min. Max.Symbol Parameter Unit tc(TA) TAiIN input cycle time ns Timer B input (In pulse period measurement mode or pulse width measurement mode) Limits Min. Max.Symbol Parameter Unit ns ns ns tc(TB) TBiIN input cycle time tw(TBH) TBiIN input high-level pulse width tw(TBL) TBiIN input low-level pulse width 8 5 109 2 • f(f2) 4 5 109 2 • f(f2) 4 5 109 2 • f(f2) Note. f(f2) represents the clock f2 frequency. For the relation to the main clock and sub clock, refer to Table 10 in data sheet “M37735MHBXXXFP”.

16-BIT CMOS MICROCOMPUTERNew product SWITCHING CHARACTERISTICS (VCC = 2.7 – 5.5 V, VSS = 0 V, Ta = –40 to +85°C, f(XIN) = 12 MHz, unless otherwise noted (Note)) Fig. 14 Measuring circuit for each pin 50 pF CS 0 – CS 4 RSMP A16, A17 A0/D0 – A15/D15 WEL WEH ALE HLDA P 4 P 5 P 6 P 7 P 8 RDE Limits Min. Max. td(WE–P4Q) Port P4 data output delay time 300 ns td(WE–P5Q) Port P5 data output delay time 300 ns td(WE–P6Q) Port P6 data output delay time 300 ns td(WE–P7Q) Port P7 data output delay time 300 ns td(WE–P8Q) Port P8 data output delay time 300 ns UnitSymbol Parameter Test conditions Fig. 14 Note. This applies when the main clock division selection bit = “0” and f(f2) = 6 MHz. Microprocessor mode

16-BIT CMOS MICROCOMPUTERNew product No wait Wait 1 Wait 0 No wait Wait 1 Wait 0 No wait Wait 1 Wait 0 No wait Wait 1 Wait 0 No wait Wait 1 Wait 0 No wait Wait 1 Wait 0 No wait Wait 1 Wait 0 No wait Wait 1 Wait 0 No wait Wait 1 Wait 0 Chip-select output delay time Chip-select hold time Address output delay time Address output delay time Address hold time ALE pulse width Address output setup time Address hold time ALE output delay time Data output delay time Data hold time WEL /WEH pulse width Floating start delay time Floating release delay time ___ RDE pulse width ____ RSMP output delay time ____ RSMP hold time 1 output delay time ____ HLDA output delay time Limits Wait mode Min. Max. Microprocessor mode (VCC = 2.7 – 5.5 V, VSS = 0 V, Ta = –40 to +85 °C, f(XIN) = 12 MHz, unless otherwise noted (Note 1)) Symbol Parameter Test conditions td(CS–WE) td(CS–RDE) th(WE–CS) th(RDE–CS) td(An–WE) td(An–RDE) td(A–WE) td(A–RDE) th(WE–An) th(RDE–An) tw(ALE) tsu(A–ALE) th(ALE–A) td(ALE–WE) td(ALE–RDE) td(WE–DQ) th(WE–DQ) tw(WE) tpxz(RDE–DZ) tpzx(RDE–DZ) tw(RDE) td(RSMP–WE) td(RSMP–RDE) th( 1–RSMP) td(WE– 1) td(RDE– 1) td( 1–HLDA) Notes 1. This applies when the main clock division selection bit = “0” and f(f2) = 6 MHz. 2. No wait : Wait bit = “1”. Wait 1 : The external memory area is accessed with wait bit = “0” and wait selection bit = “1”. Wait 0 : The external memory area is accessed with wait bit = “0” and wait selection bit = “0”. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 120 182 182 162 123 131 298 128 295 Fig. 14 (Note 2)

16-BIT CMOS MICROCOMPUTERNew product Bus timing data formulas (VCC = 2.7 – 5.5V, VSS = 0 V, Ta = –40 to +85 °C, f(XIN) = 12 MHz (Max.), unless otherwise noted (Note1)) Limits Wait mode Min. Max.Symbol Parameter Unit 1 5 109 2 • f(f2) 3 5 109 2• f(f2) ns ns No wait Wait 1 Wait 0 td(CS–WE) td(CS–RDE) th(WE–CS) th(RDE–CS) td(An–WE) td(An–RDE) td(A–WE) td(A–RDE) th(WE–An) th(RDE–An) tw(ALE) tsu(A–ALE) th(ALE–A) td(ALE–WE) td(ALE–RDE) td(WE–DQ) th(WE–DQ) tw(WE) tpxz(RDE–DZ) tpzx(RDE–DZ) tw(RDE) td(RSMP–WE) td(RSMP–RDE) th( 1–RSMP) td(WE– 1) td(RDE– 1) ns 4 1 5 109 2 • f(f2) 3 5 109 2 • f(f2) 1 5 109 2 • f(f2) 3 5 109 2 • f(f2) 1 5 109 2 • f(f2) 1 5 109 2 • f(f2) 2 5 109 2 • f(f2) 1 5 109 2 • f(f2) 2 5 109 2 • f(f2) ns ns ns ns ns ns ns ns ns ns No wait Wait 1 Wait 0 No wait Wait 1 Wait 0 No wait Wait 1 Wait 0 No wait Wait 1 Wait 0 No wait Wait 1 Wait 0 No wait Wait 1 Wait 0 No wait Wait 1 Wait 0 No wait Wait 1 Wait 0 1 5 109 2 • f(f2) ns ns ns ns ns ns 1 5 109 2 • f(f2) 1 5 109 2 • f(f2) 2 5 109 2 • f(f2) 4 5 109 2 • f(f2) ns ns 1 5 109 2 • f(f2) 2 5 109 2 • f(f2) 4 5 109 2 • f(f2) 1 5 109 2 • f(f2) ns ns ns ns ns ns Chip-select output delay time Chip-select hold time Address output delay time Address output delay time Address hold time ALE pulse width Address output setup time Address hold time ALE output delay time Data output delay time Data hold time WEL /WEH pulse width Floating start delay time Floating release delay time ___ RDE pulse width ____ RSMP output delay time ____ RSMP hold time 1 output delay time – 63 – 68 – 63 – 88 – 43 – 43 – 43 – 73 – 73 – 43 – 43 – 43 – 35 – 35 – 30 – 38 – 38 – 58 – 63 – 68 Notes 1. This applies when the main clock division selection bit = “0”. 2. f(f 2) represents the clock f2 frequency. For the relation to the main clock and sub clock, refer to Table 10 in data sheet “M37735MHBXXXFP”.

16-BIT CMOS MICROCOMPUTERNew product tw(H) td(WE–P4Q) td(WE–P5Q) td(WE–P6Q) td(WE–P7Q) td(WE–P8Q) RDE, WEL, WEH XIN Port P4 output Port P4 input Port P5 output Port P5 input Port P6 output Port P6 input Port P7 output Port P7 input Port P8 output Port P8 input tsu(P4D–RDE) tsu(P5D–RDE) tsu(P6D–RDE) tsu(P7D–RDE) tsu(P8D–RDE) tr tf tw(L)tc th(RDE–P4D) th(RDE–P5D) th(RDE–P6D) th(RDE–P7D) th(RDE–P8D) TIMING DIAGRAM

16-BIT CMOS MICROCOMPUTERNew product TAiIN input TAiOUT input tc(TA) tw(TAH) tw(TAL) tc(UP) tw(UPH) tw(UPL) th(TIN–UP) tsu(UP–TIN) TAiOUT input (Up-down input) TAiIN input (when count by falling) TAiIN input (when count by rising) In event count mode tc(TB) tw(TBH) tw(TBL) TBiIN input tsu(TAjIN–TAjOUT ) tsu(TAjIN–TAjOUT ) tsu(TAjOUT –TAjIN) tsu(TAjOUT –TAjIN) TAjIN input TAjOUT input In event counter mode (When two-phase pulse input is selected) tc(TA)

16-BIT CMOS MICROCOMPUTERNew product tc(AD) tw(ADL) tc(CK) tw(CKH) tw(CKL) tw(INL) tw(KNL) td(C–Q) tsu(D–C) th(C–D) tw(INH) AD TRG input CLK i TxD i RxD i INTi input Kli input th(C–Q)

16-BIT CMOS MICROCOMPUTERNew product Microprocessor mode (When wait bit = “1”) (When wait bit = “0”) (When wait bit = “1” or “0” in common) Test conditions

• V CC = 2.7 – 5.5 V
• Input timing voltage : VIL = 0.2VCC , VIH = 0.8VCC
• Output timing voltage : VOL = 0.8 V, VOH = 2.0 V RDY input RDY input HOLD input HLDA output tsu(RDY– 1) th( 1–RDY) tsu(RDY– 1) th( 1–RDY) tsu(HOLD– 1) td( 1–HLDA) th( 1–HOLD) td( 1–HLDA) WEL WEH RDE WEL WEH RDE

16-BIT CMOS MICROCOMPUTERNew product tw(WE) th(WE–DQ) tw(L) tw(H) tf tr tc Microprocessor mode (No wait : When wait bit = “1”) XIN CS 0 – CS 4 An ALE Am/Dm td(CS–WE) td(CS–RDE) th(WE–CS) th(RDE–CS) Address td(An–WE) td(An–RDE) th(RDE–An)tw(ALE) td(ALE–WE) Address Address tsu(A–ALE) th(ALE–A) td(A–WE) td(A–RDE) td(ALE–RDE) tpxz(RDE–DZ) tpzx(RDE–DZ) Address Data Address Address WEL, WEH th(WE–An) td(WE–DQ) Dm IN RDE RSMP Test conditions

• Output timing voltage : V OL = 0.8 V, VOL = 2.0 V
• Data input DmIN : VIL = 0.16 VCC , VIH = 0.5 VCC tsu(D–RDE) th(RDE–D) tw(RDE) td(RSMP–WE) th( 1–RSMP) td(RSMP–RDE) Data td(RDE– 1)td(WE– 1)td(WE– 1) td(RDE– 1)

16-BIT CMOS MICROCOMPUTERNew product tw(ALE) td(An–WE) tc Am/Dm Address td(CS–RDE) tw(RDE) td(RDE- 1) tw(L) tw(H) tf tr Microprocessor mode (Wait 1 : The external area is accessed when wait bit = “0” and wait selection bit = “1”.) XIN Address Address CS 0 – CS 4 An ALE WEL, WEH Dm IN RDE RSMP td(WE– 1) td(RDE– 1) td(CS–WE) td(ALE–WE) th(RDE–An) tsu(A–ALE) th(ALE–A) td(A–WE) td(WE–DQ) tw(WE) td(A–RDE) tpxz(RDE–DZ) tpzx(RDE–DZ) th(RDE–CS) th(RDE–D) tsu(D–RDE) td(RSMP–WE) th( 1–RSMP) td(RSMP–RDE) Test conditions

• Output timing voltage : V OL = 0.8 V, VOH = 2.0 V
• Data input DmIN : VIL = 0.16 VCC , VIH = 0.5 VCC Data Address th(WE–CS) Data td(WE– 1) th(WE-An) td(ALE–RDE) td(An–RDE) th(WE–DQ) Address

16-BIT CMOS MICROCOMPUTERNew product th(ALE–A) td(ALE–WE) td(WE–DQ) tw(L) tw(H) tf tctr Microprocessor mode (Wait 0 : The external memory area is accessed when wait bit = “0” and wait selection bit = “0”.) XIN Address Address Address Address Data CS 0 – CS 4 An ALE Am/Dm WEL , WEH Dm IN RDE RSMP td(CS–WE) th(WE–CS) td(CS–RDE) td(An–WE) tw(ALE) th(WE–An) td(An–RDE) th(RDE–An) tsu(A–ALE) th(WE–DQ) td(ALE–RDE) td(A–WE) tw(WE) td(A–RDE) tpxz(RDE–DZ) tpzx(RDE–DZ) th(RDE–CS) th(RDE–D)tsu(D–RDE) tw(RDE) td(RSMP–WE) th( 1–RSMP) td(RSMP–RDE) Address Data Address Test conditions

• Output timing voltage : V OL = 0.8 V, VOH = 2.0 V
• Data input DmIN : VIL = 0.16 VCC , VIH = 0.5 VCC td(WE– 1) td(RDE– 1) td(RDE– 1)td(WE– 1)

16-BIT CMOS MICROCOMPUTERNew product PACKAGE OUTLINE

16-BIT CMOS MICROCOMPUTERNew product MEMO New pr oduct

© 1996 MITSUBISHI ELECTRIC CORP. H-LF430-A KI-9606 Printed in Japan (ROD) New publication, effective Jun. 1996. Specifications subject to change without notice. Notes regarding these materials

• These materials are intended as a reference to assist our customers in the selection of the Mitsubishi semiconductor product best suited to the customer’s application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Mitsubishi Electric Corporation or a third party.
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• Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for further details on these materials or the products contained therein. Keep safety first in your circuit designs!
• Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non-flammable material or (iii) prevention against any malfunction or mishap. MITSUBISHI MICROCOMPUTERS M37735S4LHP 16-BIT CMOS MICROCOMPUTERNew pr oduct