M37733EHL MITSUBISHI | Alldatasheet

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Technical content

DESCRIPTION

The M37733EHLXXXHP is a single-chip microcomputer using the 7700 Family core. This single-chip microcomputer has a CPU and a bus interface unit. The CPU is a 16-bit parallel processor that can be an 8-bit parallel processor, and the bus interface unit enhances the memory access efficiency to execute instructions fast. This microcomputer also includes a 32 kHz oscillation circuit, in addition to the PROM, RAM, multiple-function timers, serial I/O, A-D converter, and so on. Its strong points are the low power dissipation, the low supply voltage, and the small package. The M37733EHLXXXHP has the same function as the M37733MHLXXXHP except that the built-in ROM is PROM. (Refer to the basic function blocks description.)

FEATURES

l Instruction execution time l Low power dissipation (At 3 V supply voltage, 12 MHz frequency) l Watchdog timer l Programmable input/output (0.5 mm lead pitch) APPLICATION Control devices for general commercial equipment such as office automation, office equipment, personal information equipment, and so on. Control devices for general industrial equipment such as communication equipment, and so on. PIN CONFIGURATION (TOP VIEW) PRELIMINARY Notice: This is not a final specification. Some parametric limits are subject to change. MITSUBISHI MICROCOMPUTERS M37733EHLXXXHP PROM VERSION OF M37733MHLXXXHP Outline 80P6D-A, 80P6Q-A P30/R/W P32/ALE P31/BH E P33/HL DA XOUT E CNV SS R ESET P40/HO LD P86/R xD 1 P87/TxD 1 P00/A0 P01/A1 P02/A2 P03/A3 P04/A4 P05/A5 P06/A6 P07/A7 P10/A8/D 8 P11/A9/D 9 P12/A10 /D 10 P13/A11 /D 11 P14/A12 /D 12 P15/A13 /D 13 P16/A14 /D 14 P17/A15 /D 15 P20/A16 /D 0 P21/A17 /D 1 P41/RDY P42/f1 BYT E XIN VSS P27/A23/D 7 P26/A22/D 6 P25/A21/D 5 P24/A20/D 4 P23/A19/D 3 P22/A18/D 2 P66/TB 1IN P65/TB 0IN P64/INT 2 P63/INT 1 P62/INT 0 P61/TA 4IN P60/TA 4OUT P57/TA 3IN/KI3 P56/TA 3OUT /KI2 P55/TA 2IN/KI1 P54/TA 2OUT /KI0 P53/TA 1IN P52/TA 1OUT P51/TA 0IN P50/TA 0OUT P47 P85/CL K1 P84/CT S1/RT S1 P83/TXD 0 P82/R XD 0/CL K S0 P81/CL K0 P80/CT S0/RT S0/CL K S1 VCC AV CC VRE F AV SS VSS P76/AN 6/XCO UT P75/AN 5/AD TR G/TXD 2 P74/AN 4/R XD 2 P73/AN 3/CL K2 P72/AN 2/CT S2 P71/AN 1 P70/AN 0 P67/TB 2IN /fSUB M37733E HLXXXHP P43 P44 P45 P46 P77/AN 7/XCIN

Notice: This is not a final specification. Some parametric limits are subject to change. MITSUBISHI MICROCOMPUTERS M37733EHLXXXHP PROM VERSION OF M37733MHLXXXHP M37733EHLXXXHP BLOCK DIAGRAM XIN XOUT E RESET Reset input VREF CNVss BYTE P0(8) UART1(9) UART0(9) AV SS (0V) AV CC (0V) VSSVCC A-D Converter(10) XCIN XCOUT XCIN XCOUT Clock input Clock output Enable output Reference voltage input External data bus width selection input Clock Generating Circuit Instruction Register(8) Arithmetic Logic Unit(16) Accumulator A(16) Accumulator B(16) Index Register X(16) Index Register Y(16) Stack Pointer S(16) Direct Page Register DPR(16) Processor Status Register PS(11) Input Butter Register IB(16) Data Bank Register DT(8) Program Bank Register PG(8) Program Counter PC(16) Incrementer/Decrementer(24) Data Address Register DA(24) Program Address Register PA(24) Incrementer(24) Instruction Queue Buffer Q2(8) Instruction Queue Buffer Q1(8) Instruction Queue Buffer Q0(8) Data Buffer DBL(8) Data Buffer DBH (8) PROM

124 Kbytes

Timer TA3(16) Timer TA4(16) Timer TA2(16) Timer TA1(16) Timer TA0(16) Watchdog Timer Timer TB2(16) Timer TB1(16) Timer TB0(16) Address Bus Data Bus(Odd) Data Bus(Even) Input/Output port P8 Input/Output port P7 Input/Output port P6 Input/Output port P5 Input/Output port P4 Input/Output port P3 Input/Output port P2 Input/Output port P1 Input/Output port P0 UART2(9)

PROM VERSION OF M37733MHLXXXHP PRELIMINARY Notice: This is not a final specification. Some parametric limits are subject to change. FUNCTIONS OF M37733EHLXXXHP Memory size Input/Output ports Multi-function timers Interrupts Clock generating circuit Power dissipation Parameter Functions Number of basic instructions 103 Instruction execution time 333 ns (the fastest instruction at external clock 12 MHz frequency) PROM 124 Kbytes RAM 3968 bytes P0 – P2, P4 – P8 8-bit 5 8 P3 4-bit 5 1 TA0, TA1, TA2, TA3, TA4 16-bit 5 5 TB0, TB1, TB2 16-bit 5 3 Serial I/O (UART or clock synchronous serial I/O) 5 3 A-D converter 10-bit 5 1 (8 channels) Watchdog timer 12-bit 5 1 3 external types, 16 internal types Each interrupt can be set to the priority level (0 – 7.) 2 circuits built-in (externally connected to a ceramic resonator or a quartz-crystal oscillator) Supply voltage 2.7 – 5.5 V 9 mW (at 3 V supply voltage, external clock 12 MHz frequency) 22.5 mW (at 5 V supply voltage, external clock 12 MHz frequency) Input/Output voltage 5 V Output current 5 mA Memory expansion Maximum 16 Mbytes Operating temperature range –40 to 85 °C Device structure CMOS high-performance silicon gate process Package 80-pin plastic molded fine-pitch QFP (80P6D-A;0.5 mm lead pitch) Input/Output characteristic

Notice: This is not a final specification. Some parametric limits are subject to change. MITSUBISHI MICROCOMPUTERS M37733EHLXXXHP PROM VERSION OF M37733MHLXXXHP PIN DESCRIPTION XIN Clock input Input XOUT Clock output Output Pin Name Input/Output Functions Vcc, Power source Apply 2.7 – 5.5 V to Vcc and 0 V to Vss. Vss CNVss CNVss input Input This pin controls the processor mode. Connect to Vss for the single-chip mode and the memory expansion mode, and to Vcc for the microprocessor mode._____ RESET Reset input Input When “L” level is applied to this pin, the microcomputer enters the reset state. These are pins of main-clock generating circuit. Connect a ceramic resonator or a quartz- crystal oscillator between XIN and XOUT . When an external clock is used, the clock source should be connected to the XIN pin, and the XOUT pin should be left open._ E Enable output Output This pin functions as the enable signal output pin which indicates the access status in the internal__ bus. When output level of E signal is “L”, data/instruction read or data write is performed. BYTE External data Input In the memory expansion mode or the microprocessor mode, this pin determines whether the bus width external data bus has an 8-bit width or a 16-bit width. The data bus has a 16-bit width when “L” selection input signal is input and an 8-bit width when “H” signal is input. AVcc, Analog power Power source input pin for the A-D converter. Externally connect AVcc to Vcc and AVss to Vss. AVss source input V REF Reference Input This is reference voltage input pin for the A-D converter. voltage input P00 – P07 I/O port P0 I/O In the single-chip mode, port P0 becomes an 8-bit I/O port. An I/O direction register is available so that each pin can be programmed for input or output. These ports are in the input mode when reset. In the memory expansion mode or the microprocessor mode, these pins output address (A0 – A7). P10 – P17 I/O port P1 I/O In the single-chip mode, these pins have the same functions as port P0. When the BYTE pin is set to “L” in the memory expansion mode or the microprocessor mode and external data bus has a 16-bit width, high-order data (D8 – D15) is input/output or an address (A8 – A15) is output. When the BYTE pin is “H” and an external data bus has an 8-bit width, only address (A8 – A15) is output. P20 – P27 I/O port P2 I/O In the single-chip mode, these pins have the same functions as port P0. In the memory expansion mode or the microprocessor mode, low-order data (D0 – D7) is input/output or an address (A16 – A23) is output. P30 – P33 I/O port P3 I/O In the single-chip mode, these pins have the same function as port P0. In the memory expansion__ ___ ____ mode or the microprocessor mode, R/W , BHE , ALE, and HLDA signals are output. P40 – P47 I/O port P4 I/O In the single-chip mode, these pins have the same functions as port P0. In the memory expansion____ ___ mode or the microprocessor mode, P40, P41, and P42 become HOLD and RDY input pins, and a clock φ1 output pin, respectively. Functions of the other pins are the same as in the single-chip mode. However, in the memory expansion mode, P42 can be selected as an I/O port. P50 – P57 I/O port P5 I/O In addition to having the same functions as port P0 in the single-chip mode, these pins also__ __ function as I/O pins for timers A0 to A3 and input pins for key input interrupt input (KI0 – KI3). P60 – P67 I/O port P6 I/O In addition to having the same functions as port P0 in the single-chip mode, these pins also___ ___ function as I/O pins for timer A4, input pins for external interrupt input (INT0 – INT2) and input pins for timers B0 to B2. P67 also functions as sub-clock φSUB output pin. P70 – P77 I/O port P7 I/O In addition to having the same functions as port P0 in the single-chip mode, these pins function as input pins for A-D converter. P72 to P75 also function as I/O pins for UART2. Additionally, P76 and P77 have the function as the output pin (XCOUT ) and the input pin (XCIN) of the sub-clock (32 kHz) oscillation circuit, respectively. When P76 and P77 are used as the XCOUT and XCIN pins, connect a resonator or an oscillator between the both. P80 – P87 I/O port P8 I/O In addition to having the same functions as port P0 in the single-chip mode, these pins also function as I/O pins for UART 0 and UART 1.

PROM VERSION OF M37733MHLXXXHP PRELIMINARY Notice: This is not a final specification. Some parametric limits are subject to change. Functions Supply 5V±10% to VCC and 0V to VSS . Connect to VPP when programming or verifing. Connect to VPP when programming or verifing. Connect to VSS . Connect a ceramic resonator between XIN and XOUT . Keep open. Connect AVCC to VCC and AVSS to VSS . Connect to VSS . Port P0 functions as the lower 8 bits address input (A0 – A7). Port P1 functions as the higher 8 bits address input (A8 – A15). Port P2 functions as the 8 bits data bus(D0 – D7). P30 functions as the most significant bit address input (A16). Connect to VSS . Connect to VSS . P50, P51 and P52 function as PGM , OE and CE input pins respectively. Connect P53, P54, P55 and P56 to VCC . Connect P57 to VSS . Connect to VSS . Connect to VSS . Connect to VSS . Input/Output Input Input Input Input Output Output Input Input Input I/O Input Input Input Input Input Input Input Name Power supply V PP input VPP input Reset input Clock input Clock output Enable output Analog supply input Reference voltage input Address input (A 0 – A7) Address input (A8 – A15) Data I/O (D0 – D7) Address input (A16) Input port P3 Input port P4 Control signal input Input port P6 Input port P7 Input port P8 Pin V CC , VSS CNV SS BYTE ____ RESET XIN XOUT E AV CC , AVSS VREF P00 – P07 P10 – P17 P20 – P27 P30 P31 – P33 P40 – P47 P50 – P57 P60 – P67 P70 – P77 P80 – P87 PIN DESCRIPTION (EPROM MODE)

Notice: This is not a final specification. Some parametric limits are subject to change. MITSUBISHI MICROCOMPUTERS M37733EHLXXXHP PROM VERSION OF M37733MHLXXXHP Note. Write to the oscillation circuit control register 1 as the flow shown in Figure 2. Oscillation circuit control register 1 Main clock division selection bit 0 : Main clock is divided by 2. 1 : Main clock is not divided by 2. Main clock external input selection bit 0 : Main-clock oscillation circuit is operating by itself. Watchdog timer is used at returning from STP state. 1 : Main-clock is input externally. Watchdog timer is not used at returning from STP state. Sub clock external input selection bit 0 : Sub-clock oscillation circuit is operating by itself. 6 functions as XCOUT pin. Watchdog timer is used at returning from STP state. 1 : Sub-clock is input externally. 6 functions as I/O port. Watchdog timer is not used at returning from STP state. Always “1” (“1” at reset) 0 : Always “0” (However, writing data “55 16” shown in Figure 2 is possible.) Clock prescaler reset bit Address 6F16CC 0CC 1CC 201 76543210 Fig. 1 Bit configuration of oscillation circuit control register 1 (corresponding to Figure 63 in data sheet “M37733MHBXXXFP”) Fig. 2 How to write data in oscillation circuit control register 1 (identical with Figure 64 in data sheet “M37733MHBXXXFP”) Writing data “8016” (LDM instruction) Reset clock prescaler Writing data “5516” (LDM instruction) Writing data “0Y16” (LDM instruction) CC 2 to CC0 selection bits

  • How to reset clock prescaler • How to write in CC 2 to CC0 selection bits Note. “Y” is the sum of bits to be set. For example, when setting bits 2 and 1 to “1”, “Y” becomes “6”. Next instruction BASIC FUNCTION BLOCKS The M37733EHLXXXHP has the same functions as the M37733MHBXXXFP except for the following : (1) The built-in ROM is PROM. (2) The package is different. (3) The reset circuit is different. (4) The status of bit 3 of the oscillation circuit control register 1 (address 16) at a reset is different. (5) The usage condition of bit 3 of the oscillation circuit control register 1 is different. Accordingly, refer to the basic function blocks description in the M37733MHBXXXFP except for Figure 1 (bit configuration of the oscillation circuit control register 1) , Figure 3 and Figure 4 (reset circuit). In the M37733EHLXXXHP, bit 3 of the oscillation circuit control register 1 must be “1”. (Refer to Figure 1.) The status of this bit at a reset is “1”.

Notice: This is not a final specification. Some parametric limits are subject to change. MITSUBISHI MICROCOMPUTERS M37733EHLXXXHP PROM VERSION OF M37733MHLXXXHP Fig. 3 Microcomputer internal status during reset Address 0016 0000 0016 0016 0016 0016 0016 0016 0000 ?? ? 0016 0016 0000 0000 0000 0000 1000 0010 000 0 0 0016 0016 0016 0016 0016 0016 0001 00 0 0 001 001 00 0 0 00 0 0 0016 (0416)••• (0516)••• (0816)••• (0916)••• (0C16)••• (0D16)••• (1016)••• (1116)••• (1416)••• (1E16)••• (1F16)••• (3016)••• (3816)••• (3416)••• (3C16)••• (3516)••• (3D16)••• (4016)••• (4216)••• (4416)••• (5616)••• (5716)••• (5816)••• (5916)••• (5A16)••• (5B16)••• (5C16)••• (5D16)••• (5E16)••• (5F16)••• Port P0 direction register Port P1 direction register Port P2 direction register Port P3 direction register Port P4 direction register Port P5 direction register Port P6 direction register Port P7 direction register Port P8 direction register A-D control register 0 A-D control register 1 UART 0 transmit/receive mode register UART 1 transmit/receive control register 1 UART 1 transmit/receive mode register UART 0 transmit/receive control register 0 UART 1 transmit/receive control register 0 UART 0 transmit/receive control register 1 Count start flag One- shot start flag Up-down flag Timer A0 mode register Timer A1 mode register Timer A2 mode register Timer A3 mode register Timer A4 mode register Timer B0 mode register Timer B1 mode register Timer B2 mode register Processor mode register 0 Processor mode register 1 Address (6016)••• (7F16)••• (6C16)••• (6D16)••• (6E16)••• (6F16)••• (7016)••• (7116)••• (7216)••• (7316)••• (7416)••• (7516)••• (7616)••• (7716)••• (7816)••• (7916)••• (7A16)••• (7B16)••• (7C16)••• (7D16)••• (7E16)••• Watchdog timer register Oscillation circuit control register 0 Port function control register Serial transmit control register Oscillation circuit control register 1 A-D/UART2 trans./rece. interrupt control register UART 0 transmission interrupt control register UART 0 receive interrupt control register UART 1 transmission interrupt control register UART 1 receive interrupt control register Timer A0 interrupt control register Timer B2 interrupt control register Timer A1 interrupt control register Timer A2 interrupt control register Timer A3 interrupt control register Timer A4 interrupt control register Timer B0 interrupt control register Timer B1 interrupt control register Processor status register (PS) Program bank register (PG) Program counter (PC H ) Program counter (PCL) Direct page register (DPR) Data bank register (DT) INT0 interrupt control register Contents of other registers and RAM are undefined during reset. Initialize them by software. ?000 0000 001 00 0 00 0 00 0 00 0 1? ? 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0016 0016 Content of FFFF16 Content of FFFE16 000016 FFF 16 INT1 interrupt control register INT2/Key input interrupt control register 0016 0 01000 (6116)••• (6316)••• (6416)••• (6816)••• Watchdog timer frequency selection flag Memory allocation control register UART2 transmit/receive mode register UART2 transmit/receive control register 0 0 0 001000 0000 (6916)•••UART2 transmit/receive control register 1 0 000 000 0001 0 010 0000 0016

PROM VERSION OF M37733MHLXXXHP PRELIMINARY Notice: This is not a final specification. Some parametric limits are subject to change. EPROM MODE The M37733EHLXXXHP features an EPROM mode in addition to its normal modes. When the RESET signal level is “L”, the chip automatically enters the EPROM mode. Table 1 list the correspondence between pins and Figure 5 shows the pin connections in the EPROM mode. The EPROM mode is the 1M mode for the EPROM that is equivalent to the M5M27C101K. When in the EPROM mode, ports P0, P1, P2, P3 0, P50, P51, P52, CNV SS and BYTE are used for the EPROM (equivalent to the M5M27C101K). When in this mode, the built-in PROM can be programmed or read from using these pins in the same way as with the M5M27C101K. This chip does not have Device Identifier Mode, so that set the corresponding program algorithm. The program area should specify address 01000 16 – 1FFFF16. Connect the clock which is either ceramic resonator or external clock to X IN pin and XOUT pin. Fig. 5 Pin connection in EPROM mode Outline 80P6D-A ∗ : Connect to ceramic oscillation circuit. : It is used in the EPROM mode. P86/RX D 1 « P87/TX D 1 P00/A0 P01/A1 P02/A2 P03/A3 P04/A4 P05/A5 P06/A6 P07/A7 P10/A8/D8 P11/A9/D9 P12/A10/D10 P13/A11/D11 P14/A12/D12 P15/A13/D13 P16/A14/D14 P17/A15/D15 P20/A16/D0 P21/A17/D1 P66/TB1IN P65/TB0IN P64/INT2 P63/INT1 P62/INT0 P61/TA4IN P60/TA4OUT P57/TA3IN/KI3 P56/TA3OUT /KI2 P55/TA2IN/KI1 P54/TA2OUT /KI0 P53/TA1 IN P52/TA1 OUT P51/TA0 IN P50/TA0 OUT P47 P46 P45 P44 P43 fi P85/CLK1 P84/CTS 1/RTS 1 P83/TX D 0 P82/RX D 0/CLKS0 VCC AVCC VREF AVSS P77/AN7/XCIN P76/AN6/XCOUT P75/AN5/AD TRG /TxD2 P74/AN4/RxD2 P73/AN3/CLK2 P72/AN2/CTS2 P71/AN1 P70/AN0 P81/CLK0 P80/CTS 0/RTS 0/CLKS1 VSS P22/A18/D2 « fi fi P23/A19/D3 P24/A20/D4 P25/A21/D5 P26/A22/D6 P27/A23/D7 P30/R/W P31/BHE P32/ALE P33/HLDA VSS E XOUT XIN RESET CNV SS BYTE P40/HOLD P41/RDY M37733EHLXXXHP A10 A11 A12 A13 A14 A15 D 0 D 1 PGM OE CE D 2 D 3 D 4 D 5 D 6 D 7 VPP VSS VCC üïýïþ P42/f1 A16 fSUB P67/TB2IN/

Notice: This is not a final specification. Some parametric limits are subject to change. MITSUBISHI MICROCOMPUTERS M37733EHLXXXHP PROM VERSION OF M37733MHLXXXHP Table 1 Pin function in EPROM mode VCC VPP VSS Address input Data I/O CE OE ___ PGM M37733EHLXXXHP VCC CNV SS , BYTE VSS Ports P0, P1, P30 Port P2 P52 P51 P50 M5M27C101K VCC VPP VSS A0 – A16 D 0 – D7 CE OE ___ PGM

Notice: This is not a final specification. Some parametric limits are subject to change. the CE or OE pins are in the “H” state. – D7. Set the PGM pin to a “L” level to being programming. number of pulses (0.2 5 X ms). last address has been reached. Table 2. I/O signal in each mode Note 1 : An X indicates either VIL or VIH.

Notice: This is not a final specification. Some parametric limits are subject to change. MITSUBISHI MICROCOMPUTERS M37733EHLXXXHP PROM VERSION OF M37733MHLXXXHP AC waveforms Programming algorithm flow chart Test conditions for A.C. characteristics Input voltage : VIL = 0.45 V, VIH = 2.4 V Input rise and fall times (10 % – 90 %) : ≤ 20 ns Reference voltage at timing measurement : Input, Output *4.5 V ≤ VCC = VPP ≤ 5.5 V START ADDR=FIRST LOCATION VCC =6.0 V VPP =12.5 V X=0 PROGRAM ONE PULSE OF 0.2 ms X=X+1 X=25? VERIFY BYTE LAST ADDR? VCC =VPP =*5.0 V DEVICE PASSED PROGRAM PULSE OF 0.2X ms DURATION VERIFY ALL BYTE FAIL FAIL DEVICE FAILED FAIL DEVICE FAILED YES PASS YES INCREMENT ADDR NO VERIFY BYTE PASS PASS NO tDFP tAH tDH tDS tAS tVPS tVCS tCES tPW tOPW tOES tOE DATA SET PROGRAM VERIFY VIH VIL VIH/VOH VIL/VOL VPP VCC VCC +1 VCC VIH VIL VIH VIL VIH VIL ADDRESS DATA VPP VCC CE PGM OE DATA OUTPUT VALID

PROM VERSION OF M37733MHLXXXHP PRELIMINARY Notice: This is not a final specification. Some parametric limits are subject to change. SAFETY INSTRUCTIONS (1) A high voltage is used for programming. Take care that over- voltage is not applied. Take care especially at power on. (2) The programmable M37733EHLHP that is shipped in blank is also provided. For the M37733EHLHP, Mitsubishi Electric corp. does not perform PROM programming test and screening following the assembly processes. To improve reliability after programming, performing programming and test according to the flow below before use is recommended. ADDRESSING MODES The M37733EHLXXXHP has 28 powerful addressing modes. Refer to the “7700 Family Software Manual” for the details. MACHINE INSTRUCTION LIST The M37733EHLXXXHP has 103 machine instructions. Refer to the “7700 Family Software Manual” for the details. DATA REQUIRED FOR PROM ORDERING Please send the following data for writing to PROM. (1) M37733EHLXXXHP writing to PROM order confirmation form (2) 80P6D, 80P6Q mark specification form (3) ROM data (EPROM 3 sets) Programming with PROM programmer Function check in target device Verify test with PROM programmer Caution : Never expose to 150 °C exceeding 100 hours. Screening (Leave at 150 °C for 40 hours) (Caution)

Notice: This is not a final specification. Some parametric limits are subject to change. MITSUBISHI MICROCOMPUTERS M37733EHLXXXHP PROM VERSION OF M37733MHLXXXHP Symbol Parameter Conditions Ratings Unit Vcc Power source voltage –0.3 to +7 V AVcc Analog power source voltage –0.3 to +7 V VI Input voltage RESET , CNVss, BYTE –0.3 to +12 (Note) V Input voltage P00 – P07, P10 – P17, P20 – P27, P30 – P33, P40 – P47, P50 – P57, P60 – P67, P70 – P77, P80 – P87, VREF , XIN Output voltageP00 – P07, P10 – P17, P20 – P27, P30 – P33, P40 – P47, P50 – P57, P60 – P67, P70 – P77, P80 – P87,_ XOUT , E Pd Power dissipation Ta = 25 °C 200 mW Topr Operating temperature –40 to +85 °C Tstg Storage temperature –65 to +150 °C VI VO ABSOLUTE MAXIMUM RATINGS –0.3 to Vcc + 0.3 V –0.3 to Vcc + 0.3 V Note. When the EPROM is programmed, input voltage of pins CNVSS and BYTE is 13 V respectively. Limits Min. Typ. Max. f(XIN) : Operating 2.7 5.5 f(XIN) : Stopped, f(XCIN) = 32.768 kHz 2.7 5.5 AVcc Analog power source voltage Vcc V Vss Power source voltage 0V AVss Analog power source voltage 0 V High-level input voltage P00 – P07, P30 – P33, P40 – P47, P50 – P57, P60 – P67,_____ P70 – P77, P80 – P87, XIN, RESET , CNVss, BYTE, XCIN (Note 3) High-level input voltage P10 – P17, P20 – P27 (in single-chip mode) High-level input voltage P10 – P17, P20 – P27 (in memory expansion mode and microprocessor mode) Low-level input voltage P00 – P07, P30 – P33, P40 – P47, P50 – P57, P60 – P67,_____ P70 – P77, P80 – P87, XIN, RESET , CNVss, BYTE, XCIN (Note 3) Low-level input voltage P10 – P17, P20 – P27 (in single-chip mode) Low-level input voltage P10 – P17, P20 – P27 (in memory expansion mode and microprocessor mode) High-level peak output current P00 – P07, P10 – P17, P20 – P27, P30 – P33, P40 – P47, P50 – P57, P60 – P67, P70 – P77, P80 – P87 High-level average output current P00 – P07, P10 – P17, P20 – P27, P30 – P33, P40 – P47, P50 – P57, P60 – P67, P70 – P77, P80 – P87 Low-level peak output current P00 – P07, P10 – P17, P20 – P27, P30 – P33, P40 – P43, P54 – P57, P60 – P67, P70 – P77, P80 – P87 Low-level peak output current P44 – P47, P50 – P53 Low-level average output current P00 – P07, P10 – P17, P20 – P27, P30 – P33, P40 – P43, P54 – P57, P60 – P67, P70 – P77, P80 – P87 IOL(avg) Low-level average output current P44 – P47, P50 – P53 12 mA f(XIN) Main-clock oscillation frequency (Note 4) 12 MHz f(XCIN) Sub-clock oscillation frequency 32.768 50 kHz UnitSymbol Parameter RECOMMENDED OPERATING CONDITIONS (Vcc = 2.7 – 5.5 V, Ta = –40 to +85 °C, unless otherwise noted) VVcc Power source voltage Notes 1.Average output current is the average value of a 100 ms interval. 2.The sum of IOL(peak) for ports P0, P1, P2, P3, and P8 must be 80 mA or less, the sum of IOH(peak) for ports P0, P1, P2, P3, and P8 must be 80 mA or less, the sum of IOL(peak) for ports P4, P5, P6, and P7 must be 100 mA or less, and the sum of IOH(peak) for ports P4, P5, P6, and P7 must be 80 mA or less. 3.Limits VIH and VIL for XCIN are applied when the sub clock external input selection bit = “1”. 4.The maximum value of f(XIN) = 6 MHz when the main clock division selection bit = “1”.

0.8 Vcc

0.5 Vcc

0.2Vcc 0.2Vcc 0.16Vcc –10 V V V V V V mA mA mA mA mA V IH VIH VIH VIL VIL VIL IOH(peak) IOH(avg) IOL(peak) IOL(peak) IOL(avg)

PROM VERSION OF M37733MHLXXXHP PRELIMINARY Notice: This is not a final specification. Some parametric limits are subject to change. Unit ELECTRICAL CHARACTERISTICS (Vcc = 5 V, Vss = 0 V, Ta = –40 to +85 °C, f(XIN) = 12 MHz, unless otherwise noted) Symbol Parameter Test conditions 2.5 4.7 VVOH VOH –0.5 –0.18 High-level output voltage P00 – P07, P10 – P17, P20 – P27, P33, P40 – P47, P50 – P57, P60 – P67, P70 – P77, P80 – P87 High-level output voltage P00 – P07, P10 – P17, P20 – P27, P33 High-level output voltage P30 – P32 High-level output voltage E Low-level output voltage P00 – P07, P10 – P17, P20 – P27, P33, P40 – P43, P54 – P57, P60 – P67, P70 – P77, P80 – P87 Low-level output voltage P44 – P47, P50 – P53 Low-level output voltage P00 – P07, P10 – P17, P20 – P27, P33 Low-level output voltage P30 – P32 Low-level output voltage E INT0 – INT2, AD TRG , CTS 0, CTS 1, CTS 2, CLK0,__ __ CLK 1, CLK2, KI0 – KI3 Hysteresis RESET Hysteresis XIN Hysteresis XCIN (When external clock is input) High-level input current P00 – P07, P10 – P17, P20 – P27, P30 – P33, P40 – P47, P50 – P57, P60 – P67, P70 – P77, P80 – P87, XIN, RESET , CNVss, BYTE Low-level input current P00 – P07, P10 – P17, P20 – P27, P30 – P33, P40 – P47, P50 – P53, P60, P61, P65 – P67, P70 – P77, P80 – P87, XIN, RESET , CNVss, BYTE VOH 3.1 4.8 2.6 3.4 4.8 2.6 VOH VOL V V V V 0.5 1.8

1.5 VVOL

0.45 1.9 0.43 0.4 1.6 0.4 0.4 V V V 0.4 0.1 0.2 0.1 0.1 0.06 0.1 0.06 VCC = 5 V, IOH = –10 mA VCC = 3 V, IOH = –1 mA VCC = 5 V, IOH = –400 µA VCC = 5 V, IOH = –10 mA VCC = 5 V, IOH = –400 µA VCC = 3 V, IOH = –1 mA VCC = 5 V, IOH = –10 mA VCC = 5 V, IOH = –400 µA VCC = 3 V, IOH = –1 mA VCC = 5 V, IOL = 10 mA VCC = 3 V, IOL = 1 mA VCC = 5 V, IOL = 16 mA VCC = 3 V, IOL = 10 mA VCC = 5 V, IOL = 2 mA VCC = 5 V, IOL = 10 mA VCC = 5 V, IOL = 2 mA VCC = 3 V, IOL = 1 mA VCC = 5 V, IOL = 10 mA VCC = 5 V, IOL = 2 mA VCC = 3 V, IOL = 1 mA VCC = 5 V VCC = 3 V VCC = 5 V VCC = 3 V VCC = 5 V VCC = 3 V VCC = 5 V VCC = 3 V VCC = 5 V, VI = 5 V VCC = 3 V, VI = 3 V VCC = 5 V, VI = 0 V VCC = 3 V, VI = 0 V VI = 0 V, without a pull-up transistor VI = 0 V, with a pull-up transistor When clock is stopped. 0.7 0.5 0.4 0.4 0.26 0.4 0.26 VCC = 5 V VCC = 3 V VCC = 5 V VCC = 3 V –0.25 –0.08 –1.0 –0.35 V V V V µA µA µA mA V VOL VOL VOL VT+ – VT– VT+ – VT– VT+ – VT– VT+ – VT– IIH IIL IIL VRAM Low-level input current P54 – P57, P62 – P64 RAM hold voltage Limits Min. Typ. Max.

Notice: This is not a final specification. Some parametric limits are subject to change. MITSUBISHI MICROCOMPUTERS M37733EHLXXXHP PROM VERSION OF M37733MHLXXXHP VCC = 5 V, f(XIN) = 12 MHz (square waveform), (f(f2) = 6 MHz), f(XCIN) = 32.768 kHz, in operating (Note 1) VCC = 3 V, f(XIN) = 12 MHz (square waveform), (f(f2) = 6 MHz), f(XCIN) = 32.768 kHz, in operating (Note 1) VCC = 3 V, f(XIN) = 12 MHz (square waveform), (f(f2) = 0.75 MHz), f(XCIN) : Stopped, in operating VCC = 3 V, f(XIN) = 12 MHz (square waveform), f(XCIN) = 32.768 kHz, when a WIT instruction is executed (Note 2) VCC = 3 V, f(XIN) : Stopped, f(XCIN) = 32.768 kHz, in operating (Note 3) VCC = 3 V, f(XIN) : Stopped, f(XCIN) = 32.768 kHz, when a WIT instruction is executed (Note 4) Ta = 25 °C, when clock is stopped Ta = 85 °C, when clock is stopped mA mA mA µA µA µA µA µA Max. 0.8 Limits Typ. 4.5 0.4 UnitMin. Test conditionsSymbol Parameter ELECTRICAL CHARACTERISTICS (Vcc = 5 V, Vss = 0 V, Ta = –40 to +85 °C, unless otherwise noted) When single-chip mode, output pins are open, and other pins are VSS . Power source currentICC Limits Min. Typ. Max. — Resolution V REF = VCC 10 Bits — Absolute accuracy V REF = VCC ± 3 LSB R LADDER Ladder resistance V REF = VCC 10 25 k Ω tCONV Conversion time 19.6 s VREF Reference voltage 2.7 V CC V VIA Analog input voltage 0 V REF V Symbol Parameter Test conditions Unit A–D CONVERTER CHARACTERISTICS (VCC = AVCC = 5 V, VSS = AVSS = 0 V, Ta = –40 to +85 °C, f(XIN) = 12 MHz, unless otherwise noted (Note)) Note. This applies when the main clock division selection bit = “0” and f(f2) = 6 MHz. Notes 1. This applies when the main clock external input selection bit = “1”, the main clock division selection bit = “0”, and the signal output stop bit = “1”. 2. This applies when the main clock external input selection bit = “1” and the system clock stop bit at wait state = “1”. 3. This applies when CPU and the clock timer are operating with the sub clock (32.768 kHz) selected as the system clock. 4. This applies when the XCOUT drivability selection bit = “0” and the system clock stop bit at wait state = “1”. µ

PROM VERSION OF M37733MHLXXXHP PRELIMINARY Notice: This is not a final specification. Some parametric limits are subject to change. Limits Min. Max. tc External clock input cycle time (Note 1) 83 ns tw(H) External clock input high-level pulse width (Note 2) 33 ns tw(L) External clock input low-level pulse width (Note 2) 33 ns tr External clock rise time 15 ns tf External clock fall time 15 ns Limits Min. Max. tsu(D–E) Data input setup time 50 ns tsu(RDY– 1) ___ RDY input setup time 80 ns tsu(HOLD– 1) ____ HOLD input setup time 80 ns th(E–D) Data input hold time 0n s th( 1–RDY) ___ RDY input hold time 0n s th( 1–HOLD) ____ HOLD input hold time 0n s TIMING REQUIREMENTS (VCC = 2.7 – 5.5 V, VSS = 0 V, Ta = –40 to +85 °C, f(XIN) = 12 MHz, unless otherwise noted (Note 1)) Notes 1. This applies when the main clock division selection bit = “0” and f(f2) = 6 MHZ. 2. Input signal’s rise/fall time must be 100 ns or less, unless otherwise noted. External clock input UnitSymbol Parameter Notes 1. When the main clock division selection bit = “1”, the minimum value of tc = 166 ns. 2. When the main clock division selection bit = “1”, values of tw(H) / tc and tw(L) / tc must be set to values from 0.45 through 0.55. UnitSymbol Parameter Memory expansion mode and microprocessor mode Single-chip mode UnitSymbol Parameter Limits Min. Max. tsu(P0D–E) Port P0 input setup time 200 ns tsu(P1D–E) Port P1 input setup time 200 ns tsu(P2D–E) Port P2 input setup time 200 ns tsu(P3D–E) Port P3 input setup time 200 ns tsu(P4D–E) Port P4 input setup time 200 ns tsu(P5D–E) Port P5 input setup time 200 ns tsu(P6D–E) Port P6 input setup time 200 ns tsu(P7D–E) Port P7 input setup time 200 ns tsu(P8D–E) Port P8 input setup time 200 ns th(E–P0D) Port P0 input hold time 0n s th(E–P1D) Port P1 input hold time 0n s th(E–P2D) Port P2 input hold time 0n s th(E–P3D) Port P3 input hold time 0n s th(E–P4D) Port P4 input hold time 0n s th(E–P5D) Port P5 input hold time 0n s th(E–P6D) Port P6 input hold time 0n s th(E–P7D) Port P7 input hold time 0n s th(E–P8D) Port P8 input hold time 0n s

Notice: This is not a final specification. Some parametric limits are subject to change. MITSUBISHI MICROCOMPUTERS M37733EHLXXXHP PROM VERSION OF M37733MHLXXXHP Limits Min. Max. tc(TA) TAiIN input cycle time 250 ns tw(TAH) TAiIN input high-level pulse width 125 ns tw(TAL) TAiIN input low-level pulse width 125 ns UnitSymbol Parameter Timer A input (Count input in event counter mode) Limits Min. Max. tc(TA) TAiIN input cycle time (Note) 666 ns tw(TAH) TAiIN input high-level pulse width (Note) 333 ns tw(TAL) TAiIN input low-level pulse width (Note) 333 ns UnitSymbol Parameter Timer A input (Gating input in timer mode) Limits Min. Max. tc(TA) TAiIN input cycle time (Note) 666 ns tw(TAH) TAiIN input high-level pulse width 166 ns tw(TAL) TAiIN input low-level pulse width 166 ns UnitSymbol Parameter Timer A input (External trigger input in one-shot pulse mode) Limits Min. Max. tw(TAH) TAiIN input high-level pulse width 166 ns tw(TAL) TAiIN input low-level pulse width 166 ns UnitSymbol Parameter Timer A input (External trigger input in pulse width modulation mode) Limits Min. Max. tc(UP) TAiOUT input cycle time 3333 ns tw(UPH) TAiOUT input high-level pulse width 1666 ns tw(UPL) TAiOUT input low-level pulse width 1666 ns tsu(UP–TIN) TAiOUT input setup time 666 ns th(TIN–UP) TAiOUT input hold time 666 ns UnitSymbol Parameter Timer A input (Up-down input in event counter mode) Limits Min. Max. tc(TA) TAjIN input cycle time 2000 ns tsu(TAjIN–TAjOUT ) TAjIN input setup time 500 ns tsu(TAjOUT –TAjIN) TAjOUT input setup time 500 ns UnitSymbol Parameter Timer A input (Two-phase pulse input in event counter mode) Note. Limits change depending on f(XIN). Refer to “DATA FORMULAS” on page 20. Note. Limits change depending on f(XIN). Refer to “DATA FORMULAS” on page 20.

PROM VERSION OF M37733MHLXXXHP PRELIMINARY Notice: This is not a final specification. Some parametric limits are subject to change. Limits Min. Max. tc(CK) CLK i input cycle time 333 ns tw(CKH) CLK i input high-level pulse width 166 ns tw(CKL) CLK i input low-level pulse width 166 ns td(C–Q) TXD i output delay time 100 ns th(C–Q) TXD i hold time 0n s tsu(D–C) R XD i input setup time 65 ns th(C–D) R XD i input hold time 75 ns Limits Min. Max. tc(TB) TBiIN input cycle time (one edge count) 250 ns tw(TBH) TBiIN input high-level pulse width (one edge count) 125 ns tw(TBL) TBiIN input low-level pulse width (one edge count) 125 ns tc(TB) TBiIN input cycle time (both edges count) 500 ns tw(TBH) TBiIN input high-level pulse width (both edges count) 250 ns tw(TBL) TBiIN input low-level pulse width (both edges count) 250 ns UnitSymbol Parameter Timer B input (Count input in event counter mode) Limits Min. Max. tc(TB) TBiIN input cycle time (Note) 666 ns tw(TBH) TBiIN input high-level pulse width (Note) 333 ns tw(TBL) TBiIN input low-level pulse width (Note) 333 ns UnitSymbol Parameter Timer B input (Pulse period measurement mode) Limits Min. Max. tc(TB) TBiIN input cycle time (Note) 666 ns tw(TBH) TBiIN input high-level pulse width (Note) 333 ns tw(TBL) TBiIN input low-level pulse width (Note) 333 ns UnitSymbol Parameter Timer B input (Pulse width measurement mode) UnitSymbol Parameter A-D trigger input UnitSymbol Parameter Serial I/O UnitSymbol Parameter External interrupt INTi input, key input interrupt KIi input Limits Min. Max. tw(INH) ___ INTi input high-level pulse width 250 ns tw(INL) ___ INTi input low-level pulse width 250 ns tw(KIL) KIi input low-level pulse width 250 ns Limits Min. Max. tc(AD) ____ AD TRG input cycle time (minimum allowable trigger) 1333 ns tw(ADL) ____ AD TRG input low-level pulse width 166 ns Note. Limits change depending on f(XIN). Refer to “DATA FORMULAS” on page 20. Note. Limits change depending on f(XIN). Refer to “DATA FORMULAS” on page 20.

Notice: This is not a final specification. Some parametric limits are subject to change. MITSUBISHI MICROCOMPUTERS M37733EHLXXXHP PROM VERSION OF M37733MHLXXXHP DATA FORMULAS Timer A input (Gating input in timer mode) 8 5 109 2 · f(f2) 4 5 109 2 · f(f2) 4 5 109 2 · f(f2) Limits Min. Max.Symbol Parameter Unit tc(TA) TAiIN input cycle time tw(TAH) TAiIN input high-level pulse width tw (TAL ) TAi IN input low-level pulse width ns ns ns 8 5 109 2 · f(f2) Timer A input (External trigger input in one-shot pulse mode) Limits Min. Max.Symbol Parameter Unit tc(TA) TAiIN input cycle time ns Timer B input (In pulse period measurement mode or pulse width measurement mode) Limits Min. Max.Symbol Parameter Unit ns ns ns tc(TB) TBiIN input cycle time tw(TBH) TBiIN input high-level pulse width tw(TBL) TBiIN input low-level pulse width 8 5 109 2 · f(f2) 4 5 109 2 · f(f2) 4 5 109 2 · f(f2) Note. f(f2) represents the clock f2 frequency. For the relation to the main clock and sub clock, refer to Table 9 in data sheet “M37733MHBXXXFP”.

PROM VERSION OF M37733MHLXXXHP PRELIMINARY Notice: This is not a final specification. Some parametric limits are subject to change. SWITCHING CHARACTERISTICS (VCC = 2.7 – 5.5 V, VSS = 0 V, Ta = –40 to +85°C, f(XIN) = 12 MHz, unless otherwise noted (Note)) Fig. 6 Measuring circuit for ports P0 – P8 and φ1 Limits Min. Max. td(E–P0Q) Port P0 data output delay time 300 ns td(E–P1Q) Port P1 data output delay time 300 ns td(E–P2Q) Port P2 data output delay time 300 ns td(E–P3Q) Port P3 data output delay time 300 ns td(E–P4Q) Port P4 data output delay time 300 ns td(E–P5Q) Port P5 data output delay time 300 ns td(E–P6Q) Port P6 data output delay time 300 ns td(E–P7Q) Port P7 data output delay time 300 ns td(E–P8Q) Port P8 data output delay time 300 ns UnitSymbol Parameter Test conditions Fig. 6 Note. This applies when the main clock division selection bit = “0” and f(f2) = 6 MHz. Single-chip mode 50 pF P 0 P 1 P 2 P 3 P 4 P 5 P 6 P 7 P 8 f E

Notice: This is not a final specification. Some parametric limits are subject to change. MITSUBISHI MICROCOMPUTERS M37733EHLXXXHP PROM VERSION OF M37733MHLXXXHP Symbol Parameter td(E–DQ) th(E–DQ) Address output delay time Address output delay time Address hold time ALE pulse width Address output setup time Address hold time ALE output delay time Memory expansion mode and microprocessor mode (VCC = 2.7 – 5.5 V, VSS = 0 V, Ta = –40 to +85°C, f(XIN) = 12 MHz (Note 1), unless otherwise noted) Limits Wait mode Min. Max. Test conditions Unit 182 162 123 131 298 182 182 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns t d(An–E) td(A–E) td(ALE–E) th(E–An) tw(ALE) tsu(A–ALE) th(ALE–A) tw(EL) Data output delay time Data hold time E pulse width Floating start delay time Floating release delay time ___ BHE output delay time R/W output delay time ___ BHE hold time_ R/W hold time Fig. 6 (Note 2) φ1 output delay time tpxz(E–DZ) tpzx(E–DZ) td(BHE–E) td(R/W–E) th(E–BHE) th(E–R/W) td(E–φ 1) td(φ1–HLDA) ____ HLDA output delay time 03 0 120 Notes 1.This applies when the main clock division selection bit = “0” and f(f2) = 6 MHz. 2. No wait : Wait bit = “1”. Wait 1 : The external memory area is accessed with wait bit = “0” and wait selection bit = “1”. Wait 0 : The external memory area is accessed with wait bit = “0” and wait selection bit = “0”. No wait Wait 1 Wait 0 No wait Wait 1 Wait 0 No wait Wait 1 Wait 0 No wait Wait 1 Wait 0 No wait Wait 1 Wait 0 No wait Wait 1 Wait 0 No wait Wait 1 Wait 0 No wait Wait 1 Wait 0 No wait Wait 1 Wait 0

PROM VERSION OF M37733MHLXXXHP PRELIMINARY Notice: This is not a final specification. Some parametric limits are subject to change. Address output delay time Address output delay time Address hold time ALE pulse width Address output setup time Address hold time ALE output delay time Data output delay time Data hold time E pulse width Floating start delay time Floating release delay time No wait Wait 1 Wait 0 Memory expansion mode and microprocessor mode Bus timing data formulas (VCC = 2.7 – 5.5 V, VSS = 0 V, Ta = –40 to +85 °C, f(XIN) = 12 MHz (Max., Note 1), unless otherwise noted) 1 5 109 2 · f(f2) 3 5 109 2 · f(f2) 1 5 109 2 · f(f2) 3 5 109 2 · f(f2) 1 5 109 2 · f(f2) 1 5 109 2 · f(f2) 2 5 109 2 · f(f2) 1 5 109 2 · f(f2) 2 5 109 2 · f(f2) ns ns ns ns ns ns ns ns ns ns No wait Wait 1 Wait 0 No wait Wait 1 Wait 0 No wait Wait 1 Wait 0 No wait Wait 1 Wait 0 No wait Wait 1 Wait 0 No wait Wait 1 Wait 0 No wait Wait 1 Wait 0 1 5 109 2 · f(f2) ns ns ns ns ns ns 1 5 109 2 · f(f2) 1 5 109 2 · f(f2) 2 5 109 2 · f(f2) 4 5 109 2 · f(f2) ns ns 1 5 109 2 · f(f2) 1 5 109 2 · f(f2) 3 5 109 2 · f(f2) 1 5 109 2 · f(f2) 3 5 109 2 · f(f2) 1 5 109 2 · f(f2) 1 5 109 2 · f(f2) – 63 – 68 – 63 – 88 – 43 – 43 – 43 – 73 – 73 – 43 – 43 – 43 – 35 – 35 – 30 – 63 – 68 – 63 – 68 – 50 – 50 UnitSymbol Parameter Limits Wait mode Min. Max. td(An–E) td(A–E) th(E–An) tw(ALE) tsu(A–ALE) th(ALE–A) td(ALE–E) td(E–DQ) th(E–DQ) tw(EL) tpxz(E–DZ) tpzx(E–DZ) No wait Wait 1 Wait 0 ___ BHE output delay time R/W output delay time td(BHE–E) td(R/W–E) th(E–BHE) th(E–R/W) td(E–φ1) φ1 output delay time R/W hold time ___ BHE hold time 0 30 ns ns ns ns ns ns ns ns Notes 1.This applies when the main-clock division selection bit = “0”. 2. f(f 2) represents the clock f2 frequency. For the relation to the main clock and sub clock, refer to Table 9 in data sheet “M37733MHBXXXFP”.

Notice: This is not a final specification. Some parametric limits are subject to change. MITSUBISHI MICROCOMPUTERS M37733EHLXXXHP PROM VERSION OF M37733MHLXXXHP TIMING DIAGRAM tw(H) td(E–P0Q) td(E–P2Q) td(E–P3Q) td(E–P4Q) td(E–P5Q) td(E–P6Q) td(E–P7Q) td(E–P8Q) Port P0 output Port P0 input Port P1 output Port P1 input Port P2 output Port P2 input Port P3 output Port P3 input E XIN Port P4 output Port P4 input Port P5 output Port P5 input Port P6 output Port P6 input Port P7 output Port P7 input Port P8 output Port P8 input tsu(P0D–E) th(E–P0D) td(E–P1Q) tr tf tw(L) tc tsu(P1D–E) th(E–P1D) tsu(P2D–E) th(E–P2D) tsu(P3D–E) th(E–P3D) tsu(P4D–E) th(E–P4D) tsu(P5D–E) th(E–P5D) tsu(P6D–E) th(E–P6D) tsu(P7D–E) th(E–P7D) tsu(P8D–E) th(E–P8D)

PROM VERSION OF M37733MHLXXXHP PRELIMINARY Notice: This is not a final specification. Some parametric limits are subject to change. TAiIN input TAiOUT input tc(TA) tw(TAH) tw(TAL) tc(UP) tw(UPH) tw(UPL) th(TIN–UP) tsu(UP–TIN) TAiOUT input (Up-down input) TAiIN input (when count by falling) TAiIN input (when count by rising) In event counter mode TAjIN input TAjOUT input tc(TA) tsu(TAjIN–TAjOUT ) tsu(TAjIN–TAjOUT ) tsu(TAjOUT –TAjIN) tsu(TAjOUT –TAjIN) In event counter mode (When two-phase pulse input is selected) tc(TB) tw(TBH) tw(TBL) TBiIN input

Notice: This is not a final specification. Some parametric limits are subject to change. MITSUBISHI MICROCOMPUTERS M37733EHLXXXHP PROM VERSION OF M37733MHLXXXHP tc(AD) tw(ADL) tc(CK) tw(CKH) tw(CKL) tw(INL) tw(KNL) td(C–Q) tsu(D–C) th(C–D) tw(INH) AD TRG input CLK i TxD i RxD i INTi input Kli input th(C–Q)

PROM VERSION OF M37733MHLXXXHP PRELIMINARY Notice: This is not a final specification. Some parametric limits are subject to change. Memory expansion mode and microprocessor mode (When wait bit = “1”) ( When wait bit = “0”) (When wait bit = “1” or “0” in common) Test conditions

  • Input timing voltage : VIL = 0.2 VCC , VIH = 0.8 VCC
  • Output timing voltage : VOL = 0.8 V, VOH = 2.0 V RDY input E RDY input HOLD input HLDA output tsu(RDY– f1) th(f1–RDY) tsu(RDY– f1) th(f1–RDY) tsu(HOLD– f1) td(f1–HLDA) th(f1–HOLD) td(f1–HLDA) E

Notice: This is not a final specification. Some parametric limits are subject to change. MITSUBISHI MICROCOMPUTERS M37733EHLXXXHP PROM VERSION OF M37733MHLXXXHP td(E-φ1) td(An-E) tw(ALE) td(ALE-E) tsu(A-ALE) td(A-E) td(E-DQ) th(ALE-A) td(BHE-E) th(E-BHE) td(R/W-E) th(E-R/W) th(E-DQ) tpxz(E-DZ) tsu(D-E) th(E-D) tpzx(E-DZ) th(E-An) td(E-φ1) tw(EL) tw(H) E An ALE Am/Dm Dm IN BHE R/W Address Address Address Data Data Address Address Address tf tr tctw(L) Memory expansion mode and microprocessor mode (No wait : When wait bit = “1”) Test conditions VCC = 2.7 – 5.5 V Output timing voltage : VOL = 0.8 V, VOH = 2.0 V Data input DmIN : VIL = 0.16 VCC , VIH = 0.5 VCC XIN

PROM VERSION OF M37733MHLXXXHP PRELIMINARY Notice: This is not a final specification. Some parametric limits are subject to change. tw(ALE) tc Address tw(L) tw(H) tf tr Memory expansion mode and microprocessor mode (Wait 1 : The external memory area is accessed when wait bit = “0” and wait selection bit = “1”.) Address Address td(E–f1) td(An–E) td(ALE–E) tsu(A–ALE) th(ALE–A) td(A–E) td(E–DQ) th(E–D) tpzx(E–DZ) th(E–BHE) tsu(D–E) Test conditions

  • Output timing voltage : VOL = 0.8 V, VOH = 2.0 V
  • Data input DmIN : VIL = 0.16 Vcc, VIH = 0.5 Vcc Data Address Data td(E–f1) Address tpxz(E–DZ) tw(EL) th(E–An) th(E–DQ) th(E–R/W)td(R/W–E) td(BHE–E) XIN E An ALE Am/Dm Dm IN BHE R /W

Notice: This is not a final specification. Some parametric limits are subject to change. MITSUBISHI MICROCOMPUTERS M37733EHLXXXHP PROM VERSION OF M37733MHLXXXHP th(ALE–A) td(ALE–E) td(E–DQ) tw(L) tw(H) tf tctr Memory expansion mode and microprocessor mode (Wait 0 : The external memory area is accessed when wait bit = “0” and wait selection bit = “0”.) XIN Address Address Address Address Data An ALE Am/Dm Dm IN R /W td(An–E) tw(ALE) tsu(A–ALE) th(E–DQ) td(A–E) tpxz(E–DZ) tpzx(E–DZ) th(E–D)tsu(D–E) AddressDataAddress Test conditions

  • Output timing voltage : VOL = 0.8 V, VOH = 2.0 V
  • Data input DmIN : VIL = 0.16 Vcc, VIH = 0.5 Vcc td(E–f1) td(E–f1) td(R/W–E) th(E–R/W) tw(EL) th(E–An) td(BHE–E) th(E–BHE) E BHE

PROM VERSION OF M37733MHLXXXHP PRELIMINARY Notice: This is not a final specification. Some parametric limits are subject to change. PACKAGE OUTLINE

Notice: This is not a final specification. Some parametric limits are subject to change. MITSUBISHI MICROCOMPUTERS M37733EHLXXXHP PROM VERSION OF M37733MHLXXXHP

7700 FAMILY WRITING TO PROM ORDER CONFIRMATION FORM

SINGLE-CHIP 16-BIT MICROCOMPUTER M37733EHLXXXHP MITSUBISHI ELECTRIC Date: Receipt GZZ–SH00–42B<68A0> ( ) Note : Please fill in all items marked Customer ROM number SupervisorCompany name Date issued Date: TEL 1. Confirmation Specify the name of the product being ordered and the type of EPROMs submitted. Three sets of EPROMs are required for each pattern. If at least two of the three sets of EPROMs submitted contain the identical data, we will produce writing to PROM based on this data. We shall assume the responsibility for errors only if the written PROM data on the products we produce differ from this data. Thus, the customer must be especially careful in verifying the data contained in the EPROMs submitted. Checksum code for entire EPROM areas EPROM Type : 2. Mark specification Mark specification must be submitted using the correct form for the type of package being ordered fill out the appropriate 80P6D Mark Specification Form (for M37733EHLXXXHP) and attach to the Writing to PROM Order Confirmation Form. (1) Set “FF16” in the shaded area. (2) Address 016 to 0F16 are the area for storing the data on model designation.This area must be written with the data shown below. Address and data are written in hexadecimal notation. 3. Comments F A E C B (hexadecimal notation) 27C201 128K 3FFFF DATA Address Address D Responsible officer Section head signature Supervisor signature Issuance signatures FF FF FF FF FF FF FF 00010 20000 00000

PROM VERSION OF M37733MHLXXXHP PRELIMINARY Notice: This is not a final specification. Some parametric limits are subject to change.

© 1996 MITSUBISHI ELECTRIC CORP. H-LF447-A KI-9610 Printed in Japan (ROD) 2 New publication, effective Oct. 1996. Specifications subject to change without notice. Notes regarding these materials ¡ These materials are intended as a reference to assist our customers in the selection of the Mitsubishi semiconductor product best suited to the customer’s application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Mitsubishi Electric Corporation or a third party. ¡ Mitsubishi Electric Corporation assumes no responsibility for any damage, or infringement of any third-party’s rights, originating in the use of any product data, diagrams, charts or circuit application examples contained in these materials. ¡ All information contained in these materials, including product data, diagrams and charts, represent information on products at the time of publication of these materials, and are subject to change by Mitsubishi Electric Corporation without notice due to product improvements or other reasons. It is therefore recommended that customers contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for the latest product information before purchasing a product listed herein. ¡ Mitsubishi Electric Corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. ¡ The prior written approval of Mitsubishi Electric Corporation is necessary to reprint or reproduce in whole or in part these materials. ¡ If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. ¡ Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for further details on these materials or the products contained therein. Keep safety first in your circuit designs! ¡ Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non-flammable material or (iii) prevention against any malfunction or mishap. MITSUBISHI MICROCOMPUTERS M37733EHLXXXHP PROM VERSION OF M37733MHLXXXHP PRELIMINARY Notice: This is not a final specification. Some parametric limits are subject to change.

(TOP VIEW) Fig. 5 P13 Right column Line 2 Line 10 P17 Memory expan- sion mode and microprocessor mode Rev. Rev. No. date

1.00 First Edition 970604

1.01 The following are added: 980421

  • PROM ORDER CONFIRMATION FORM
  • MARK SPECIFICATION FORM

2.00 The following are revised: 980731

REVISION DESCRIPTION LIST M37733EHLXXXHP Datasheet (1) Revision Description Previous Version Outline 80P6D-A The M37733EHLXXXHP has 28 powerful addressing modes. Refer to the MITSUBISHI SEMICONDUCTORS DATA BOOK SINGLE- CHIP 16-BIT MICROCOMPUTERS for the details of each addressing mode. MACHINE INSTRUCTION LIST The M37733EHLXXXHP has 103 machine instructions. Refer to the MITSUBISHI SEMICONDUCTORS DATA BOOK SINGLE- CHIP 16-BIT MICROCOMPUTERS for details. Revised Version Outline 80P6D-A, 80P6Q-A The M37733EHLXXXHP has 28 powerful addressing modes. Refer to the “7700 Family Software Manual” for the details. MACHINE INSTRUCTION LIST The M37733EHLXXXHP has 103 machine instructions. Refer to the “7700 Family Software Manual” for the details. Previous Version Revised Version Symbol Parameter Limits Unit Min. Max. tsu(D–E) Data input setup time 80 ns Symbol Parameter Limits UnitMin. Max. tsu(D–E) Data input setup time 50 ns (2) 80P6D mark specification form (2) 80P6D, 80P6Q mark specification form