M37702S1LGP

Mitsubishi Electric Sem...

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Manufacturer: Mitsubishi Electric Sem...

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M37702M2LXXXGP, M37702S1LGP M37702M2LXXXHP, M37702S1LHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

DESCRIPTION

The M37702M2LXXXGP is a single-chip 16-bit microcomputer designed with high-performance CMOS silicon gate technology. This is housed in a small 80-pin plastic molded QFP . This single- chip microcomputer has a large 16 M bytes address space, three instruction queue buffers, and two data buffers for high-speed in- struction execution. The CPU is a 16-bit parallel processor that can also be switched to perform 8-bit parallel processing. This microcomputer is suitable for communication, office, business and industrial equipment controller that require high-speed processing of large data. The strong points of the M37702M2LXXXGP , M37702S1LGP , M37702M2LXXXHP and M37702S1LHP are the low supply voltage and small package. The differences between M37702M2LXXXGP , M37702S1LGP , M37702M2LXXXHP and M37702S1LHP are the ROM size and the package as shown below. Therefore, the following descriptions will be for the M37702M2LXXXGP unless otherwise noted.

FEATURES

Instruction execution time
Low power dissipation
12-bit watchdog timer
Programmable input/output
Small package M37702M2LXXXGP , M37702S1LGP M37702M2LXXXHP , M37702S1LHP Package 80-pin plastic molded QFP (80P6S-A) 80-pin plastic molded QFP (80P6S-A) 80-pin plastic molded fine-pitch QFP (80P6D-A) 80-pin plastic molded fine-pitch QFP (80P6D-A) Type name M37702M2LXXXGP M37702S1LGP M37702M2LXXXHP M37702S1LHP ROM size

16 K bytes

Control devices for communication equipment such as cellular ra- dio telephones, cordless telephones, and radio communications Control devices for office equipment such as copiers, printers, typewriters, facsimiles, word processors, and personal computers Control devices for industrial equipments such as ME, NC, and measuring instruments NOTE Refer to “Chapter 5 PRECAUTIONS” when using this microcom- puter.

M37702M2LXXXGP, M37702S1LGP M37702M2LXXXHP, M37702S1LHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER PIN CONFIGURATION (TOP VIEW) P86/RXD 1 P87/TXD 1 P00/A0 P01/A1 P02/A2 P03/A3 P04/A4 P05/A5 P06/A6 P07/A7 P10/A8/D8 P11/A9/D9 P12/A10/D10 P13/A11/D11 P14/A12/D12 P15/A13/D13 P16/A14/D14 P17/A15/D15 P20/A16/D0 P21/A17/D1 P66/TB1IN P65/TB0IN P64/INT 2 P63/INT 1 P62/INT 0 P61/TA4IN P60/TA4OUT P57/TA3IN P56/TA3OUT P55/TA2IN P54/TA2OUT P53/TA1IN P52/TA1OUT P51/TA0IN P50/TA0OUT P47/DBC ] P46/VPA] Outline M37702M2LXXXGP, M37702S1LGP••••••80P6S-A M37702M2LXXXHP, M37702S1LHP••••••80P6D-A P45/VDA] P44/QCL] P43/MX] ] : Used in the evaluation chip mode only P74/AN4 P73/AN3 P70/AN0 P67/TB2IN P75/AN5 P76/AN6 P77/AN7/ADTRG VSS AV SS VREF AV CC VCC P81/CLK0 P83/TXD 0 P85/CLK1 P31/BHE Vss P32/ALE P33/HLDA P30/R/W P27/A23/D7 P26/A22/D6 P25/A21/D5 P24/A20/D4 P23/A19/D3 P22/A18/D2 P42/f1 P41/RDY E P40/HOLD RESET XOUT CNV SS BYTE XIN P84/CTS1/RTS1 P82/RXD 0 P80/CTS0/RTS0 P72/AN2 P71/AN1 M37702M2LXXXGP or M37702S1LGP or M37702M2LXXXHP or M37702S1LHP

M37702M2LXXXGP, M37702S1LGP M37702M2LXXXHP, M37702S1LHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER M37702M2LXXXGP BLOCK DIAGRAM XIN XOUT E RESET Reset input VREF CNVss BYTE P0(8) UART1(9) UART0(9) AV SS (0V) AV CC (0V) VSSVCC A-D Converter(8) Clock inputClock output Enable output Reference voltage input Bus width selection input Clock Generating Circuit Instruction Register(8) Arithmetic Logic Unit(16) Accumulator A(16) Accumulator B(16) Index Register X(16) Index Register Y(16) Stack Pointer S(16) Direct Page Register DPR(16) Processor Status Register PS(11) Input Buffer Register IB(16) Data Bank Register DT(8) Program Bank Register PG(8) Program Counter PC(16) Incrementer/Decrementer(24) Data Address Register DA(24) Program Address Register PA(24) Incrementer(24) Instruction Queue Buffer Q2(8) Instruction Queue Buffer Q1(8) Instruction Queue Buffer Q0(8) Data Buffer DBL(8) Data Buffer DBH (8) ROM 16K Bytes RAM

512 Bytes

Timer TA3(16) Timer TA4(16) Timer TA2(16) Timer TA1(16) Timer TA0(16) Watchdog Timer Timer TB2(16) Timer TB1(16) Timer TB0(16) Address Bus Data Bus(Odd) Data Bus(Even) Input/Output port P8 Input/Output port P7 Input/Output port P6 Input/Output port P5 Input/Output port P4 Input/Output port P3 Input/Output port P2 Input/Output port P1 Input/Output port P0 27 28 29 26 67 30 71 25 (5V) (0V) 70 68 (5V) 69 24 58575655545352515049484746454443424140393837363523222120191817161514131211109876543218079787776757473726665646362616059 34333231

M37702M2LXXXGP, M37702S1LGP M37702M2LXXXHP, M37702S1LHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FUNCTIONS OF M37702M2LXXXGP Parameter Number of basic instructions Instruction execution time Memory size Input/Output ports Multi-function timers Serial I/O A-D converter Watchdog timer Interrupts Clock generating circuit Supply voltage Power dissipation Input/Output characteristic Memory expansion Operating temperature range Device structure Package Functions 103 500 ns (the fastest instruction at external clock 8 MHz frequency) (UART or clock synchronous serial I/O) 5 2 8-bit 5 1 (8 channels) 12-bit 5 1 3 external types, 16 internal types (Each interrupt can be set the priority levels to 0 – 7.) Built-in (externally connected to a ceramic resonator or quartz crystal resonator) 2.7 – 5.5 V 12 mW (at 3 V supply voltage, external clock 8 MHz frequency) 30 mW (at 5 V supply voltage, external clock 8 MHz frequency) 5 V 5 mA Maximum 16 M bytes –40 – 85°C CMOS high-performance silicon gate process 80-pin plastic molded QFP (80P6S-A: 0.65 mm lead pitch) 80-pin plastic molded fine-pitch QFP (80P6D-A: 0.5 mm lead pitch) ROM RAM P0 – P2, P4 – P8 TA0, TA1, TA2, TA3, TA4 TB0, TB1, TB2 Input/Output voltage Output current M37702M2LXXXGP , M37702S1LGP M37702M2LXXXHP , M37702S1LHP

M37702M2LXXXGP, M37702S1LGP M37702M2LXXXHP, M37702S1LHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Name Power supply CNV SS input Reset input Clock input Clock output Enable output Bus width selection input Analog supply input Reference voltage input I/O port P0 I/O port P1 I/O port P2 I/O port P3 I/O port P4 I/O port P5 I/O port P6 I/O port P7 I/O port P8 PIN DESCRIPTION Pin VCC , VSS CNV SS RESET XIN XOUT E BYTE AV CC , AV SS VREF P00 – P07 P10 – P17 P20 – P27 P30 – P33 P40 – P47 P50 – P57 P60 – P67 P70 – P77 P80 – P87 Functions Supply 2.7 – 5.5 V to VCC and 0 V to VSS . This pin controls the processor mode. Connect to VSS for single-chip mode, and to VCC for external ROM types. To enter the reset state, this pin must be kept at a “L ” condition which should be maintained for the required time. These are I/O pins of internal clock generating circuit. Connect a ceramic or quartz crystal resonator between XIN and XOUT . When an external clock is used, the clock source should be connected to the XIN pin and the XOUT pin should be left open. Data or instruction read and data write are performed when output from this pin is “L”. In memory expansion mode or microprocessor mode, this pin determines whether the external data bus is 8-bit width or 16-bit width. The width is 16 bits when “L” signal inputs and 8 bits when “H” signal inputs. Power supply for the A-D converter. Connect AVCC to VCC and AVSS to VSS externally. This is reference voltage input pin for the A-D converter. In single-chip mode, port P0 becomes an 8-bit I/O port. An I/O direction register is available so that each pin can be programmed for input or output. These ports are in input mode when reset. Address (A 7 – A0) is output in memory expansion mode or microprocessor mode. In single-chip mode, these pins have the same functions as port P0. When the BYTE pin is set to “L” in memory expansion mode or microprocessor mode and external data bus is 16-bit width, high-order data (D15 – D8) is input or output__ when E output is “L” and an address (A15 – A8) is output when E output is “H”. If the BYTE pin is “H” that is an external data bus is 8-bit width, only address (A15 – A8) is output. In single-chip mode, these pins have the same functions as port P0. In memory expansion mode or microprocessor mode low-order data (D7 – D0) is input or__ output when E output is “L ” and an address (A23 – A16) is output when E output is “H”. In single-chip mode, these pins have the same functions as port P0. In memory__ ____ _____ expansion mode or microprocessor mode, R/W, BHE, ALE and HLDA signals are output. In single-chip mode, these pins have the same functions as port P0. In memory_____ ____ expansion mode or microprocessor mode, P40 and P41 become HOLD and RDY input pin respectively. Functions of other pins are the same as in single-chip mode. In single-chip mode or memory expansion mode, port P42 can be pro- grammed for φ1 output pin divided the clock to XIN pin by 2. In microprocessor mode. P42 always has the function as φ1 output pin. In addition to having the same functions as port P0 in single-chip mode, these pins also function as I/O pins for timer A0, timer A1, timer A2 and timer A3. In addition to having the same functions as port P0 in single-chip mode, these____ ____ pins also function as I/O pins for timer A4, external interrupt input INT0, INT1 and____ INT2 pins, and input pins for timer B0, timer B1 and timer B2. In addition to having the same functions as port P0 in single-chip mode, these pins also function as analog input AN0 – AN7 input pins. P77 also has an A-D conversion trigger input function. In addition to having the same functions as port P0 in single-chip mode, these____ ____ pins also function as RXD, TXD, CLK, CTS/RTS pins for UART 0 and UART 1. Input/Output Input Input Input Output Output Input Input I/O I/O I/O I/O I/O I/O I/O I/O I/O

M37702M2LXXXGP, M37702S1LGP M37702M2LXXXHP, M37702S1LHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER MEMORY The memory map is shown in Figure 3. ADDRESSING MODES The M37702M2LXXXGP has 28 powerful addressing modes. Refer to the 7700 Family addressing mode description for the de- tails of each addressing mode. MACHINE INSTRUCTION LIST The M37702M2LXXXGP has 103 machine instructions. Refer to the 7700 Family machine instruction list for details. DATA REQUIRED FOR MASK ORDERING Please send the following data for mask orders. M37702M2LXXXGP; (1) M37702M2LXXXGP mask ROM order confirmation form (2) 80P6S mark specification form (3) ROM data (EPROM 3 sets) M37702M2LXXXHP; (1) M37702M2LXXXHP mask ROM order confirmation form (2) 80P6D mark specification form (3) ROM data (EPROM 3 sets) Fig. 2 Example of a reset circuit (perform careful evaluation at the system design level before using) Fig. 3 Memory map VCCRESET 2.7V 0.55V Power on M37702M2LXXXGP 6726 VCC RESET A-D conversion Timer B2 Timer B1 Timer B0 Timer A4 Timer A3 Timer A2 Timer A1 Timer A0 INT2 INT0 Watchdog timer DBC BRK instruction Zero divide RESET Peripheral devices control registers Interrupt vector table 00000016 00FFFF 16 01000016 01FFFF 16 Bank 016 Bank 116 FE0000 16 FEFFFF 16 FF000016 FFFFFF 16 Bank FF16 Bank FE16 00FFFF 16 00FFD6 16 00027F16 00000016 00007F16 00008016 Internal RAM 512 bytes 00FFFE 16 00FFD6 16 00007F16 00000016 UART1 transmission UART1 receive UART0 transmission UART0 receive INT1 00C000 16 Internal ROM 16K bytes

M37702M2LXXXGP, M37702S1LGP M37702M2LXXXHP, M37702S1LHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER ABSOLUTE MAXIMUM RATINGS VCC AV CC VI VI VO Pd Topr Tstg Supply voltage Analog supply voltage Input voltage RESET, CNV SS , BYTE Input voltage P00–P0 7, P10–P17, P20–P2 7, P30–P3 3, P40–P4 7, P50–P5 7, P60–P67, P70–P7 7, P80–P87, VREF , XIN Output voltage P00–P0 7, P10–P17, P20–P2 7, P30–P3 3, P40–P4 7, P50–P5 7, P60–P67, P70–P7 7,_ P80–P87, XOUT , E Power dissipation Operating temperature Storage temperature T a = 25 °C RatingsSymbol Parameter Conditions Unit –0.3 to 7 –0.3 to 7 –0.3 to 12 –0.3 to VCC +0.3 –0.3 to VCC +0.3 300 (Note 1) –40 to 85 –65 to 150 V V V V V mW VCC AV CC VSS AV SS VIH VIH VIH VIL VIL VIL IOH(peak) IOH(avg) IOL(peak) IOL(avg) f(XIN) Supply voltage Analog supply voltage Supply voltage Analog supply voltage High-level input voltage P0 P60–P6 7, P70–P7 7, P80–P87, XIN, RESET , CNV SS , BYTE High-level input voltage P1 0–P1 7, P20–P27 (in single-chip mode) High-level input voltage P1 0–P1 7, P20–P27 (in memory expansion mode and micro- processor mode) Low-level input voltage P0 0–P0 7, P30–P33, P40–P4 7, P50–P5 7,______ P60–P6 7, P70–P7 7, P80–P87, XIN, RESET , CNV SS , BYTE Low-level input voltage P1 0–P1 7, P20–P27 (in single-chip mode) Low-level input voltage P1 0–P1 7, P20–P27 (in memory expansion mode and micro- processor mode) High-level peak output current P00–P0 7, P10–P17, P20–P2 7, P30–P3 3, P40–P4 7, P50–P5 7, P60–P67, P70–P7 7, P80–P8 7 High-level average output current P00–P0 7, P10–P17, P20–P2 7, P30–P3 3, P40–P4 7, P50–P5 7, P60–P67, P70–P7 7, P80–P8 7 Low-level peak output current P00–P0 7, P10–P17, P20–P2 7, P30–P3 3, P40–P4 7, P50–P5 7, P60–P67, P70–P7 7, P80–P8 7 Low-level average output current P00–P0 7, P10–P17, P20–P2 7, P30–P3 3, P40–P4 7, P50–P5 7, P60–P67, P70–P7 7, P80–P8 7 External clock frequency input LimitsSymbol Parameter Unit Min. 2.7 0.8VCC 0.8VCC 0.5VCC Typ. VCC Max. 5.5 VCC VCC VCC 0.2VCC 0.2VCC 0.16VCC –10 V V V V V V V V V V mA mA mA mA MHz RECOMMENDED OPERATING CONDITIONS (VCC = 2.7 to 5.5 V, Ta = –40 to 85 °C, unless otherwise noted) Note 2.Average output current is the average value of a 100 ms interval. 3.The sum of IOL(peak) for ports P0, P1, P2, P3, and P8 must be 80 mA or less, the sum of IOH(peak) for ports P0, P1, P2, P3, and P8 must be 80 mA or less, the sum of IOL(peak) for ports P4, P5, P6, and P7 must be 80 mA or less, and the sum of IOH(peak) for ports P4, P5, P6, and P7 must be 80 mA or less. Note 1. In the case of M37702M2LXXXHP and M37702S1LHP , the rating of power dissipation is 200 mW.

M37702M2LXXXGP, M37702S1LGP M37702M2LXXXHP, M37702S1LHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER In single- chip mode output only pin is open and other pins are VSS during reset. VOH VOH VOH VOH VOL VOL VOL VOL VT+ – VT– VT+ – VT– VT+ – VT– IIH IIL VRAM ICC High-level output voltage P00–P0 7, P10–P1 7, P20–P2 7, P30, P31, P33, P40–P4 7, P50–P5 7, P60–P6 7, P70–P7 7, P80–P8 7 High-level output voltage P00–P0 7, P10–P1 7, P20–P2 7, P30, P31, P33 High-level output voltage P32 High-level output voltage E Low-level output voltage P00–P0 7, P10–P1 7, P20–P2 7, P30, P31, P33, P40–P4 7, P50–P5 7, P60–P6 7, P70–P7 7, P80–P8 7 Low-level output voltage P00–P0 7, P10–P1 7, P20–P2 7, P30, P31, P33 Low-level output voltage P32 Low-level output voltage E Hysteresis INT0–INT2, ADTRG , CTS0, CTS1, CLK0, CLK1 Hysteresis RESET Hysteresis XIN High-level input current P00–P0 7, P10–P1 7, P20–P2 7, P30–P3 3, P40–P4 7, P50–P5 7, XIN, RESET, CNVSS , BYTE Low-level input current P00–P0 7, P10–P1 7, P20–P2 7, P30–P3 3, P40–P4 7, P50–P5 7, XIN, RESET, CNVSS , BYTE RAM hold voltage Power supply current VCC = 5 V, IOH = –10 mA LimitsSymbol Parameter Test conditions Unit Min. Typ. Max. 3.1 4.8 2.6 3.4 4.8 2.6 ELECTRICAL CHARACTERISTICS (VCC = 5 V, VSS = 0 V , Ta = 25 °C, f(XIN) = 8 MHz, unless otherwise noted) LimitsSymbol Parameter Test conditions Unit R LADDER tCONV VREF VIA Resolution Absolute accuracy Ladder resistance Conversion time Reference voltage Analog input voltage Min. Typ. Max. 28.5 2.7 VCC VREF Bits LSB kΩ µs V V VREF = VCC VREF = VCC VREF = VCC A-D CONVERTER CHARACTERISTICS (VCC = 5 V, VSS = 0 V, Ta = 25 °C, f(XIN) = 8 MHz, unless otherwise noted) Ta = 25 °C when clock is stopped. Ta = 85 °C when clock is stopped. f(XIN) = 8 MHz, square waveform VCC = 5 V VCC = 3 V VCC = 3 V, IOH = –1 mA VCC = 5 V , IOH = –400 µA VCC = 5 V, IOH = –10 mA VCC = 5 V , IOH = –400 µA VCC = 3 V, IOH = –1 mA VCC = 5 V, IOH = –10 mA VCC = 5 V , IOH = –400 µA VCC = 3 V, IOH = –1 mA VCC = 5 V, IOL = 10 mA VCC = 3 V, IOL = 1 mA VCC = 5 V, IOL = 10 mA VCC = 5 V, IOL = 2 mA VCC = 3 V, IOL = 1 mA VCC = 5 V, IOL = 10 mA VCC = 5 V, IOL = 2 mA VCC = 3 V, IOL = 1 mA VCC = 5 V VCC = 3 V VCC = 5 V VCC = 3 V VCC = 5 V VCC = 3 V VCC = 5 V, IOL = 2 mA VCC = 5 V, VI = 5 V VCC = 3 V, VI = 3 V VCC = 5 V, VI = 0 V VCC = 3 V, VI = 0 V When clock is stopped. 0.4 0.1 0.2 0.1 0.1 0.06 2.5 4.7 0.5 0.45 1.9 0.43 0.4 1.6 0.4 0.4 0.7 0.5 0.4 0.3 0.2 V V V V V V V V V V V µA µA mA µA V

M37702M2LXXXGP, M37702S1LGP M37702M2LXXXHP, M37702S1LHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER TIMING REQUIREMENTS (VCC = 2.7 to 5.5 V , VSS = 0 V, Ta = 25 °C, f(XIN) = 8 MHz, unless otherwise noted) LimitsSymbol Parameter Unit tC tW(H) tW(L) tr tf External clock input cycle time External clock input high-level pulse width External clock input low-level pulse width External clock rise time External clock fall time ns ns ns ns ns External clock input Min. 125 Max. LimitsSymbol Parameter Unit tsu(P0D–E) tsu(P1D–E) tsu(P2D–E) tsu(P3D–E) tsu(P4D–E) tsu(P5D–E) tsu(P6D–E) tsu(P7D–E) tsu(P8D–E) th(E–P0D) th(E–P1D) th(E–P2D) th(E–P3D) th(E–P4D) th(E–P5D) th(E–P6D) th(E–P7D) th(E–P8D) Port P0 input setup time Port P1 input setup time Port P2 input setup time Port P3 input setup time Port P4 input setup time Port P5 input setup time Port P6 input setup time Port P7 input setup time Port P8 input setup time Port P0 input hold time Port P1 input hold time Port P2 input hold time Port P3 input hold time Port P4 input hold time Port P5 input hold time Port P6 input hold time Port P7 input hold time Port P8 input hold time ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Single-chip mode Min. 300 300 300 300 300 300 300 300 300 Max. LimitsSymbol Parameter Unit tsu(P1D–E) tsu(P2D–E) tsu(RDY– φ1) tsu(HOLD– φ1) th(E–P1D) th(E–P2D) th(φ1–RDY) th(φ1–HOLD) Port P1 input setup time Port P2 input setup time ____ RDY input setup time HOLD input setup time Port P1 input hold time Port P2 input hold time ____ RDY input hold time HOLD input hold time ns ns ns ns ns ns ns ns Memory expansion mode and microprocessor mode Min. Max.

M37702M2LXXXGP, M37702S1LGP M37702M2LXXXHP, M37702S1LHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER LimitsSymbol Parameter Unit tC(TA) tW(TAH) tW(TAL) TAiIN input cycle time TAiIN input high-level pulse width TAiIN input low-level pulse width ns ns ns Timer A input (Count input in event counter mode) Min. 250 125 125 Max. LimitsSymbol Parameter Unit tC(TA) tW(TAH) tW(TAL) TAiIN input cycle time TAiIN input high-level pulse width TAiIN input low-level pulse width ns ns ns Timer A input (Gating input in timer mode) Min. 1000 500 500 Max. LimitsSymbol Parameter Unit tC(TA) tW(TAH) tW(TAL) TAiIN input cycle time TAiIN input high-level pulse width TAiIN input low-level pulse width ns ns ns Timer A input (External trigger input in one-shot pulse mode) Min. 500 250 250 Max. LimitsSymbol Parameter Unit tW(TAH) tW(TAL) TAiIN input high-level pulse width TAiIN input low-level pulse width ns ns Timer A input (External trigger input in pulse width modulation mode) Min. 250 250 Max.LimitsSymbol Parameter Unit tC(UP) tW(UPH) tW(UPL) tsu(UP-TIN) th(TIN-UP) TAiOUT input cycle time TAiOUT input high-level pulse width TAiOUT input low-level pulse width TAiOUT input setup time TAiOUT input hold time ns ns ns ns ns Timer A input (Up-down input in event counter mode) Min. 5000 2500 2500 1000 1000 Max.

M37702M2LXXXGP, M37702S1LGP M37702M2LXXXHP, M37702S1LHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER LimitsSymbol Parameter Unit tC(TB) tW(TBH) tW(TBL) tC(TB) tW(TBH) tW(TBL) TBiIN input cycle time (one edge count) TBiIN input high-level pulse width (one edge count) TBiIN input low-level pulse width (one edge count) TBiIN input cycle time (both edges count) TBiIN input high-level pulse width (both edges count) TBiIN input low-level pulse width (both edges count) ns ns ns ns ns ns Timer B input (Count input in event counter mode) Min. 250 125 125 500 250 250 Max. LimitsSymbol Parameter Unit tC(TB) tW(TBH) tW(TBL) TBiIN input cycle time TBiIN input high-level pulse width TBiIN input low-level pulse width ns ns ns Timer B input (Pulse period measurement mode) Min. 1000 500 500 Max. LimitsSymbol Parameter Unit tC(TB) tW(TBH) tW(TBL) TBiIN input cycle time TBiIN input high-level pulse width TBiIN input low-level pulse width ns ns ns Timer B input (Pulse width measurement mode) Min. 1000 500 500 Max. LimitsSymbol Parameter Unit tC(AD) tW(ADL) ns ns A-D trigger input Min. 2000 250 Max. LimitsSymbol Parameter Unit tC(CK) tW(CKH) tW(CKL) td(C–Q) th(C–Q) tsu(D–C) th(C–D) CLK i input cycle time CLK i input high-level pulse width CLK i input low-level pulse width TxD i output delay time TxD i hold time RxD i input setup time RxD i input hold time ns ns ns Serial I/O Min. 500 250 250 100 Max. 170 LimitsSymbol Parameter Unit tW(INH) tW(INL) ____ INTi input high-level pulse width ____ INTi input low-level pulse width ns ns External interrupt INTi input Min. 250 250 Max. AD TRG input cycle time (minimum allowable trigger) AD TRG input low-level pulse width ns ns ns ns

M37702M2LXXXGP, M37702S1LGP M37702M2LXXXHP, M37702S1LHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER LimitsSymbol Parameter Unit td(E–P0Q) td(E–P1Q) td(E–P2Q) td(E–P3Q) td(E–P4Q) td(E–P5Q) td(E–P6Q) td(E–P7Q) td(E–P8Q) Port P0 data output delay time Port P1 data output delay time Port P2 data output delay time Port P3 data output delay time Port P4 data output delay time Port P5 data output delay time Port P6 data output delay time Port P7 data output delay time Port P8 data output delay time ns ns ns ns ns ns ns ns ns Single-chip mode Min. Max. 300 300 300 300 300 300 300 300 300 LimitsSymbol Parameter Unit td(P0A–E) td(E–P1Q) tPXZ(E–P1Z) td(P1A–E) td(P1A–ALE) td(E–P2Q) tPXZ(E–P2Z) td(P2A–E) td(P2A–ALE) td(φ1–HLDA) td(ALE–E) tW(ALE) td(BHE–E) td(R/W–E) td(E–φ1) th(E–P0A) th(ALE–P1A) th(E–P1Q) tPZX(E–P1Z) th(E–P1A) th(ALE–P2A) th(E–P2Q) tPZX(E–P2Z) th(E–BHE) th(E–R/W) tW(EL) Port P0 address output delay time Port P1 data output delay time (BYTE = “L”) Port P1 floating start delay time (BYTE = “L”) Port P1 address output delay time Port P1 address output delay time Port P2 data output delay time Port P2 floating start delay time Port P2 address output delay time Port P2 address output delay time HLDA output delay time ALE output delay time ALE pulse width ____ BHE output delay time R/W output delay time φ 1 output delay time Port P0 address hold time Port P1 address hold time (BYTE = “L”) Port P1 data hold time (BYTE = “L”) Port P1 floating release delay time (BYTE = “L”) Port P1 address hold time (BYTE = “H”) Port P2 address hold time Port P2 data hold time Port P2 floating release delay time ____ BHE hold time R/W hold time E pulse width ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Memory expansion mode and microprocessor mode (when wait bit = “0”, and external memory area is accessed) Min. 460 Max. 130 130 120 SWITCHING CHARACTERISTICS (VCC = 2.7 to 5.5 V, VSS = 0 V, Ta = 25 °C, f(XIN) = 8 MHz, unless otherwise noted) Test conditions Fig. 4 Test conditions Fig. 4

M37702M2LXXXGP, M37702S1LGP M37702M2LXXXHP, M37702S1LHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER P 0 P 1 P 2 P 3 P 4 P 5 P 6 P 7 P 8 f E 100 pF LimitsSymbol Parameter Unit td(P0A–E) td(E–P1Q) tPXZ(E–P1Z) td(P1A–E) td(P1A–ALE) td(E–P2Q) tPXZ(E–P2Z) td(P2A–E) td(P2A–ALE) td(φ1–HLDA) td(ALE–E) tW(ALE) td(BHE–E) td(R/W–E) td(E–φ1) th(E–P0A) th(ALE–P1A) th(E–P1Q) tPZX(E–P1Z) th(E–P1A) th(ALE–P2A) th(E–P2Q) tPZX(E–P2Z) th(E–BHE) th(E–R/W) tW(EL) Port P0 address output delay time Port P1 data output delay time (BYTE = “L”) Port P1 floating start delay time (BYTE = “L”) Port P1 address output delay time Port P1 address output delay time Port P2 data output delay time Port P2 floating start delay time Port P2 address output delay time Port P2 address output delay time HLDA output delay time ALE output delay time ALE pulse width ____ BHE output delay time R/W output delay time φ 1 output delay time Port P0 address hold time Port P1 address hold time (BYTE = “L”) Port P1 data hold time (BYTE = “L”) Port P1 floating release delay time (BYTE = “L”) Port P1 address hold time (BYTE = “H”) Port P2 address hold time Port P2 data hold time Port P2 floating release delay time ____ BHE hold time R/W hold time E pulse width ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Memory expansion mode and microprocessor mode (when wait bit = “1”) Min. 210 Max. 130 130 120 Test conditions Fig. 4 Fig. 4 Testing circuit for ports P0–P8, φ1

M37702M2LXXXGP, M37702S1LGP M37702M2LXXXHP, M37702S1LHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER tw(H) td(E–P0Q) td(E–P2Q) td(E–P3Q) td(E–P4Q) td(E–P5Q) td(E–P6Q) td(E–P7Q) td(E–P8Q) Port P0 output Port P0 input Port P1 output Port P1 input Port P2 output Port P2 input Port P3 output Port P3 input E f(XIN) Port P4 output Port P4 input Port P5 output Port P5 input Port P6 output Port P6 input Port P7 output Port P7 input Port P8 output Port P8 input Single-chip mode tsu(P0D–E) th(E–P0D) td(E–P1Q) tr tf tw(L) tc tsu(P1D–E) th(E–P1D) tsu(P2D–E) th(E–P2D) tsu(P3D–E) th(E–P3D) tsu(P4D–E) th(E–P4D) tsu(P5D–E) th(E–P5D) tsu(P6D–E) th(E–P6D) tsu(P7D–E) th(E–P7D) tsu(P8D–E) th(E–P8D) TIMING DIAGRAM

M37702M2LXXXGP, M37702S1LGP M37702M2LXXXHP, M37702S1LHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER TAiIN input TAiOUT input tc(TA) tw(TAH) tw(TAL) tc(UP) tw(UPH) tw(UPL) th(TIN–UP) tsu(UP–TIN) TAiOUT input (Up-down input) TAiIN input (when count by falling) TAiIN input (when count by rising) In Event counter mode tc(TB) tw(TBH) tw(TBL) TBiIN input tc(AD) tw(ADL) tc(CK) tw(CKH) tw(CKL) tw(INL) td(C–Q) tsu(D–C) th(C–D) tw(INH) AD TRG input CLK i TxD i RxD i INTi input th(C–Q)

M37702M2LXXXGP, M37702S1LGP M37702M2LXXXHP, M37702S1LHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Memory expansion mode and microprocessor mode (When wait bit = “1”) ( When wait bit = “0”) (When wait bit = “1” or “0” in common) Test conditions

VCC = 2.7 to 5.5 V
Input timing voltage : VIL = 0.2 VCC , VIH = 0.8 VCC
Output timing voltage : VOL = 0.8 V, VOH = 2.0 V RDY input E RDY input HOLD input HLDA output tsu(RDY– f1) th(f1–RDY) tsu(RDY– f1) th(f1–RDY) tsu(HOLD– f1) td(f1–HLDA) th(f1–HOLD) td(f1–HLDA) E

M37702M2LXXXGP, M37702S1LGP M37702M2LXXXHP, M37702S1LHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER f(XIN) trtf tc tw(H)tw(L) AddressAddress Address Data Address Address Address Address Address Data Address Address td(E- φ1)td(E- φ1) tw(EL) td(P0A-E) td(P1A-E) td(P2A-E) td(ALE-E) tpxz(E-P2Z) tpxz(E-P1Z) td(E-P1Q) tpzx(E-P1Z) tpzx(E-P2Z) th(E-P0A) th(E-P1Q) th(E-P1A) tsu(P1D-E) th(E-P1D) th(E-P2D) td(E-P2Q) th(E-P2Q)th(ALE-P2A) td(P2A-ALE) tw(ALE) td(BHE-E) td(R/W-E) th(E-BHE) th(E-R/W) th(ALE-P1A) tsu(P2D-E) td(P1A-ALE) E Port P0 output (A0 to A7) Port P1 output (A8 to A15/D8 to D15) (BYTE = “L”) Port P1 input Port P2 input Port P2 output (A16 to A23/D0 to D7) Port P32 output (ALE) Port P31 output (BHE) Port P1 output (A8 to A15) (BYTE = “H”) Port P30 output (R/W) Test conditions

VCC = 2.7 to 5.5 V
Output timing voltage : VOL = 0.8 V, VOH = 2.0 V
Ports P1, P2 input : VIL = 0.16 VCC , VIH = 0.5 VCC Memory expansion mode and microprocessor mode (When wait bit = “1”)

M37702M2LXXXGP, M37702S1LGP M37702M2LXXXHP, M37702S1LHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER f(XIN) tc AddressAddress Address Data Address Address Address Address Address Data Address Address td(E- φ1)td(E- φ1) tw(EL) td(P0A-E) td(P1A-E) td(P2A-E) td(ALE-E) tpxz(E-P2Z) tpxz(E-P1Z) td(E-P1Q) tpzx(E-P1Z) tpzx(E-P2Z) th(E-P0A) th(E-P1Q) th(E-P1A) tsu(P1D-E) th(E-P1D) th(E-P2D)td(E-P2Q) th(E-P2Q)th(ALE-P2A) td(P2A-ALE) tw(ALE) td(BHE-E) td(R/W-E) th(E-BHE) th(E-R/W) th(ALE-P1A) tsu(P2D-E) td(P1A-ALE) E Port P0 output (A0 to A7) Port P1 output (A8 to A15/D8 to D15) (BYTE = “L”) Port P1 input Port P2 input Port P2 output (A16 to A23/D0 to D7) Port P32 output (ALE) Port P31 output (BHE) Port P1 output (A8 to A15) (BYTE = “H”) Port P30 output (R/W) Test conditions

VCC = 2.7 to 5.5 V
Output timing voltage : VOL = 0.8 V, VOH = 2.0 V
Ports P1, P2 input : VIL = 0.16 VCC , VIH = 0.5 VCC Memory expansion mode and microprocessor mode (When wait bit = “0”, and external memory area is accessed)

Mar. First Edition 1996 Editioned by Committee of editing of Mitsubishi Semiconductor Data Book Published by Mitsubishi Electric Corp., Semiconductor Division MITSUBISHI DATA BOOK SINGLE-CHIP 16-BIT MICROCOMPUTERS Vol.1 This book, or parts thereof, may not be reproduced in any form without permission of Mitsubishi Electric Corporation. © 1996 MITSUBISHI ELECTRIC CORPORATION Printed in Japan

Product Information

M37702S1LGP specifications and overview.

Summary

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Description

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Source title M37702S1LGP Datasheet(PDF) - Mitsubishi Electric Semiconductor

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