M37630E4FP

M37630M4T MITSUBISHI | Alldatasheet

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Technical content

7630 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

DESCRIPTION

The 7630 group is a single chip 8-bit microcomputer designed with CMOS silicon gate technology. Being equipped with a CAN (Controller Area Network) module cir- cuit, the microcomputer is suited to drive automotive equipments. The CAN module complies with CAN specification version 2.0, part B and allows priority-based message management. In addition to the microcomputers simple instruction set, the ROM, RAM and I/O addresses are placed in the same memory map to enable easy pro gramming. The built-in ROM is available as mask ROM or One Time PROM. For development purposes, emulator- and EPROM-type microcom- puters are available as well.

FEATURES

/G7A Minimum instruction execution time /G7A Memory size /G7A I/O ports Pro /G7A Timers /G7A Serial I/Os /G7A CAN module Built-in with internal feedback resistor /G7A Power source voltage /G7A Power dissipation (at 8 MHz oscillation frequency, at 5 V power source voltage) APPLICATION Automotive controls Fig. 1 Pin configuration of M37630M4T–XXXFP 34 22 35 21 36 20 37 19 38 18 39 17 40 16 41 15 42 14 43 13 44 12 M37630M4T-XXXFP M37630E4T-XXXFP P17 P20/SIN P21/SOUT P22/SCLK P23/SRDY VSS P24/URXD P25/UTXD P26/URTS P27/UCTS P30 P02/AN2 P01/AN1 P00/AN0 VREF AVSS VCC XOUT XIN VSS RESET P47/KW 7 P16/PWM P15/CNTR 1 P14/CNTR 0 P13/TX0 P12/INT1 P11/INT0 P07/AN7 P06/AN6 P05/AN5 P04/AN4 P03/AN3 P31/CTX P32/CRX P33 P34 P40/KW 0 P41/KW 1 P42/KW 2 P43/KW 3 P44/KW 4 P45/KW 5 P46/KW 6 Package type: 44P6N-A PIN CONFIGURATION (TOP VIEW) 44-pin plastic molded QFP

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Fig. 2 Functional block diagram 2021222324252627 P0 (8) 28293031323334 P1 (7) 35363738404142 P2 (8) 43441234 P3 (5) 1516 13 17 14 39 18 RAMROM VREF input I/O port P0I/O port P1I/O port P2I/O port P3 UART Serial I/OCAN 567891011 P4 (8) I/O port P4 key on wake up Clock generating circuit A (8) X (8) Y (8) S (8) PC L (8) PS (8) PC H (8) CPU Timer X (16) Timer Y (16) Timer 1 (8) Timer 2 (8) Timer 3 (8) PWM INT0, INT1 A-D Converter Clock output XOUT Clock input XIN Reset input RESET VCC VSS AV SS M37630MXT-XXXFP FUNCTIONAL BLOCK DIAGRAM (PACKAGE: 44P6N-A) WDT

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER PIN DESCRIPTION Table 1: Pin description Pin Name Input/Output Description VCC , VSS Power source voltage Power supply pins; apply 4.0 to 5.5 V to VCC and 0 V to VSS AV SS Analog power source voltage Ground pin for A-D converter. Connect to VSS RESET Reset input Input Reset pin. This pin must be kept at “L” level for more than 2 µs, to enter the reset state. If the crystal or ceramic resonator requires more time to stabilize, extend the “L” level period. XIN Clock input Input Input and output pins of the internal clock generating circuit. Connect a ceramic or quartz–crystal resonator between the XIN and XOUT pins. When an external clock source is used, connect it to XIN and leave XOUT open.XOUT Clock output Output VREF Reference volt- age input Input Reference volta ge input pin for A-D converter P00/AN0— P07/AN7 I/O port P0 I/O CMOS I/O ports or analo g input ports P11/INT0 Input CMOS input port or external interrupt input port. The active edge (rising or falling) of external interrupts can be selected. This pin will be used as VPP pin during PROM programming of One Time PROM Versions. P12/INT1 CMOS I/O port or external interrupt input port. The active edge (rising or falling) of external interrupts can be selected. P13/TX0 CMOS I/O port or input pin used in the bi-phase counter mode P14/CNTR 0 I/O port P1 I/O CMOS I/O port or timer X input pin used for the event counter, pulse width measure- ment and bi-phase counter mode P15/CNTR 1 CMOS I/O port or timer Y input pin used for the event counter, pulse width and pulse period measurement mode P16/PWM CMOS I/O port or PWM output pin used in the PWM mode of timers 2 and 3 P17 CMOS I/O port P20/SIN P21/SOUT P22/SCLK P23/SRDY CMOS I/O ports or clock synchronous serial I/O pins P24/URXD P25/UTX D P26/URTS P27/UCTS CMOS I/O ports or asynchronous serial I/O pins P30 CMOS I/O port P31/CTX CMOS I/O port or CAN transmit data pin P32/CRX CMOS I/O port or CAN receive data pin P33—P3 4 CMOS I/O port P40/KW 0— P47/KW 7 I/O port P4 I/O CMOS I/O ports. These ports can be used for key-on wake-up when configured as inputs. I/O port P2 I/O port P3 I/O I/O

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER PART NUMBERING Fig. 3 Part numbering Product M37630 M 4 T– XXX FP Package type FP: 44P6N-A package FS: 80D0 package ROM number Omitted in One Time PROM version (blank) and EPROM version T: Automotive use ROM/PROM size 4: 16384 bytes The first 128 bytes and the last 4 bytes of ROM are reserved areas. They cannot be used. Memory type M: Mask ROM version E: EPROM or One Time PROM version

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER GROUP EXPANSION Mitsubishi plans to expand the 7630 group as follows: Memory Type Support mask ROM, One Time PROM and EPROM versions. Memory Size Package Fig. 4 Memory expansion plan Currently supported products are listed below: ROM External 60K 48K 32K 28K 24K 20K 16K 12K 384 512 640 768 896 1024 RAM size (bytes) M37630M4T M37630E4T Under development Mass product Table 2: List of supported products Product (P)ROM size (bytes) ROM size for User ( )RAM size (bytes) Packa ge Remarks M37630M4T-XXXFP Mask ROM version M37630E4T-XXXFP 16384 512 44P6N-A One Time PROM version M37630E4FP (16252) One Time PROM version (blank) M37630E4FS 80D0 EPROM version As of March 1998

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER FUNCTIONAL DESCRIPTION Central Processing Unit (CPU) The core of 7630 group microcomputers is the 7600 series CPU. This core is based on the standard instruction set of 740 series; however the performance is improved by allowin g to execute the same instructions as that of the 740 series in less cycles. Refer to the 7600 Series Software Manual for details of the instruction set. CPU Mode Register CPUM The CPU mode register contains the stack page selection bit and internal system clock selection bit. The CPU mode register is allo- cated to address 000016. Fig. 5 Structure of CPU mode register CPU mode register (address 000016) CPUM Processor mode bits (set these bits to “00”) b1 b0 0 0: Single–chip mode 0 1: Not used 1 0: Not used 1 1: Not used Stack page selection bit 0 : 0 page 1 : 1 page Not used (“0” when read, do not write “1”) Internal system clock selection bit 0 : φ=f(X IN) divided by 2 (high–speed mode) 1 : φ=f(XIN) divided by 8 (middle–speed mode) Not used (“0” when read, do not write “1”)

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MEMORY Special Function Register (SFR) Area The special function register (SFR) area contains the registers relating to functions such as I/O ports and timers. RAM RAM is used for data storage and for stack area of subroutine calls and interrupts. ROM ROM is used for storing user’s program code as well as the inter- rupt vector area. Interrupt Vector Area The interrupt vector area is for storing jump destination addresses used at reset or when an interrupt is generated. Zero Page This area can be accessed most efficiently by means of the zero page addressing mode. Special Page This area can be accessed most efficiently by means of the special page addressing mode. Fig. 6 Memory map diagram 004016 000016 00FF16 006016 XXXX 16 YYYY 16 ZZZZ 16 FF0016 FFCA 16 FFFB 16 FFFC 16 FFFF 16 SFR area Not used Reserved ROM area Interrupt vector area Reserved ROM area Zero page Special page CAN SFRs RAM area RAM size (byte) Address XXXX 16 192 011F16 256 015F16 384 01DF 16 512 025F16 640 02DF 16 768 035F16 896 03DF 16 1024 045F16 1536 06DF 16 2048 085F16 ROM area ROM size (byte) Address YYYY 16 Address ZZZZ 16

4096 F00016 F08016

8192 E00016 E08016

12288 D000 16 D080 16

16384 C000 16 C080 16

20480 B00016 B08016

24576 A00016 A08016

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER SPECIAL FUNCTION REGISTERS (SFR) Fig. 7 Memory map of special register (SFR)

003016 CAN transmit control register CTRM

003116 CAN bus timing control register 1 CBTCON1

003216 CAN bus timing control register 2 CBTCON2

003316 CAN acceptance code register 0 CAC0

003416 CAN acceptance code register 1 CAC1

003516 CAN acceptance code register 2 CAC2

003616 CAN acceptance code register 3 CAC3

003716 CAN acceptance code register 4 CAC4

003816 CAN acceptance mask register 0 CAM0

003916 CAN acceptance mask register 1 CAM1

003A16 CAN acceptance mask register 2 CAM2 003B16 CAN acceptance mask register 3 CAM3 003C 16 CAN acceptance mask register 4 CAM4 003D 16 CAN receive control register CREC 003E16 CAN transmit abort register CABORT 003F16 Reserved

004016 CAN transmit buffer register 0 CTB0

004116 CAN transmit buffer register 1 CTB1

004216 CAN transmit buffer register 2 CTB2

004316 CAN transmit buffer register 3 CTB3

004416 CAN transmit buffer register 4 CTB4

004516 CAN transmit buffer register 5 CTB5

004616 CAN transmit buffer register 6 CTB6

004716 CAN transmit buffer register 7 CTB7

004816 CAN transmit buffer register 8 CTB8

004916 CAN transmit buffer register 9 CTB9

004A16 CAN transmit buffer register A CTBA 004B16 CAN transmit buffer register B CTBB 004C 16 CAN transmit buffer register C CTBC 004D 16 CAN transmit buffer register D CTBD 004E16 Reserved 004F16 Reserved

005016 CAN receive buffer register 0 CRB0

005116 CAN receive buffer register 1 CRB1

005216 CAN receive buffer register 2 CRB2

005316 CAN receive buffer register 3 CRB3

005416 CAN receive buffer register 4 CRB4

005516 CAN receive buffer register 5 CRB5

005616 CAN receive buffer register 6 CRB6

005716 CAN receive buffer register 7 CRB7

005816 CAN receive buffer register 8 CRB8

005916 CAN receive buffer register 9 CRB9

005A16 CAN receive buffer register A CRBA 005B16 CAN receive buffer register B CRBB 005C 16 CAN receive buffer register C CRBC 005D 16 CAN receive buffer register D CRBD 005E16 Reserved 005F16 Reserved

000016 CPU mode register CPUM

000116 Not used

000216 Interrupt request register A IREQA

000316 Interrupt request register B IREQB

000416 Interrupt request register C IREQC

000516 Interrupt control register A ICONA

000616 Interrupt control register B ICONB

000716 Interrupt control register C ICONC

000816 Port P0 register P0

000916 Port P0 direction register P0D

000A 16 Port P1 register P1 000B 16 Port P1 direction register P1D 000C 16 Port P2 register P2 000D 16 Port P2 direction register P2D 000E 16 Port P3 register P3 000F16 Port P3 direction register P3D

001016 Port P4 register P4

001116 Port P4 direction register P4D

001216 Serial I/O shift register SIO

001316 Serial I/O control register SIOCON

001416 A-D conversion register AD

001516 A-D control register ADCON

001616 Timer 1 T1

001716 Timer 2 T2

001816 Timer 3 T3

001916 Timer 123 mode register T123M

001E 16 Timer X mode register TXM 001F16 Timer Y mode register TYM

002016 UART mode register UMOD

002116 UART baud rate generator UBRG

002216 UART control register UCON

002316 UART status register USTS

002416 UART transmit buffer register 1 UTBR1

002516 UART transmit buffer register 2 UTBR2

002616 UART receive buffer register 1 URBR1

002716 UART receive buffer register 2 URBR2

002816 Port P0 pull-up control register PUP0

002916 Port P1 pull-up control register PUP1

002A 16 Port P2 pull-up control register PUP2 002B 16 Port P3 pull-up control register PUP3 002C 16 Port P4 pull-up/down control register PUP4 002D 16 Interrupt polarity selection register IPOL 002E 16 Watchdog timer register WDT 002F16 Polarity control register PCON

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER I/O PORTS The 7630 group has 35 programmable I/O pins and one input pin arranged in five I/O ports (ports P0 to P4). The I/O ports are con- trolled by the corresponding port registers and port direction regis- ters; each I/O pin can be controlled separately. When data is read from a port configured as an output port, the port latch’s contents are read instead of the port level. A port configured as an input port becomes floating and its level can be read. Data written to this port will affect the port latch only; the port remains floatin Refer to Structure of port- and port direction registers, Structure of port I/Os (1) and Structure of port I/Os (2). Fig. 8 Structure of port- and port direction registers Port Pij direction control bit (j = 0 to 7) 0 : Port configured as input 1 : Port configured as output Note : The direction control bits corresponding to P10, P11, P35, P36 and P37 are not used (“0” when read, do not write “1”). Port direction re- gisters are undefined when read (write only). Port Pi direction register (i = 0 to 4) (address 000916 + 2 · i) PiD Port Pij control bit (j = 0 to 7) 0 : “L” level 1 : “H” level Note : The control bits corresponding to P10, P35, P36 and P37 are not used (“0” when read, do not write “1”). Port Pi register (i = 0 to 4) (address 000816 + 2 · i) Pi

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Fig. 9 Structure of port I/Os (1) (1) Ports P00/AN0 to P07/AN7 (2) Port P11/INT0 Data bus Interrupt input (3) Port P12/INT1 Data bus Pull-up control bit Port latch Direction register Interrupt input (4) Port P13/TX0 Data bus Pull-up control bit Port latch direction register Timer bi-phase mode input (5) Ports P14/CNTR 0, P15/CNTR 1 Data bus Pull-up control bit Port latch Direction register Timer bi-phase mode input (6) Port P16/PWM Data bus Pull-up control bit Port latch Direction register PWM output PWM output enable Data bus Pull-up control bit Port latch Direction register ADC input Analog input selection Analog input selection

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Fig. 10 Structure of port I/Os (2) (13) Ports P25/UTXD, P26/URTS (14) Port P31/CTX (15) Port P32/CRX Data bus CAN dominant level control bit Port latch (16) Ports P40/KW 0 to P47/KW 7 Data bus Pull-up control bit Port latch Direction register Transmission or reception in progress Transmit or receive enable bit U TXD or URTS output Data bus Pull-up control bit Port latch Direction register CAN port selection bit CTX output Direction register Pull-up/down control bit CAN interrupt CRX input Data bus Key-on wake-up control bit Port latch Direction register Pull-up/down control bit Key-on wake-up interrupt (9) Port P21/SOUT Data bus Pull-up control bit Port latch Direction register SIO output SIO port selection bit Transmit complete signal (10) Port P22/SCLK Data bus Pull-up control bit Port latch direction register SIO clock output Clock selection bit Port selection bit External clock input (11) Port P23/SRDY Data bus Pull-up control bit Port latch Direction register SRDY output SRDY output selection bit (12) Ports P24/URXD, P27/UCTS Data bus Pull-up control bit Port latch Direction register Transmission or reception* in progress Transmit or receive* enable bit U RXD or UCTS input (7) Ports P17, P30, P33, P34 Data bus Pull-up control bit Port latch Direction register (8) Port P20/SIN Data bus Pull-up control bit Port latch Direction register SIO1 input (*) for UCTS (**) for URTS SIO Port Select

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Port Pull-up/pull-down Function Each pin of ports P0 to P4 except P11 is equipped with a program- mable pull-up transistor. P32/CRX and P4 0/KW 0 to P47/KW 7 are equipped with programmable pull-down transistors as well. The pull-up function of P0 to P3 can be controlled by the corresponding port pull-up control registers (see Structure of port pull-up/down control registers). The pull-up/down function of ports P32 and P4 can be controlled by the corresponding port pull-up/pull-down regis- ters together with the polarity control register (see Structure of polarity control register). Fig. 11 Structure of port pull-up/down control registers Fig. 12 Structure of polarity control register P3j pull-up transistor control bit (j = 0, 1) P32 pull-up/down transistor control bit P3j pull-up transistor control bit (j = 3, 4) Not used (“0” when read, do not write “1”) Pij pull-up transistor control bit (j = 0 to 7) 0 : Pull-up transistor disabled 1 : Pull-up transistor enabled Port Pi pull-up control register (address 002816 + i) (i = 0, 2) PUP0, PUP2 Port P1 pull-up control register (address 002916) PUP1 Port P3 pull-up control register (address 002B16) PUP3 P4j pull-up/down transistor control bit (j = 0 to 7) Not used (“0” when read, do not write “1”) P1j pull-up transistor control bit (j = 2 to 7) 0 : Pull-up/down transistor disabled 1 : Pull-up/down transistor enabled Port P4 pull-up/down control register (address 002C16) PUP4 Key-on wake-up polarity control bit 0 : Low level active 1 : High level active CAN module dominant level control bit 0 : Low level dominant 1 : High level dominant Not used (undefined when read) Polarity control register (address 002F16) PCON

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Port Overvoltage Application When configured as input ports, P1 to P4 may be subjected to over- voltage (VI >V CC ) if the input current to the applicable port is limited to the specified values (see “Table 8:”). Use a serial resistor of appropriate size to limit the input current. To estimate the resistor value, assume the port volta ge to be VCC at overvoltage condition. Notes:

• Subjecting ports to overvoltage may effect the supply voltage. Assure to keep VCC and VSS within the target limits.
• Avoid to subject ports to overvoltage causing VCC to rise above 5.5 V.
• The overvoltage condition causing input current flowing through the internal port protection circuits has a negative effect on the ports noise immunity. Therefore, careful and intense testing of the target system’s noise immunity is required. Refer to the “countermeasures against noise” of the corresponding users manual.
• Port P0 must not be subjected to overvoltage conditions.

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER INTERRUPTS There are 24 interrupts: 6 external, 17 internal, and 1 software. Interrupt Control Each interrupt except the BRK instruction interrupt has both an interrupt request bit and an interrupt enable bit, and is controlled by the interrupt disable fla g. An interrupt occurs when the correspond- ing interrupt request and enable bits are “1” and the interrupt dis- able flag is “0”. Interrupt enable bits can be cleared or set by software. Interrupt request bits can be cleared by software but can- not be set by software. The BRK instruction interrupt and reset can- not be disabled with any flag or bit. The I flag disables all interrupts except the BRK instruction interrupt and reset. If several interrupt requests occur at the same time, the interrupt with the highest prior- ity is accepted first. Interrupt Operation Upon acceptance of an interrupt, the following operations are auto- matically performed. 1. The processing being executed is stopped. 2. The contents of the program counter and processor status register are automatically pushed onto the stack. 3. Concurrently with the push operation, the interrupt jump destination address is read from the vector table into the program counter. 4. The interrupt disable flag is set and the corresponding interrupt request bit is cleared. Notes on use When the active edge of an external interrupt (INT0, INT1, CNTR0, CNTR 1, CWKU or KOI) is changed, the corresponding interrupt request bit may also be set. Therefore, take the following sequence. (1) Disable the external interrupt which is selected. (2) Chan ge the active edge in interrupt edge selection register. (in the case of CNTR0: Timer X mode register; in the case of CNTR 1: Timer Y mode register) (3) Clear the interrupt request bit to “0”. (4) Enable the external interrupt which is selected.

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Table 3: Interrupt vector addresses and priority Interrupt source Priority Vector Address (Note 1) Interrupt Request Generating Conditions Remarks High Low Reset (Note 2) 1 FFFB 16 FFFA 16 At Reset Non-maskable Watchdog timer 2 FFF9 16 FFF8 16 At Watchdog timer underflow Non-maskable INT0 3 FFF7 16 FFF6 16 At detection of either rising or falling edge of INT0 interrupt External Interrupt (active edge selectable) INT1 4 FFF5 16 FFF4 16 At detection of either rising or falling edge of INT1 interrupt External Interrupt (active edge selectable) CAN successful transmit 5 FFF3 16 FFF2 16 At CAN module successful transmission of message Valid when CAN module is activated and request transmit CAN successful receive 6 FFF116 FFF0 16 At CAN module successful reception of message Valid when CAN module is activated CAN overrun 7 FFEF 16 FFEE 16 If CAN module receives message when receive buffers are full. Valid when CAN module is activated CAN error passive 8 FFED 16 FFEC 16 When CAN module enters into error passive state Valid when CAN module is active CAN error bus off 9 FFEB 16 FFEA 16 When CAN module enters into bus off state Valid when CAN module is active CAN wake up 10 FFE9 16 FFE8 16 When CAN module wakes up via CAN bus Timer X 11 FFE7 16 FFE6 16 At Timer X underflow or overflow Timer Y 12 FFE5 16 FFE4 16 At Timer Y underflow Timer 1 13 FFE3 16 FFE2 16 At Timer 1 underflow Timer 2 14 FFE1 16 FFE0 16 At Timer 2 underflow Timer 3 15 FFDF 16 FFDE 16 At Timer 3 underflow CNTR 0 16 FFDD 16 FFDC 16 At detection of either rising or falling edge in CNTR0 input External Interrupt (active edge selectable) CNTR 1 17 FFDB 16 FFDA 16 At detection of either rising or falling edge in CNTR1 input External Interrupt (active edge selectable) UART receive 18 FFD9 16 FFD8 16 At completion of UART receive Valid when UART is selected UART transmit 19 FFD7 16 FFD6 16 At completion of UART transmit Valid when UART is selected UART transmit buffer empty 20 FFD5 16 FFD4 16 At UART transmit buffer empty Valid when UART is selected UART receive error 21 FFD3 16 FFD2 16 When UART reception error occurs. Valid when UART is selected Serial I/O 22 FFD1 16 FFD0 16 At completion of serial I/O data transmit and receive Valid when serial I/O is selected A-D conversion 23 FFCF 16 FFCE 16 At completion of A-D conversion Key-on wake-up 24 FFCD 16 FFCC 16 At detection of either rising or falling edge of P4 input External Interrupt (active edge selectable) BRK instruction 25 FFCB 16 FFCA 16 At BRK instruction execution Non-maskable Notes 1: Vector addresses contain interrupt jump destination address 2: Reset function in the same way as an interrupt with the highest priority

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Fig. 13 Interrupt control Fig. 14 Structure of interrupt polarity selection register BRK instruction Reset Interrupt disable flag I Interrupt request bit Interrupt enable bit Interrupt request Not used (returns to “0” when read, do not write “1” in this bit) INT0 interrupt edge selection bit INT1 interrupt edge selection bit Not used (returns to “0” when read, do not write “1” in these bits) Interrupt polarity selection register (Address 002D16) IPOL 0 : Falling edge active 1 : Rising edge active For the external interrupts INT0 and INT1, the active edge causing the interrupt request can be selected by the INT0 and INT1 interrupt ed ge selection bits of the interrupt polarity selection register (IPOL); please refer to Fig. 14 below.

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Fig. 15 Structure of interrupt request and control registers A, B and C

7 Interrupt request register A

(address 000216) IREQA CAN wake up interrupt request bit Timer X interrupt request bit Timer Y interrupt request bit Timer 1 interrupt request bit Timer 2 interrupt request bit Timer 3 interrupt request bit CNTR 0 interrupt request bit CNTR 1 interrupt request bit 7 0 7 0 0 : No interrupt request 1 : Interrupt requested Not used (returns to ”0” when read) External interrupt INT0 request bit External interrupt INT1 request bit CAN successful transmission interrupt request bit CAN successful receive interrupt request bit CAN overrun interrupt request bit CAN error passive interrupt request bit CAN bus off interrupt request bit Interrupt request register B (address 000316) IREQB Interrupt request register C (address 000416) IREQC UART receive complete (receive buffer full) interrupt request bit UART transmit complete (transmit re gister empty) interrupt request bit UART transmit buffer empty interrupt request bit UART receive error interrupt request bit Serial I/O interrupt request bit AD conversion complete interrupt request bit Key-on wake-up interrupt request bit Not used (returns to ”0” when read) 7 0 Not used (returns to ”0” when read) External interrupt INT0 enable bit External interrupt INT1 enable bit CAN successful transmission interrupt enable bit CAN successful receive interrupt enable bit CAN overrun interrupt enable bit CAN error passive interrupt enable bit CAN bus off interrupt enable bit Interrupt control re gister A (address 000516) ICONA 7 0 Interrupt control register B (address 000616) ICONB CAN wake–up interrupt enable bit Timer X interrupt enable bit Timer Y interrupt enable bit Timer 1 interrupt enable bit Timer 2 interrupt enable bit Timer 3 interrupt enable bit CNTR 0 interrupt enable bit CNTR 1 interrupt enable bit 7 0 Interrupt control register C (address 000716) ICONC UART receive complete (receive buffer full) interrupt enable bit UART transmit complete (transmit re gister empty) interrupt enable bit UART transmit buffer empty interrupt enable bit UART receive error interrupt enable bit Serial I/O interrupt enable bit AD conversion complete interrupt enable bit Key-on wake-up interrupt enable bit Not used (returns to ”0” when read) 0: Interrupt disabled 1: Interrupt enabled

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER KEY-ON WAKE-UP “Key-on wake-up” is one way of returning from a power-down state caused by the STP or WIT instruction. Any terminal of port P4 can be used to generate the key-on wake-up interrupt request. The active polarity can be selected by the key-on wake-up polarity con- trol bit of PCON (see Fig. 12). If any pin of port P4 has the selected active level applied, the key-on wake-up interrupt request will be set to “1”. Please refer to Fi g. 16. Fig. 16 Block diagram of key-on wake-up circuit PUP4 j key-on wake-up interrupt key-on wake-up control bit P4D j port P4j I/O circuit port P4j/KW j j = 0 to 7

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER TIMERS The 7630 group has five timers: two 16-bit timers and three 8-bit timers . All these timers will be described in detail below. 16-bit Timers Timers X and Y are 16-bit timers with multiple operating modes. Please refer to Fig. 17. Fig. 17 Block diagram of timers X and Y (φ is internal system clock) Timer X Timer X is a 16-bit timer with a 16-bit reload latch supporting the fol- lowing operating modes: (1) Timer mode (2) Bi-phase counter mode (3) Event counter mode (4) Pulse width measurement mode These modes can be selected by the timer X mode re gister (TXM). In the timer- and pulse width measurement mode, the timer’s count source can be selected by the timer X count source selection bits of the timer Y mode re gister (TYM). Please refer to the Figures below for the TXM and TYM bit assignment. On read or write access to timer X, note that the high-order and low- order bytes must be accessed in the specific order. Write method When writing to the timer X, write the low-order byte first. The data written is stored in a temporary register which is assigned to the same address as TXL. Next, write the high-order byte. When this is finished, the data is placed in the timer X high-order reload latch and the low-order byte is transferred from its temporary register to the timer X low-order reload latch. Depending on the timer X write control bit, the latch contents are reloaded to the timer immediately (write control bit = “0”) or on the next timer underflow (write control bit = “1”). Read method When reading the timer X, read the high-order byte first. This causes the timer X high- and low-order bytes to be transferred to temporary registers being assigned to the same addresses as TXH and TXL. Next, read the low-order byte which is read from the tem- porary register. This method assures the correct timer value can be read during the timer count operation. Timer X count stop control Re gardless of the actual operating mode, timer X can be stopped by setting the timer X count stop bit (bit 7 of the timer X mode regis- ter) to “1”. TYM 5, 4=“11” TYM 7 TYM 1,0φ P13/TX0 P14/CNTR 0 edge detector edge detector sign generator TX L counter (8) TX H latch (8) TX H counter (8) TXM 7 TX L latch (8) count direction control TXM 5, 4 down “00”, “10”, “11”“01” “00”, “11” “01” “10” TXM 6 TXM 5, 4=“11” TX interrupt request CNTR0 interrupt request P15/CNTR 1 TYM 6 TYM 5, 4 “10” “0x”, “11” TY L counter (8) TY H latch (8) TY H counter (8) TY L latch (8) TY interrupt request CNTR1 interrupt request rising edge detector falling edge detector TYM 5, 4=“01” TYM 5, 4 “11” “0x”, “10” “0” “1” TYM 3, 2 TXM 5,4 “00” “01” “10” “11” “00” “01” “10” “11” “0” “1”

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Fig. 18 Structure of Timer X mode register Timer Y Timer Y is a 16 bit timer with a 16-bit reload latch supporting the fol- lowing operating modes: (1) Timer mode (3) Event counter mode (5) Pulse period measurement mode (6) H/L pulse width measurement mode These modes can be selected by the timer Y mode re gister (TYM). In the timer, pulse period- and pulse width measurement modes’ the timer’s count source can be selected by the timer Y count source selection bits. Please refer to Fig. 19. On read or write access to timer Y, note that the high-order and low- order bytes must be accessed in a specific order. Write method When writing to timer Y, write the low-order byte first. The data writ- ten is stored in a temporary register which is assigned to the same address as TYL. Next, write the high-order byte. When this is fin- ished, the data is placed in the timer Y high-order reload latch and the low-order byte is transferred from its temporary register to the timer Y low-order reload latch. Read method When reading the timer Y, read the high-order byte first. This causes the timer Y high- and low-order bytes to be transferred to temporary registers being assigned to the same addresses as TYH and TYL. Next, read the low-order byte which is read from the tem- porary register. This method assures the correct timer value can be read during timer count operation. Timer Y count stop control Re gardless of the actual operating mode, timer Y can be stopped by setting the timer Y count stop bit (bit 7 of the timer Y mode regis- ter) to “1”. Timer X data write control bit 0 : Data is written to latch and timer 1 : Data is written to latch only Not used (“0” when read, do not write “1”) Timer X mode bits b5 b4 0 0: Timer mode 0 1: Bi-phase counter mode 1 0: Event counter mode 1 1: Pulse width measurement mode CNTR 0 polarity selection bit 0 : For event counter mode, rising edge active For interrupt request, falling edge active For pulse width measurement mode, measure “H” period 1 : For event counter mode, falling edge active For interrupt request, rising edge active For pulse width measurement mode, measure “L” period Timer X stop control bit 0 : Timer counting 1 : Timer stopped Timer X mode register (address 001E16) TXM

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Fig. 19 Structure of timer Y mode register (φ is internal system clock) Operating Modes (1) Timer mode This mode is available with timer X and timer Y.

• Count source The count source for timer X and Y is the output of the corre- spondin g clock divider. The division ratio can be selected by the timer Y mode register.
• Operation Both timers X and Y are down counters. On a timer underflow, the corresponding timer interrupt request bit will be set to “1”, the contents of the corresponding timer latches will be reloaded to the counters and counting continues. (2) Bi-phase counter mode (quadruplicate) This mode is available with timer X only.
• Count source The count sources are P14/CNTR 0 and the P13/TX0 pins.
• Operation Timer X will count both rising and falling edges on both input pins (see above). Refer to Timer X bi-phase counter mode operation for the timing chart of the bi-phase counter mode. The count direction is determined by the edge polarity and level of count source inputs and may change during the count opera- tion. Refer to the table below. On a timer over- or underflow, the corresponding interrupt request bit will be set to “1” and counting continues. Timer X count source selection bits b1 b0 0 0: φ divided by 4 0 1: φ divided by 16 1 0: φ divided by 64 1 1: φ divided by 128 Timer Y count source selection bits b3 b2 0 0: φ divided by 2 0 1: φ divided by 8 1 0: φ divided by 32 1 1: φ divided by 64 Timer Y operation mode bits b5 b4 0 0: Timer mode 0 1: Pulse period measurement mode 1 0: Event counter mode 1 1: H/L pulse width measurement mode CNTR 1 polarity selection bit 0 : For event counter mode, rising edge active For interrupt request, falling edge active For pulse period measurement mode, refer to falling edges 1 : For event counter mode, falling edge active For interrupt request, rising edge active For pulse period measurement mode, refer to rising edges Timer Y stop control bit 0 : Timer counting 1 : Timer stopped Timer Y mode register (address 001F16) TYM Table 4: Timer X count direction in Bi-phase counter mode P13/TX0 P14/CNTR 0 Count direction ↑ Edge LU p H Down ↓ Edge L Down HU p L ↑ Edge Down HU p L ↓ Edge Up H Down

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Fig. 20 Timer X bi-phase counter mode operation (3) Event counter mode This mode is available with timer X and timer Y.

• Count source The count source for timer X is the input signal to the P14/CNTR 0 pin and for timer Y the input signal to P15/CNTR 1 pin.
• Operation The timer counts down. On a timer underflow, the corresponding timer interrupt request bit will be set to “1”, the contents of the correspondin g timer latches will be reloaded to the counters and counting continues. The active edge used for counting can be selected by the polarity selection bit of the corresponding pin P14/CNTR 0 or P15/CNTR 1. These bits are part of TXM (Structure of Timer X mode register) and TYM (Structure of timer Y mode register (f is internal system clock)) registers. (4) Pulse width measurement mode This mode is available with timer X only.
• Count source The count source is the output of timer X clock divider. The divi- sion ratio can be selected by the timer Y mode re gister.
• Operation The timer counts down while the input signal level on P14/CNTR 0 matches the active polarity selected by the CNTR0 polarity selection bit of TXM (Structure of Timer X mode regis- ter). On a timer underflow, the timer X interrupt request bit will be set to “1”, the contents of the timer latches are reloaded to the counters and countin g continues. When the input level changes from active polarity (as selected), the CNTR0 interrupt request bit will be set to “1.” The measurement result may be obtained by reading timer X during interrupt service. (5) Pulse period measurement mode This mode is available with timer Y only.
• Count source The count source is the output of timer Y clock divider.
• Operation The active edge of input signal to be measured can be selected by CNTR 1 polarity selection bit (Fig. 18). When this bit is set to “0”, the time between two consecutive falling edges of the signal input to P15/CNTR 1 pin will be measured, when the polarity bit is set to “1”, the time between two consecutive rising edges will be measured. The timer counts down. On detection of an active edge of input signal, the contents of the TY counters will be transferred to tem- porary registers assigned to the same addresses as TY. At the same time, the contents of TY latches will be reloaded to the counters and counting continues. The active edge of input signal also causes the CNTR1 interrupt request bit to be set to “1”. The measurement result may be obtained by reading timer Y during interrupt service. (6) H/L pulse width measurement mode This mode is available with timer Y only.
• Count source The count source is the output of the timer Y’s clock divider.
• Operation This mode measures both the “H” and “L” periods of a signal input to P15/CNTR 1 pin continuously. On detection of any edge (rising or falling) of input signal to P15/CNTR 1 pin, the contents of timer Y counters are stored to temporary registers which are assigned to the same addresses as timer Y. At the same time, the contents of timer Y latches are reloaded to the counters and counting continues. The detection of an edge causes the CNTR1 interrupt request bit to be set to “1” as well. The result of measurement may be obtained by reading timer Y during inter- rupt service. This read access will address the temporary regis- ters. On a timer underflow, the timer Y interrupt request bit will be set to “1”, the contents of timer Y latches will be transferred to the counters and counting continues. P13/TX0 input signal P14/CNTR 0 input signal TX counter count direction down up

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER TIMER 1, TIMER 2, TIMER 3 Timers 1 to 3 are 8-bit timers with 8-bit reload latches and one com- mon pre-divider. Timer 1 can operate in the timer mode only, whereas timers 2 and 3 can be used to generate a PWM output sig- nal timing as well. Timers 1 to 3 are down count timers. See Fig. 21. Fig. 21 Block diagram of timers 1 to 3 (φ is internal system clock) Timer 1 The count source of timer 1 is the output of timer 123 pre-divider. The division ratio of the pre-divider can be selected by the pre- divider division ratio bits of timer 123 mode re gister (T123M). Refer to Timer 123 mode register configuration (f is internal system clock). On a timer 1 underflow, the timer 1 interrupt request bit will be set to “1”. Writing to timer 1 initializes the latch and counter. Timers 2 and 3 The count source of timers 2 and 3 can be either the output of the timer 123 pre-divider or the timer 1 underflow. The count source can be selected by the timer count source selection bits of timer 123 mode register (T123M). Writing to timer 2 register affects the reload latch only or both of the reload latch and counter depending on the timer 2 write control bit of T123M. When the timer write control bit is set to “0”, both latch and counter will be initialized simultaneously; when set to “1” only the reload latch will be initialized, on an underflow, the counter will be set to the modified reload value. Writin g to timer 3 initializes latch and counter both. Timer 2 or 3 underflow causes the timer 2 or 3 interrupt request bit to be set to “1”. T123M 0 T123M 67φ T1 counter (8) T1 latch (8) T2 counter (8) T2 latch (8) T3 counter (8) T3 latch (8) T1 interrupt T2 interrupt T3 interrupt S R Q S R Q T123M 3 T123M 4 T123M 1 T123M 1 S TQP16/PWM P16 latch P1D 6 T123M 1 “00” “01” “10” “11” “1” “0” “0” “1” “1” “0” “0” “1”

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Fig. 22 Timer 123 mode register configuration (φ is internal system clock) Operating Modes (1) Timer Mode This mode is available with timers 1 to 3.

• Count source For timer 1, the count source is the output of the corresponding pre-divider. For timers 2 and 3, the count source can be sepa- rately selected to be either the pre-divider output or timer 1 underflow.
• Operation The timer counts down. On a timer underflow, the correspondin g timer interrupt request bit will be set to “1”, the contents of the correspondin g timer latch will be reloaded to the counter and counting continues. (2) PWM Mode This mode is available with timer 2 and 3.
• Count source The count source can be separately selected to be either the pre-divider output or timer 1 underflow.
• Operation When the PWM-mode is enabled, timer 2 starts counting. As soon as timer 2 underflows, timer 2 stops and timer 3 starts counting. If bit 0 is set, timer 2 determines the low duration and the initial output level is low. Timer 3 determines the high dura- tion. If bit 0 is zero timer 2 determines the high duration and the initial output level is high. In this case timer 3 determines the low duration. Note: Be sure to configure the P16/PWM pin as an output port before using PWM mode. PWM polarity selection bit 0 : Start on “H” level output 1 : Start on “L” level output PWM output enable bit 0 : PWM output disabled 1 : PWM output enabled Timer 2 write control bit 0 : Latch and counter 1 : Latch only Timer 2 count source selection bit 0 : Timer 1 underflow 1 : Pre-divider output Timer 3 count source selection bit 0 : Timer 1 underflow 1 : Pre-divider output Not used (“0” when read, do not write “1”) Pre-divider division ratio bits b7 b6 0 0: φ divided by 1 0 1: φ divided by 8 1 0: φ divided by 32 1 1: φ divided by 128 Timer 123 mode register (address 001916) T123M

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER SERIAL I/Os The serial I/O section of 7630 group consists of one clock synchro- nous and one asynchronous (UART) interface. Clock Synchronous Serial I/O (SI/O) The clock synchronous interface allows full duplex communication based on 8 bit word length. The transfer clock can be selected from an internal or external clock. When an internal clock is selected, a pro grammable clock divider allows eight different transmission speeds. Refer to Block diagram of clock synchronous I/O (f is inter- nal system clock). The operation of the clock synchronous serial I/O can be confi gured by the serial I/O control register SIOCON; refer to Fig. 25. Fig. 23 Block diagram of clock synchronous I/O (φ is internal system clock) (1) Clock synchronous serial I/O operation Either an internal or external transfer clock can be selected by bit 6 of SIOCON. The internal clock divider can be programmed by bits 0 to 2 of SIOCON. Bit 3 of SIOCON determines whether the double function pins P20 to P22 will act as I/O ports or serve as SIO pins. Bit 4 of SIOCON allows the same selection for pin P23. When an internal transfer clock is selected, transmission can be triggered by writing data to the SI/O shift register (SIO, address 001216). After an 8–bit transmission has been completed, the SOUT pin will change to high impedance and the SIO interrupt request bit will be set to “1”. When an external transfer clock is selected, the SIO interrupt request bit will be set to “1” after 8 cycles but the contents of the SI/O shift re gister continue to be shifted while the transfer clock is being input. Therefore, the clock needs to be controlled externally; the SOUT pin will not change to high impedance automatically. SIOCON 2, 1, 0φ SIO interrupt Sync. circuit P23 latch P22/SCLK P23/SRDY P22 latch SIO counter (3) P21/SOUT P21 latch SIO shift register (8) P20/SIN P20 latch SIOCON 4 SIOCON 3 SIOCON 3 SIOCON 3 SIOCON 6 Clock divider “0” “1” “0” “0” “0” “0” “1” “1” “1” “1”

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Fig. 24 Timing of clock synchronous SI/O function (LSB first selected) Fig. 25 Structure of serial I/O control register (φ is internal system clock) Clock Asynchronous Serial I/O (UART) The UART is a full duplex asynchronous transmit/receive unit. The built-in clock divider and baud rate generator enable a broad range of transmission speeds. Please refer to Block diagram of UART. (1) Description The transmit and receive shift registers have a buffer (consisting of high and low order byte) each. Since the shift registers cannot be written to or read from directly, transmit data is written to the trans- mit buffer and receive data is read from the receive buffer. A trans- mit or receive operation will be triggered by the transmit enable bit and receive enable bit of the UART control register UCON (see Structure of UART control register). The double function terminals P25/UTXD, P26/URTS and P24/URXD, P27/UCTS will be switched to serve as UART pins automatically. D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7 D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7Serial input SIN Serial Output SOUT write signal to SIO receive enable signal SRDY transfer clock SIO interrupt request bit = “1” Note: When an internal clock is selected, SOUT pin will change to high impedance after 8 bits of data have been transmitted. synchronous clock Clock divider selection bits b2 b1 b0 0 0 0: φ divided by 4 0 0 1:φ divided by 8 0 1 0: φ divided by 16 0 1 1: φ divided by 32 1 0 0: φ divided by 64 1 0 1: φ divided by 128 1 1 0: φ divided by 256 1 1 1: φ divided by 512 P20/SIN, P21/SOUT and P22/SCLK function selection bit 0 : I/O port function 1 : SI/O function P23/SRDY function selection bit 0 : I/O port function 1 : SI/O function Transmission order selection bit 0 : LSB first 1 : MSB first Synchronization clock selection bit 0 : use external clock 1 : use internal clock Not used (“0” when read) SIO control register (address 001316) SIOCON

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER (2) Baud rate selection The baud rate of transmission and reception is determined by the setting of the prescaler and the contents of the UART baud rate generator register. It is calculated by: where p is the division ratio of the prescaler and n is the content of UART baud rate generator reg- ister. The prescalers division ration can be selected by the UART mode register (see below). UART mode register (UMOD, Structure of UART mode register) The UART mode re gister allows to select the transmission and reception format with the following options:

• word length: 7, 8 or 9 bits
• parity: none, odd or even
• stop bits: 1 or 2 It allows to select the prescalers division ratio as well. UART baud rate generator (UBRG) This 8 bit register allows to select the baud rate of the UART (see above). Set this register to the desired value before enabling recep- tion or transmission. UART control register (UCON, Structure of UART control register) The UART control register consists of four control bits (bit 0 to bit 3) which allow to control reception and transmission. UART status register (USTS, Structure of UART status register) The read-only UART status register consists of 7 bits (bit 0 to bit 6) which indicate the operating status of the UART function and vari- ous errors. (3) Handshaking signals When used as transmitter the UART will recognize the clear-to- send signal via P27/UCTS terminal for handshaking. When used as receiver it will issue a request-to-send signal through P26/URTS pin. Clear-to-send input When used as a transmitter (transmit enable bit set to “1”), the UART starts transmission after recognizing “L” level on P27/UCTS . After started the UART will continue to transmit regardless of the actual level of P27/UCTS or status of the transmit enable bit. Request-to-send output The UART controls the P26/URTS output according to the following conditions. Table 5: Output control conditions Fig. 26 Block diagram of UART b φ Condition P26/URTS Receive enable bit is set to “1” “L”Reception completed during receive enable bit set to “1” Start bit (falling edge) detected “H” Receive enable bit is set to “0” before recep- tion started Hardware reset Receive initialization bit is set to “1” UMOD 4,3,2 φ UMOD 2, 1 UBRG (8) transmit shift register (9) transmission control circuit reception control circuit P25/UTXD P27/UCTS P26/URTS bit counter bit counter UMOD 7, 6 UMOD 7, 6 UART status register transmit buffer empty flag receive error flags receive buffer full interrupt request receive error interrupt request P24/URXD transmit buffer (9) data bus data bus transmit buffer empty interrupt request transmit register empty interrupt request receive buffer full flag transmit register empty flag receive shift register (9) receive buffer (9) UART control register “00” “01” “10” “11”

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Fig. 27 Structure of UART mode register Fig. 28 Structure of UART control register Not used (“0” when read, do not write “1”) clock divider selection bits b2 b1 0 0 : φ divided by 1 0 1 : φ divided by 8 1 0 : φ divided by 32 1 1 : φ divided by 256 Stop bits selection bit 0 : One stop bit 1 : Two stop bits Parity selection bit 0 : Even parity 1 : Odd parity Parity enable bit 0 : Parity disabled 1 : Parity enabled UART word length selection bits b7 b6 0 0 : 7 bits 0 1 : 8 bits 1 0 : 9 bits 1 1 : Not used UART mode register UMOD (address 002016) Transmit enable bit 0 : Transmit disabled (an ongoing transmission will be finished correctly) 1 : Transmit enabled Receive enable bit 0 : Receive disabled (an ongoing reception will be finished correctly) 1 : Receive enabled Transmission initialization bit 0 : No action 1 : Clear transmit buffer full flag and transmit shifter full flag, set the transmit status register bits and stop transmission Receive initialization bit 0 : No action 1 : Clear receive status flags and the receive enable bit Not used (“0” when read, do not write “1”) UART control register UCON (address 002216)

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Fig. 29 Structure of UART status register Transmit register empty flag 0 : Register full 1 : Register empty Transmit buffer empty flag 0 : Buffer full 1 : Buffer empty Receive buffer full flag 0 : Buffer full 1 : Buffer empty Receive parity error flag 0 : No parity error detected 1 : Parity error detected Receive framing error flag 0 : No framing error detected 1 : Framing error detected Receive overrun flag 0 : No overrun detected 1 : Overrun detected Receive error sum flag 0 : No error detected 1 : Error detected Not used (“0” when read) Note: this re gister is read only; writing does not affect its contents. UART status register (address 002316) USTS

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER CAN MODULE The CAN (Controller Area Network) interface of the 7630 group complies with the 2.0B specification, enabling reception and trans- mission of frames with either 11- or 29- bit identifier length. Refer to Fig. 31 for a block diagram of the CAN interface. The programmer’s interface to the CAN module is formed by three status/control registers (Fig. 32, Fig. 33, Fig. 34), two bus timing control registers (Fig. 35 Fig. 36), several registers for acceptance filtering (Fig. 37), the transmit and receive buffer registers (Fig. 38) and one dominant level control bit (Fig. 22). Baud Rate Selection A programmable clock prescaler is used to derive the CAN mod- ule’s basic clock from the internal system clock frequency (φ). Bit 0 to bit 3 of the CAN bus timing control register represent the pres- caler allowing a division ratio from 1 to 1/16 to be selected. So the CAN module basic clock frequency fCANB can be calculated as fol- lows: where p is the value of the prescaler (selectable from 1 to 15). The effective baud rate of the CAN bus communication depends on the CAN bus timing control parameters and will be explained below. CAN Bus Timing Control Each bit-time consists of four different segments (see Fig. 30):

• Synchronization segment (SS),
• Propa gation time segment (PTS),
• Phase buffer segment 1 (PBS1) and
• Phase buffer segment 2 (PBS2). Fig. 30 Bit time of CAN module The first of these segments is of fixed length (one Time Quantum) and the latter three can be programmed to be 1 to 8 Time Quanta by the CAN bus timing control register 1 and 2 (see Fig. 35 and Fig. 36). The whole bit-time has to consist of minimum 8 and maximum 25 Time Quanta. The duration of one Time Quantum is the cycle time of fCANB . For example, assuming φ = 5 MHz, p = 0, one Time Quantum will be 200 ns long. This allows the maximum transmis- sion rate of 625 kb/s to be reached (assuming 8 Time Quanta per bit-time). Fig. 31 Block diagram of CAN module fCANB φ SS PTS PBS1 PBS2 Sample point Bit-time bus timing control register data bus acceptance mask register acceptance code register transmit buffer receive buffer 1 receive buffer 2 acceptance filter data bus P31/CTX P32/CRX protocol controller CAN wake-upwake-up logic polarity control register CAN status/control registers

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Fig. 32 Structure of CAN transmit control register CAN transmit control register (address 003016) CTRM Sleep control bit 0 : CAN module in normal mode 1 : CAN module in sleep mode Reset/configuration control bit 0 : CAN module in normal mode 1 : CAN module in configuration mode (plus reset at write) Port double function control bit 0 : P31/CTX serves as I/O port 1 : P31/CTX serves as CTX output port Transmit request bit 0 : No transmission requested 1 : Transmission requested (write “0” has no effect) Not used (no operation, “0” when read) Transmit buffer control bit 0 : CPU access possible 1 : No CPU access (write “0” has no effect, while CTRM(3) = 1) Not used (no operation, “0” when read) Transmit status bit (read only) 0 : CAN module idle or receiving 1 : CAN module transmitting

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Fig. 33 Structure of CAN receive control register Fig. 34 Structure of CAN transmit abort register CAN receive control register (address 003D16) CREC Receive buffer control bit 0 : Receive buffer empty 1 : Receive buffer full (write “1” has no effect) Receive status bit (read only) 0 : CAN module idle or transmitting 1 : CAN module receiving Not used (do not write “1”, read as “0”) Auto-receive disable bit 0 : Auto-receive enabled 1 : Auto-receive disabled Note: Suppresses reception of self initiated/transmitted frames Not used (do not write “1”, “0” when read) CAN transmit abort register (address 003E16) CABORT Transmit Abort control bit 0 : No Transmit Abort Request 1 : Transmit Abort Request (write “1” has no effect, while CTRM(3) = 0) Not used (No operation, “0” when read)

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Fig. 35 Structure of CAN bus timing control register 1 Fig. 36 Structure of CAN bus timing control register 2 CAN bus timing control register 1 (address 003116) CBTCON1 Prescaler division ratio selection bits b3 b2 b1 b0 0 0 0 0:φ divided by 1 0 0 0 1:φ divided by 2 0 0 1 0:φ divided by 3 1 1 1 0:φ divided by 15 1 1 1 1:φ divided by 16 Sampling control bit 0 : One sample per bit 1 : Three sample per bit Propagation time duration control bits b7 b6 b5 0 0 0: One Time Quantum 0 0 1: Two Time Quanta 1 1 0: Seven Time Quanta 111 :E ight Time Quanta CAN bus timing control register 2 (address 003216) CBTCON2 Phase buffer segment 1 duration control bits b2 b1 b0 0 0 0: One Time Quantum 0 0 1: Two Time Quanta 1 1 0: Seven Time Quanta 111 :E i ght Time Quanta Phase buffer segment 2 duration control bits b5 b4 b3 0 0 0: One Time Quantum 0 0 1: Two Time Quanta 1 1 0: Seven Time Quanta 111 :E i ght Time Quanta Synchronization jump width control bits b7 b6 0 0 : One Time Quantum 0 1 : Two Time Quanta 1 0 : Three Time Quanta 1 1 : Four Time Quanta

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Fig. 37 Structure of CAN mask and code registers Fig. 38 Structure of CAN transmission and reception buffer registers address7 0 Not used Not used Not used CSID10 CSID 9 CSID 8 CSID 7 CSID 6 CSID 5 CSID 4 CSID 3 CSID 2 CSID 1 CSID 0 Not used Not used Not used Not used Not used Not used CEID17 CEID 16 CEID 15 CEID 14 CEID 13 CEID 12 CEID 11 CEID 10 CEID 9 CEID 8 CEID 7 CEID 6 CEID 5 CEID 4 CEID 3 CEID 2 CEID 1 CEID 0 Not used Not used 7 0 Not used Not used Not used MSID10 MSID 9 MSID 8 MSID 7 MSID 6 MSID 5 MSID 4 MSID 3 MSID 2 MSID 1 MSID 0 Not used Not used Not used Not used Not used Not used MEID17 MEID 16 MEID 15 MEID 14 MEID 13 MEID 12 MEID 11 MEID 10 MEID 9 MEID 8 MEID 7 MEID 6 MEID 5 MEID 4 MEID 3 MEID 2 MEID 1 MEID 0 Not used Not used 003316 003416 003516 003616 003716 003816 003916 003A16 003B16 003C 16 Acceptance code registers: Acceptance mask registers: Select the bit pattern of identifiers which allows to pass acceptance filtering. 0 : Mask identifier bit (do not care) 1 : Compare identifier bit with acceptance code register bit (Not used: write to “0”) name CAC0 CAC1 CAC2 CAC3 CAC4 CAM0 CAM1 CAM2 CAM3 CAM4 offset7 0 Not used Not used Not used SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 SID2 SID1 SID0 RTR/SRR IDE Not used Not used Not used Not used EID17 EID16 EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 RTR r1 000016 000116 000216 000316 000416 Not used Not used Not used r0 DLC 3 DLC 2 DLC 1 DLC 0 000516 000616data byte 0 000716data byte 1 000816data byte 2 000916data byte 3 000A16data byte 4 000B16data byte 5 000C 16data byte 6 000D 16data byte 7 Calculate the actual address as follows: TxD buffer address = 004016 + offset RxD buffer address = 005016 +offset (Not used: write to “0”) name CTB0, CRB0 CTB1, CRB1 CTB2, CRB2 CTB3, CRB3 CTB4, CRB4 CTB5, CRB5 CTB6, CRB6 CTB7, CRB7 CTB8, CRB8 CTB9, CRB9 CTBA, CRBA CTBB, CRBB CTBC, CRBC CTBD, CRBD Note 1: All CAN related SFRs must not be written in “CAN sleep” mode.

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER A-D CONVERTER The A-D converter uses the successive approximation method with 8 bit resolution. The functional blocks of the A-D converter are described below. Refer to Block diagram of A-D converter. Comparison Voltage Generator The comparison voltage generator divides the voltage between AV SS and VREF by 256, and outputs the divided voltage. Channel Selector The channel selector selects one of ports P00/AN0 to P07/AN7, and inputs its voltage to the comparator. A-D conversion register AD The A-D conversion register is a read-only register that stores the result of an A-D conversion. This register must not be read during an A-D conversion. Fig. 39 Block diagram of A-D converter A-D control register (Structure of A-D control reg- ister) The A-D control register controls the A-D conversion process. Bits 0 to 2 select a specific analog input pin. Bit 3 signals the completion of an A-D conversion. The value of this bit remains “0” during an A- D conversion, and changes to “1” when an A-D conversion ends. Writing “0” to this bit starts the A-D conversion. Bit 4 is the VREF / Input switch bit. AV SS P00/AN0 A-D control register b7 b0 comparison voltage generator A-D control circuit Comparator P07/AN7 VREF A-D interrupt request A-D conversion register channel selector Data bus VREF /Input switch bit

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Fig. 40 Structure of A-D control register A-D Converter Operation The comparator and control circuit reference an analog input volt- age with the reference voltage, then stores the result in the A-D conversion register. When an A-D conversion is complete, the con- trol circuit sets the A-D conversion completion bit and the A-D inter- rupt request bit to “1”. The result of A-D conversion can be obtained from the A-D conversion register, AD (address 001416). Note that the comparator is linked to a capacitor, so set f(XIN) to 500 kHz or higher during A-D conversion. A-D control register (address 001516) ADCON Analog input pin selection bits b2 b1 b0 0 0 0 : P00/AN0 0 0 1 : P01/AN1 0 1 0 : P02/AN2 0 1 1 : P03/AN3 1 0 0 : P04/AN4 1 0 1 : P05/AN5 1 1 0 : P06/AN6 1 1 1 : P07/AN7 A-D conversion completion bit 0 : Conversion in progress 1 : Conversion completed VREF /Input switch bit 0 : Off 1 : On Not used (“0” when read, do not write “1”)

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER WATCHDOG TIMER The watchdog timer consists of two separate counters: one 7-bit counter (WDH ) and one 4-bit counter (WDL). Cascading both counters or using the high-order counter allows only to select the time-out from either 524288 or 32768 cycles of the internal clock φ. Refer to Fig. 41 and Fig. 42. Both counters are addressed by the same watchdog timer register (WDT). When writing to this register, both counters will be set to the following default values:

• t h e h igh-order counter will be set to address 7F16
• the low-order counter will be set to address F16 regardless of the data written to the WDT register. Reading the watchdog timer register will return the corresponding control bit sta- tus, not the counter contents. Once the WDT re gister is written to, the watchdog timer starts counting down and the watchdog timer interrupt is enabled. Once it is running, the watchdog timer cannot be disabled or stopped except by reset. On a watchdog timer underflow, a non-maskable watchdog timer interrupt will be requested. To prevent the system being stopped by STP instruction, this instruction can be disabled by the STP instruction disable bit of WDT re gister. Once the STP instruction is disabled, it cannot be enabled again except by RESET. Fig. 41 Block diagram of watchdog timer Fig. 42 Structure of watchdog timer register (φ is internal clock system) φ WDT interruptWD L counter (4) WD H counter (7) WDT 7 “F16”“ 7 F 16” WDT register (8) “0” “1” Not used (undefined when read) Stop instruction disable bit 0 : Stop instruction enabled 1 : Execute two NOP instructions instead (once this bit is set to “1” it can not be cleared to “0” again, except on RESET.) Upper byte count source selection bit 0 : Underflow of the low order counter 1 : φ divided by 256 Watchdog timer register (address 002E16) WDT

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER RESET CIRCUIT The 7630 group is reset according to the sequence shown in Fig. 44. It starts program execution from the address formed by the con- tents of the addresses FFFB16 and FFFA16, when the RESET pin is held at “L” level for more than 2 µs while the power supply voltage is in the recommended operating condition and then returned to “H” level. Refer to Fig. 43 for an example of the reset circuit. Fig. 43 Example of reset circuit Fig. 44 Reset sequence power on power source voltage reset input voltage 4.0V 0.8V 7630 group M51953AL RESET VSS VCC 0.1µF XIN RESET internal reset Address 28 to 34 cycles of XIN AD L AD H FFFA 16 FFFB 16 AD L, ADH 1st op code 20 cycles of XIN24 cycles of XIN 8192 cycles of XIN (T1, T2)

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Fig. 45 Internal status of microcomputer after reset Register Address Register contents Timer XH 001B16 FF16 Timer YL 001C 16 FF16 Timer YH 001D 16 FF16 Timer X mode reg. 001E16 0016 Timer Y mode reg. 001F16 0016 UART mode reg. 002016 0010 UART control reg. 002216 0016 UART status reg. 002316 0710 Port P0 pull-up control reg. 002816 0016 Port P1 pull-up control reg. 002916 0016 Port P2 pull-up control reg. 002A16 0016 Port P3 pull-up control reg. 002B16 0016 Port P4 pull-up/down control reg.002C 16 0016 Interrupt polarity selection reg.002D 16 0016 Watchdog timer reg. 002E16 3F16 Polarity control reg. 002F16 0016 CAN transmit control reg. 003016 0216 CAN bus timing control reg. 1 003116 0016 CAN bus timing control reg. 2 003216 0016 CAN receive control reg. 003D 16 0016 CAN transmit abort reg. 003E16 0016 Processor status reg. (PS) 0416 Program counter (high-order byte) (PCH) contents of FFFB16 Program counter (low-order byte) (PCL) contents of FFFA16 Register Address Register contents CPU mode reg. 000016 4816 Interrupt request reg. A 000216 0016 Interrupt request reg. B 000316 0016 Interrupt request reg. C 000416 0016 Interrupt control reg. A 000516 0016 Interrupt control reg. B 000616 0016 Interrupt control reg. C 000716 0016 Port P0 reg. 000816 0016 Port P0 direction reg. 000916 0016 Port P1 reg. 000A16 0016 Port P1 direction reg. 000B16 0016 Port P2 reg. 000C 16 0016 Port P2 direction reg. 000D 16 0016 Port P3 reg. 000E16 0016 Port P3 direction reg. 000F16 0016 Port P4 reg. 001016 0016 Port P4 direction reg. 001116 0016 Serial I/O control reg. 001316 0016 A-D control reg. 001516 0816 Timer 1 001616 FF16 Timer 2 001716 0116 Timer 3 001816 FF16 Timer 123 mode reg. 001916 4016 Timer XL 001A16 FF16 Note: The contents of RAM and registers other than the above registers are undefined after reset; thus software initialization is required.

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER CLOCK GENERATING CIRCUIT The 7630 group is equipped with an internal clock generating cir- cuit. Please refer to Fig. 46 for a circuit example using a ceramic resona- tor or quartz crystal oscillator. For the capacitor values, refer to the manufacturers recommended parameters which depend on each oscillators characteristics. When using an external clock, input it to the XIN pin and leave XOUT open. Fig. 46 Ceramic resonator circuit . Oscillation Control The 7630 group has two low power modes: the stop and the wait mode. Stop mode The microcomputer enters the stop mode by executin g the STP instruction. The oscillator stops with the internal clock φ at “H” level. Timers 1 and 2 will be cascaded and initialized by their reload latches contents. The count source for timer 1 will be set to f(X IN)/16. Oscillation is restarted if an external interrupt is accepted or at reset. When using an external interrupt, the internal clock φ remains at “H” level until timer 2 underflows allowing a time-out until the clock oscillation becomes stable. When using reset, a fixed time-out will be generated allowing oscillation to stabilize. Wait mode The microcomputer enters the wait mode by executing the WIT instruction. The internal clock ø stops at “H” level while the oscillator keeps running. Recovery from wait mode can be done in the same way as from stop mode. However, the time-out period mentioned above is not required to return from wait-mode, thus no such time-out mecha- nism has been implemented. Note: Set the interrupt enable bit of the interrupt source to be used to return from stop or wait mode to “1” before executin g STP or WIT instruction. Fig. 47 Block diagram of clock generating circuit C IN C OUT XIN XOUT WIT STP XIN XOUT CPUM 6 interrupt request interrupt disable flag S R QRESET delaySTP D T Q D T QR S Q R S Q R S Q STP internal clock for peripherals internal clock for CPU oscillator countdown (timer 1 and 2) φ φ “1” “0”

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER DATA REQUIRED FOR MASK ORDERS The following are necessary when ordering a mask ROM produc- tion:

1 Mask ROM Order Confirmation Form

2 Mark Specification Form

3 Contents of Mask ROM, in EPROM form (three identical

copies) PROM PROGRAMMING METHOD The built-in PROM of the blank One Time PROM version and built- in EPROM version can be read or pro grammed with a general pur- pose PROM programmer using a special programming adapter. Set the address of PROM programmer to the user ROM area. For the programming adapter type name, please refer to the follow- ing table: The PROM of the blank One Time PROM version is not tested or screened in the assembly process and following processes. To ensure proper operation after programming, the procedure shown in Fig. 48 is recommended to verify programming. Fig. 48 Programming and testing of One Time PROM version Table 6: Programming adapter name MCU type Packa geP r o gramming adapter type One Time PROM 44P6N-A PCA7430 EPROM 80D0 PCA7431 Programming with PROM programmer Screening *(Note) (150°C for 40 hours) Verification with PROM programmer Functional test in target unit Note on screening: The screening temperature is far higher than the storage temper- ature. Never subject the device to 150 °C exceeding 100 hours.

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Table 7: ABSOLUTE MAXIMUM RATINGS Table 8: RECOMMENDED OPERATING CONDITIONS Symbol Parameter Conditions Ratin gsU n i t VCC Power source voltage All voltages with respect to VSS and output transistors are “off”. –0.3 to 7.0 V VI Input voltageP 0 0—P0 7, P11—P1 7, P20—P2 7, P30—P3 4, P40—P4 7, RESET, XIN –0.3 to VCC + 0.3 V VO Output voltageP 0 0—P0 7, P12—P1 7, P20—P2 7, P30—P3 4, P40—P4 7, XOUT –0.3 to VCC + 0.3 V Pd Power dissipation Ta = 25 °C 500 mW Topr Operating temperature –40 to 85 °C Tstg Storage temperature –60 to 150 °C Symbol Parameter Limits Unit min. typ. max. VCC Power source voltage 4.0 5.0 5.5 V VSS 0V VIH “H” Input voltage P00—P0 7, P11—P1 7, P20—P2 7, P30—P3 4, P40—P4 7, RESET, XIN 0.8 · VCC VCC V VIL “L” Input voltage P00—P0 7, P11—P1 7, P20—P2 7, P30—P3 4, P40—P4 7, RESET, XIN 0 0.2 · VCC V ∑ IOH (peak) “H” sum peak output current P00—P0 7, P12—P1 7, P20—P2 7, P30—P3 4, P40—P4 7 –80 mA ∑ IOH (avg) “H” sum average output current –40 mA ∑ IOL (peak) “L” sum peak output current 80 mA ∑ IOL (avg) “L” sum average output current 40 mA IOH (peak) “H” peak output current –10 mA IOH (avg) “H” average output current –5 mA IOL (peak) “L” peak output current 10 mA IOL (avg) “L” average output current 5m A IIO input current at overvoltage condi- tion (VI > VCC ) P11—P1 7, P20—P2 7, P30—P3 4, P40—P4 7 1m A ∑ IIO total input current at overvoltage condition (VI > VCC ) P11—P1 7, P20—P2 7, P30—P3 4, P40—P4 7 16 mA f(CNTR) Timer input frequency (based on 50 % duty) P14/CNTR 0, P15/CNTR 1 (except bi-phase counter mode) f(XIN)/16 MHz P13/TX0, P14/CNTR 0 (bi-phase counter mode) f(XIN)/32 MHz f(XIN) Clock input oscillation frequency 10 MHz (VCC = 4.0 to 5.5 V, VSS = AVSS = 0 V, Ta = – 40 to 85 °C unless otherwise noted)

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Table 9: ELECTRICAL CHARACTERISTICS Symbol Parameter Test conditions Limits Unit min. typ. max. VOH “H” output voltage P00—P0 7, P12—P1 7, P20—P2 7, P30—P3 4, P40—P4 7 IOH = –5 mA 0.8 · V CC V VOL “L” output voltage P00—P0 7, P12—P1 7, P20—P2 7, P30—P3 4, P40—P4 7 IOL = 5 mA 2.0 V VT+ – VT– Hysteresis P11/INT0, P12/INT1, P13/TX0, P14/CNTR 0, P15/CNTR 1,P20/SIN, P22/SCLK , P26/URTS , P27/UCTS , P32/CRX, RESET 0.5 V IIH “H” input current P00—P0 7, P11—P1 7, P20—P2 7, P30—P3 4, P40—P4 7, RESET VI = VCC 5 µA IIH “H” input current XIN VI = VCC 4 µA IIL “L” input current P00—P0 7, P11—P1 7, P20—P2 7, P30—P3 4, P40—P4 7, RESET VI = VSS –5 µA IIL “L” input current XIN VI = VSS –4 µA IIH “H” input current P32, P40—P4 7 VI = VCC Pull-Down = ’On’ 20 200 µA IIL “L” input current P00—P0 7, P11—P1 7, P20—P2 7, P30—P3 4, P40—P4 7, RESET VI = VSS Pull-Up = ’On’ -200 -20 µA VRAM RAM hold voltage When clock stopped 2.0 V (VCC = 4.0 to 5.5 V, VSS = AVSS = 0 V, Ta = – 40 to 85 °C unless otherwise noted)

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER ICC Power source current high speed mode, f(XIN)=8 M H z , VCC =5 V , output transistors off, CAN module running, ADC running 11.0 18.0 mA high speed mode, f(XIN)=8 M H z , VCC =5 V , output transistors off, CAN module stopped, ADC running 9.0 16.0 mA middle speed mode, f(X IN)=8 M H z , VCC =5 V , output transistors off, CAN module running, ADC running 6.0 11.0 mA middle speed mode, wait mode, f(X IN)=8 M H z , VCC = 5V, output transis- tors off, CAN module stopped, ADC stopped 2.0 mA stop mode, f(XIN)=0 M H z , VCC =5 V , Ta =2 5°C 0.1 1.0 µA stop mode, f(XIN)=0 M H z , VCC =5 V , Ta =8 5°C 10.0 µA Symbol Parameter Test conditions Limits Unit min. typ. max. Table 10: A-D converter characteristics Symbol Parameter Test conditions Limits Unit min. typ. max. — Resolution 8B i t — Absolute accuracy ±1.0 ±2.5 LSB tCONV Conversion time high–speed mode 106 108 tC (XIN) middle–speed mode 424 432 tC (XIN) VREF Reference input voltage2 . 0 VCC V IREF Reference input current VCC = VREF = 5.12 V 150 200 µA R LADDER Ladder resistor value 35 k Ω IIAN Analog input current VI = VSS to VCC 0.5 5.0 µA (VCC = 4.0 to 5.5 V, VSS = AVSS = 0 V, Ta = –40 to 85 °C, unless otherwise noted)

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Table 11: Timing requirements Symbol Parameter Limits Unit min. typ. max. tW (RESET ) Reset input “L” pulse width 2 µs tC (XIN) External clock input cycle time 100 ns tWH (XIN) External clock input “H” pulse width 37 ns tWL (XIN) External clock input “L” pulse width 37 ns tC (CNTR) CNTR 0, CNTR1 input cycle time (except bi-phase counter mode) 1600 ns CNTR 0 input cycle time (bi-phase counter mode) 2000 ns tWH (CNTR) CNTR 0, CNTR1 input “H” pulse width (except bi-phase counter mode) 800 ns CNTR 0 input “H” pulse width (bi-phase counter mode)1000 ns tWL (CNTR) CNTR 0, CNTR1 input “L” pulse width (except bi-phase counter mode) 800 ns CNTR 0 input “L” pulse width (bi-phase counter mode)1000 ns tL(CNTR 0-TX0) Lag of CNTR0 and TX0 input edges (bi-phase counter mode) 500 ns tC (TX0)T X 0 input cycle time (bi-phase counter mode) 3200 ns tWH (TX0)T X 0 input “H” pulse width (bi-phase counter mode) 1600 ns tWL (TX0)T X 0 input “L” pulse width (bi-phase counter mode) 1600 ns tWH (INT) INT 0, INT1 input “H” pulse width 460 ns tWL (INT) INT 0, INT1 input “L” pulse width 460 ns tC (SCLK ) Serial I/O clock input cycle time 8·tC (XIN) ns tWH (SCLK ) Serial I/O clock input “H” pulse width 4·tC (XIN) ns tWL (SCLK ) Serial I/O clock input “L” pulse width 4·tC (XIN) ns tSU (SIN–SCLK ) Serial I/O input setup time 200 ns tH (SCLK –SIN) Serial I/O input hold time 150 ns (VCC =4.0 to 5.5 V, VSS =AV SS =0 V, Ta=–40 to 85 °C unless otherwise noted)

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Fig. 49 Circuit for measuring output switching characteristics Table 12: Switching characteristics Symbol Parameter Limits Unit min. typ. max. tWH (SCLK ) Serial I/O clock output “H” pulse width 0.5 · t C (SCLK )–5 0 ns tWL (SCLK ) Serial I/O clock output “L” pulse width 0.5 · t C (SCLK )–5 0 ns tD (SCLK –SOUT ) Serial I/O output delay time 50 ns tV(SCLK –SOUT ) Serial I/O output valid time 0 50 ns tR (SCLK ) Serial I/O clock output rise time 50 ns tR (CMOS) CMOS output rise time 10 50 ns tF(CMOS) CMOS output fall time 10 50 ns measurement output pin 100 pF CMOS output (VCC = 4.0 to 5.5 V, VSS = AVSS = 0 V, Ta = –40 to 85 °C, unless otherwise noted)

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER TIMING DIAGRAM Fig. 50 Timing diagram tWL (INT)tWH (INT) 0.8·VCC 0.2·VCC tWL (RESET ) 0.2·VCC tWL (XIN)tWH (XIN) 0.8·VCC 0.2·VCC tC (XIN) 0.8·VCC 0.2·VCC tWL (SCLK )t WH (SCLK ) tC (SCLK ) tF tR 0.2·VCC 0.8·VCC tSU (SIN-SCLK ) tH (SCLK -SIN) tD (SCLK -SOUT )t V(SCLK -SOUT ) SOUT SIN SCLK XIN RESET INT0, INT1 tWL (CNTR)tWH (CNTR) 0.8·VCC 0.2·VCC CNTR 0, CNTR1 tC (CNTR) tWL (TX0)tWH (TX0) 0.8·VCC 0.2·VCC TX 0 tC (TX0)

1Revision Report M37630 E4/M4 REVISION

7630 English Data Sheets

REVISION DATE Page MODIFICATIONS 1.1 10. 98 “CAN controller” is replaced by “CAN module” in whole document. 11 11 Schematics (8) and (11) are corrected. 18 18 Replaced: “PUPD j” with “PUP4j” 26 26 Replaced: “UT X D” with “SOUT” Replaced: “URX D” with “SIN” 38 38 Replaced: “FFFB H ” with “FFFB16” Replaced: “FFFAH ” with “FFFA16”

41 Replaced: “44P6N” with “44P6N-A)

(1.2) 13.01.99 43 43 Values changed:Iih(35, 113) to (20, 200) and Iil(-122, -70) to (-200, -20); typical values are removed. 10 10 Schematic (1) is modified. 35 35 Fig. 39 is modified. New Old