M37516RSS

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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

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M38503MXH MITSUBISHI | Alldatasheet

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3850 Group (Spec. H) SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS

DESCRIPTION

The 3850 group (spec. H) is the 8-bit microcomputer based on the 740 family core technology. The 3850 group (spec. H) is designed for the household products and office automation equipment and includes serial I/O functions, 8-bit timer, and A-D converter.

FEATURES

(at 8 MHz oscillation frequency) G Memory size (connect to external ceramic resonator or quartz-crystal oscillator) PIN CONFIGURATION (TOP VIEW) Fig. 1 M38503MXH-XXXFP/SP pin configuration G Power source voltage (at 8 MHz oscillation frequency) (at 8 MHz oscillation frequency) (at 32 kHz oscillation frequency) G Power dissipation (at 8 MHz oscillation frequency, at 5 V power source voltage) (at 32 kHz oscillation frequency, at 3 V power source voltage) APPLICATION Office automation equipment, FA equipment, Household products, Consumer electronics, etc. P 40/ C N T R 1 P 41/ I N T0 P 42/ I N T1 P43/INT2/SCMP2 A VS S P44/INT3/PWM VR E F VC C P 00/ SI N P 04 P 05 P 06 P 07 P 11/ ( L E D 1) P 12/ ( L E D 2) P13/(LED3) P 14/ ( L E D 4) P 15/ ( L E D 5) P10/(LED0) P 01/ SO U T P02/SCLK2 P31/AN1 P 32/ A N 2 P 30/ A N 0 P 33/ A N 3 P34/AN4 P 03/ SR D Y M 3 8 5 0 3 M X H - X X X F P / S P P 16/ ( L E D 6) P 17/ ( L E D 7) P 27/ C N T R 0/ SR D Y P 26/ SC L K P 25/ T x D P24/RxD P23 P 22 C N VS S P 21/ XC I N P20/XCOU T RESE T XI N XO U T VS S VP P : Flash memory version

3850 Group (Spec. H) SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS FUNCTIONAL BLOCK DIAGRAM Fig. 2 Functional block diagram FUNCTIONAL BLOCK I N T0– VR E F A VS S R A M R O M C P U A X Y S P C H P C L P S V S S 2 1 R E S E T 1 8 V C C 1 1 5 C N V S S X I N 1 9 2 0 S I O R e s e t i n p u t C l o c k g e n e r a t i n g c i r c u i t M a i n c l o c k i n p u t M a i n c l o c k o u t p u t A D c o n v e r t e r C N T R C N T R T i m e r Y T i m e r X P r e s c a l e r P r e s c a l e r X P r e s c a l e r Y T i m e r T i m e r S u b c l o c k i n p u t X O U T X C I N X C O U T S u b c l o c k o u t p u t W a t c h d o g t i m e r R e s e t P 2 P 3 I / O p o r t P I / O p o r t P P 4 I / O p o r t P I N 3 9 4 1 3 8 4 0 4 2 1 1 1 3 1 7 1 0 1 2 1 41 6 P 1 I / O p o r t P 2 2 2 4 2 6 2 8 2 3 2 5 2 7 2 9 P 0 I / O p o r t P 3 03 13 2 3 33 43 53 63 7 P W M XC I NXC O U T S I O

3850 Group (Spec. H) SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS VCC , VSS PIN DESCRIPTION FunctionsNamePin

Apply voltage of 2.7 V – 5.5 V to Vcc, and 0 V to Vss.
This pin controls the operation mode of the chip.
Normally connected to VSS .
Reset input pin for active “L.”
Input and output pins for the clock generating circuit.
Connect a ceramic resonator or quartz-crystal oscillator between the XIN and XOUT pins to set the oscillation frequency.
When an external clock is used, connect the clock source to the XIN pin and leave the XOUT pin open.
8-bit CMOS I/O port.
I/O direction register allows each pin to be individually programmed as either input or output.
CMOS compatible input level.
CMOS 3-state output structure.
P10 to P17 (8 bits) are enabled to output large current for LED drive. Power source Table 1 Pin description Function except a port function Clock input Clock output I/O port P0 CNV SS inputCNV SS RESET Reset input XIN XOUT P00/SIN2 P01/SOUT2 P02/SCLK2 P03/SRDY2 P04–P07 I/O port P1P10–P17
Serial I/O2 function pin
Sub-clock generating circuit I/O pins (connect a resonator) I/O port P2 I/O port P3 I/O port P4
8-bit CMOS I/O port.
I/O direction register allows each pin to be individually programmed as either input or output.
CMOS compatible input level.
P20, P21, P24 to P27: CMOS3-state output structure.
P22, P23: N-channel open-drain structure.
Serial I/O1 function pin
Serial I/O1 function pin/ Timer X function pin
A-D converter input pin
Timer Y function pin
Interrupt input pins
Interrupt input pin
SCMP2 output pin
Interrupt input pin
PWM output pin
8-bit CMOS I/O port with the same function as port P0.
CMOS compatible input level.
CMOS 3-state output structure.
8-bit CMOS I/O port with the same function as port P0.
CMOS compatible input level.
CMOS 3-state output structure. P20/XCOUT P21/XCIN P22 P23 P24/RxD P25/TxD P26/SCLK P27/CNTR 0/ SRDY1 P30/AN0– P34/AN4 P40/CNTR 1 P41/INT0 P42/INT1 P43/INT2/SCMP2 P44/INT3/PWM

3850 Group (Spec. H) SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS PART NUMBERING Fig. 3 Part numbering M 3 8 5 03 M 4 H – X X XS PP r o d u c t n a m e Package type SP : 42P4B FP : 42P2R-A/E SS : 42S1B-A ROM number Omitted in One Time PROM version shipped in blank, EPROM version, and flash memory version. ROM/PROM/Flash memory size : 4 0 9 6 b y t e s b y t e s b y t e s b y t e s b y t e s b y t e s b y t e s b y t e s The first 128 bytes and the last 2 bytes of ROM are reserved areas ; they cannot be used as a user’s ROM area. However, they can be programmed or erased in the flash memory version, so that the users can use them. Memory type M : Mask ROM version E : EPROM or One Time PROM version F : Flash memory version R A M s i z e : 192 bytes : 256 bytes : 384 bytes : 512 bytes : 640 bytes – : standard Omitted in One Time PROM version shipped in blank, EPROM version, and flash memory version. H –: Partial specification changed version : 3 6 8 6 4 b y t e s b y t e s b y t e s b y t e s b y t e s b y t e s b y t e s A B C D E F : 7 6 8 b y t e s b y t e s b y t e s b y t e s b y t e s

3850 Group (Spec. H) SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS GROUP EXPANSION Mitsubishi plans to expand the 3850 group (spec. H) as follows. Memory Type Support for mask ROM, One Time PROM, and flash memory ver- sions. Memory Size Packages Fig. 4 Memory expansion plan Memory Expansion Plan 32K 28K 24K 20K 1 6 K 1 2 K 8 K 3 8 45 1 2 640 7 6 8 896 1024 1152 1280 1408 1 5 3 6 2048 R O M e x t e r a n a l R O M s i z e ( b y t e s ) RAM size (bytes) A s o f N o v . 2 0 0 0 M38507M8/F8 M38504M6/E6 M 3 8 5 0 3 M 4 H M 3 8 5 0 3 M 2 H U n d e r d e v e l o p m e n t Products under development or planning: the development schedule and specification may be revised without notice. The development of planning products may be stopped. M a s s p r o d u c t i o n M a s s p r o d u c t i o n Mass production

3850 Group (Spec. H) SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS Currently planning products are listed below. RAM size (bytes) RemarksPackage Table 2 Support products Product name As of Nov. 2000 24576 (24446) ROM size (bytes) ROM size for User in ( ) M38503M2H-XXXSP M38503M2H-XXXFP M38503M4H-XXXSP M38503M4H-XXXFP M38504M6-XXXSP M38504E6-XXXSP M388504E6SP M388504E6SS M38504M6-XXXFP M38504E6-XXXFP M38504E6FP 42P4B 42P2R-A/E 424P4B 42P2R-A/E 424P4B 42S1B-A 42P2R-A/E Mask ROM version Mask ROM version Mask ROM version Mask ROM version Mask ROM version One Time PROM version One Time PROM version (blank) EPROM version Mask ROM version One Time PROM version One Time PROM version (blank) 8192 (8062) 512 16384 (16254) 640 512 Table 3 3850 group (standard) and 3850 group (spec. H) corresponding products 3850 group (standard) M38503M2-XXXFP/SP M38503M4-XXXFP/SP M38503E4-XXXFP/SP M38503E4FP/SP M38503E4SS 3850 group (spec. H) M38503M2H-XXXFP/SP M38503M4H-XXXFP/SP M38504M6-XXXFP/SP M38504E6-XXXFP/SP M38504E6FP/SP M38504E6SS M38507M8-XXXFP/SP M38507F8FP/SP M37516RSS Table 4 Differences between 3850 group (standard) and 3850 group (spec. H) Serial I/O A-D converter Large current port 3850 group (standard) 1: Serial I/O (UART or Clock-synchronized) Unserviceable in low-speed mode 5: P13–P17 3850 group (spec. H) 2: Serial I/O1 (UART or Clock-synchronized) Serial I/O2 (Clock-synchronized) Serviceable in low-speed mode 8: P1 0–P17 Notes on differences between 3850 group (standard) and 3850 group (spec. H) (1) The absolute maximum ratings of 3850 group (spec. H) is smaller than that of 3850 group (standard).

Power source voltage Vcc = –0.3 to 6.5 V
CNVss input voltage VI = –0.3 to Vcc +0.3 V (2) The oscillation circuit constants of XIN-XOUT , XCIN-XCOUT may be some differences between 3850 group (standard) and 3850 group (spec. H). (3) Do not write any data to the reserved area and the reserved bit. (Do not change the contents after rest.) (4) Fix bit 3 of the CPU mode register to “1”. (5) Be sure to perform the termination of unused pins.

3850 Group (Spec. H) SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS FUNCTIONAL DESCRIPTION CENTRAL PROCESSING UNIT (CPU) The 3850 group (spec. H) uses the standard 740 Family instruc- tion set. Refer to the table of 740 Family addressing modes and machine instructions or the 740 Family Software Manual for de- tails on the instruction set. Machine-resident 740 Family instructions are as follows: The FST and SLW instructions cannot be used. The STP , WIT, MUL, and DIV instructions can be used. [Accumulator (A)] The accumulator is an 8-bit register. Data operations such as data transfer, etc., are executed mainly through the accumulator. [Index Register X (X)] The index register X is an 8-bit register. In the index addressing modes, the value of the OPERAND is added to the contents of register X and specifies the real address. [Index Register Y (Y)] The index register Y is an 8-bit register. In partial instruction, the value of the OPERAND is added to the contents of register Y and specifies the real address. [Stack Pointer (S)] The stack pointer is an 8-bit register used during subroutine calls and interrupts. This register indicates start address of stored area (stack) for storing registers during subroutine calls and interrupts. The low-order 8 bits of the stack address are determined by the contents of the stack pointer. The high-order 8 bits of the stack ad- dress are determined by the stack page selection bit. If the stack page selection bit is “0” , the high-order 8 bits becomes “00 16”. If the stack page selection bit is “1”, the high-order 8 bits becomes “0116”. The operations of pushing register contents onto the stack and popping them from the stack are shown in Figure 6. Store registers other than those described in Figure 6 with pro- gram when the user needs them during interrupts or subroutine calls. [Program Counter (PC)] The program counter is a 16-bit counter consisting of two 8-bit registers PC H and PCL. It is used to indicate the address of the next instruction to be executed. Fig. 5 740 Family CPU register structure A Accumulator b7 b0 b7b15 b0 b7 b0 X Index register X Y Index register Y S Stack pointer PC L Program counterPC H N V T B D I Z C Processor status register (PS) Carry flag Zero flag Interrupt disable flag Decimal mode flag Break flag Index X mode flag Overflow flag Negative flag

3850 Group (Spec. H) SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS Table 5 Push and pop instructions of accumulator or processor status register Accumulator Processor status register Push instruction to stack PHA PHP Pop instruction from stack PLA PLP Fig. 6 Register push and pop at interrupt generation and subroutine call Note: Condition for acceptance of an interrupt Interrupt enable flag is “1” Execute JSR On-going Routine M S P C H ) S S M (S) (PC L) E x e c u t e R T S (PCL)M ( S ) S S (S) (S) + 1 S S P C H )M S Subroutine POP return address from stack P u s h r e t u r n a d d r e s s o n s t a c k M (S) (PS) Execute RTI (PS) M (S) (S) (S) – 1 (S) (S) + 1 I n t e r r u p t S e r v i c e R o u t i n e P O P c o n t e n t s o f p r o c e s s o r s t a t u s r e g i s t e r f r o m s t a c k M S P C H ) S S M (S) (PC L) (S) (S) – 1 (PCL)M ( S ) S S S S P C H )M S P O P r e t u r n a d d r e s s f r o m s t a c k I F l a g i s s e t f r o m t o F e t c h t h e j u m p v e c t o r P u s h r e t u r n a d d r e s s o n s t a c k P u s h c o n t e n t s o f p r o c e s s o r s t a t u s r e g i s t e r o n s t a c k I n t e r r u p t r e q u e s t N o t e Interrupt disable flag is “0”

3850 Group (Spec. H) SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS [Processor status register (PS)] The processor status register is an 8-bit register consisting of 5 flags which indicate the status of the processor after an arithmetic operation and 3 flags which decide MCU operation. Branch opera- tions can be performed by testing the Carry (C) flag , Zero (Z) flag, Overflow (V) flag, or the Negative (N) flag. In decimal mode, the Z, V, N flags are not valid.

Bit 0: Carry flag (C) The C flag contains a carry or borrow generated by the arithmetic logic unit (ALU) immediately after an arithmetic operation. It can also be changed by a shift or rotate instruction.
Bit 1: Zero flag (Z) The Z flag is set if the result of an immediate arithmetic operation or a data transfer is “0”, and cleared if the result is anything other than “0”.
Bit 2: Interrupt disable flag (I) The I flag disables all interrupts except for the interrupt generated by the BRK instruction. Interrupts are disabled when the I flag is “1”.
Bit 3: Decimal mode flag (D) The D flag determines whether additions and subtractions are executed in binary or decimal. Binary arithmetic is executed when this flag is “0”; decimal arithmetic is executed when it is “1”. Decimal correction is automatic in decimal mode. Only the ADC and SBC instructions can be used for decimal arithmetic.
Bit 4: Break flag (B) The B flag is used to indicate that the current interrupt was generated by the BRK instruction. The BRK flag in the processor status register is always “0”. When the BRK instruction is used to generate an interrupt, the processor status register is pushed onto the stack with the break flag set to “1”.
Bit 5: Index X mode flag (T) When the T flag is “0”, arithmetic operations are performed between accumulator and memory. When the T flag is “1”, direct arithmetic operations and direct data transfers are enabled between memory locations.
Bit 6: Overflow flag (V) The V flag is used during the addition or subtraction of one byte of signed data. It is set if the result exceeds +127 to -128. When the BIT instruction is executed, bit 6 of the memory location operated on by the BIT instruction is stored in the overflow flag.
Bit 7: Negative flag (N) The N flag is set if the result of an arithmetic operation or data transfer is negative. When the BIT instruction is executed, bit 7 of the memory location operated on by the BIT instruction is stored in the negative flag. Table 6 Set and clear instructions of each bit of processor status register Set instruction Clear instruction C flag Z flag I flag D flag B flag T flag V flag N flag SEC CLC SEI CLI SED CLD SET CLT CLV _ _

3850 Group (Spec. H) SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS [CPU Mode Register (CPUM)] 003B16 The CPU mode register contains the stack page selection bit, etc. The CPU mode register is allocated at address 003B16. Fig. 7 Structure of CPU mode register C P U m o d e r e g i s t e r (CPUM : address 003B16) b 7 b0 S t a c k p a g e s e l e c t i o n b i t p a g e p a g e F i x t h i s b i t t o “ 1 ” . P r o c e s s o r m o d e b i t s b b S i n g l e c h i p m o d e N o t a v a i l a b l e P o r t XC s w i t c h b i t I O p o r t f u n c t i o n s t o p o s c i l l a t i n g XC I N – XC O U T o s c i l l a t i n g f u n c t i o n Main clock (XIN–XOUT ) stop bit 0 : Oscillating 1 : Stopped Main clock division ratio selection bits b7 b6 0 0 : φ = f(X IN)/2 (high-speed mode) 0 1 : φ = f(XIN)/8 (middle-speed mode) 1 0 : φ = f(XCIN)/2 (low-speed mode) 1 1 : Not available

3850 Group (Spec. H) SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS MEMORY Special Function Register (SFR) Area The Special Function Register area in the zero page contains control registers such as I/O ports and timers. RAM RAM is used for data storage and for stack area of subroutine calls and interrupts. ROM The first 128 bytes and the last 2 bytes of ROM are reserved for device testing and the rest is user area for storing programs. Interrupt Vector Area The interrupt vector area contains reset and interrupt vectors. Zero Page Access to this area with only 2 bytes is possible in the zero page addressing mode. Special Page Access to this area with only 2 bytes is possible in the special page addressing mode. Fig. 8 Memory map diagram 0 1 0 01 000016 0 0 4 01 FF0016 F F D C 1 FFFE 16 FFFF 16 1 9 2 X X X X1 0 0 F F1 B B B 4 0 9 6 F 0 0 01 E D C B A F 0 8 01 E D C B A Y Y Y Y1 ZZZZ 16 RAM R O M 0FF016 0FFF 16 SFR area Not used I n t e r r u p t v e c t o r a r e a ROM area R e s e r v e d R O M a r e a b y t e s Z e r o p a g e Special page RAM area R A M s i z e b y t e s A d d r e s s X X X R O M s i z e b y t e s Address YYYY 16 Reserved ROM area Address ZZZZ 16 N o t u s e d SFR area (Note) N o t e : F l a s h m e m o r y v e r s i o n o n l y

3850 Group (Spec. H) SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS Fig. 9 Memory map of special function register (SFR) 0 0 2 01 0 0 2 11 0 0 2 21 002316 0 0 2 41 0 0 2 51 0 0 2 61 0 0 2 71 0 0 2 81 0 0 2 91 0 0 2 A1 0 0 2 B1 0 0 2 C 1 0 0 2 D 1 0 0 2 E1 0 0 2 F1 003016 0 0 3 11 0 0 3 21 003316 0 0 3 41 0 0 3 51 003616 003716 0 0 3 81 003916 003A16 0 0 3 B1 0 0 3 C 1 003D 16 0 0 3 E1 0 0 3 F1 0 0 0 01 0 0 0 11 0 0 0 21 000316 0 0 0 41 0 0 0 51 0 0 0 61 0 0 0 71 0 0 0 81 0 0 0 91 0 0 0 A1 0 0 0 B1 0 0 0 C 1 0 0 0 D 1 0 0 0 E1 0 0 0 F1 001016 0 0 1 11 0 0 1 21 001316 0 0 1 41 0 0 1 51 001616 001716 0 0 1 81 001916 001A16 0 0 1 B1 0 0 1 C 1 001D 16 0 0 1 E1 0 0 1 F1 P o r t P 0 ( P 0 ) P o r t P 0 d i r e c t i o n r e g i s t e r ( P 0 D ) P o r t P 1 ( P 1 ) P o r t P 1 d i r e c t i o n r e g i s t e r ( P 1 D ) P o r t P 2 ( P 2 ) P o r t P 2 d i r e c t i o n r e g i s t e r ( P 2 D ) Port P3 (P3) P o r t P 3 d i r e c t i o n r e g i s t e r ( P 3 D ) P o r t P 4 ( P 4 ) P o r t P 4 d i r e c t i o n r e g i s t e r ( P 4 D ) T r a n s m i t / R e c e i v e b u f f e r r e g i s t e r ( T B / R B ) Serial I/O1 status register (SIOSTS) S e r i a l I / O 1 c o n t r o l r e g i s t e r ( S I O C O N ) U A R T c o n t r o l r e g i s t e r ( U A R T C O N ) B a u d r a t e g e n e r a t o r ( B R G ) Interrupt control register 2 (ICON2) A-D conversion low-order register (ADL) Prescaler Y (PREY) Timer Y (TY) A-D control register (ADCON) A-D conversion high-order register (ADH) Interrupt edge selection register (INTEDGE) CPU mode register (CPUM) Interrupt request register 1 (IREQ1) Interrupt request register 2 (IREQ2) Interrupt control register 1 (ICON1) Prescaler 12 (PRE12) Timer 2 (T2) Prescaler X (PREX) Timer X (TX) Timer 1 (T1) Timer XY mode register (TM) Reserved ✽ MISRG Watchdog timer control register (WDTCON) P W M c o n t r o l r e g i s t e r ( P W M C O N ) P W M p r e s c a l e r ( P R E P W M ) P W M r e g i s t e r ( P W M ) T i m e r c o u n t s o u r c e s e l e c t i o n r e g i s t e r ( T C S S ) Serial I/O2 control register 1 (SIO2CON1) S e r i a l I / O 2 c o n t r o l r e g i s t e r 2 ( S I O 2 C O N 2 ) Serial I/O2 register (SIO2) R e s e r v e d D o n o t w r i t e a n y d a t a t o t h i s a d d r e s s e s b e c a u s e t h e s e a r e a s a r e r e s e r v e d Reserved ✽ Reserved ✽ Reserved ✽ Reserved ✽ Reserved ✽ Reserved ✽ Reserved ✽ R e s e r v e d Reserved ✽ Reserved ✽

3850 Group (Spec. H) SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS I/O PORTS The I/O ports have direction registers which determine the input/ output direction of each individual pin. Each bit in a direction register corresponds to one pin, and each pin can be set to be input port or output port. When “0” is written to the bit corresponding to a pin, that pin becomes an input pin. When “1” is written to that bit, that pin becomes an output pin. If data is read from a pin which is set to output, the value of the port output latch is read, not the value of the pin itself. Pins set to input are floating. If a pin set to input is written to, only the port output latch is written to and the pin remains floating. Pin Name Input/Output I/O Structure Non-Port Function Table 7 I/O port function Related SFRs Port P0 Port P1 Port P2 P00/SIN2 P01/SOUT2 P02/SCLK2 P03/SRDY2 P04–P07 P10–P17 P20/XCOUT P21/XCIN P22 P23 P24/RxD P25/TxD P26/SCLK P27/CNTR 0/SRDY1 P30/AN0– P34/AN4 P40/CNTR 1 P41/INT0 P42/INT1 P43/INT2/SCMP2 CMOS compatible input level CMOS 3-state output Serial I/O2 function I/O Serial I/O2 control register Sub-clock generating circuit CPU mode register CMOS compatible input level CMOS 3-state output Input/output, individual bits Interrupt edge selection register PWM control register External interrupt input PWM output Ref.No. (5) (1) (2) (3) (4) (6) (7) (8) (9) (10) (11) (17) CMOS compatible input level N-channel open-drain output Serial I/O1 control registerSerial I/O1 function I/O Serial I/O1 function I/O Timer X function I/O Serial I/O1 control register Timer XY mode register (12) Timer Y function I/O A-D conversion input A-D control register Timer XY mode register (13) (14) (15) (16) Interrupt edge selection register External interrupt input External interrupt input S CMP2 output Interrupt edge selection register Serial I/O2 control register P44/INT3/PWM Port P3 Port P4

3850 Group (Spec. H) SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS Fig. 10 Port block diagram (1) P o r t l a t c h P o r t P 00 ( P o r t P P01/SOUT2 P-channel output disable bit P 02/ SC L K P c h a n n e l o u t p u t d i s a b l e b i t D i r e c t i o n r e g i s t e r Port latch D i r e c t i o n r e g i s t e r Port latch D i r e c t i o n r e g i s t e r P o r t l a t c h D i r e c t i o n r e g i s t e r Port latch Direction register D i r e c t i o n r e g i s t e r P o r t l a t c h Direction register P o r t l a t c h Direction register Port latch Data bus D a t a b u s Data bus Data bus Data bus Data bus S e r i a l I / O 2 i n p u t S e r i a l I / O 2 o u t p u t Serial I/O2 Transmit completion signal Serial I/O2 port selection bit (3) Port P02 S e r i a l I O s y n c h r o n o u s c l o c k s e l e c t i o n b i t Serial I/O2 port selection bit S e r i a l I O c l o c k o u t p u t S e r i a l I / O 2 e x t e r n a l c l o c k i n p u t P o r t P S e r i a l I / O 2 r e a d y o u t p u t SRDY2 output enable bit (5) Ports P04-P07,P1 ( P o r t P Port XC switch bit O s c i l l a t o r Port XC switch bit Port P21 P o r t P P o r t XC s w i t c h b i t D a t a b u s S u b - c l o c k g e n e r a t i n g c i r c u i t i n p u t P o r t s P Data bus

3850 Group (Spec. H) SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS Fig. 11 Port block diagram (2) Port latch Direction register Data bus (9) Port P24 Port latch Direction register Data bus Port latch Direction register Data bus Port latch Direction register Data bus Port latch Direction register Data bus Port latch Direction register Data bus Port latch Direction register Data bus Port latch Direction register Data bus Serial I/O1 enable bit Receive enable bit Serial I/O1 input (11) Port P26 Serial I/O1 synchronous clock selection bit Serial I/O1 enable bit Serial I/O1 enable bit Serial I/O1 mode selection bit Serial I/O1 clock output External clock input (13) Ports P30-P34 A-D converter input Analog input pin selection bit (15) Ports P41,P42 Interrupt input (10) Port P25 P-channel output disable bit Serial I/O1 enable bit Transmit enable bit Serial I/O1 output (12) Port P27 Serial I/O1 enable bit Serial I/O1 mode selection bit Pulse output mode SRDY1 output enable bit Timer output CNTR 0 interrupt input Serial ready output Pulse output mode (14) Port P40 Timer output CNTR 1 interrupt input Pulse output mode (16) Port P43 Interrupt input Serial I/O2 I/O comparison signal control bit Serial I/O2 I/O comparison signal output

3850 Group (Spec. H) SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS Fig. 12 Port block diagram (3) (17) Port P44 PWM output Data bus PWM output enable bit Interrupt input Port latch Direction register

3850 Group (Spec. H) SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS INTERRUPTS Interrupts occur by 15 sources among 15 sources: six external, eight internal, and one software. Interrupt Control Each interrupt is controlled by an interrupt request bit, an interrupt enable bit, and the interrupt disable flag except for the software in- terrupt set by the BRK instruction. An interrupt occurs if the corresponding interrupt request and enable bits are “1” and the in- terrupt disable flag is “0”. Interrupt enable bits can be set or cleared by software. Interrupt request bits can be cleared by software, but cannot be set by software. The BRK instruction cannot be disabled with any flag or bit. The I (interrupt disable) flag disables all interrupts except the BRK in- struction interrupt. When several interrupts occur at the same time, the interrupts are received according to priority. Interrupt Operation By acceptance of an interrupt, the following operations are auto- matically performed: 1. The contents of the program counter and the processor status register are automatically pushed onto the stack. 2. The interrupt disable flag is set and the corresponding interrupt request bit is cleared. 3. The interrupt jump destination address is read from the vector table into the program counter. I Notes When the active edge of an external interrupt (INT0–INT3, CNTR0, CNTR 1) is set, the corresponding interrupt request bit may also be set. Therefore, take the following sequence: 1. Disable the interrupt 2. Change the interrupt edge selection register (the timer XY mode register for CNTR 0 and CNTR1) 3. Clear the interrupt request bit to “0” 4. Accept the interrupt.

3850 Group (Spec. H) SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS Interrupt Request Generating Conditions RemarksInterrupt Source Low FFFC 16 High FFFD 16 Priority Table 8 Interrupt vector addresses and priority Notes 1: Vector addresses contain interrupt jump destination addresses. 2: Reset function in the same way as an interrupt with the highest priority. Vector Addresses (Note 1) Reset (Note 2) INT0 Reserved INT1 INT2 INT3/ Serial I/O2 Reserved Timer X Timer Y Timer 1 Timer 2 Serial I/O1 reception Serial I/O1 transmission CNTR CNTR 1 A-D converter BRK instruction At reset At detection of either rising or falling edge of INT0 input At detection of either rising or falling edge of INT1 input At detection of either rising or falling edge of INT2 input At detection of either rising or falling edge of INT3 input/ At completion of serial I/O2 data reception/transmission Reserved At completion of serial I/O1 data reception At completion of serial I/O1 transfer shift or when transmis- sion buffer is empty At timer X underflow At timer Y underflow At timer 1 underflow At timer 2 underflow Non-maskable External interrupt (active edge selectable) Valid when serial I/O1 is selected Valid when serial I/O1 is selected External interrupt (active edge selectable) STP release timer underflow External interrupt (active edge selectable) Reserved At detection of either rising or falling edge of CNTR 0 input At detection of either rising or falling edge of CNTR1 input At completion of A-D conversion At BRK instruction execution External interrupt (active edge selectable) External interrupt (active edge selectable) External interrupt (active edge selectable) Switch by Serial I/O2/INT interrupt source bit FFFA 16 FFF8 16 FFF6 16 FFF4 16 FFF2 16 FFF0 16 FFEE 16 FFEC 16 FFEA 16 FFE8 16 FFE6 16 FFE4 16 FFE2 16 FFE0 16 FFDE 16 FFFB 16 FFF9 16 FFF7 16 FFF5 16 FFF3 16 FFF1 16 FFEF 16 FFED 16 FFEB 16 FFE9 16 FFE7 16 FFE5 16 FFE3 16 FFE1 16 FFDF 16 FFDC 16FFDD 16

17 Non-maskable software interrupt

3850 Group (Spec. H) SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS Fig. 13 Interrupt control Fig. 14 Structure of interrupt-related registers I n t e r r u p t d i s a b l e f l a g ( I ) I n t e r r u p t r e q u e s t I n t e r r u p t r e q u e s t b i t Interrupt enable bit BRK instruction Reset b 7 b 0 b 7 b 0 b7 b0 b7 b0 b7 b0 I n t e r r u p t e d g e s e l e c t i o n r e g i s t e r I N T0 a c t i v e e d g e s e l e c t i o n b i t I N a c t i v e e d g e s e l e c t i o n b i t I N a c t i v e e d g e s e l e c t i o n b i t I N a c t i v e e d g e s e l e c t i o n b i t S e r i a l I O I N i n t e r r u p t s o u r c e b i t I N i n t e r r u p t s e l e c t e d S e r i a l I O i n t e r r u p t s e l e c t e d N o t u s e d r e t u r n s w h e n r e a d ( I N T E D G E : a d d r e s s 0 0 3 A1 0 : Falling edge active 1 : Rising edge active I n t e r r u p t r e q u e s t r e g i s t e r 1 I N T0 i n t e r r u p t r e q u e s t b i t R e s e r v e d I N i n t e r r u p t r e q u e s t b i t I N i n t e r r u p t r e q u e s t b i t I N T3 / S e r i a l I O i n t e r r u p t r e q u e s t b i t R e s e r v e d T i m e r X i n t e r r u p t r e q u e s t b i t T i m e r Y i n t e r r u p t r e q u e s t b i t 0 : No interrupt request issued 1 : Interrupt request issued ( I R E Q 1 : a d d r e s s 0 0 3 C 1 Interrupt request register 2 Timer 1 interrupt request bit Timer 2 interrupt request bit Serial I/O1 reception interrupt request bit Serial I/O1 transmit interrupt request bit CNTR 0 interrupt request bit CNTR 1 interrupt request bit AD converter interrupt request bit Not used (returns “0” when read) (IREQ2 : address 003D 16) 0 : N o i n t e r r u p t r e q u e s t i s s u e d I n t e r r u p t r e q u e s t i s s u e d Interrupt control register 1 I N T0 i n t e r r u p t e n a b l e b i t R e s e r v e d D o n o t w r i t e t o t h i s b i t I N i n t e r r u p t e n a b l e b i t I N i n t e r r u p t e n a b l e b i t I N T3 / S e r i a l I O 2 i n t e r r u p t e n a b l e b i t R e s e r v e d D o n o t w r i t e t o t h i s b i t T i m e r X i n t e r r u p t e n a b l e b i t T i m e r Y i n t e r r u p t e n a b l e b i t ( I C O N 1 : a d d r e s s 0 0 3 E1 I n t e r r u p t c o n t r o l r e g i s t e r 2 Timer 1 interrupt enable bit Timer 2 interrupt enable bit Serial I/O1 reception interrupt enable bit Serial I/O1 transmit interrupt enable bit CNTR 0 interrupt enable bit CNTR 1 interrupt enable bit AD converter interrupt enable bit Not used (returns “0” when read) (Do not write “1” to this bit.) 0 : I n t e r r u p t s d i s a b l e d I n t e r r u p t s e n a b l e d ( I C O N 2 : a d d r e s s 0 0 3 F1 0 : I n t e r r u p t s d i s a b l e d I n t e r r u p t s e n a b l e d

3850 Group (Spec. H) SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS TIMERS The 3850 group (spec. H) has four timers: timer X, timer Y , timer 1, and timer 2. The division ratio of each timer or prescaler is given by 1/(n + 1), where n is the value in the corresponding timer or prescaler latch. All timers are count down. When the timer reaches “00 16”, an un- derflow occurs at the next count pulse and the corresponding timer latch is reloaded into the timer and the count is continued. When a timer underflows, the interrupt request bit corresponding to that timer is set to “1”. Timer 1 and Timer 2 The count source of prescaler 12 is the oscillation frequency which is selected by timer 12 count source selection bit. The out- put of prescaler 12 is counted by timer 1 and timer 2, and a timer underflow sets the interrupt request bit. Timer X and Timer Y Timer X and Timer Y can each select in one of four operating modes by setting the timer XY mode register. (1) Timer Mode The timer counts the count source selected by Timer count source selection bit. (2) Pulse Output Mode The timer counts the count source selected by Timer count source selection bit. Whenever the contents of the timer reach “00 16”, the signal output from the CNTR0 (or CNTR1) pin is inverted. If the CNTR 0 (or CNTR1) active edge selection bit is “0”, output begins at “ H”. If it is “1”, output starts at “L”. When using a timer in this mode, set the corresponding port P27 ( or port P40) direction register to out- put mode. (3) Event Counter Mode Operation in event counter mode is the same as in timer mode, except that the timer counts signals input through the CNTR 0 or CNTR 1 pin. When the CNTR 0 (or CNTR1) active edge selection bit is “0”, the rising edge of the CNTR0 (or CNTR1) pin is counted. When the CNTR0 (or CNTR1) active edge selection bit is “1”, the falling edge of the CNTR0 (or CNTR1) pin is counted. (4) Pulse Width Measurement Mode If the CNTR0 (or CNTR1) active edge selection bit is “0”, the timer counts the selected signals by the count source selection bit while the CNTR 0 (or CNTR1) pin is at “H ”. If the CNTR0 (or CNTR1) ac- tive edge selection bit is “1”, the timer counts it while the CNTR0 (or CNTR1) pin is at “L”. The count can be stopped by setting “1” to the timer X (or timer Y) count stop bit in any mode. The corresponding interrupt request bit is set each time a timer underflows. Fig. 15 Structure of timer XY mode register I Note When switching the count source by the timer 12, X and Y count source bit, the value of timer count is altered in unconsiderable amount owing to generating of a thin pulses in the count input signals. Therefore, select the timer count source before set the value to the prescaler and the timer. Fig. 16 Structure of timer count source selection register Timer X count stop bit 0: Count start 1: Count stop T i m e r X Y m o d e r e g i s t e r T M a d d r e s s Timer Y operating mode bits 0 0: Timer mode 0 1: Pulse output mode 1 0: Event counter mode 1 1: Pulse width measurement mode CNTR 1 active edge selection bit 0: Interrupt at falling edge Count at rising edge in event counter mode 1: Interrupt at rising edge Count at falling edge in event counter mode b 7 CNTR 0 active edge selection bit 0: Interrupt at falling edge Count at rising edge in event counter mode 1: Interrupt at rising edge Count at falling edge in event counter mode b 0 T i m e r X o p e r a t i n g m o d e b i t T i m e r m o d e P u l s e o u t p u t m o d e E v e n t c o u n t e r m o d e P u l s e w i d t h m e a s u r e m e n t m o d e b 1 b 0 b 5 b 4 Timer Y count stop bit 0: Count start 1: Count stop T i m e r c o u n t s o u r c e s e l e c t i o n r e g i s t e r T C S S a d d r e s s b 7 b0 T i m e r X c o u n t s o u r c e s e l e c t i o n b i t f XI N ) f XC I N ) a t l o w s p e e d m o d e f XI N ) f XC I N ) a t l o w s p e e d m o d e T i m e r Y c o u n t s o u r c e s e l e c t i o n b i t f XI N ) f XC I N ) a t l o w s p e e d m o d e f XI N ) f XC I N ) a t l o w s p e e d m o d e Timer 12 count source selection bit 0 : f(XIN)/16 (f(XCIN)/16 at low-speed mode) 1 : f(XCIN) Not used (returns “0” when read)

3850 Group (Spec. H) SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS Fig. 17 Block diagram of timer X, timer Y, timer 1, and timer 2 Q Q “ 1 ” “0” P 27/ C N T R 0 Q Q P40/CNTR 1 “ 0 ” “ 1 ” R R “1” “0” “ 0 ” “ 1 ” T T Prescaler X latch (8) P r e s c a l e r X ( 8 ) Timer X latch (8) Timer X (8) T o t i m e r X i n t e r r u p t r e q u e s t b i t T o g g l e f l i p - f l o p T i m e r X c o u n t s t o p b i t P u l s e w i d t h m e a s u r e m e n t m o d e E v e n t c o u n t e r m o d e T o C N T R 0 i n t e r r u p t r e q u e s t b i t Pulse output mode P o r t P 27 l a t c hP o r t P 27 d i r e c t i o n r e g i s t e r C N T R 0 a c t i v e e d g e s e l e c t i o n b i t Timer X latch write pulse Pulse output mode T i m e r m o d e P u l s e o u t p u t m o d e Prescaler Y latch (8) Prescaler Y (8) Timer Y latch (8) Timer Y (8) T o t i m e r Y i n t e r r u p t r e q u e s t b i t Toggle flip-flop Timer Y count stop bit To CNTR 1 interrupt request bit P u l s e o u t p u t m o d e Port P40latchPort P40 direction register C N T R 1 a c t i v e e d g e s e l e c t i o n b i t T i m e r Y l a t c h w r i t e p u l s e P u l s e o u t p u t m o d e Timer mode Pulse output mode D a t a b u s Data bus Prescaler 12 latch (8) Prescaler 12 (8) Timer 1 latch (8) Timer 1 (8) Data bus Timer 2 latch (8) T i m e r 2 ( 8 ) To timer 2 interrupt request bit T o t i m e r 1 i n t e r r u p t r e q u e s t b i t C N T R 0 a c t i v e e d g e s e l e c t i o n b i t CNTR 1 active edge selection bit P u l s e w i d t h m e a s u r e m e n t m o d e Event counter mode f ( XC I N ) T i m e r 1 2 c o u n t s o u r c e s e l e c t i o n b i t f(XIN)/16 f ( XI N ) / 2 T i m e r Y c o u n t s o u r c e s e l e c t i o n b i t f ( XI N ) / 1 6 f ( XI N ) / 2 T i m e r X c o u n t s o u r c e s e l e c t i o n b i t f ( XI N ) / 1 6 ( f ( XC I N ) / 1 6 a t l o w - s p e e d m o d e ) ( f ( XC I N ) / 2 a t l o w - s p e e d m o d e ) ( f ( XC I N ) / 1 6 a t l o w - s p e e d m o d e ) ( f ( XC I N ) / 2 a t l o w - s p e e d m o d e ) (f(XCIN)/16 at low-speed mode)

3850 Group (Spec. H) SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS SERIAL I/O G SERIAL I/O1 Serial I/O1 can be used as either clock synchronous or asynchro- nous (UART) serial I/O. A dedicated timer is also provided for baud rate generation. (1) Clock Synchronous Serial I/O Mode Clock synchronous serial I/O mode can be selected by setting the serial I/O1 mode selection bit of the serial I/O1 control register (bit 6 of address 001A 16) to “1”. For clock synchronous serial I/O, the transmitter and the receiver must use the same clock. If an internal clock is used, transfer is started by a write signal to the TB/RB. Fig. 18 Block diagram of clock synchronous serial I/O1 Fig. 19 Operation of clock synchronous serial I/O1 function F/F P26/SCLK Serial I/O1 status register Serial I/O1 control register P27/SRDY1 P24/RXD P25/TXD XIN Receive buffer register Address 001816 Receive shift register Receive buffer full flag (RBF) Receive interrupt request (RI) Clock control circuitShift clock Serial I/O1 synchronous clock selection bit Frequency division ratio 1/(n+1) Baud rate generator Address 001C BRG count source selection bit Clock control circuitFalling-edge detector Transmit buffer register Data bus Address 001816 Shift clock Transmit shift completion flag (TSC) Transmit buffer empty flag (TBE) Transmit interrupt request (TI) Transmit interrupt source selection bit Address 001916 Data bus Address 001A16 Transmit shift register D 7 D 7 D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 0 D 1 D 2 D 3 D 4 D 5 D 6 RBF = 1 TSC = 1 TBE = 0 TBE = 1 TSC = 0 Transfer shift clock (1/2 to 1/2048 of the internal clock, or an external clock) Serial output TxD Serial input RxD Write pulse to receive/transmit buffer register (address 0018 16) Overrun error (OE) detection Notes 1: As the transmit interrupt (TI), either when the transmit buffer has emptied (TBE=1) or after the transmit shift operation has ended (TSC=1), by setting the transmit interrupt source selection bit (TIC) of the serial I/O1 control register. 2: If data is written to the transmit buffer register when TSC=0, the transmit clock is generated continuously and serial data is output continuously from the TxD pin. 3: The receive interrupt (RI) is set when the receive buffer full flag (RBF) becomes “1” . Receive enable signal SRDY1

3850 Group (Spec. H) SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS (2) Asynchronous Serial I/O (UART) Mode Clock asynchronous serial I/O mode (UART) can be selected by clearing the serial I/O1 mode selection bit (b6) of the serial I/O1 control register to “0”. Eight serial data transfer formats can be selected, and the transfer formats used by a transmitter and receiver must be identical. The transmit and receive shift registers each have a buffer, but the two buffers have the same address in memory. Since the shift reg- ister cannot be written to or read from directly, transmit data is written to the transmit buffer register, and receive data is read from the receive buffer register. The transmit buffer register can also hold the next data to be transmitted, and the receive buffer register can hold a character while the next character is being received. Fig. 20 Block diagram of UART serial I/O1 XI N O E P EF E 1 / 1 6 1 / 1 6 D a t a b u s R e c e i v e b u f f e r r e g i s t e r A d d r e s s 0 0 1 81 Receive shift register R e c e i v e b u f f e r f u l l f l a g ( R B F ) R e c e i v e i n t e r r u p t r e q u e s t ( R I ) Baud rate generator F r e q u e n c y d i v i s i o n r a t i o 1 / ( n + 1 ) Address 001C16 S T / S P / P A g e n e r a t o r Transmit buffer register D a t a b u s T r a n s m i t s h i f t r e g i s t e r Address 001816 Transmit shift completion flag (TSC) T r a n s m i t b u f f e r e m p t y f l a g ( T B E ) Transmit interrupt request (TI) Address 001916 ST detector SP detector UART control register A d d r e s s 0 0 1 B1 C h a r a c t e r l e n g t h s e l e c t i o n b i t A d d r e s s 0 0 1 A1 B R G c o u n t s o u r c e s e l e c t i o n b i t Transmit interrupt source selection bit Serial I/O1 synchronous clock selection bit Clock control circuit C h a r a c t e r l e n g t h s e l e c t i o n b i t 7 bits 8 b i t s Serial I/O1 control register P 26/ SC L K Serial I/O1 status register P 24/ R XD P 25/ TXD

3850 Group (Spec. H) SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS Fig. 21 Operation of UART serial I/O1 function [Transmit Buffer Register/Receive Buffer Register (TB/RB)] 001816 The transmit buffer register and the receive buffer register are lo- cated at the same address. The transmit buffer is write-only and the receive buffer is read-only. If a character bit length is 7 bits, the MSB of data stored in the receive buffer is “0”. [Serial I/O1 Status Register (SIOSTS)] 001916 The read-only serial I/O1 status register consists of seven flags (bits 0 to 6) which indicate the operating status of the serial I/O1 function and various errors. Three of the flags (bits 4 to 6) are valid only in UART mode. The receive buffer full flag (bit 1) is cleared to “0” when the receive buffer register is read. If there is an error, it is detected at the same time that data is transferred from the receive shift register to the receive buffer reg- ister, and the receive buffer full flag is set. A write to the serial I/O1 status register clears all the error flags OE, PE, FE, and SE (bit 3 to bit 6, respectively). Writing “0” to the serial I/O1 enable bit SIOE (bit 7 of the serial I/O1 control register) also clears all the status flags, including the error flags. Bits 0 to 6 of the serial I/O1 status register are initialized to “0” at reset, but if the transmit enable bit (bit 4) of the serial I/O1 control register has been set to “1”, the transmit shift completion flag (bit 2) and the transmit buffer empty flag (bit 0) become “1”. [Serial I/O1 Control Register (SIOCON)] 001A16 The serial I/O1 control register consists of eight control bits for the serial I/O1 function. [UART Control Register (UARTCON)] 001B16 The UART control register consists of four control bits (bits 0 to 3) which are valid when asynchronous serial I/O is selected and set the data format of an data transfer and one bit (bit 4) which is al- ways valid and sets the output structure of the P2 5/TX D pin. [Baud Rate Generator (BRG)] 001C16 The baud rate generator determines the baud rate for serial trans- fer. The baud rate generator divides the frequency of the count source by 1/(n + 1), where n is the value written to the baud rate genera- tor. TSC=0 TBE=1 RBF=0 TBE=0 TBE=0 RBF=1 RBF=1 STD 0 D 1 SP D 0 D 1ST SP TBE=1 TSC=1 STD 0 D 1 SP D 0 D 1ST SP Transmit or receive clock Transmit buffer write signal Generated at 2nd bit in 2-stop-bit mode 1 start bit 7 or 8 data bit 1 or 0 parity bit 1 or 2 stop bit (s) 1: Error flag detection occurs at the same time that the RBF flag becomes “1” (at 1st stop bit, during reception). 2: As the transmit interrupt (TI), when either the TBE or TSC flag becomes “1,” can be selected to occur depending on the setting of the transmit interrupt source selection bit (TIC) of the serial I/O1 control register. 3: The receive interrupt (RI) is set when the RBF flag becomes “1.” 4: After data is written to the transmit buffer when TSC=1, 0.5 to 1.5 cycles of the data shift cycle is necessary until changing to TSC=0. Notes Serial output TXD Serial input RXD Receive buffer read signal

3850 Group (Spec. H) SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS b 7 T r a n s m i t b u f f e r e m p t y f l a g T B E B u f f e r f u l l B u f f e r e m p t y R e c e i v e b u f f e r f u l l f l a g R B F B u f f e r e m p t y B u f f e r f u l l T r a n s m i t s h i f t c o m p l e t i o n f l a g T S C T r a n s m i t s h i f t i n p r o g r e s s T r a n s m i t s h i f t c o m p l e t e d O v e r r u n e r r o r f l a g O E N o e r r o r O v e r r u n e r r o r P a r i t y e r r o r f l a g P E N o e r r o r P a r i t y e r r o r F r a m i n g e r r o r f l a g F E N o e r r o r F r a m i n g e r r o r S u m m i n g e r r o r f l a g S E O E U P E U F E O E U P E U F E N o t u s e d r e t u r n s w h e n r e a d S e r i a l I O s t a t u s r e g i s t e r S e r i a l I O c o n t r o l r e g i s t e r b 7 b 0 b 0 B R G c o u n t s o u r c e s e l e c t i o n b i t C S S f XI N ) f XI N ) S e r i a l I O s y n c h r o n o u s c l o c k s e l e c t i o n b i t S C S B R G o u t p u t d i v i d e d b y w h e n c l o c k s y n c h r o n o u s s e r i a l I O i s s e l e c t e d B R G o u t p u t d i v i d e d b y w h e n U A R T i s s e l e c t e d E x t e r n a l c l o c k i n p u t w h e n c l o c k s y n c h r o n o u s s e r i a l I O i s s e l e c t e d e x t e r n a l c l o c k i n p u t d i v i d e d b y w h e n U A R T i s s e l e c t e d SR D Y o u t p u t e n a b l e b i t S R D Y P p i n o p e r a t e s a s o r d i n a r y I O p i n P p i n o p e r a t e s a s SR D Y o u t p u t p i n T r a n s m i t i n t e r r u p t s o u r c e s e l e c t i o n b i t T I C I n t e r r u p t w h e n t r a n s m i t b u f f e r h a s e m p t i e d I n t e r r u p t w h e n t r a n s m i t s h i f t o p e r a t i o n i s c o m p l e t e d T r a n s m i t e n a b l e b i t T E T r a n s m i t d i s a b l e d T r a n s m i t e n a b l e d R e c e i v e e n a b l e b i t R E R e c e i v e d i s a b l e d R e c e i v e e n a b l e d S e r i a l I O m o d e s e l e c t i o n b i t S I O M C l o c k a s y n c h r o n o u s U A R T s e r i a l I O C l o c k s y n c h r o n o u s s e r i a l I O S e r i a l I O e n a b l e b i t S I O E S e r i a l I O d i s a b l e d p i n s P t o P o p e r a t e a s o r d i n a r y I O p i n s S e r i a l I O e n a b l e d p i n s P t o P o p e r a t e a s s e r i a l I O p i n s b 7 UART control register C h a r a c t e r l e n g t h s e l e c t i o n b i t C H A S b i t s b i t s P a r i t y e n a b l e b i t P A R E P a r i t y c h e c k i n g d i s a b l e d P a r i t y c h e c k i n g e n a b l e d P a r i t y s e l e c t i o n b i t P A R S E v e n p a r i t y O d d p a r i t y S t o p b i t l e n g t h s e l e c t i o n b i t S T P S s t o p b i t s t o p b i t s P 25/ TXD P c h a n n e l o u t p u t d i s a b l e b i t P O F F C M O S o u t p u t i n o u t p u t m o d e N c h a n n e l o p e n d r a i n o u t p u t i n o u t p u t m o d e N o t u s e d r e t u r n w h e n r e a d b 0 S I O S T S a d d r e s s S I O C O N a d d r e s s (UARTCON : address 001B16) Fig. 22 Structure of serial I/O1 control registers

3850 Group (Spec. H) SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS G SERIAL I/O2 The serial I/O2 can be operated only as the clock synchronous type. As a synchronous clock for serial transfer, either internal clock or external clock can be selected by the serial I/O2 synchronous clock selection bit (b6) of serial I/O2 control register 1. The internal clock incorporates a dedicated divider and permits se- lecting 6 types of clock by the internal synchronous clock selection bits (b2, b1, b0) of serial I/O2 control register 1. Regarding S OUT2 and SCLK2 being output pins, either CMOS output format or N-channel open-drain output format can be selected by the 1/SOUT2 , P02/SCLK2 P-channel output disable bit (b7) of serial I/O2 control register 1. When the internal clock has been selected, a transfer starts by a write signal to the serial I/O2 register (address 0017 16). After comple- tion of data transfer, the level of the SOUT2 pin goes to high imped- ance automatically but bit 7 of the serial I/O2 control register 2 is not set to “1” automatically. When the external clock has been selected, the contents of the serial I/O2 register is continuously sifted while transfer clocks are input. Accordingly, control the clock externally. Note that the S OUT2 pin does not go to high impedance after completion of data transfer. To cause the S OUT2 pin to go to high impedance in the case where the external clock is selected, set bit 7 of the serial I/O2 control reg- ister 2 to “1” when S CLK2 is “H ” after completion of data transfer. After the next data transfer is started (the transfer clock falls), bit 7 of the serial I/O2 control register 2 is set to “0” and the S OUT2 pin is put into the active state. Regardless of the internal clock to external clock, the interrupt re- quest bit is set after the number of bits (1 to 8 bits) selected by the optional transfer bit is transferred. In case of a fractional number of bits less than 8 bits as the last data, the received data to be stored in the serial I/O2 register becomes a fractional number of bits close to MSB if the transfer direction selection bit of serial I/O2 control regis- ter 1 is LSB first, or a fractional number of bits close to LSB if the said bit is MSB first. For the remaining bits, the previously received data is shifted. At transmit operation using the clock synchronous serial I/O, the S CMP2 signal can be output by comparing the state of the transmit pin SOUT2 with the state of the receive pin SIN2 in synchronization with a rise of the transfer clock. If the output level of the SOUT2 pin is equal to the input level to the SIN2 pin, “L” is output from the SCMP2 pin. If not, “H ” is output. At this time, an INT2 interrupt request can also be gener- ated. Select a valid edge by bit 2 of the interrupt edge selection reg- ister (address 003A 16). [Serial I/O2 Control Registers 1, 2 (SIO2CON1 / SIO2CON2)] 001516, 001616 The serial I/O2 control registers 1 and 2 are containing various se- lection bits for serial I/O2 control as shown in Figure 23. Fig. 23 Structure of Serial I/O2 control registers 1, 2 S e r i a l I / O 2 c o n t r o l r e g i s t e r 1 S I O C O N a d d r e s s S e r i a l I / O 2 c o n t r o l r e g i s t e r 2 S I O C O N a d d r e s s b7 b0 O p t i o n a l t r a n s f e r b i t s b b b b i t b i t b i t b i t b i t b i t b i t b i t N o t u s e d r e t u r n s w h e n r e a d S e r i a l I O I O c o m p a r i s o n s i g n a l c o n t r o l b i t P I O SC M P o u t p u t SO U T p i n c o n t r o l b i t P 01) O u t p u t a c t i v e O u t p u t h i g h i m p e d a n c e Internal synchronous clock selection bits b2 b1 b0 0 0 0: f(XIN)/8 (f(XCIN)/8 in low-speed mode) 0 0 1: f(XIN)/16 (f(XCIN)/16 in low-speed mode) 0 1 0: f(XIN)/32 (f(XCIN)/32 in low-speed mode) 0 1 1: f(XIN)/64 (f(XCIN)/64 in low-speed mode) 1 1 0: f(XIN)/128 f(XCIN)/128 in low-speed mode) 1 1 1: f(XIN)/256 (f(XCIN)/256 in low-speed mode) Serial I/O2 port selection bit 0: I/O port 1: S OUT2 ,SCLK2 output pin SRDY2 output enable bit 0: P03 pin is normal I/O pin 1: P03 pin is SRDY2 output pin Transfer direction selection bit 0: LSB first 1: MSB first Serial I/O2 synchronous clock selection bit 0: External clock 1: Internal clock 1/SOUT2 ,P02/SCLK2 P-channel output disable bit 0: CMOS output (in output mode) 1: N-channel open-drain output (in output mode ) b 7 b 0

3850 Group (Spec. H) SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS Fig. 24 Block diagram of Serial I/O2 Fig. 25 Timing chart of Serial I/O2 XIN “1” “0 ” “0 ” “1” “0 ” “1” SR D Y SC L K “0 ” “1 ” “1” “0” XCIN “10” “0 0 ” Data bus S e r i a l I / O 2 i n t e r r u p t r e q u e s t Serial I/O2 port selection bit Serial I/O counter 2 (3) Serial I/O2 register (8) S y n c h r o n o u s c i r c u i t Serial I/O2 port selection bit S e r i a l I / O 2 s y n c h r o n o u s c l o c k s e l e c t i o n b i t SR D Y 2 o u t p u t e n a b l e b i t External clock I n t e r n a l s y n c h r o n o u s c l o c k s e l e c t i o n b i t s D i v i d e r Optional transfer bits (3) P 02/ SC L K P01/SOUT2 P 00/ SI N P 02 l a t c h P 01 l a t c h P 03 l a t c h P 03/ SR D Y P 43/ SC M P 2/ I N T2 Serial I/O2 I/O comparison signal control bit P43 latch Q D M a i n c l o c k d i v i s i o n r a t i o s e l e c t i o n b i t s N o t e N o t e : E i t h e r h i g h - s p e e d , m i d d l e - s p e e d o r l o w - s p e e d m o d e i s s e l e c t e d b y b i t s 6 a n d 7 o f C P U m o d e r e g i s t e r . D 7D 0 D 1 D 2 D 3 D 4 D 5 D 6 T r a n s f e r c l o c k ( N o t e 1 ) S e r i a l I / O 2 o u t p u t SO U T S e r i a l I / O 2 i n p u t SI N R e c e i v e e n a b l e s i g n a l SR D Y W r i t e - i n s i g n a l t o s e r i a l I O r e g i s t e r (Note 2) Serial I/O2 interrupt request bit set 1 : W h e n t h e i n t e r n a l c l o c k i s s e l e c t e d a s a t r a n s f e r c l o c k , t h e f ( XI N ) c l o c k d i v i s i o n ( f ( XC I N ) i n l o w - s p e e d m o d e ) c a n b e s e l e c t e d b y s e t t i n g b i t s t o o f s e r i a l I O c o n t r o l r e g i s t e r W h e n t h e i n t e r n a l c l o c k i s s e l e c t e d a s a t r a n s f e r c l o c k t h e SO U T p i n h a s h i g h i m p e d a n c e a f t e r t r a n s f e r c o m p l e t i o n N o t e s

3850 Group (Spec. H) SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS Fig. 26 SCMP2 output operation SCLK2 SIN2 SOUT2 SCMP2 Judgement of I/O data comparison

3850 Group (Spec. H) SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS PULSE WIDTH MODULATION (PWM) The 3850 group (spec. H) has a PWM function with an 8-bit resolution, based on a signal that is the clock input XIN or that clock input divided by 2. Data Setting The PWM output pin also functions as port P44. Set the PWM period by the PWM prescaler, and set the “H ” term of output pulse by the PWM register. If the value in the PWM prescaler is n and the value in the PWM register is m (where n = 0 to 255 and m = 0 to 255) : PWM period = 255 ✕ (n+1) / f(X IN) (when f(XIN) = 8 MHz,count source selection bit = “0”) Output pulse “H ” term = PWM period ✕ m / 255 (when f(XIN) = 8 MHz,count source selection bit = “0”) Fig. 27 Timing of PWM period Fig. 28 Block diagram of PWM function PWM Operation When bit 0 (PWM enable bit) of the PWM control register is set to “1”, operation starts by initializing the PWM output circuit, and pulses are output starting at an “H ”. If the PWM register or PWM prescaler is updated during PWM output, the pulses will change in the cycle after the one in which the change was made. 3 1 . 8 7 5 ✕ m ✕ ( n + 1 ) 2 5 5 µs T = [ 3 1 . 8 7 5 ✕ ( n + 1 ) ] µs P W M o u t p u t m : C o n t e n t s o f P W M r e g i s t e r n C o n t e n t s o f P W M p r e s c a l e r T P W M p e r i o d w h e n f XI N ) M H z c o u n t s o u r c e s e l e c t i o n b i t Data bus Count source selection bit “0” “ 1 ” PWM prescaler pre-latch P W M r e g i s t e r p r e l a t c h PWM prescaler latch PWM register latch Transfer control circuit PWM register XI N Port P44 latch P W M e n a b l e b i t Port P44 P W M p r e s c a l e r (XCIN at low-speed mode)

3850 Group (Spec. H) SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS Fig. 29 Structure of PWM control register Fig. 30 PWM output timing when PWM register or PWM prescaler is changed I Note The PWM starts after the PWM function enable bit is set to enable and “L” level is output from the PWM pin. The length of this “L” level output is as follows: sec (Count source selection bit = 0, where n is the value set in the prescaler) sec (Count source selection bit = 1, where n is the value set in the prescaler) n+1 2 • f(X IN) n+1 f(XIN) P W M c o n t r o l r e g i s t e r P W M C O N a d d r e s s D 1 P W M f u n c t i o n e n a b l e b i t C o u n t s o u r c e s e l e c t i o n b i t N o t u s e d r e t u r n w h e n r e a d b 7 b 0 0 : P W M d i s a b l e d P W M e n a b l e d 0 : f ( XI N ) ( f ( XC I N ) a t l o w - s p e e d m o d e ) f XI N ) f XC I N ) a t l o w s p e e d m o d e AB C B T C T PWM output P W M r e g i s t e r w r i t e s i g n a l PWM prescaler write signal ( C h a n g e s “ H ” t e r m f r o m “ A ” t o “ B ” . ) (Changes PWM period from “T” to “T2”.) When the contents of the PWM register or PWM prescaler have changed, the PWM output will change from the next period after the change. T T T2

3850 Group (Spec. H) SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS A-D CONVERTER [A-D Conversion Registers (ADL, ADH)] 0035 16, 003616 The A-D conversion registers are read-only registers that store the result of an A-D conversion. Do not read these registers during an A-D conversion. [AD Control Register (ADCON)] 003416 The AD control register controls the A-D conversion process. Bits 0 to 2 select a specific analog input pin. Bit 4 indicates the completion of an A-D conversion. The value of this bit remains at “0” during an A-D conversion and changes to “1” when an A-D conversion ends. Writing “0” to this bit starts the A-D conversion. Comparison Voltage Generator The comparison voltage generator divides the voltage between AV SS and VREF into 1024 and outputs the divided voltages. Channel Selector The channel selector selects one of ports P30/AN0 to P34/AN4 and inputs the voltage to the comparator. Comparator and Control Circuit The comparator and control circuit compare an analog input volt- age with the comparison voltage, and the result is stored in the A-D conversion registers. When an A-D conversion is completed, the control circuit sets the A-D conversion completion bit and the A-D interrupt request bit to “1”. Note that because the comparator consists of a capacitor cou- pling, set f(X IN) to 500 kHz or more during an A-D conversion. When the A-D converter is operated at low-speed mode, f(XIN) and f(XCIN) do not have the lower limit of frequency, because of the A-D converter has a built-in self-oscillation circuit. Fig. 31 Structure of AD control register Fig. 32 Structure of A-D conversion registers Fig. 33 Block diagram of A-D converter C h a n n e l s e l e c t o r A D c o n t r o l c i r c u i t A-D conversion low-order register Resistor ladder VREF AV SS C o m p a r a t o r A D i n t e r r u p t r e q u e s t b P 30/ A N 0 P 31/ A N 1 P 32/ A N 2 P 33/ A N 3 P 34/ A N 4 D a t a b u s A D c o n t r o l r e g i s t e r A-D conversion high-order register A d d r e s s (Address 003616) (Address 003516) A D c o n t r o l r e g i s t e r A D C O N a d d r e s s A n a l o g i n p u t p i n s e l e c t i o n b i t s P 30/ A N 0 P 31/ A N 1 P 32/ A N 2 P 33/ A N 3 P 34/ A N 4 N o t u s e d r e t u r n s w h e n r e a d A D c o n v e r s i o n c o m p l e t i o n b i t C o n v e r s i o n i n p r o g r e s s C o n v e r s i o n c o m p l e t e d N o t u s e d r e t u r n s w h e n r e a d b 7 b0 b 2 b 1 b 0 10-bit reading (Read address 003616 before 003516) (Address 003616) (Address 003516) 8-bit reading (Read only address 003516) (Address 003516) b7 b 6b 5b 4 b b7 b b 7 b Note : The high-order 6 bits of address 003616 become “0” at reading. b9 b8 b7 b6 b5 b4 b3 b2 b7 b

3850 Group (Spec. H) SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS WATCHDOG TIMER The watchdog timer gives a mean of returning to the reset status when a program cannot run on a normal loop (for example, be- cause of a software run-away). The watchdog timer consists of an 8-bit watchdog timer L and an 8-bit watchdog timer H. Standard Operation of Watchdog Timer When any data is not written into the watchdog timer control reg- ister (address 0039 16) after reset, the watchdog timer is in the stop state. The watchdog timer starts to count down by writing an optional value into the watchdog timer control register (address 0039 16) and an internal reset occurs at an underflow of the watch- dog timer H. Accordingly, programming is usually performed so that writing to the watchdog timer control register (address 0039 16) may be started before an underflow. When the watchdog timer control reg- ister (address 0039 16) is read, the values of the high-order 6 bits of the watchdog timer H, STP instruction disable bit, and watch- dog timer H count source selection bit are read. G Initial value of watchdog timer At reset or writing to the watchdog timer control register (address 0039 16), each watchdog timer H and L is set to “FF 16.” Fig. 35 Structure of Watchdog timer control register G Watchdog timer H count source selection bit operation Bit 7 of the watchdog timer control register (address 003916) per- mits selecting a watchdog timer H count source. When this bit is set to “0”, the count source becomes the underflow signal of watchdog timer L. The detection time is set to 131.072 ms at f(X IN) = 8 MHz frequency and 32.768 s at f(XCIN) = 32 kHz frequency. When this bit is set to “1”, the count source becomes the signal divided by 16 for f(XIN) (or f(XCIN)). The detection time in this case is set to 512 µ s at f(XIN) = 8 MHz frequency and 128 ms at f(XCIN) = 32 kHz frequency. This bit is cleared to “0” after reset. G Operation of STP instruction disable bit Bit 6 of the watchdog timer control register (address 003916) per- mits disabling the STP instruction when the watchdog timer is in operation. When this bit is “0”, the STP instruction is enabled. When this bit is “1”, the STP instruction is disabled, once the STP instruction is executed, an internal reset occurs. When this bit is set to “1”, it cannot be rewritten to “0” by program. This bit is cleared to “0” after reset. Fig. 34 Block diagram of Watchdog timer XI N Data bus XC I N “ 1 0 ” “ 0 0 ” M a i n c l o c k d i v i s i o n r a t i o s e l e c t i o n b i t s N o t e “0” “1”1 / 1 6 Watchdog timer H count source selection bit R e s e t c i r c u i t S T P i n s t r u c t i o n d i s a b l e b i t W a t c h d o g t i m e r H ( 8 ) “FF16” is set when watchdog timer control register is written to. Internal resetR E S E T Watchdog timer L (8) Note: Any one of high-speed, middle-speed or low-speed mode is selected by bits 7 and 6 of the CPU mode register. S T P i n s t r u c t i o n “FF16” is set when watchdog timer control register is written to. b 0 STP instruction disable bit 0: STP instruction enabled 1: STP instruction disabled W a t c h d o g t i m e r H c o u n t s o u r c e s e l e c t i o n b i t W a t c h d o g t i m e r L u n d e r f l o w f X I N ) o r f XC I N ) W a t c h d o g t i m e r H ( f o r r e a d - o u t o f h i g h - o r d e r 6 b i t ) Watchdog timer control register (WDTCON : address 003916) b 7

3850 Group (Spec. H) SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS RESET CIRCUIT To reset the microcomputer, RESET pin must be held at an “L” level for 20 cycles or more of XIN. Then the RESET pin is returned to an “H ” level (the power source voltage must be between 2.7 V and 5.5 V, and the oscillation must be stable), reset is released. After the reset is completed, the program starts from the address contained in address FFFD 16 (high-order byte) and address FFFC 16 (low-order byte). Make sure that the reset input voltage is less than 0.54 V for VCC of 2.7 V. Fig. 37 Reset sequence Fig. 36 Reset circuit example ( N o t e ) 0 . 2 VC C 0 V P o w e r o n VC CR E S E T VC CR E S E T P o w e r s o u r c e v o l t a g e d e t e c t i o n c i r c u i t P o w e r s o u r c e v o l t a g e Reset input voltage N o t e : R e s e t r e l e a s e v o l t a g e ; V c c = 2 . 7 V R E S E T D a t a φ A d d r e s s S Y N C XI N : 8 t o 1 3 c l o c k c y c l e s XI N ? ? ?? ? F F F C FFFD AD H ,L 1 : T h e f r e q u e n c y r e l a t i o n o f f ( XI N ) a n d f (φ) i s f ( XI N ) = 2 • f (φ) . T h e q u e s t i o n m a r k s i n d i c a t e a n u n d e f i n e d s t a t e t h a t d e p e n d s o n t h e p r e v i o u s s t a t e A l l s i g n a l s e x c e p t XI N a n d R E S E T a r e i n t e r n a l s R e s e t a d d r e s s f r o m t h e v e c t o r t a b l e . N o t e s R E S E TO U T

3850 Group (Spec. H) SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS Fig. 38 Internal status at reset Note :X : Not fixed Since the initial values for other than above mentioned registers and RAM contents are indefinite at reset, they must be set. (1) (2) (3) (4) (5) (6) (7) (8) (9) (10) (11) (12) (13) (14) (15) (16) (17) (18) (19) (20) (21) (22) (23) (24) (25) (26) (27) (28) (29) (30) (31) (32) (33) Address Register contents 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 FF16 0116 0016 0016 FF16 FF16 FF16 FF16 0016 Port P0 (P0) Port P0 direction register (P0D) Port P1 (P1) Port P1 direction register (P1D) Port P2 (P2) Port P2 direction register (P2D) Port P3 (P3) Port P3 direction register (P3D) Port P4 (P4) Port P4 direction register (P4D) Serial I/O2 control register 1 (SIO2CON1) Serial I/O2 control register 2 (SIO2CON2) Serial I/O2 register (SIO2) Transmit/Receive buffer register (TB/RB) Serial I/O1 status register (SIOSTS) Serial I/O1 control register (SIOCON) UART control register (UARTCON) Baud rate generator (BRG) PWM control register (PWMCON) PWM prescaler (PREPWM) PWM register (PWM) Prescaler 12 (PRE12) Timer 1 (T1) Timer 2 (T2) Timer XY mode register (TM) Prescaler X (PREX) Timer X (TX) Prescaler Y (PREY) Timer Y (TY) Timer count source selection register (TCSS) A-D control register (ADCON) A-D conversion low-order register (ADL) A-D conversion high-order register (ADH) 0000 0111 1000 0000 XXXXXXXX 000016 000116 000216 000316 000416 000516 000616 000716 000816 000916 001516 001616 001716 001816 001916 001A16 001B16 001C 16 001D 16 001E16 001F16 002016 002116 002216 002316 002416 002516 002616 002716 002816 003416 003516 003616 1110 0000 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 000 10000 XXXXXXXX XX 0016 0016 0016 0016 0016 0016 (34) (35) (36) (37) (38) (39) (40) (41) (42) (43) Register contents 003816 003916 003A16 003B16 003C 16 003D 16 003E16 003F16 (PS) (PCH ) (PCL) Address XXXXX1XX FFFD 16 contents FFFC 16 contents 0011 1111 0100 10 00 MISRG Watchdog timer control register (WDTCON) Interrupt edge selection register (INTEDGE) CPU mode register (CPUM) Interrupt request register 1 (IREQ1) Interrupt request register 2 (IREQ2) Interrupt control register 1 (ICON1) Interrupt control register 2 (ICON2) Processor status register Program counter 000000

3850 Group (Spec. H) SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS CLOCK GENERATING CIRCUIT The 3850 group (spec. H) has two built-in oscillation circuits. An oscillation circuit can be formed by connecting a resonator be- tween X IN and XOUT (XCIN and XCOUT ). Use the circuit constants in accordance with the resonator manufacturer’s recommended values. No external resistor is needed between XIN and XOUT since a feed-back resistor exists on-chip. However, an external feed-back resistor is needed between X CIN and XCOUT . Immediately after power on, only the XIN oscillation circuit starts oscillating, and XCIN and XCOUT pins function as I/O ports. Frequency Control (1) Middle-speed mode The internal clock φ is the frequency of XIN divided by 8. After re- set, this mode is selected. (2) High-speed mode The internal clock φ is half the frequency of XIN. (3) Low-speed mode The internal clock φ is half the frequency of XCIN. I Note If you switch the mode between middle/high-speed and low- speed, stabilize both XIN and XCIN oscillations. The sufficient time is required for the sub-clock to stabilize, especially immediately af- ter power on and at returning from the stop mode. When switching the mode between middle/high-speed and low-speed, set the fre- quency on condition that f(X IN) > 3•f(XCIN). (4) Low power dissipation mode The low power consumption operation can be realized by stopping the main clock XIN in low-speed mode. To stop the main clock, set bit 5 of the CPU mode register to “1.” When the main clock XIN is restarted (by setting the main clock stop bit to “0”), set sufficient time for oscillation to stabilize. The sub-clock X CIN-XCOUT oscillating circuit can not directly input clocks that are generated externally. Accordingly, make sure to cause an external resonator to oscillate. Oscillation Control (1) Stop mode If the STP instruction is executed, the internal clock φ stops at an “H ” level, and XIN and XCIN oscillation stops. When the oscillation stabilizing time set after STP instruction released bit is “0,” the prescaler 12 is set to “FF 16” and timer 1 is set to “0116.” When the oscillation stabilizing time set after STP instruction released bit is “1,” set the sufficient time for oscillation of used oscillator to stabi- lize since nothing is set to the prescaler 12 and timer 1. Either X IN or XCIN divided by 16 is input to the prescaler 12 as count source. Oscillator restarts when an external interrupt is re- ceived, but the internal clock φ is not supplied to the CPU (remains at “H ”) until timer 1 underflows. The internal clock φ is supplied for the first time, when timer 1 underflows. This ensures time for the clock oscillation using the ceramic resonators to be stabilized. When the oscillator is restarted by reset, apply “L” level to the RESET pin until the oscillation is stable since a wait time will not be generated. Fig. 39 Ceramic resonator circuit Fig. 40 External clock input circuit (2) Wait mode If the WIT instruction is executed, the internal clock φ stops at an “H ” level, but the oscillator does not stop. The internal clock φ re- starts at reset or when an interrupt is received. Since the oscillator does not stop, normal operation can be started immediately after the clock is restarted. To ensure that the interrupts will be received to release the STP or WIT state, their interrupt enable bits must be set to “1” before ex- ecuting of the STP or WIT instruction. When releasing the STP state, the prescaler 12 and timer 1 will start counting the clock X IN divided by 16. Accordingly, set the timer 1 interrupt enable bit to “0” before executing the STP instruc- tion. I Note When using the oscillation stabilizing time set after STP instruction released bit set to “1”, evaluate time to stabilize oscillation of the used oscillator and set the value to the timer 1 and prescaler 12. XCIN XCOUT XIN XOUT C IN C OUTC CIN C COUT Rf Rd XC I N XC O U T XI N XO U T C C I N C C O U T R f R d O p e n E x t e r n a l o s c i l l a t i o n c i r c u i t V c c V s s

3850 Group (Spec. H) SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS Fig. 41 Structure of MISRG [MISRG (MISRG)] 003816 MISRG consists of three control bits (bits 1 to 3) for middle-speed mode automatic switch and one control bit (bit 0) for oscillation stabilizing time set after STP instruction released. By setting the middle-speed mode automatic switch start bit to “1” while operating in the low-speed mode and setting the middle- speed mode automatic switch set bit to “1”, X IN oscillation automatically starts and the mode is automatically switched to the middle-speed mode. Fig. 42 System clock generating circuit block diagram (Single-chip mode) M I S R G M I S R G a d d r e s s O s c i l l a t i o n s t a b i l i z i n g t i m e s e t a f t e r S T P i n s t r u c t i o n r e l e a s e d b i t A u t o m a t i c a l l y s e t t o T i m e r F t o P r e s c a l e r A u t o m a t i c a l l y s e t n o t h i n g b 7 b 0 N o t e :W h e n t h e m o d e i s a u t o m a t i c a l l y s w i t c h e d f r o m t h e l o w - s p e e d m o d e t o t h e m i d d l e s p e e d m o d e t h e v a l u e o f C P U m o d e r e g i s t e r a d d r e s s c h a n g e s Not used (return “0” when read) Middle-speed mode automatic switch start bit (Depending on program) 0: Invalid 1: Automatic switch start Middle-speed mode automatic switch wait time set bit 0: 4.5 to 5.5 machine cycles 1: 6.5 to 7.5 machine cycles Middle-speed mode automatic switch set bit 0: Not set automatically 1: Automatic switching enable WIT instruction STP instruction Timing φ (internal clock) S R Q S T P i n s t r u c t i o n S R Q M a i n c l o c k s t o p b i t S R Q 1 / 2 1/4 XIN XO U T XCOUTXC I N I n t e r r u p t r e q u e s t R e s e t I n t e r r u p t d i s a b l e f l a g l Port XC switch bit “ 1 ” “0” L o w - s p e e d m o d e High-speed or middle-speed mode Middle-speed mode High-speed or low-speed mode Main clock division ratio selection bits (Note 1) N o t e s 1 : A n y o n e o f h i g h - s p e e d , m i d d l e - s p e e d o r l o w - s p e e d m o d e i s s e l e c t e d b y b i t s 7 a n d 6 o f t h e C P U m o d e r e g i s t e r . W h e n l o w s p e e d m o d e i s s e l e c t e d s e t p o r t X c s w i t c h b i t b t o W h e n b i t o f M I S R G M a i n c l o c k d i v i s i o n r a t i o s e l e c t i o n b i t s N o t e FF16 0116 Prescaler 12 T i m e r 1 Reset or STP instruction (Note 2)

3850 Group (Spec. H) SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS Fig. 43 State transitions of system clock CM 4 : Port Xc switch bit 0 : I/O port function (stop oscillating) 1 : X CIN-XCOUT oscillating function CM 5 : Main clock (XIN- XOUT ) stop bit 0 : Operating 1 : Stopped CM 7, CM6: Main clock division ratio selection bit b7 b6 0 0 : φ = f(XIN)/2 ( High-speed mode) 0 1 : φ = f(XIN)/8 (Middle-speed mode) 1 0 : φ = f(XCIN)/2 (Low-speed mode) 1 1 : Not available N o t e s R e s e t C M ” C M4“ C M6“ C M4 C “ 0 ” C M 7 C M 4 C M 5 CM 6 C M 6 CPU mode register b 7b 4 C M7“ C M6“ (CPUM : address 003B16) C M 7 = 0 C M 6 C M 5 M H z o s c i l l a t i n g C M 4 k H z s t o p p e d M i d d l e - s p e e d m o d e f (φ) M H z C M 7 = 0 C M 6 C M 5 M H z o s c i l l a t i n g C M 4 k H z o s c i l l a t i n g M i d d l e - s p e e d m o d e f (φ) M H z CM 7 = 0 CM 6 = 0 CM 5 = 0 (8 MHz oscillating) CM 4 = 0 (32 kHz stopped) H i g h - s p e e d m o d e f (φ) M H z CM 7 = 1 CM 6 = 0 CM 5 = 0 (8 MHz oscillating) CM 4 = 1 (32 kHz oscillating) Low-speed mode (f(φ)=16 kHz) C M 7 = 1 C M 6 C M 5 M H z s t o p p e d C M 4 k H z o s c i l l a t i n g L o w - s p e e d m o d e f (φ) k H z CM 7 = 0 CM 6 = 0 CM 5 = 0 (8 MHz oscillating) CM 4 = 1 (32 kHz oscillating) High-speed mode (f(φ) = 4 MHz) 1 : Switch the mode by the allows shown between the mode blocks. (Do not switch between the modes directly without an allow.) 2 : The all modes can be switched to the stop mode or the wait mode and return to the source mode when the stop mode or the wait mode is ended. 3 : Timer operates in the wait mode. 4 : When bit 0 of MISRG is “0” and the stop mode is ended, a delay of approximately 1 ms occurs by connecting timer 1 in middle/high-speed mode. 5 : When bit 0 of MISRG is “0” and the stop mode is ended, the following is performed. (1) After the clock is restarted, a delay of approximately 256 ms occurs in low-speed mode if Timer 12 count source selection bit is “0”. (2) After the clock is restarted, a delay of approximately 16 ms occurs in low-speed mode if Timer 12 count source selection bit is “1”. 6 :Wait until oscillation stabilizes after oscillating the main clock XIN before the switching from the low-speed mode to middle/high-speed mode. 7 : The example assumes that 8 MHz is being applied to the XIN pin and 32 kHz to the XCIN pin. φ indicates the internal clock.

3850 Group (Spec. H) SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS FLASH MEMORY VERSION Summary Table 9 shows the summary of the M38507F8 (flash memory version). Table 9 Summary of M38507F8 (flash memory version) P o w e r s o u r c e v o l t a g e V c c V N o t e V c c V N o t e P r o g r a m E r a s e VP P v o l t a g e V f XI N ) M H z F l a s h m e m o r y m o d m o d e s P a r a l l e l I O m o d e S t a n d a r d s e r i a l I O m o d e C P U r e w r i t e m o d e E r a s e b l o c k d i v i s i o n U s e r R O M a r e a B o o t R O M a r e a b l o c k K b y t e s b l o c k K b y t e s N o t e P r o g r a m m e t h o dB y t e p r o g r a m Erase method Batch erasing P r o g r a m E r a s e c o n t r o l m e t h o dP r o g r a m E r a s e c o n t r o l b y s o f t w a r e c o m m a n d Nu m b e r o f c o m m a n d c o m m a n d s Nu m b e r o f p r o g r a m E r a s e t i m e t i m e s R O M c o d e p r o t e c t i o nA v a i l a b l e i n p a r a l l e l I O m o d e a n d s t a n d a r d s e r i a l I O m o d e Notes 1: The power source voltage must be Vcc = 4.5–5.5 V at program and erase operation. 2: The power source voltage can be Vcc = 3.0–3.6 V also at program and erase operation. 3: The Boot ROM area has had a standard serial I/O mode control program stored in it when shipped from the factory. This Boot ROM area can be rewritten in only parallel I/O mode. S p e c i f i c a t i o nI t e m

3850 Group (Spec. H) SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS Flash Memory Mode The M38507F8 (flash memory version) has an internal new DINOR (DIvided bit line NOR) flash memory that can be rewritten with a single power source when V CC is 5 V, and 2 power sources when VCC is 3.3 V. For this flash memory , three flash memory modes are available in which to read, program, and erase: parallel I/O and standard serial I/ O modes in which the flash memory can be manipulated using a programmer and a CPU rewrite mode in which the flash memory can be manipulated by the Central Processing Unit (CPU). Each mode is detailed in the pages to follow. Fig. 44 Block diagram of flash memory version The flash memory of the M38507F8 is divided into User ROM area and Boot ROM area as shown in Figure 44. In addition to the ordinary user ROM area to store a microcomputer operation control program, the flash memory has a Boot ROM area that is used to store a program to control rewriting in CPU rewrite and standard serial I/O modes. This Boot ROM area has had a stan- dard serial I/O mode control program stored in it when shipped from the factory. However, the user can write a rewrite control program in this area that suits the user’s application system. This Boot ROM area can be rewritten in only parallel I/O mode. B l o c k k b y t e User ROM area 4 kbyte F F F F 6 F F F B o o t R O M a r e a Notes 1: The Boot ROM area can be rewritten in only parallel input/output mode. (Access to any other areas is inhibited.) 2: To specify a block, use the maximum address in the block. P r o d u c t n a m e F l a s h m e m o r y s t a r t a d d r e s s M38507F8 8000 16 P a r a l l e l I O m o d e 800016 Block 1 : 32 kbyte FFFF 16 C P U r e w r i t e m o d e s t a n d a r d s e r i a l I O m o d e User ROM area 4 kbyte F F F F Boot ROM area BSEL = 0 B S E L U s e r a r e a B o o t a r e a s e l e c t i o n b i t s e r a r e a B o o t a r e a s e l e c t i o n b i t

3850 Group (Spec. H) SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS Fig. 45 Flash memory control registers Fig. 46 CPU rewrite mode set/reset flowchart F l a s h m e m o r y c o n t r o l r e g i s t e r S y m b o lA d d r e s sW h e n r e s e t F M C F F 6 X X X WR b 7 b 5 b 4 b 2 b 1 b 0 F M C R B i t s y m b o l B i t n a m e Function R W 0: Busy (being written or erased) 1: Ready C P U r e w r i t e m o d e s e l e c t b i t N o t e 0: Normal mode (Software commands invalid) 1: CPU rewrite mode (Software commands acceptable) F M C R C P U r e w r i t e m o d e e n t r y f l a g F l a s h m e m o r y r e s e t b i t N o t e 0: Normal operation 1: Reset F M C R F M C R Notes 1: For this bit to be set to “1”, the user needs to write a “0” and then a “1” to it in succession. 2: Effective only when the CPU rewrite mode select bit = 1. Set this bit to “0” subsequently after setting it to “1” (reset). R Y B Y s t a t u s f l a g 0: Normal mode (Software commands invalid) 1: CPU rewrite mode (Software commands acceptable) Nothing is assigned. When write, set “0”. When read, values are indeterminate. U s e r a r e a B o o t a r e a s e l e c t i o n b i t 0: User ROM area 1: Boot ROM areaF M C R b3b 6 E n d S t a r t E x e c u t e r e a d a r r a y c o m m a n d o r r e s e t f l a s h m e m o r y b y s e t t i n g f l a s h m e m o r y r e s e t b i t b y w r i t i n g a n d t h e n i n s u c c e s s i o n N o t e S i n g l e - c h i p m o d e , o r b o o t m o d e S e t C P U m o d e r e g i s t e r ( N o t e 1 ) U s i n g s o f t w a r e c o m m a n d e x e c u t e e r a s e , p r o g r a m o r o t h e r o p e r a t i o n J u m p t o t r a n s f e r r e d c o n t r o l p r o g r a m i n R A M S u b s e q u e n t o p e r a t i o n s a r e e x e c u t e d b y c o n t r o l p r o g r a m i n t h i s R A M Transfer CPU rewrite mode control program to internal RAM Notes 1: Set bit 6, 7 (Main clock division ratio selection bits ) at CPU mode register (003B 16). 2: Before exiting the CPU rewrite mode after completing erase or program operation, always be sure to execute a read array command or reset the flash memory. W r i t e “ 0 ” t o C P U r e w r i t e m o d e s e l e c t b i t S e t C P U r e w r i t e m o d e s e l e c t b i t t o “ 1 ” ( b y w r i t i n g a n d t h e n i n s u c c e s s i o n C h e c k t h e C P U r e w r i t e m o d e e n t r y f l a g * 1 * 1 P r o g r a m i n R O M Program in RAM

3850 Group (Spec. H) SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS Software Commands Table 10 lists the software commands. After setting the CPU rewrite mode select bit to “1”, write a software command to specify an erase or program operation. The content of each software command is explained below. Read Array Command (FF16) The read array mode is entered by writing the command code “FF16” in the first bus cycle. When an address to be read is input in one of the bus cycles that follow, the content of the specified address is read out at the data bus (D 0–D7). The read array mode is retained intact until another command is writ- ten. And after power on and after recover from deep power down mode, this mode is selected also. Table 10 List of software commands (CPU rewrite mode) Read Status Register Command (7016) When the command code “7016” is written in the first bus cycle, the content of the status register is read out at the data bus (D0–D 7) by a read in the second bus cycle. The status register is explained in the next section. Clear Status Register Command (5016) This command is used to clear the bits SR1,SR4 and SR5 of the status register after they have been set. These bits indicate that op- eration has ended in an error. To use this command, write the com- mand code “50 16” in the first bus cycle. C o m m a n d Program C l e a r s t a t u s r e g i s t e r Read array R e a d s t a t u s r e g i s t e r X X X X First bus cycle Second bus cycle FF16 7 01 5 01 4016 Write Write Write Write XS R DRead Write Erase all block X 2016Write X 2016Write (Note 1) WA (Note 2) WD (Note 2) B l o c k e r a s e X2 01 6Write D0 16W r i t e B A (Note 3) Mode A d d r e s s M o d e A d d r e s s D a t a (D0 to D7) Data ( D 0 t o D 7) (Note 4) Notes 1: SRD = Status Register Data 2: WA = Write Address, WD = Write Data 3: BA = Block Address (Enter the maximum address of each block.) 4: X denotes a given address in the user ROM area . C y c l e n u m b e r

3850 Group (Spec. H) SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS Fig. 47 Program flowchart Program Command (40 16) Program operation starts when the command code “4016” is written in the first bus cycle. Then, if the address and data to program are written in the 2nd bus cycle, program operation (data programming and verification) will start. Whether the write operation is completed can be confirmed by read- ing the status register or the RY/BY status flag. When the program starts, the read status register mode is accessed automatically and the content of the status register is read into the data bus (D0–D7). The status register bit 7 (SR7) is set to “0” at the same time the write operation starts and is returned to “1” upon completion of the write operation. In this case, the read status register mode remains active until the read array command (FF 16) is written. ____ The RY/BY status flag is “0” during write operation and “1” when the write operation is completed as is the status register bit 7. At program end, program results can be checked by reading the sta- tus register. Erase All Blocks Command (2016/2016) By writing the command code “2016” in the first bus cycle and the confirmation command code “2016” in the second bus cycle that fol- lows, the system starts erase all blocks( erase and erase verify). Whether the erase all blocks command is terminated can be con- ____ firmed by reading the status register or the RY/BY status flag. When the erase all blocks operation starts, the read status register mode is accessed automatically and the content of the status register can be read out. The status register bit 7 (SR7) is set to “0” at the same time the erase operation starts and is returned to “1” upon completion of the erase operation. In this case, the read status register mode re- mains active until the read array command (FF 16) is written. ____ The RY/BY status flag is “0” during erase operation and “1” when the erase operation is completed as is the status register bit 7. At erase all blocks end, erase results can be checked by reading the status register. For details, refer to the section where the status reg- ister is detailed. Block Erase Command (2016/D016) By writing the command code “2016” in the first bus cycle and the confirmation command code “D0 16” in the second bus cycle that follows to the block address of a flash memory block, the system initiates a block erase (erase and erase verify) operation. Whether the block erase operation is completed can be confirmed ____ by reading the status register or the RY/BY status flag. At the same time the block erase operation starts, the read status register mode is automatically entered, so the content of the status register can be read out. The status register bit 7 (SR7) is set to “0” at the same time the block erase operation starts and is returned to “1” upon comple- tion of the block erase operation. In this case, the read status regis- ter mode remains active until the read array command (FF 16) is writ- ten. ____ The RY/BY status flag is “0” during block erase operation and “1” when the block erase operation is completed as is the status register bit 7. After the block erase operation is completed, the status register can be read out to know the result of the block erase operation. For de- tails, refer to the section where the status register is detailed. Fig. 48 Erase flowchart Start Write 4016 Status register read Program completed NO YES Write address Write data SR4=0? Program error NO YES SR7=1? or RY/BY=1? Write Write 2016 2016/D016 Block address Erase completed NO YES Start Write SR5=0? Erase error YES NO 2016:Erase all blocks D0 16:Block erase SR7=1? or RY/BY=1? Status register read

3850 Group (Spec. H) SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS Table 11 Definition of each bit in status register Status Register The status register shows the operating state of the flash memory and whether erase operations and programs ended successfully or in error. It can be read in the following ways. (1) By reading an arbitrary address from the user ROM area after writing the read status register command (70 16) (2) By reading an arbitrary address from the user ROM area in the period from when the program starts or erase operation starts to when the read array command (FF 16) is input Table 11 shows the status register. Also, the status register can be cleared in the following way. (1) By writing the clear status register command (50 16) (2) In the deep power down mode (3) In the power supply off state After a reset, the status register is set to “80 16”. Each bit in this register is explained below. Sequencer status (SR7) After power-on, and after recover from deep power down mode, the sequencer status is set to “1”(ready). The sequencer status indicates the operating status of the device. This status bit is set to “0” (busy) during write or erase operation and is set to “1” upon completion of these operations. Erase status (SR5) The erase status informs the operating status of erase operation to the CPU. When an erase error occurs, it is set to “1”. The erase status is reset to “0” when cleared. Program status (SR4) The program status informs the operating status of write operation to the CPU. When a write error occurs, it is set to “1”. The program status is reset to “0” when cleared. If “1” is written for any of the SR5 or SR4 bits, the program, erase all blocks, and block erase commands are not accepted. Before ex- ecuting these commands, execute the clear status register com- mand (50 16) and clear the status register. Also, any commands are not correct, both SR5 and SR4 are set to “1”. Each bit of SRD0 bits SR7 (bit7) SR6 (bit6) SR5 (bit5) SR4 (bit4) SR3 (bit3) SR2 (bit2) SR1 (bit1) SR0 (bit0) Definition “1” “0” Sequencer status Reserved Erase status Program status Reserved Reserved Reserved Reserved Ready Terminated in error Terminated in error Status name Busy Terminated normally Terminated normally

3850 Group (Spec. H) SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS Full Status Check By performing full status check, it is possible to know the execution results of erase and program operations. Figure 49 shows a full sta- Fig. 49 Full status check flowchart and remedial procedure for errors tus check flowchart and the action to be taken when each error oc- curs. Read status register SR4=1 and SR5 =1 ? NO YES SR5=0? YES Block erase errorNO SR4=0? YES NO Command sequence error Program error End (block erase, program) Execute the clear status register command (5016) to clear the status register. Try performing the operation one more time after confirming that the command is entered correctly. Should a block erase error occur, the block in error cannot be used. Note: When one of SR5 to SR4 is set to “1” , none of the program, erase all blocks, and block erase commands is accepted. Execute the clear status register command (50 16) before executing these commands. Should a program error occur, the block in error cannot be used.

3850 Group (Spec. H) SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS Functions To Inhibit Rewriting Flash Memory Version To prevent the contents of the flash memory version from being read out or rewritten easily, the device incorporates a ROM code protect function for use in parallel I/O mode and an ID code check function for use in standard serial I/O mode. ROM code protect function The ROM code protect function is the function inhibit reading out or modifying the contents of the flash memory version by using the ROM code protect control address (FFDB 16) during parallel I/O mode. Figure 50 shows the ROM code protect control address (FFDB 16). (This address exists in the user ROM area.) If one of the pair of ROM code protect bits is set to “0”, ROM code protect is turned on, so that the contents of the flash memory ver- sion are protected against readout and modification. ROM code protect is implemented in two levels. If level 2 is selected, the flash memory is protected even against readout by a shipment inspection LSI tester, etc. When an attempt is made to select both level 1 and level 2, level 2 is selected by default. If both of the two ROM code protect reset bits are set to “00”, ROM code protect is turned off, so that the contents of the flash memory version can be read out or modified. Once ROM code protect is turned on, the contents of the ROM code protect reset bits cannot be modified in parallel I/O mode. Use the serial I/O or some other mode to rewrite the contents of the ROM code protect reset bits. Fig. 50 ROM code protect control address S y m b o lA d d r e s sW h e n r e s e t R O M C PF F D 6 F R O M c o d e p r o t e c t l e v e l s e t b i t N o t e ) 00: Protect enabled 01: Protect enabled 10: Protect enabled 11: Protect disabled R O M c o d e p r o t e c t c o n t r o l a d d r e s s B i t n a m e FunctionB i t s y m b o l b7 b6 b 00: Protect removed 01: Protect set bit effective 10: Protect set bit effective 11: Protect set bit effective 00: Protect enabled 01: Protect enabled 10: Protect enabled 11: Protect disabled R O M c o d e p r o t e c t r e s e t b i t N o t e R O M c o d e p r o t e c t l e v e l s e t b i t N o t e R O M C P 2 R O M C R ROMCP1 b3 b2 b5 b4 b7 b6 N o t e s 1 : W h e n R O M c o d e p r o t e c t i s t u r n e d o n , t h e o n - c h i p f l a s h m e m o r y i s p r o t e c t e d a g a i n s t r e a d o u t o r m o d i f i c a t i o n i n p a r a l l e l i n p u t o u t p u t m o d e W h e n R O M c o d e p r o t e c t l e v e l i s t u r n e d o n R O M c o d e r e a d o u t b y a s h i p m e n t i n s p e c t i o n L S I t e s t e r e t c a l s o i s i n h i b i t e d T h e R O M c o d e p r o t e c t r e s e t b i t s c a n b e u s e d t o t u r n o f f R O M c o d e p r o t e c t l e v e l a n d R O M c o d e p r o t e c t l e v e l H o w e v e r s i n c e t h e s e b i t s c a n n o t b e c h a n g e d i n p a r a l l e l i n p u t o u t p u t m o d e t h e y n e e d t o b e r e w r i t t e n i n s e r i a l i n p u t o u t p u t m o d e o r s o m e o t h e r m o d e Reserved bit A l w a y s s e t t h i s b i t t o “ 1 ”

3850 Group (Spec. H) SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS ID Code Check Function Use this function in standard serial I/O mode. When the contents of the flash memory are not blank, the ID code sent from the peripheral unit is compared with the ID code written in the flash memory to see if they match. If the ID codes do not match, the commands sent from the peripheral unit are not accepted. The ID code consists of 8-bit data, the areas of which are FFD4 16 to FFDA16. Write a program which has had the ID code preset at these addresses to the flash memory. Fig. 51 ID code store addresses ROM cord Protect control ID7 ID6 ID5 ID4 ID3 ID2 ID1 FFDB 16 FFDA 16 FFD9 16 FFD8 16 FFD7 16 FFD6 16 FFD5 16 FFD4 16 Address Interrupt vector area

3850 Group (Spec. H) SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS Bus Operation Modes Read The Read mode is entered by pulling the OE pin low when the CE pin is low and the WE and RP pins are high. There are two read modes: array, and status register, which are selected by software command input. In read mode, the data corresponding to each soft- ware command entered is output from the data I/O pins D 0–D 7. The read array mode is automatically selected when the device is pow- ered on or after it exits deep power down mode. Output Disable The output disable mode is entered by pulling the CE pin low and the WE, OE, and RP pins high. Also, the data I/O pins are placed in the high-impedance state. Standby The standby mode is entered by driving the CE pin high when the RP pin is high. Also, the data I/O pins are placed in the high-impedance state. However, if the CE pin is set high during erase or program operation, the internal control circuit does not halt immediately and normal power consumption is required until the operation under way is completed. Write The write mode is entered by pulling the WE pin low when the CE pin is low and the OE and RP pins are high. In this mode, the device accepts the software commands or write data entered from the data I/O pins. A program, erase, or some other operation is initiated de- pending on the content of the software command entered here. The input data such as address and software command is latched at the rising edge of WE or CE whichever occurs earlier. Deep Power Down The deep power down is entered by pulling the RP pin low. Also, the data I/O pins are placed in the high-impedance state. When the de- vice is freed from deep power down mode, the read array mode is selected and the content of the status register is set to “80 16.” If the RP pin is pulled low during erase or program operation, the opera- tion under way is canceled and the data in the relevant block be- comes invalid. User ROM and Boot ROM Areas In parallel I/O mode, the user ROM and boot ROM areas shown in Fig- ure 44 can be rewritten. The BSEL pin is used to choose between these two areas. The user ROM area is selected by pulling the BSEL input low; the boot ROM area is selected by driving the BSEL input high. Both areas of flash memory can be operated on in the same way. Program and block erase operations can be performed in the user ROM area. The user ROM area and its block is shown in Figure 44. The user ROM area is 32 Kbytes in size. In parallel I/O mode, it is located at addresses 8000 16 through FFFF16. The boot ROM area is 4 Kbytes in size. In parallel I/O mode, it is located at addresses F000 16 through FFFF16. Make sure program and block erase opera- tions are always performed within this address range. (Access to any location outside this address range is prohibited.) In the Boot ROM area, an erase block operation is applied to only one 4 Kbyte block. The boot ROM area has had a standard serial I/O mode control program stored in it when shipped from the Mitsubishi factory. Therefore, using the device in standard serial input/output mode, you do not need to write to the boot ROM area. Functional Outline (Parallel I/O Mode) In parallel I/O mode, bus operation modes— Read, Output Disable, Standby, Write, and Deep Power Down— are selected by the status of the CE, OE, WE, and RP input pins. The contents of erase, program, and other operations are selected by writing a software command. The data, status register, etc. in memory can only be read out by a read after software command input. Program and erase operations are controlled using software com- mands. The following explains about bus operation modes, software com- mands, and status register. D 0 to D7 Data output Status register data output High impedance High impedance Command/data input Command input Command input High impedance RP VIH VIH VIH VIH VIH VIH VIH VIL WE VIH VIH VIH X VIL VIL VIL X OE VIL VIL VIH X VIH VIH VIH X CE VIL VIL VIL VIH VIL VIL VIL X Pin nameMode Array Status register Output disabled Stand by Program Write Erase Other Deep power down Read Note : X can be VIL or VIH. Table 12 Relationship between control signals and bus operation modes Parallel I/O Mode The parallel I/O mode is entered by making connections shown in Figure 52 and then turning the Vcc power supply on. Address The user ROM is only one block as shown in Figure 44. The block address referred to in this data sheet is the maximum address value of each block.

3850 Group (Spec. H) SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS Table 13 Description of Pin Function (Flash Memory Parallel I/O Mode) P i n n a m eS i g n a l n a m e I/O Function VC C , VS S P o w e r s u p p l y i n p u tA p p l y V t o t h e V c c p i n a n d V t o t h e V s s p i n C N VS S C N VS S C o n n e c t t h i s p i n t o Vc c.I R e s e t i n p u t R e s e t i n p u t p i n W h e n r e s e t i s h e l d l o w m o r e t h a n c y c l e s o f c l o c k a r e r e q u i r e d a t t h e XI N p i n .IR E S E T I XI N C l o c k i n p u t C o n n e c t a c e r a m i c o r c r y s t a l r e s o n a t o r b e t w e e n t h e XI N a n d XO U T p i n s W h e n e n t e r i n g a n e x t e r n a l l y d r i v e d c l o c k e n t e r i t f r o m XI N a n d l e a v e XO U T o p e n I XO U T C l o c k o u t p u tO A VS S A n a l o g p o w e r s u p p l y i n p u t VR E F R e f e r e n c e v o l t a g e i n p u t I C o n n e c t A V s s t o V s s I n p u t A D r e f e r e n c e v o l t a g e o r k e e p o p e n P t o P A d d r e s s i n p u t A0 t o A7 These are address A0–A7 input pins.I P10 to P17 I These are address A8–A15 input pins. D a t a I O D 0 t o D 7 T h e s e a r e d a t a D 0– D 7 i n p u t o u t p u t p i n s O P20 to P27 IP 30 B S E L i n p u tT h i s i s a B S E L i n p u t p i n . Address input A8 to A15 P 33 I P34 I RP input This is a RP input pin. W E i n p u t T h i s i s a W E i n p u t p i n . I P42 to P44 I P41 Input P41 CE input OE input T h i s i s a O E i n p u t p i n . This is a CE input pin. P40 ORY/BY output T h i s i s a R Y / B Y o u t p u t p i n . Input P4 I IP 31 IP 32 Input “H ” or “L” or keep open. Enter low signals to this pin.

3850 Group (Spec. H) SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS Fig. 52 Pin connection diagram in parallel I/O mode P40/CNTR 1 P41/INT0 P42/INT1 P43/INT2/SCMP2 AV SS P44/INT3/PWM VREF P31/AN1 P32/AN2 P00/SIN2 P04 P05 P06 P07 P11/(LED1) P12/(LED2) P13/(LED3) P14/(LED4) P15/(LED5) P10/(LED0) P01/SOUT2 P02/SCLK2 P30/AN0 P33/AN3 P34/AN4 M38507F8SP/FP P16/(LED6) P17/(LED7) P27/CNTR 0/SRDY1 P26/SCLK1 P25/SCL2/TxD P24/SDA2/RxD CNV SS P21/XCIN P20/XCOUT RESET XIN XOUT VSS P03/SRDY2 D 1 D 0 A15 A14 A13 A12 A11 A10 D 7 D 6 D 5 D 4 D 3 D 2 CE OE RP WE BSEL RY/BY P23/SCL1 P22/SDA1 VCC VSS VCC Signal Value CNV SS VCC P41/INT0 VSS VSSRESET ✽ Connect oscillator circuitMode setup method

3850 Group (Spec. H) SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS Software Commands Table 14 lists the software commands. By entering a software com- mand from the data I/O pins (D0–D 7) in Write mode, specify the con- tent of the operation, such as erase or program operation, to be per- formed. The following explains the content of each software command. Read Array Command (FF16) The read array mode is entered by writing the command code “FF16” in the first bus cycle. When an address to be read is input in one of the bus cycles that follow, the content of the specified address is output from the data I/O pins (D 0–D7). The read array mode is retained intact until another command is writ- ten. The read array mode is also selected automatically when the device is powered on and after it exits deep power down mode. Command Read array Read status register Clear status register Program All block erase Block erase Mode Write Write Write Write Write Write Address X(Note 4) X X X X X Data (D0 to D7) FF16 7016 5016 4016 2016 2016 Mode Read Write Write Write Address X WA (Note 2) X BA (Note 3) Data (D0 to D7) SRD (Note 1) WD (Note 2) 2016 D0 16 First bus cycle Second bus cycle Notes 1: SRD = Status Register Data 2: WA = Write Address, WD = Write Data 3: BA = Block Address (Enter the maximum address of each block) 4: X denotes a given address in the user ROM area or boot ROM area. Read Status Register Command (7016) When the command code “7016” is written in the first bus cycle, the content of the status register is output from the data I/O pins (D0–D 7) by a read in the second bus cycle. Since the content of the status register is updated at the falling edge of OE or CE, the OE or CE signal must be asserted each time the status is read. The status register is explained in the next section. Clear Status Register Command (5016) This command is used to clear the bits SR4,SR5 of the status regis- ter after they have been set. These bits indicate that operation has ended in an error. To use this command, write the command code “50 16” in the first bus cycle. Table 14 Software command list (parallel I/O mode) Cycle number

3850 Group (Spec. H) SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS Fig. 54 Block erase flowchart Program Command (40 16) The program operation starts when the command code “4016” is writ- ten in the first bus cycle. Then, if the address and data to program are written in the 2nd bus cycle, program operation (data program- ming and verification) will start. Whether the write operation is completed can be confirmed by read- ing the status register or the RY/BY signal status. When the program starts, the read status register mode is accessed automatically and the content of the status register can be read out from the data bus 0–D 7). The status register bit 7 (SR7) is set to “0” at the same time the write operation starts and is returned to “1” upon completion of the write operation. In this case, the read status register mode re- mains active until the read array command (FF 16) is written. ____ The RY/BY pin is “L” during write operation and “H ” when the write operation is completed as is the status register bit 7. At program end, program results can be checked by reading the sta- tus register. Erase All Blocks Command (2016/2016) By writing the command code “2016” in the first bus cycle and the confirmation command code “2016” in the second bus cycle that fol- lows, the system starts erase all blocks( erase and erase verify). Whether the erase all blocks command is terminated can be con- ____ firmed by reading the status register or the RY/BY signal status . When the erase all blocks operation starts, the read status register mode is accessed automatically and the content of the status regis- ter can be read out. The status register bit 7 (SR7) is set to “0” at the same time the erase operation starts and is returned to “1” upon completion of the erase operation. In this case, the read status regis- ter mode remains active until the read array command (FF 16) is writ- ten. ____ The RY/BY pin is “L” during erase operation and “H ” when the erase operation is completed as is the status register bit 7. At erase all blocks end, erase results can be checked by reading the status register. For details, refer to the section where the status reg- ister is detailed. Block Erase Command (2016/D016) By writing the command code “2016” in the first bus cycle and the confirmation command code “D0 16” in the second bus cycle that follows to the block address of a flash memory block, the system initiates a block erase (erase and erase verify) operation. Whether the block erase operation is completed can be confirmed ____ by reading the status register or the RY/BY signal. At the same time the block erase operation starts, the read status register mode is automatically entered, so the content of the status register can be read out. The status register bit 7 (SR7) is set to “0” at the same time the block erase operation starts and is returned to “1” upon comple- tion of the block erase operation. In this case, the read status regis- ter mode remains active until the read array command (FF 16) is writ- ten. ____ The RY/BY pin is “L” during block erase operation and “H ” when the block erase operation is completed as is the status register bit 7. After the block erase operation is completed, the status register can be read out to know the result of the block erase operation. For de- tails, refer to the section where the status register is detailed. Fig. 53 Page program flowchart Start Write 4016 Status register read Program completed NO YES Write address Write data SR4=0? Program error NO YES SR7=1? or RY/BY=1? Write Write 2016 2016/D016 Block address Erase completed NO YES Start Write SR5=0? Erase error YES NO 2016:Erase all blocks D0 16:Block erase SR7=1? or RY/BY=1? Status register read

3850 Group (Spec. H) SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS Status Register The status register indicates status such as whether an erase opera- tion or a program ended successfully or in error. It can be read under the following conditions. (1) In the read array mode when the read status register command (70 16) is written and the block address is subsequently read. (2) In the period from when the program write or auto erase starts to when the read array command (FF16) The status register is cleared in the following situations. (1) By writing the clear status register command (5016) (2) In the deep power down mode (3) In the power supply off state Table 15 gives the definition of each status register bit. When power is turned on or returning from the deep power down mode, the status register outputs “80 16”. Sequencer status (SR7) The sequencer status indicates the operating status of the flash memory. When power is turned on or returning from the deep power down mode, “1” is set for it. This bit is “0” (busy) during the write or erase operations and becomes “1” when these operations ends. Erase Status (SR5) The erase status reports the operating status of the erase operation. If an erase error occurs, it is set to “1”. When the erase status is cleared, it is set to “0”. Program Status (SR4) The program status reports the operating status of the write opera- tion. If a write error occurs, it is set to “1”. When the program status is cleared, it is set to “0”. If “1” is written for any of the SR5, SR4 bits, the program erase all blocks, block erase, commands are not accepted. Before executing these commands, execute the clear status register command (50 16) and clear the status register. Also, any commands are not correct, both SR5 and SR4 are set to “1”. Full Status Check Results from executed erase and program operations can be known by running a full status check. Figure 55 shows a flowchart of the full status check and explains how to remedy errors which occur. ____ Ready/Busy (RY/BY) pin ____ The RY/BY pin is an output pin (N-chanel open drain output) which, like the sequencer status (SR7), indicates the operating status of the flash memory. It is “L” level during auto program or auto erase opera- tions and becomes to the high impedance state (ready state) when ____ these operations end. The RY/BY pin requires an external pull-up. Table 15 Status register Each bit of SRD0 bits SR7 (D7) SR6 (D6) SR5 (D5) SR4 (D4) SR3 (D3) SR2 (D2) SR1 (D1) SR0 (D0) Sequencer status Reserved Erase status Program status Reserved Reserved Reserved Reserved “1” Ready Ended in error Ended in error Status name “0” Busy Ended successfully Ended successfully Definition

3850 Group (Spec. H) SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS Fig. 55 Full status check flowchart and remedial procedure for errors Read status register SR4=1 and SR5 =1 ? NO YES SR5=0? YES Block erase errorNO SR4=0? YES NO Command sequence error Program error End (block erase, program) Execute the clear status register command (5016) to clear the status register. Try performing the operation one more time after confirming that the command is entered correctly. Should a block erase error occur, the block in error cannot be used. Note: When one of SR5 to SR4 is set to “1” , none of the program, all blocks erase, or block erase is accepted. Execute the clear status register command (5016) before executing these commands. Should a program error occur, the block in error cannot be used.

3850 Group (Spec. H) SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS Standard serial I/O mode The standard serial I/O mode inputs and outputs the software com- mands, addresses and data needed to operate (read, program, erase, etc.) the internal flash memory. This I/O is clock synchronized serial. This modes require a purpose-specific peripheral unit. The standard serial I/O mode is different from the parallel I/O mode in that the CPU controls flash memory rewrite (uses the CPU's re- write mode), rewrite data input and so forth. The standard serial I/O mode is started by connecting “H ” to the P4 1(INT0) pin and “H ” to the CNV SS pin (when VCC = 4.5 V to 5.5 V, connect to VCC ; when VCC = 2.7 V to 4.5 V, supply 4.5 V to 5.5 V to Vpp from an external source), and releasing the reset operation. (In the ordinary command mode, set CNVss pin to “L” level.) This control program is written in the boot ROM area when the prod- uct is shipped from Mitsubishi. Accordingly, make note of the fact that the standard serial I/O mode cannot be used if the boot ROM area is rewritten in the parallel I/O mode. Figure 56 shows the pin connections for the standard serial I/O mode. Serial data I/O uses SI/ O1 data serially in 8-bit units. To use standard serial I/O mode. The operation uses the four SI/O1 pins SCLK , RxD, TxD and SRDY1 (BUSY). The SCLK pin is the trans- fer clock input pin through which an external transfer clock is input. The TxD pin is for CMOS output. The SRDY1 (BUSY) pin outputs an “L” level when ready for reception and an “H ” level when reception starts. In the standard serial I/O mode, only the user ROM area indicated in Figure 44 can be rewritten. The boot ROM cannot. In the standard serial I/O mode, a 7-byte ID code is used. When there is data in the flash memory, commands sent from the periph- eral unit (programmer) are not accepted unless the ID code matches. Overview of standard serial I/O mode In standard serial I/O mode, software commands, addresses and data are input and output between the MCU and peripheral units (serial programer, etc.) using 4-wire clock-synchronized serial I/O (SI/O1). In reception, software commands, addresses and program data are synchronized with the rise of the transfer clock that is input to the S CLK pin, and are then input to the MCU via the RxD pin. In transmis- sion, the read data and status are synchronized with the fall of the transfer clock, and output from the TxD pin. The TxD pin is for CMOS output. Transfer is in 8-bit units with LSB first. When busy, such as during transmission, reception, erasing or pro- gram execution, the SRDY1 (BUSY) pin is “H ” level. Accordingly, al- ways start the next transfer after the SRDY1 (BUSY) pin is “L” level. Also, data and status registers in memory can be read after inputting software commands. Status, such as the operating state of the flash memory or whether a program or erase operation ended success- fully or not, can be checked by reading the status register. Here fol- lowing are explained software commands, status registers, etc.

3850 Group (Spec. H) SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS Table 16 Pin functions (Flash memory standard serial I/O mode) Pin Description VCC ,VSS Apply program/erase protection voltage to Vcc pin and 0 V to Vss pin. CNV SS Connect to VCC when VCC = 4.5 V to 5.5 V. RESET Reset input pin. While reset is “L” level, a 20 cycle or longer clock must be input to XIN pin. XIN Connect a ceramic resonator or crystal oscillator between XIN and XOUT pins. To input an externally generated clock, input it to XIN pin and open XOUT pin.XOUT Name Power input CNV SS Reset input Clock input Clock output I/O I I I O AV SS VREF Connect AVSS to VSS . Enter the reference voltage for AD from this pin. P00 to P07 Input “H ” or “L” level signal or open. P10 to P17 Input “H ” or “L” level signal or open. P20 to P23 Input “H ” or “L” level signal or open. Analog power supply input Reference voltage input Input port P0 Input port P1 Input port P2 I I I I P41 Input “H ” level signal, when reset is released. P40, P42 to P44 Input “H ” or “L” level signal or open. P24 Serial data input pin P25 P26 Serial clock input pin P27 BUSY signal output pin Input P41 Input port P4 RxD input TxD output SCLK input BUSY output I I O I O Serial data output pin I P30 to P34 Input “H ” or “L” level signal or open.Input port P3 I

3850 Group (Spec. H) SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS Fig. 56 Connection for serial I/O mode P40/CNTR 1 P41/INT0 P42/INT1 P 43/ I N T2/ SC M P A VS S P 44/ I N T3/ P W M VR E F P 31/ A N 1 P 32/ A N 2 P 00/ SI N P 04 P 05 P 06 P 07 P 11/ ( L E D 1) P 12/ ( L E D 2) P 13/ ( L E D 3) P 14/ ( L E D 4) P 15/ ( L E D 5) P 10/ ( L E D 0) P 01/ SO U T P 02/ SC L K P 30/ A N 0 P 33/ A N 3 P 34/ A N 4 M 3 8 5 0 7 F 8 S P / F P P 16/ ( L E D 6) P 17/ ( L E D 7) P 27/ C N T R 0/ SR D Y P 26/ SC L K P 25/ S C L2/ T x D P 24/ S D A2/ R x D C N VS S P 21/ XC I N P 20/ XC O U T RESET XIN XO U T VS S P 03/ SR D Y P 41 SC L K P 23/ S C L1 P 22/ S D A1 VC C VS S VC C R E S E T VPP✽ R XD T x D R x D BU S Y N o t e s C o n n e c t o s c i l l a t o r c i r c u i t C o n n e c t t o V c c w h e n V c c V t o V C o n n e c t t o VP P V t o V w h e n V c c V t o V I t i s n e c e s s a r y t o a p p l y V c c o n l y w h e n r e s e t i s r e l e a s e d S i g n a l Value C N VS S P 41 R E S E T M o d e s e t u p m e t h o d t o V VC C VS S → VC C

3850 Group (Spec. H) SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS Software Commands Table 17 lists software commands. In the standard serial I/O mode, erase operations, programs and reading are controlled by transfer- ring software commands via the RxD pin. Software commands are Control command 2nd byte 3rd byte 4th byte 5th byte 6th byte

1 Page read

2 Page program

3 Erase all blocks

4 Read status register

5 Clear status register

6 ID check

7 Download function

8 Version data output function

(middle) Address (middle) D0 16 SRD output Address (low) Size (low) Version data output Address (high) Address (high) SRD1 output Address (middle) Size (high) Version data output Data output Data input Address (high) Check- sum Version data output Data output Data input ID size Data input Version data output Data output Data input ID1 To required number of times Version data output Data output to 259th byte Data input to 259th byte To ID7 Version data output to 9th byte FF 16 4116 A7 16 7016 5016 F516 FA 16 FB 16 When ID is not verified Not acceptable Not acceptable Not acceptable Acceptable Not acceptable Acceptable Not acceptable Acceptable 1st byte transfer Notes 1: Shading indicates transfer from flash memory microcomputer to peripheral unit. All other data is transferred from the peripheral unit to the flash memory microcomputer. 2: SRD refers to status register data. SRD1 refers to status register 1 data. 3: All commands can be accepted when the flash memory is totally blank. 4: Address high (A16 to A23) must be “0016”. explained here below. Basically, the software commands of the standard serial I/O mode is as same as that of the parallel I/O mode, but it is excluded 1 command of block erase, and it is added 3 com- mand of ID check, download function, version data output function. Table 17 Software commands (Standard serial I/O mode 1)

3850 Group (Spec. H) SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS Read Status Register Command This command reads status information. When the “7016” command code is sent with the 1st byte, the contents of the status register (SRD) specified with the 2nd byte and the contents of status register 1 (SRD1) specified with the 3rd byte are read. Page Read Command This command reads the specified page (256 bytes) in the flash memory sequentially one byte at a time. Execute the page read com- mand as explained here following. (1) Transfer the “FF 16” command code with the 1st byte. (2) Transfer addresses A8 to A15 and A16 to A23 (“0016”) with the 2nd and 3rd bytes respectively. (3) From the 4th byte onward, data (D0–D 7) for the page (256 bytes) specified with addresses A8 to A23 will be output sequentially from the smallest address first in sync with the fall of the clock. Fig. 57 Timing for page read Fig. 58 Timing for reading the status register Clear Status Register Command This command clears the bits (SR4–SR5) which are set when the status register operation ends in error. When the “5016” command code is sent with the 1st byte, the aforementioned bits are cleared. When the clear status register operation ends, the SRDY1 (BUSY) signal changes from the “H ” to the “L” level. Fig. 59 Timing for clearing the status register data0 data255 t o 6 t o F F1 SC L K R x D T x D SR D Y B U S Y S R D o u t p u t S R D 1 o u t p u t SCLK RxD TxD SRDY1 (BUSY) 7 01 SCLK RxD TxD SRDY1 (BUSY) 5016

3850 Group (Spec. H) SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS Page Program Command This command writes the specified page (256 bytes) in the flash memory sequentially one byte at a time. Execute the page program command as explained here following. (1) Transfer the “41 16” command code with the 1st byte. (2) Transfer addresses A8 to A15 and A16 to A23 (“0016”) with the 2nd and 3rd bytes respectively. (3) From the 4th byte onward, as write data (D0–D 7) for the page (256 bytes) specified with addresses A8 to A23 is input sequentially from the smallest address first, that page is automatically written. When reception setup for the next 256 bytes ends, the SRDY1 (BUSY) signal changes from the “H ” to the “L” level. The result of the page program can be known by reading the status register. For more information, see the section on the status register. Erase All Blocks Command This command erases the content of all blocks. Execute the erase all blocks command as explained here following. (1) Transfer the “A7 16” command code with the 1st byte. (2) Transfer the verify command code “D0 16” with the 2nd byte. With the verify command code, the erase operation will start and con- tinue for all blocks in the flash memory. When block erasing ends, the SRDY1 (BUSY) signal changes from the “H ” to the “L” level . The result of the erase operation can be known by reading the status register. Fig. 61 Timing for erasing all blocks Fig. 60 Timing for the page program A8 to A15 A16 to A23 4 11 6 data0 d a t a 2 5 5 SC L K R x D T x D SR D Y B U S Y A716 D0 16 SC L K R x D T x D SR D Y B U S Y

3850 Group (Spec. H) SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS Version Information Output Command This command outputs the version information of the control pro- gram stored in the boot area. Execute the version information output command as explained here following. Download Command This command downloads a program to the RAM for execution. Ex- ecute the download command as explained here following. (1) Transfer the “FA 16” command code with the 1st byte. (2) Transfer the program size with the 2nd and 3rd bytes. (3) Transfer the check sum with the 4th byte. The check sum is added to all data sent with the 5th byte onward. (4) The program to execute is sent with the 5th byte onward. When all data has been transmitted, if the check sum matches, the downloaded program is executed. The size of the program will vary according to the internal RAM. Fig. 62 Timing for download (1) Transfer the “FB 16” command code with the 1st byte. (2) The version information will be output from the 2nd byte onward. This data is composed of 8 ASCII code characters. Fig. 63 Timing for version information output F A1 Program data Program data D a t a s i z e l o w C h e c k s u m SC L K R x D T x D SR D Y B U S Y Data size (high) F B1 ‘X’ ‘V ’‘ E’‘ R ’ SC L K R x D T x D SR D Y B U S Y

3850 Group (Spec. H) SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS ID Check This command checks the ID code. Execute the boot ID check com- mand as explained here following. (1) Transfer the “F5 16” command code with the 1st byte. (2) Transfer addresses A0 to A7, A8 to A15 and A16 to A23 (“0016”) of the 1st byte of the ID code with the 2nd, 3rd and 4th bytes re- spectively. (3) Transfer the number of data sets of the ID code with the 5th byte. (4) The ID code is sent with the 6th byte onward, starting with the 1st byte of the code. Fig. 64 Timing for the ID check ID Code When the flash memory is not blank, the ID code sent from the pe- ripheral units and the ID code written in the flash memory are com- pared to see if they match. If the codes do not match, the command sent from the peripheral units is not accepted. An ID code contains 8 bits of data. Area is, from the 1st byte, addresses FFD4 16 to FFDA16. Write a program into the flash memory, which already has the ID code set for these addresses. Fig. 65 ID code storage addresses I D s i z e I D 1 I D 7F 51

6 D4 16 F F1

L K R x D T x D SR D Y B U S Y ROM cord Protect control ID7 ID6 ID5 ID4 ID3 ID2 ID1 FFDB 16 FFDA 16 FFD9 16 FFD8 16 FFD7 16 FFD6 16 FFD5 16 FFD4 16 Address Interrupt vector area

3850 Group (Spec. H) SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS Status Register 1 (SRD1) Status register 1 indicates the status of serial communications, re- sults from ID checks and results from check sum comparisons. It can be read after the SRD by writing the read status register command (70 16). Also, status register 1 is cleared by writing the clear status register command (5016). Table 19 gives the definition of each status register bit. “0016” is out- put when power is turned on and the flag status is maintained even after the reset. Boot Update Completed Bit (SR15) This flag indicates whether the control program was downloaded to the RAM or not, using the download function. Status Register (SRD) The status register indicates operating status of the flash memory and status such as whether an erase operation or a program ended successfully or in error. It can be read by writing the read status reg- ister command (70 16). Also, the status register is cleared by writing the clear status register command (5016). Table 18 gives the definition of each status register bit. After clearing the reset, the status register outputs “80 16”. Sequencer status (SR7) After power-on and recover from deep power down mode, the se- quencer status is set to “1”(ready). The sequencer status indicates the operating status of the device. This status bit is set to “0” (busy) during write or erase operation and is set to “1” upon completion of these operations. Erase Status (SR5) The erase status reports the operating status of the auto erase op- eration. If an erase error occurs, it is set to “1”. When the erase sta- tus is cleared, it is set to “0”. Program Status (SR4) The program status reports the operating status of the auto write operation. If a write error occurs, it is set to “1”. When the program status is cleared, it is set to “0”. SRD0 bits SR7 (bit7) SR6 (bit6) SR5 (bit5) SR4 (bit4) SR3 (bit3) SR2 (bit2) SR1 (bit1) SR0 (bit0) Definition “1” “0” Table 18 Status register (SRD) Table 19 Status register 1 (SRD1)

00 Not verified

01 Verification mismatch

10 Reserved

11 Verified

SR15 (bit7) SR14 (bit6) SR13 (bit5) SR12 (bit4) SR11 (bit3) SR10 (bit2) SR9 (bit1) SR8 (bit0) Boot update completed bit Reserved Reserved Checksum match bit ID check completed bits Data reception time out Reserved “1” Update completed Match Time out “0” Not Update Mismatch Normal operation DefinitionSRD1 bits Status name Status name Sequencer status Reserved Erase status Program status Reserved Reserved Reserved Reserved Ready Terminated in error Terminated in error Busy Terminated normally Terminated normally Check Sum Consistency Bit (SR12) This flag indicates whether the check sum matches or not when a program is downloaded for execution using the download function. ID Check Completed Bits (SR11 and SR10) These flags indicate the result of ID checks. Some commands can- not be accepted without an ID check. Data Reception Time Out (SR9) This flag indicates when a time out error is generated during data reception. If this flag is attached during data reception, the received data is discarded and the microcomputer returns to the command wait state.

3850 Group (Spec. H) SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS Full Status Check Results from executed erase and program operations can be known Example Circuit Application for The Standard Serial I/O Mode Fig. 66 Full status check flowchart and remedial procedure for errors Fig. 67 Example circuit application for the standard serial I/O mode by running a full status check. Figure 66 shows a flowchart of the full status check and explains how to remedy errors which occur. Figure 67 shows a circuit application for the standard serial I/O mode. Control pins will vary according to programmer, therefore see the peripheral unit manual for more information. R e a d s t a t u s r e g i s t e r S R 4 = 1 a n d S R5 N O C o m m a n d s e q u e n c e e r r o r Y E S S R 5 = 0 ? Y E S Er a s e e r r o r N O S R 4 = 0 ? Y E S Program error N O End (block erase, program) Execute the clear status register command (5016) to clear the status register. Try performing the operation one more time after confirming that the command is entered correctly. Should a block erase error occur, the block in error cannot be used. N o t e W h e n o n e o f S R t o S R i s s e t t o n o n e o f t h e p r o g r a m e r a s e a l l b l o c k s c o m m a n d s i s a c c e p t e d E x e c u t e t h e c l e a r s t a t u s r e g i s t e r c o m m a n d b e f o r e e x e c u t i n g t h e s e c o m m a n d s Should a program error occur, the block in error cannot be used. SR D Y B U S Y SC L K R XD TXD C N V s s C l o c k i n p u t B U S Y o u t p u t D a t a i n p u t D a t a o u t p u t M 3 8 5 0 7 F 8 N o t e s 1 : C o n t r o l p i n s a n d e x t e r n a l c i r c u i t r y w i l l v a r y a c c o r d i n g t o p e r i p h e r a l u n i t . F o r m o r e i n f o r m a t i o n s e e t h e p e r i p h e r a l u n i t m a n u a l : I n t h i s e x a m p l e t h e V p p p o w e r s u p p l y i s s u p p l i e d f r o m a n e x t e r n a l s o u r c e w r i t e r T o u s e t h e u s e r s p o w e r s o u r c e c o n n e c t t o V t o V VP P p o w e r s o u r c e i n p u t P

3850 Group (Spec. H) SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS Table 21 Flash memory mode Electrical characteristics (Ta = 25oC, VCC = 4.5 to 5.5V unless otherwise noted) Flash memory Electrical characteristics VPP power source current (read) VPP power source current (program) VPP power source current (erase) “L” input voltage (Note) “H ” input voltage (Note) VPP power source voltage Limits Parameter Min. Typ. Max.Symbol Unit Note: Input pins for parallel I/O mode. VPP = VCC VPP = VCC VPP = VCC Microcomputer mode operation at VCC = 2.7 to 5.5V Microcomputer mode operation at V CC = 2.7 to 3.6V Conditions IPP1 IPP2 IPP3 VIL VIH VPP 2.0 4.5 100 0.8 VCC 5.5 µA mA mA V V V Table 20 Absolute maximum ratings Power source voltage Input voltage P00–P07, P10–P17, P20, P21, P24–P27, P30–P34, P40–P44, VREF Input voltage P22, P23 Input voltage RESET, XIN Input voltage CNVSS Output voltage P00–P07, P10–P17, P20, P21, P24–P27, P30–P34, P40–P44, XOUT Output voltage P22, P23 Power dissipation Operating temperature Storage temperature VCC VI VI VI VI VO VO Pd Topr Tstg Symbol Parameter Conditions Ratings –0.3 to 6.5 –0.3 to VCC +0.3 –0.3 to 5.8 –0.3 to VCC +0.3 –0.3 to VCC +0.3 –0.3 to VCC +0.3 –0.3 to 5.8 1000 (Note) 25±5 –40 to 125 V V V V V V V mW Unit Ta = 25 °C All voltages are based on VSS . Output transistors are cut off. Note: The rating becomes 300 mW at the 42P2R-A/E package. VCC VCC power source voltage 4.5 3.0 5.5 3.6 V V

3850 Group (Spec. H) SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS (Ta = 25oC, VCC = 4.5 to 5.5V unless otherwise noted) Table 22 Read-only mode Read cycle time Address access time CE access time OE access time Output enable time (after CE) Output floating time (after CE) Output enable time (after OE) Output floating time (after OE) Output floating time (after PR) Output valid time (after CE, OE, address) Write recovery time (before read) RP recovery time Limits ns ns ns ns ns ns ns ns ns ns ns µs Parameter Min. 200 200 Typ. Max. 100 100 300 Symbol Unit Note :Timing measurement condition is showed in Figure 71. tRC ta (AD) ta (CE) ta (OE) tCLZ tDF(CE) tOLZ tDF(OE) tPHZ tOH tOEH tPS LimitsParameter 200 100 100 100 Symbol Unit Note :The read timing parameter in the command write operation mode is same as that of the read-only mode. Typical value is at VCC = 5.0 V, Ta = 25 °C condition. Write cycle time Address set up time Address hold time Data set up time Data hold time CE set up time CE hold time WE pulse width “H ” write pulse width Program time Erase all blocks time RY/BY delay time RP recovery time tWC tAS tAH tDS tDH tCS tCH tWP tWPH tDAP tDAE tWHRL tPS Min. Typ. Max. 1.5 200 ns ns ns ns ns ns ns ns ns µ s s ns µ s Table 23 Read / Write mode (WE control)

3850 Group (Spec. H) SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS LimitsParameter 200 100 100 100 Symbol Unit Write cycle time Address set up time Address hold time Data set up time Data hold time WE set up time WE hold time CE pulse width “H ” CE pulse width Program time Erase all blocks time RY/BY delay time RP recovery time tWC tAS tAH tDS tDH tWS tWH tCEP tCEPH tDAP tDAE tEHRL tPS Min. Typ. Max. 1.5 200 ns ns ns ns ns ns ns ns ns µs s ns µs Table 24 Read / Write mode (CE control) Parameter Erase all blocks time Block erase time Program time (1byte) 1.5 1.0 s s µs Min. Typ. Max. Unit Table 25 Erase and program operation Symbol Min. Typ. Max. Unit Table 26 VCC power up / power down timing Parameter RP = VIH set up time (after rised VCC = VCC min.)tVCS 10 Note :The read timing parameter in the command write operation mode is same as that of the read-only mode. Typical value is at VCC = 5.0 V, Ta = 25 °C condition. Note :Miserase or miswrite may happen, in case of noise pulse due to the power supply on or off is input to the control pins. Therefore disableing the write mode is need for prevent from memory data break at the power supply on or off. 10µ s (min.) waiting time is need to initiate read or write op- eration after VCC rises to VCC min. at power supply on. The memory data is protected owing to keep the RP pin VIL level at power supply off. The RP pin must be kept VIL level for 10µs (min.) after VCC rises to VCC min. at the power supply on. The RP pin must be kept VIL level until the VCC falls to the GND level at power supply off. RP pin doesn't have latch mode, so RP pin must be kept VIH level during read, erase and program op- eration. Flash memory mode Electrical characteristics (Ta = 25oC, VCC = 4.5 to 5.5V unless otherwise noted) µ s

3850 Group (Spec. H) SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS Fig. 68 VCC power up / power down timing 5.0V GND VCC VIH VIL RP Inhibit read / write tVCS VIH VIL CE VIH VIL WE tPS tPS Inhibit read / write Inhibit read / write

3850 Group (Spec. H) SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS Fig. 69 AC wave for program operation (WE control) Fig. 70 AC wave for program operation (CE control) VIH VIL Address VIH VIL VIH VIL VIH VoH CE OE WE DATA RY/BY VIL VIH VIL VoL 40H DIN tCS tCH tWPH tWP tDS tWHRL tOEH ta(CE) ta(OE) tDH SRD FFH tAHtAStWC VIH VIL RP tPS tDAP Valid Address Valid Address Program Read status register Write read array command VIH VIL Address VIH VIL VIH VIL VIH VoH CE OE WE DATA RY/BY VIL VIH VIL VoL 40H DIN tWS tWH tCEP tDS tEHRL tOEH ta(CE) ta(OE) tDH SRD FFH tAHtAStWC VIH VIL RP tPS tDAP Program Read status register Write read array command Valid Address Valid Address

3850 Group (Spec. H) SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS Fig. 71 AC wave for read operation and test condition Fig. 72 AC electrical characteristics test condition Valid output HIGH-Z tDF(OE) tRC VIH VIL VIH VIL VIH VIL VIH VIL VOH VOL Address CE OE WE DATA Valid address tOH tOLZ ta (CE) tOEH tCLZ ta (AD) ta (OE) HIGH-Z VIH VIL RP tPS tDF(CE) tPHZ 3.3k 1N914 1.3V C L =100pF AC electrical characteristics test condition Input voltage : VIL = 0V, VIH = 5.0V Input signal rising time, falling time : 10ns Timing measurement Reference voltage : 1.5V Load circuit : 1TTL gate+ CL(100pF ) or measurement pin

3850 Group (Spec. H) SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS Fig. 73 AC wave for erase operation (WE control) Fig. 74 AC wave for erase operation (CE control) 20H D0H tWPH tWP tDS tDH tCS tCH tWC VIH VIL VIH VIL VIH VIL VIH VIL tAH VIH VOH VOL VILAddress tAS FFHSRD tOEH tDAE tWHRL ta(OE) ta(CE) CE OE WE DATA RY/BY VIH VIL tPS RP Erase Read status register Write read array command Valid Address Valid Address 20H D0H tCEPHtCEP tDS tDH tWS tWH tWC VIH VIL VIH VIL VIH VIL VIH VIL tAH VIH VOH VOL VIL Address tAS FFHSRD tOEH tDAE tEHRL ta(OE) ta(CE) CE OE WE DATA RY/BY VIH VIL tPS RP Valid Address Erase Read status register Write read array command Valid Address

3850 Group (Spec. H) SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS NOTES ON PROGRAMMING Processor Status Register The contents of the processor status register (PS) after a reset are undefined, except for the interrupt disable flag (I) which is “1.” Af- ter a reset, initialize flags which affect program execution. In particular, it is essential to initialize the index X mode (T) and the decimal mode (D) flags because of their effect on calculations. Interrupts The contents of the interrupt request bits do not change immedi- ately after they have been written. After writing to an interrupt request register, execute at least one instruction before perform- ing a BBC or BBS instruction. Decimal Calculations

To calculate in decimal notation, set the decimal mode flag (D) to “1”, then execute an ADC or SBC instruction. After executing an ADC or SBC instruction, execute at least one instruction be- fore executing a SEC, CLC, or CLD instruction.
In decimal mode, the values of the negative (N), overflow (V), and zero (Z) flags are invalid. Timers If a value n (between 0 and 255) is written to a timer latch, the fre- quency division ratio is 1/(n+1). Multiplication and Division Instructions
The index X mode (T) and the decimal mode (D) flags do not af- fect the MUL and DIV instruction.
The execution of these instructions does not change the con- tents of the processor status register. Ports The contents of the port direction registers cannot be read. The following cannot be used:
The data transfer instruction (LDA, etc.)
The operation instruction when the index X mode flag (T) is “1”
The addressing mode which uses the value of a direction regis- ter as an index
The bit-test instruction (BBC or BBS, etc.) to a direction register
The read-modify-write instructions (ROR, CLB, or SEB, etc.) to a direction register. Use instructions such as LDM and STA, etc., to set the port direc- tion registers. Serial I/O In clock synchronous serial I/O, if the receive side is using an ex- ternal clock and it is to output the S RDY1 signal, set the transmit enable bit, the receive enable bit, and the SRDY1 output enable bit to “1.” Serial I/O1 continues to output the final bit from the TX D pin after transmission is completed. S OUT2 pin for serial I/O2 goes to high impedance after transmis- sion is completed. When an external clock is used as synchronous clock in serial I/ O1 or serial I/O2, write transmission data to the transmit buffer register or serial I/O2 register while the transfer clock is “H.” A-D Converter The comparator uses capacitive coupling amplifier whose charge will be lost if the clock frequency is too low. Therefore, make sure that f(X IN) in the middle/high-speed mode is at least on 500 kHz during an A-D conversion. Do not execute the STP or WIT instruction during an A-D conver- sion. Instruction Execution Time The instruction execution time is obtained by multiplying the fre- quency of the internal clock φ by the number of cycles needed to execute an instruction. The number of cycles required to execute an instruction is shown in the list of machine instructions. The frequency of the internal clock φ is half of the X IN frequency in high-speed mode. NOTES ON USAGE Differences between 3850 group (standard) and 3850 group (spec. H) (1) The absolute maximum ratings of 3850 group (spec. H) is smaller than that of 3850 group (standard).
Power source voltage Vcc = –0.3 to 6.5 V
CNVss input voltage V I = –0.3 to Vcc +0.3 V (2) The oscillation circuit constants of XIN-XOUT , XCIN-XCOUT may be some differences between 3850 group (standard) and 3850 group (spec. H). (3) Do not write any data to the reserved area and the reserved bit. (Do not change the contents after rest.) (4) Fix bit 3 of the CPU mode register to “1”. (5) Be sure to perform the termination of unused pins. Handling of Source Pins In order to avoid a latch-up occurrence, connect a capacitor suit- able for high frequencies as bypass capacitor between power source pin (V CC pin) and GND pin (VSS pin) and between power source pin (VCC pin) and analog power source input pin (AVSS pin). Besides, connect the capacitor to as close as possible. For bypass capacitor which should not be located too far from the pins to be connected, a ceramic capacitor of 0.01 µF–0.1µ F is recom- mended. EPROM Version/One Time PROM Version/ Flash Memory Version The CNVss pin is connected to the internal memory circuit block by a low-ohmic resistance, since it has the multiplexed function to be a programmable power source pin (V PP pin) as well. To improve the noise reduction, connect a track between CNVss pin and Vss pin or Vcc pin with 1 to 10 kΩ resistance. The mask ROM version track of CNVss pin has no operational in- terference even if it is connected to Vss pin or Vcc pin via a resistor.

3850 Group (Spec. H) SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS DATA REQUIRED FOR MASK ORDERS The following are necessary when ordering a mask ROM produc- tion: 1. Mask ROM Order Confirmation Form ✽ 1 2. Mark Specification Form✽ 2 3. Data to be written to ROM, in EPROM form (three identical cop- ies) or one floppy disk. DATA REQUIRED FOR One Time PROM PROGRAMMING ORDERS The following are necessary when ordering a PROM programming service: 1. ROM Programming Confirmation Form ✽ 1 2. Mark Specification Form✽ 2 (only special mark with customer’s trade mark logo) 3. Data to be programmed to PROM, in EPROM form (three iden- tical copies) or one floppy disk. For the mask ROM confirmation and the mark specifications, refer to the “Mitsubishi MCU Technical Information” Homepage. ✽ 1 Mask ROM Confirmation Forms ✽ 2 Mark Specification Forms ROM PROGRAMMING METHOD The built-in PROM of the blank One Time PROM version and buit- in EPROM version can be read or programmed with a general-purpose PROM programmer using a special programming adapter. Set the address of PROM programmer in the user ROM area. Table 27 Programming adapter Package 42P4B, 42S1B 42P2R-A/E Name of Programming Adapter PCA4738S-42A PCA4738F-42A The PROM of the blank One Time PROM version is not tested or screened in the assembly process and following processes. To en- sure proper operation after programming, the procedure shown in Figure 75 is recommended to verify programming. Fig. 75 Programming and testing of One Time PROM version Programming with PROM programmer Screening (Caution) (150 °C for 40 hours) Verification with PROM programmer Functional check in target device The screening temperature is far higher than the storage temperature. Never expose to 150 °C exceeding 100 hours. Caution :

3850 Group (Spec. H) SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS VCC VSS VREF AV SS VIA VIH VIH VIL VIL VIL

ELECTRICAL CHARACTERISTICS

Table 28 Absolute maximum ratings Power source voltage Input voltage P00–P07, P10–P17, P20, P21, P24–P27, P30–P34, P40–P44, VREF Input voltage P22, P23 Input voltage RESET , XIN Input voltage CNVSS Output voltage P00–P07, P10–P17, P20, P21, P24–P27, P30–P34, P40–P44, XOUT Output voltage P22, P23 Power dissipation Operating temperature Storage temperature VCC VI VI VI VI VO VO Pd Topr Tstg Symbol Parameter Conditions Ratings –0.3 to 6.5 –0.3 to VCC +0.3 –0.3 to 5.8 –0.3 to VCC +0.3 –0.3 to VCC +0.3 –0.3 to VCC +0.3 –0.3 to 5.8 1000 (Note) –20 to 85 –40 to 125 V V V V V V V mW Unit T a = 25 °C All voltages are based on VSS . Output transistors are cut off. 5.5 5.5 VCC VCC VCC VCC 0.2VCC 0.2VCC 0.16VCC Power source voltage Power source voltage A-D convert reference voltage Analog power source voltage Analog input voltage AN 0–AN 4 “H ” input voltage P0 0–P07, P10–P17, P20–P27, P30–P34, P40–P44 “H ” input voltage RESET , X IN, CNVSS “L” input voltage P0 0–P07, P10–P17, P20–P27, P30–P34, P40–P44 “L” input voltage RESET , CNV SS “L” input voltage X IN Symbol Parameter Limits Min. Unit Table 29 Recommended operating conditions (1) (VCC = 2.7 to 5.5 V, Ta = –20 to 85 °C, unless otherwise noted) 4.0 2.7 2.0 AV SS 0.8VCC 0.8VCC 5.0 5.0 Typ. Max. –80 –80 120 –40 –40 “H ” total peak output current P0 0–P07, P10–P17, P30–P34 (Note) “H ” total peak output current P20, P21, P24–P27, P40–P44 (Note) “L” total peak output current (Note) P00–P07, P30–P34 “L” total peak output current (Note) P10–P17 “L” total peak output current P2 0–P27,P40–P44 (Note) “H ” total average output current P00–P07, P10–P17, P30–P34 (Note) “H ” total average output current P20, P21, P24–P27, P40–P44 (Note) “L” total average output current (Note)P00–P07, P30–P34 “L” total average output current (Note)P10–P17 “L” total average output current P20–P27,P40–P44 (Note) Σ IOH(peak) Σ IOH(peak) Σ IOL(peak) Σ IOL(peak) Σ IOL(peak) Σ IOH(avg) Σ IOH(avg) Σ IOL(avg) Σ IOL(avg) Σ IOL(avg) mA mA mA mA mA mA mA mA mA mA Note :The total output current is the sum of all the currents flowing through all the applicable ports. The total average current is an average value measured over 100 ms. The total peak current is the peak value of all the currents. V V V V V V V V V V Note :The rating becomes 300mW at the 42P2R-A/E package.

8 MHz (high-speed mode)

8 MHz (middle-speed mode), 4 MHz (high-speed mode)

3850 Group (Spec. H) SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS Table 30 Recommended operating conditions (2) (VCC = 2.7 to 5.5 V, Ta = –20 to 85 °C, unless otherwise noted) –10 “H ” peak output current P0 0–P07, P10–P17, P20, P21, P24–P27, P30–P34, P40–P44 (Note 1) “L” peak output current (Note 1) P00–P07, P20–P27, P30–P34, P40–P44 “L” peak output current (Note 1) P10–P17 “H ” average output current P0 0–P07, P10–P17, P20, P21, P24–P27, P30–P34, P40–P44 (Note 2) “L” average output current (Note 2)P00–P07, P20–P27, P30–P34, P40–P44 “L” average output current (Note 2)P10–P17 Internal clock oscillation frequency (VCC = 4.0 to 5.5V) (Note 3) Internal clock oscillation frequency (VCC = 2.7 to 5.5V) (Note 3) IOH(peak) IOL(peak) IOL(peak) IOH(avg) IOL(avg) IOL(avg) f(XIN) f(XIN) Symbol Parameter Limits Min. mA mA mA mA mA mA MHz MHz Unit Typ. Max. Notes 1: The peak output current is the peak current flowing in each port. 2: The average output current IOL (avg), IOH (avg) are average value measured over 100 ms. 3: When the oscillation frequency has a duty cycle of 50%.

3850 Group (Spec. H) SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS Table 31 Electrical characteristics (1) (VCC = 2.7 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted) “H ” output voltage P00–P07, P10–P17, P20, P21, P24–P27, P30–P34, P40–P44 (Note) “L” output voltage P00–P07, P20–P27,P30–P34, P40–P44 “L” output voltage P10–P17 Hysteresis CNTR 0, CNTR1, INT0–INT3 Hysteresis RxD, SCLK Hysteresis RESET “H ” input current P00–P07, P10–P17, P20, P21, P24–P27, P30–P34, P40–P44 “H ” input current RESET , CNVSS “H ” input current XIN “L” input current P00–P07, P10–P17, P20–P27 P30–P34, P40–P44 “L” input current RESET ,CNVSS “L” input current XIN RAM hold voltage Limits V V V V V V V V V µA µA µA µA µA µA V Parameter Min. Typ. Max.Symbol Unit Note: P25 is measured when the P25/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”. IOH = –10 mA VCC = 4.0–5.5 V IOH = –1.0 mA VCC = 2.7–5.5 V IOL = 10 mA VCC = 4.0–5.5 V IOL = 1.0 mA VCC = 2.7–5.5 V IOL = 20 mA VCC = 4.0–5.5 V IOL = 10 mA VCC = 2.7–5.5 V VI = VCC VI = VCC VI = VCC VI = VSS VI = VSS VI = VSS When clock stopped VCC –2.0 VCC –1.0 2.0 Test conditions 0.4 0.5 0.5 2.0 1.0 2.0 1.0 5.0 5.0 –5.0 –5.0 5.5 VOH VOL VOL VT+–VT– VT+–VT– VT+–VT– IIH IIH IIH IIL IIL IIL VRAM

3850 Group (Spec. H) SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS Table 32 Electrical characteristics (2) (VCC = 2.7 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted) Power source current Limits Parameter Min. Typ. Max.Symbol Unit High-speed mode f(XIN) = 8 MHz f(XCIN) = 32.768 kHz Output transistors “off” High-speed mode f(XIN) = 8 MHz (in WIT state) f(XCIN) = 32.768 kHz Output transistors “off” Low-speed mode f(XIN) = stopped f(XCIN) = 32.768 kHz Output transistors “off” Low-speed mode f(XIN) = stopped f(XCIN) = 32.768 kHz (in WIT state) Output transistors “off” Low-speed mode (VCC = 3 V) f(XIN) = stopped f(XCIN) = 32.768 kHz Output transistors “off” Low-speed mode (VCC = 3 V) f(XIN) = stopped f(XCIN) = 32.768 kHz (in WIT state) Output transistors “off” Middle-speed mode f(XIN) = 8 MHz f(XCIN) = stopped Output transistors “off” Middle-speed mode f(XIN) = 8 MHz (in WIT state) f(XCIN) = stopped Output transistors “off” Increment when A-D conversion is executed f(X IN) = 8 MHz Test conditions ICC Ta = 25 °C Ta = 85 °C 6.8 mA All oscillation stopped (in STP state) Output transistors “off” 1.6 5.0 4.0 1.5 800 0.1 200 10.0 7.0 1.0 mA µA µA µA µA mA mA µA µA µA Except M38507F8FP/SP M38507F8FP/SP Except M38507F8FP/SP M38507F8FP/SP T.B.D. T.B.D. µA µA

3850 Group (Spec. H) SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS bit LSB 2tc(XIN) µ s kΩ µA µA Resolution Absolute accuracy (excluding quantization error) Conversion time Ladder resistor Reference power source input current A-D port input current Min. Typ. 150 0.5 Max. 200 5.0 5.0 High-speed mode, Middle-speed mode Low-speed mode V REF = 5.0 V Table 33 A-D converter characteristics (VCC = 2.7 to 5.5 V, VSS = AVSS = 0 V , Ta = –20 to 85 °C, f(XIN) = 8 MHz, unless otherwise noted) Unit Limits Parameter tCONV R LADDER IVREF II(AD) Test conditionsSymbol VREF “on” VREF “off”

3850 Group (Spec. H) SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS TIMING REQUIREMENTS Table 34 Timing requirements (1) (VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted) Reset input “L” pulse width External clock input cycle time External clock input “H ” pulse width External clock input “L” pulse width CNTR 0, CNTR1 input cycle time CNTR 0, CNTR1 input “H ” pulse width CNTR 0, CNTR1 input “L” pulse width INT0 to INT3 input “H ” pulse width INT0 to INT3 input “L” pulse width Serial I/O1 clock input cycle time (Note) tW (RESET) tC (XIN) tWH (XIN) tWL (XIN) tC (CNTR) tWH (CNTR) tWL (CNTR) tWH (INT) tWL (INT) tC (SCLK1 ) tWH (SCLK1 ) tWL (SCLK1 ) tsu(RxD-SCLK1 ) th(SCLK1 -RxD) tC (SCLK2 ) tWH (SCLK2 ) tWL (SCLK2 ) tsu(SIN2-SCLK2 ) th(SCLK2 -SIN2) Limits XIN cycle ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Parameter Min. 125 200 800 370 370 220 100 1000 400 400 200 200 Typ. Max.Symbol Unit Note : When f(XIN) = 8 MHz and bit 6 of address 001A16 is “1” (clock synchronous). Divide this value by four when f(XIN) = 8 MHz and bit 6 of address 001A16 is “0” (UART). Serial I/O1 clock input “H ” pulse width (Note) Serial I/O1 clock input “L” pulse width (Note) Serial I/O1 input setup time Serial I/O1 input hold time Serial I/O2 clock input cycle time Serial I/O2 clock input “H ” pulse width Serial I/O2 clock input “L” pulse width Serial I/O2 clock input setup time Serial I/O2 clock input hold time Table 35 Timing requirements (2) CC = 2.7 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted) Reset input “L” pulse width External clock input cycle time External clock input “H ” pulse width External clock input “L” pulse width CNTR 0, CNTR1 input cycle time CNTR 0, CNTR1 input “H ” pulse width CNTR 0, CNTR1 input “L” pulse width INT0 to INT3 input “H ” pulse width INT0 to INT3 input “L” pulse width Serial I/O1 clock input cycle time (Note) Serial I/O1 clock input “H ” pulse width (Note) Serial I/O1 clock input “L” pulse width (Note) Serial I/O1 input setup time Serial I/O1 input hold time Serial I/O2 clock input cycle time Serial I/O2 clock input “H ” pulse width Serial I/O2 clock input “L” pulse width Serial I/O2 clock input setup time Serial I/O2 clock input hold time tW (RESET) tC (XIN) tWH (XIN) tWL (XIN) tC (CNTR) tWH (CNTR) tWL (CNTR) tWH (INT) tWL (INT) tC (SCLK1 ) tWH (SCLK1 ) tWL (SCLK1 ) tsu(RxD-SCLK1 ) th(SCLK1 -RxD) tC (SCLK2 ) tWH (SCLK2 ) tWL (SCLK2 ) tsu(SIN2-SCLK2 ) th(SCLK2 -SIN2) Limits XIN cycle ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Parameter Min. 250 100 100 500 230 230 230 230 2000 950 950 400 200 2000 950 950 400 300 Typ. Max.Symbol Unit Note : When f(XIN) = 4 MHz and bit 6 of address 001A16 is “1” (clock synchronous). Divide this value by four when f(XIN) = 4 MHz and bit 6 of address 001A16 is “0” (UART).

3850 Group (Spec. H) SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS Table 36 Switching characteristics (1) (VCC = 4.0 to 5.5 V, VSS = 0 V , Ta = –20 to 85 °C, unless otherwise noted) Serial I/O1 clock output “H ” pulse width Serial I/O1 clock output “L” pulse width Serial I/O1 output delay time (Note 1) Serial I/O1 output valid time (Note 1) Serial I/O1 clock output rising time Serial I/O1 clock output falling time Serial I/O2 clock output “H ” pulse width Serial I/O2 clock output “L” pulse width Serial I/O2 output delay time (Note 2) Serial I/O2 output valid time (Note 2) Serial I/O2 clock output falling time CMOS output rising time (Note 3) CMOS output falling time (Note 3) tWH (SCLK1 ) tWL (SCLK1 ) td (SCLK1 -TX D) tv (SCLK1 -TX D) tr (SCLK1 ) tf (SCLK1 ) tWH (SCLK2 ) tWL (SCLK2 ) td (SCLK2 -SOUT2 ) tv (SCLK2 -SOUT2 ) tf (SCLK2 ) tr (CMOS) tf (CMOS) Limits ns ns ns ns ns ns ns ns ns ns ns ns ns Parameter Min. t C (SCLK1 )/2–30 tC (SCLK1 )/2–30 –30 tC (SCLK2 )/2–160 tC (SCLK2 )/2–160 Typ. Max. 140 200 Symbol Unit Notes 1:When the P25/TX D P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”. 2:When the P01/SOUT2 and P02/SCLK2 P-channel output disable bit of the Serial I/O2 control register 1 (bit 7 of address 001516) is “0”. 3:The XOUT pin is excluded. Test conditions Fig.76 Table 37 Switching characteristics (2) (VCC = 2.7 to 5.5 V, VSS = 0 V , Ta = –20 to 85 °C, unless otherwise noted) Serial I/O1 clock output “H ” pulse width Serial I/O1 clock output “L” pulse width Serial I/O1 output delay time (Note 1) Serial I/O1 output valid time (Note 1) Serial I/O1 clock output rising time Serial I/O1 clock output falling time Serial I/O2 clock output “H ” pulse width Serial I/O2 clock output “L” pulse width Serial I/O2 output delay time (Note 2) Serial I/O2 output valid time (Note 2) Serial I/O2 clock output falling time CMOS output rising time (Note 3) CMOS output falling time (Note 3) tWH (SCLK1 ) tWL (SCLK1 ) td (SCLK1 -TX D) tv (SCLK1 -TX D) tr (SCLK1 ) tf (SCLK1 ) tWH (SCLK2 ) tWL (SCLK2 ) td (SCLK2 -SOUT2 ) tv (SCLK2 -SOUT2 ) tf (SCLK2 ) tr (CMOS) tf (CMOS) Limits ns ns ns ns ns ns ns ns ns ns ns ns ns Parameter Min. t C (SCLK1 )/2–50 tC (SCLK1 )/2–50 –30 tC (SCLK2 )/2–240 tC (SCLK2 )/2–240 Typ. Max. 350 400 Symbol Unit Notes 1:When the P25/TX D P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”. 2:When the P01/SOUT2 and P02/SCLK2 P-channel output disable bit of the Serial I/O2 control register 1 (bit 7 of address 001516) is “0”. 3:The XOUT pin is excluded. Test conditions Fig.76

3850 Group (Spec. H) SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS Fig. 76 Circuit for measuring output switching characteristics Measurement output pin 1 0 0 p F C M O S o u t p u t

3850 Group (Spec. H) SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS Fig. 77 Timing diagram tC(CNTR) 0.2VCC tWL(INT) 0.8VCC tWH(INT) 0.2VCC 0.8VCC tW(RESET) RESET 0.2VCC tWL(CNTR) 0.8VCC tWH(CNTR) 0.2VCC 0.2VCC 0.8VCC 0.8VCC 0.2VCC tWL(X IN) 0.8VCC tWH(X IN) tC(XIN) XIN tf tr td(SCLK1 -TXD), td(SCLK2 -SOUT2 ) tv(SCLK1 -TXD), tv(SCLK2 -SOUT2 ) tC(SCLK1 ), tC(SCLK2 ) tWL(S CLK1 ), tWL(S CLK2 ) tWH(S CLK1 ), tWH(S CLK2 ) th(SCLK1 -R xD), th(SCLK2 -SIN2) tsu(RxD -SCLK1 ), tsu(SIN2-SCLK2 ) TXD SOUT2 R XD SIN2 SCLK1 SCLK2 INT0 to INT3 CNTR 0 CNTR 1

3850 Group (Spec. H) SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS PACKAGE OUTLINE SDIP42-P-600-1.78 Weight(g) JEDEC Code 4.1 Alloy 42/Cu Alloy 42P4B Plastic 42pin 600mil SDIP Symbol Min Nom Max A b c E D L Dimension in Millimeters A1 0.51 –– – 3.8 – 0.35 0.45 0.55 0.9 1.0 1.3 0.63 0.73 1.03 0.22 0.27 0.34 36.5 36.7 36.9 12.85 13.0 13.15 – 1.778 – – 15.24 – 3.0 –– 0° – 15° –– 5.5 e 42 22 211 E ce1 A2A1 bb1 b2e L A SEATING PLANE D SSOP42-P-450-0.80 Weight(g) JEDEC Code 0.63 Alloy 42 42P2R-A/E Plastic 42pin 450mil SSOP Symbol Min Nom Max A b c D E L y Dimension in Millimeters H E .250 .050 .130 .317 .28 .6311 .30 .271 .02 .30 .150 .517 .48 .80 .9311 .50 .7651 .4311 .42 .40 .20 .717 .68 .2312 .70 .150 b2 – .50 – 0° – 10° e 42 22 211 H E E D e y F A A2 A1 L c e b2 Recommended Mount Pad Detail F z Z1 Detail G –Z1 0.75 0.9 z b G

3850 Group (Spec. H) SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS WDIP42-C-600-1.78 Weight(g)JEDEC CodeEIAJ Package Code 42S1B-A Metal seal 42pin 600mil DIP 0.46 0.25 3.44 15.8 –– 3.05–– Symbol Min Nom Max A A b c D E L Z Dimension in Millimeters 3.05 15.24 1.778 41.1 0.33 0.17 0.9 0.8 0.7 0.540.38 1.0 5.0 e e E D 42 22 bZ SEATING PLANE AL A2A1 c

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Rev. Rev. No. date

1.0 First Edition 000309

1.1 Font errors are revised. 000322 2.0 Page 1; “G Interrupts” of “FEATURES ” is revised. 001222 Page 1; Figure 1 is partly revised. Page 6; Table 3 is partly revised. Page 17; Explanations of “INTERRUPTS ” are partly revised. Page 23; Figure 20 is partly revised. Page 27; Figure 24 is partly revised. Page 33; Explanations of “RESET CIRCUIT ” are partly revised. Page 36; Note 1 into Figure 42 is partly revised. Pages 38 to 71; Explanations of “FLASH MEMORY VERSION ” are added. Page 41; Figure 45 is partly revised. Page 72; “EPROM Version/One Time PROM Version/Flash Memory Version” of “NOTES ON USAGE ” is added. Page 73; “DATA REQUIRED FOR MASK ORDERS ” is added. Page 73; “DATA REQUIRED FOR One Time PROM PROGRAMMING ORDERS ” is added. Page 73; “ROM PROGRAMMING METHOD ” is added. Page 77; Table 32 is partly revised. Page 79; Limit of tw(RESET) into Table 34 is revised. Page 79; Limit of tw(RESET) into Table 35 is revised. REVISION DESCRIPTION LIST 3850 GROUP (SPEC. H) DATA SHEET (1/1) Revision Description

Product Information

M37516RSS specifications and overview.

Summary

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

Description

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

Source title M37516RSS Datasheet(PDF) - Mitsubishi Electric Semiconductor

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