M37516F8HP MITSUBISHI | Alldatasheet

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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS PRELIMINARY Notice: This is not a final specification. Some parametric limits are subject to change.

DESCRIPTION

The M37516F8HP is the 8-bit microcomputer based on the 740 family core technology. The M37516F8HP is designed for household products and office automation equipment and includes serial I/O functions, 8-bit timer, A-D converter, and I 2C-BUS interface.

FEATURES

(at 8 MHz oscillation frequency) l Memory size l Multi-master I PIN CONFIGURATION (TOP VIEW) Fig. 1 M37516F8HP pin configuration (connect to external ceramic resonator or quartz-crystal oscillator) l Power source voltage (at 8 MHz oscillation frequency) (at 4 MHz oscillation frequency) (at 8 MHz oscillation frequency) (at 32 kHz oscillation frequency) l Power dissipation (at 8 MHz oscillation frequency, at 5 V power source voltage) (at 32 kHz oscillation frequency, at 3 V power source voltage) APPLICATION Office automation equipment, FA equipment, Household products, Consumer electronics, etc. P a c k a g e t y p e P Q A P 17/ L E D 7) P 42/ I N P 41/ I N P 40/ C N T R 1 P 27/ C N T R 0/ SR D Y P 26/ SC L K P 25/ S C L2/ TXD P 23/ S C P 22/ S D C N VS S P 12/ L E D 2) P 13/ L E D 3) P 14/ L E D 4) P 15/ L E D 5) P 16/ L E D 6) VS S XO U T XI N P 36/ A N 6 P 37/ A N 7 P 00/ SI N P 01/ SO U T P 02/ SC L K P 03/ SR D Y P P P P 11/ L E D 1) P P 10/ L E D 0) R E S E T P 20/ XC O U T P 21/ XC I N P 44/ I N T3/ P W M P 24/ S D A2/ R XD P 35/ A N 5 P 34/ A N 4 P 31/ A N 1 P 30/ A N 0 VC C A VS S P P P 33/ A N 3 P 32/ A N 2 VR E F P P 43/ I N T2/ SC M P M F H P

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS PRELIMINARY Notice: This is not a final specification. Some parametric limits are subject to change.FUNCTIONAL BLOCK DIAGRAM Fig. 2 Functional block diagram FUNCTIONAL BLOCK XI N XO U T S I O R A M F l a s h m e m o r y C P U A X Y S P C H P C L P S VS S R E S E T VC C 3 1 C N VS S C N T R 0 P 7 2 8 2 9 3 0 3 1 3 2 3 3 3 P 9 2 1 2 3 2 0 2 2 2 4 2 P 6 8 1 0 1 37 9 1 1 1 9 4 0 4 P 6 4 8 44 7 1 3 54 4 4 I O p o r t P 3 I O p o r t P O p o r t P O p o r t P O p o r t P 6 1 5 3 6 3 A D c o n v e r t e r VR E F A VS S I2C C N T R 1 XC I N XC O U T I N T0–I N P W M ) S I O M a i n - cl o c k i n p u t S u b - cl o c k i n p u t S u b - cl o c k o u t p u t 3 1 M a i n - cl o c k o u t p u t R e s e t i n p u t P r e s c a l e r 1 2 ( 8 ) T i m e r 1 ( 8 ) T i m e r 2 ( 8 ) T i m e r X ( 8 ) T i m e r Y ( 8 ) P r e s c a l e r X P r e s c a l e r Y C l o c k g e n e r a t i n g c i r c u i t W a t c h d o g t i m e r R e s e t XC I N XC O U T

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS PRELIMINARY Notice: This is not a final specification. Some parametric limits are subject to change. VCC , VSS CNV SS RESET XIN XOUT P00/SIN2 P01/SOUT2 P02/SCLK2 P03/SRDY2 P04–P07 P10/–P17 P20/XCOUT P21/XCIN P22/SDA 1 P23/SCL1 P24/SDA 2/RxD P25/SCL2/TxD P26/SCLK P27/CNTR 0/ SRDY1 P30/AN0– P37/AN7 P40/CNTR 1 P41/INT0 P42/INT1 P43/INT2/SCMP2 P44/INT3/PWM P45–P47 PIN DESCRIPTION FunctionsNamePin

  • Apply voltage of 2.7 V – 5.5 V to Vcc, and 0 V to Vss.
  • This pin controls the operation mode of the chip.
  • Normally connected to V SS .
  • Reset input pin for active “L.”
  • Input and output pins for the clock generating circuit.
  • Connect a ceramic resonator or quartz-crystal oscillator between the X IN and XOUT pins to set the oscillation frequency.
  • When an external clock is used, connect the clock source to the XIN pin and leave the XOUT pin open.
  • 8-bit CMOS I/O port.
  • I/O direction register allows each pin to be individually programmed as either input or output.
  • CMOS compatible input level.
  • CMOS 3-state output structure.
  • P1 0 to P17 (8 bits) are enabled to output large current for LED drive. Power source Table 1 Pin description Function except a port function
  • Sub-clock generating circuit I/O pins (connect a resonator)
  • I2C-BUS interface function pins
  • I2C-BUS interface function pin/ Serial I/O1 function pins
  • Serial I/O1 function pin
  • Serial I/O1 function pin/ Timer X function pin Clock input Clock output I/O port P0 I/O port P1 I/O port P2 CNV SS input Reset input I/O port P3 I/O port P4
  • 8-bit CMOS I/O port.
  • I/O direction register allows each pin to be individually programmed as either input or output.
  • CMOS compatible input level.
  • P22 to P25 can be switched between CMOS compat- ible input level or SMBUS input level in the I2C-BUS interface function.
  • P20, P21, P24 to P27: CMOS3-state output structure.
  • P24, P25: N-channel open-drain structure in the I2C- BUS interface function.
  • P22, P23: N-channel open-drain structure.
  • 8-bit CMOS I/O port with the same function as port P0.
  • CMOS compatible input level.
  • CMOS 3-state output structure.
  • 8-bit CMOS I/O port with the same function as port P0.
  • CMOS compatible input level.
  • CMOS 3-state output structure.
  • Serial I/O2 function pin
  • A-D converter input pin
  • Timer Y function pin
  • Interrupt input pins
  • Interrupt input pin/SCMP2 output pin
  • Interrupt input pin/PWM output pin

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS PRELIMINARY Notice: This is not a final specification. Some parametric limits are subject to change. FUNCTIONAL DESCRIPTION CENTRAL PROCESSING UNIT (CPU) The M37516F8HP uses the standard 740 Family instruction set. Refer to the table of 740 Family addressing modes and machine instructions or the 740 Family Software Manual for details on the instruction set. Machine-resident 740 Family instructions are as follows: The FST and SLW instructions cannot be used. The STP, WIT, MUL, and DIV instructions can be used. Fig. 3 Structure of CPU mode register [CPU Mode Register (CPUM)] 003B16 The CPU mode register contains the stack page selection bit, etc. The CPU mode register is allocated at address 003B 16. C P U m o d e r e g i s t e r P U M a d d r e s s 0 0 3 B1 b 7 b 0 F i x t h i s b i t t o S t a c k p a g e s e l e c t i o n b i t p a g e p a g e P r o c e s s o r m o d e b i t s b b S i n g l e c h i p m o d e N o t a v a i l a b l e P o r t XC s w i t c h b i t I O p o r t f u n c t i o n s t o p o s c i l l a t i n g XC I N – XC O U T o s c i l l a t i n g f u n c t i o n M a i n c l o c k XI N – XO U s t o p b i t O s c i l l a t i n g S t o p p e d M a i n c l o c k d i v i s i o n r a t i o s e l e c t i o n b i t s b b f f XI N ) h i g h s p e e d m o d e f f XI N ) m i d d l e s p e e d m o d e f f XC I N ) l o w s p e e d m o d e N o t a v a i l a b l e

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS PRELIMINARY Notice: This is not a final specification. Some parametric limits are subject to change. MEMORY Special Function Register (SFR) Area The Special Function Register area in the zero page contains con- trol registers such as I/O ports and timers. RAM RAM is used for data storage and for stack area of subroutine calls and interrupts. Flash Memory The first 128 bytes and the last 2 bytes of flash memory are re- served for device testing and the rest is user area for storing programs. Interrupt Vector Area The interrupt vector area contains reset and interrupt vectors. Zero Page Access to this area with only 2 bytes is possible in the zero page addressing mode. Special Page Access to this area with only 2 bytes is possible in the special page addressing mode. Fig. 4 Memory map diagram F F F F D C 1 F F F F F F R A M b y t e s F l a s h m e m o r y K b y t e s F F D 1 F F F F D S F R a r e a N o t u s e d I n t e r r u p t v e c t o r a r e a R e s e r v e d m e m o r y a r e a b y t e Z e r o p a g e S p e c i a l p a g e R e s e r v e d m e m o r y a r e a S F R a r e a F l a s h m e m o r y I D c o d e N o t u s e d

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS PRELIMINARY Notice: This is not a final specification. Some parametric limits are subject to change. Fig. 5 Memory map of special function register (SFR) 0 0 2 01 0 0 2 11 0 0 2 21 0 0 2 31 0 0 2 41 0 0 2 51 0 0 2 61 0 0 2 71 0 0 2 81 0 0 2 91 0 0 2 A1 0 0 2 B1 0 0 2 C 1 0 0 2 D 1 0 0 2 E1 0 0 2 F1 0 0 3 01 0 0 3 11 0 0 3 21 0 0 3 31 0 0 3 41 0 0 3 51 0 0 3 61 0 0 3 71 0 0 3 81 0 0 3 91 0 0 3 A1 0 0 3 B1 0 0 3 C 1 0 0 3 D 1 0 0 3 E1 0 0 3 F1 0 0 0 01 0 0 0 11 0 0 0 21 0 0 0 31 0 0 0 41 0 0 0 51 0 0 0 61 0 0 0 71 0 0 0 81 0 0 0 91 0 0 0 A1 0 0 0 B1 0 0 0 C 1 0 0 0 D 1 0 0 0 E1 0 0 0 F1 0 0 1 01 0 0 1 11 0 0 1 21 0 0 1 31 0 0 1 41 0 0 1 51 0 0 1 61 0 0 1 71 0 0 1 81 0 0 1 91 0 0 1 A1 0 0 1 B1 0 0 1 C 1 0 0 1 D 1 0 0 1 E1 0 0 1 F1 P o r t P 0 ( P 0 ) P o r t P 0 d i r e c t i o n r e g i s t e r ( P 0 D ) P o r t P 1 ( P 1 ) P o r t P 1 d i r e c t i o n r e g i s t e r ( P 1 D ) P o r t P 2 ( P 2 ) P o r t P 2 d i r e c t i o n r e g i s t e r ( P 2 D ) P o r t P 3 ( P 3 ) P o r t P 3 d i r e c t i o n r e g i s t e r ( P 3 D ) P o r t P 4 ( P 4 ) P o r t P 4 d i r e c t i o n r e g i s t e r ( P 4 D ) T r a n s m i t / R e c e i v e b u f f e r r e g i s t e r ( T B / R B ) S e r i a l I / O 1 s t a t u s r e g i s t e r ( S I O S T S ) S e r i a l I / O 1 c o n t r o l r e g i s t e r ( S I O C O N ) U A R T c o n t r o l r e g i s t e r ( U A R T C O N ) B a u d r a t e g e n e r a t o r ( B R G ) I n t e r r u p t c o n t r o l r e g i s t e r 2 ( I C O N 2 ) A - D c o n v e r s i o n l o w - o r d e r r e g i s t e r ( A D L ) P r e s c a l e r Y ( P R E Y ) T i m e r Y ( T Y ) A - D c o n t r o l r e g i s t e r ( A D C O N ) A - D c o n v e r s i o n h i g h - o r d e r r e g i s t e r ( A D H ) I n t e r r u p t e d g e s e l e c t i o n r e g i s t e r ( I N T E D G E ) C P U m o d e r e g i s t e r ( C P U M ) I n t e r r u p t r e q u e s t r e g i s t e r 1 ( I R E Q 1 ) I n t e r r u p t r e q u e s t r e g i s t e r 2 ( I R E Q 2 ) I n t e r r u p t c o n t r o l r e g i s t e r 1 ( I C O N 1 ) P r e s c a l e r 1 2 ( P R E 1 2 ) T i m e r 2 ( T 2 ) P r e s c a l e r X ( P R E X ) T i m e r X ( T X ) T i m e r 1 ( T 1 ) T i m e r X Y m o d e r e g i s t e r ( T M ) I2C d a t a s h i f t r e g i s t e r S I2C a d d r e s s r e g i s t e r S D I2C s t a t u s r e g i s t e r S I2C c o n t r o l r e g i s t e r S D I2C c l o c k c o n t r o l r e g i s t e r S I2C s t a r t s t o p c o n d i t i o n c o n t r o l r e g i s t e r S D M I S R G W a t c h d o g t i m e r c o n t r o l r e g i s t e r ( W D T C O N ) P W M c o n t r o l r e g i s t e r ( P W M C O N ) P W M p r e s c a l e r ( P R E P W M ) P W M r e g i s t e r ( P W M ) T i m e r c o u n t s o u r c e s e l e c t i o n r e g i s t e r ( T C S S ) R e s e r v e d R e s e r v e d R e s e r v e d R e s e r v e d D o n o t w r i t e a n y d a t a t o t h e r e s e r v e d a r e a S e r i a l I / O 2 c o n t r o l r e g i s t e r 1 ( S I O 2 C O N 1 ) S e r i a l I / O 2 c o n t r o l r e g i s t e r 2 ( S I O 2 C O N 2 ) S e r i a l I / O 2 r e g i s t e r ( S I O 2 ) R e s e r v e d R e s e r v e d

0 F F D 1

0 F F E1

0 F F F1

F l a s h m e m o r y c o n t r o l r e g i s t e r ( F C O N ) R e s e r v e d R e s e r v e d

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS PRELIMINARY Notice: This is not a final specification. Some parametric limits are subject to change. Pin Name Input/Output I/O Structure Non-Port Function Ref.No. Table 2 I/O port function Related SFRs I/O PORTS The I/O ports have direction registers which determine the input/ output direction of each individual pin. Each bit in a direction reg- ister corresponds to one pin, and each pin can be set to be input port or output port. When “0” is written to the bit corresponding to a pin, that pin be- comes an input pin. When “1” is written to that bit, that pin becomes an output pin. If data is read from a pin which is set to output, the value of the port output latch is read, not the value of the pin itself. Pins set to input are floating. If a pin set to input is written to, only the port output latch is written to and the pin remains floating. Port P0 Port P1 Port P3 Input/output, individual bits CMOS compatible input level CMOS 3-state output Sub-clock generating circuit CPU mode register (1) (2) (3) (4) (5) (6) (7) (8) (9) (10) (11) (12) Port P2 Port P4 CMOS compatible input level CMOS/SMBUS input level (when selecting I 2C-BUS interface function) N-channel open-drain output CMOS compatible input level CMOS/SMBUS input level (when selecting I 2C-BUS interface function) CMOS 3-state output N-channel open-drain output (when selecting I 2C-BUS interface function) CMOS compatible input level CMOS 3-state output I2C-BUS interface func- tion I/O I2C-BUS interface func- tion I/O Serial I/O1 function I/O Serial I/O1 function I/O I2C control register I2C control register Serial I/O1 control register Serial I/O1 control register Serial I/O1 control register Timer XY mode register A-D control register Timer XY mode register Interrupt edge selection register Interrupt edge selection register Serial I/O2 control register Interrupt edge selection register PWM control register External interrupt input PWM output P00/SIN2 P01/SOUT2 P02/SCLK2 P03/SRDY2 P04–P07 P10/–P17 P20/XCOUT P21/XCIN P22/SDA 1 P23/SCL1 Serial I/O2 control register Serial I/O2 function I/O P24/SDA 2/RxD P25/SCL2/TxD P26/SCLK (13)P27/CNTR 0/ SRDY1 Serial I/O1 function I/O Timer X function I/O A-D conversion input Timer Y function I/O External interrupt input P30/AN0– P37/AN7 P40/CNTR 1 P41/INT0 P42/INT1 P43/INT2/SCMP2 External interrupt input SCMP2 output P44/INT3/PWM P45–P47 (14) (15) (16) (17) (18) (5)

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS PRELIMINARY Notice: This is not a final specification. Some parametric limits are subject to change. Fig. 6 Port block diagram (1) P o r t s P 04– P 07, P P 45–P P o r t P S D A S C L p i n s e l e c t i o n b i t P o r t P P o r t P P o r t P P o r t P P o r t P P o r t P P 01/ SO U T P c h a n n e l o u t p u t d i s a b l e b i t P o r t P P 02/ SC L K P c h a n n e l o u t p u t d i s a b l e b i t D i r e c t i o n r e g i s t e r D a t a b u s P o r t l a t c h D i r e c t i o n r e g i s t e r D a t a b u s P o r t l a t c h D a t a b u s P o r t l a t c h D i r e c t i o n r e g i s t e r D a t a b u s P o r t l a t c h D i r e c t i o n r e g i s t e r D a t a b u s P o r t l a t c h D i r e c t i o n r e g i s t e r D a t a b u s P o r t l a t c h D i r e c t i o n r e g i s t e r D a t a b u s P o r t l a t c h D i r e c t i o n r e g i s t e r D a t a b u s P o r t l a t c h D i r e c t i o n r e g i s t e r S e r i a l I / O 2 i n p u t S e r i a l I / O 2 t r a n s m i t c o m p l e t i o n s i g n a l S e r i a l I / O 2 p o r t s e l e c t i o n b i t S e r i a l I / O 2 o u t p u t SR D Y 2 o u t p u t e n a b l e b i t S e r i a l I / O 2 r e a d y o u t p u t S e r i a l I / O 2 s y n c h r o n o u s c l o c k s e l e c t i o n b i t S e r i a l I / O 2 p o r t s e l e c t i o n b i t S e r i a l I / O 2 e x t e r n a l c l o c k i n p u t S e r i a l I / O 2 c l o c k o u t p u t P o r t XC s w i t c h b i t P o r t XC s w i t c h b i t O s c i l l a t o r S D A o u t p u t S D A i n p u t I2C B U S i n t e r f a c e e n a b l e b i tP o r t XC s w i t c h b i t S u b - c l o c k g e n e r a t i n g c i r c u i t i n p u t

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS PRELIMINARY Notice: This is not a final specification. Some parametric limits are subject to change. Fig. 7 Port block diagram (2) P o r t P 23 ( P o r t P P o r t P 26( P o r t P P o r t s P 30– P 37( P o r t P P o r t P P o r t s P 41, P D a t a b u s P o r t l a t c h D i r e c t i o n r e g i s t e r S D A S C L p i n s e l e c t i o n b i t I2C B U S i n t e r f a c e e n a b l e b i t S C L o u t p u t S C L i n p u t S D A o u t p u t S D A i n p u t S D A S C L p i n s e l e c t i o n b i t I2C B U S i n t e r f a c e e n a b l e b i t D a t a b u s P o r t l a t c h D i r e c t i o n r e g i s t e r D a t a b u s P o r t l a t c h D i r e c t i o n r e g i s t e r D a t a b u s P o r t l a t c h D i r e c t i o n r e g i s t e r D a t a b u s P o r t l a t c h D i r e c t i o n r e g i s t e r D a t a b u s P o r t l a t c h D i r e c t i o n r e g i s t e r D a t a b u s P o r t l a t c h D i r e c t i o n r e g i s t e r D a t a b u s P o r t l a t c h D i r e c t i o n r e g i s t e r S e r i a l I / O 1 i n p u t S e r i a l I / O 1 e n a b l e b i t R e c e i v e e n a b l e b i t S e r i a l I / O 1 e n a b l e b i t S e r i a l I / O 1 m o d e s e l e c t i o n b i t S e r i a l I / O 1 e n a b l e b i t S e r i a l I / O 1 s y n c h r o n o u s c l o c k s e l e c t i o n b i t Ex t e r n a l c l o c k i n p u t S e r i a l I / O 1 c l o c k o u t p u t P c h a n n e l o u t p u t d i s a b l e b i t S e r i a l I / O 1 e n a b l e b i t T r a n s m i t e n a b l e b i t S D A S C L p i n s e l e c t i o n b i t I2C-BUS interface enable bit S C L i n p u tS e r i a l I / O 1 o u t p u t S C L o u t p u t C N T R 0 i n t e r r u p t i n p u t P u l s e o u t p u t m o d e T i m e r o u t p u t S e r i a l r e a d y o u t p u t A - D c o n v e r t e r i n p u t A n a l o g i n p u t p i n s e l e c t i o n b i t I n t e r r u p t i n p u t C N T R 1 i n t e r r u p t i n p u t P u l s e o u t p u t m o d e T i m e r o u t p u t P u l s e o u t p u t m o d e S e r i a l I / O 1 e n a b l e b i t S e r i a l I / O 1 m o d e s e l e c t i o n b i t SR D Y 1 o u t p u t e n a b l e b i t

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS PRELIMINARY Notice: This is not a final specification. Some parametric limits are subject to change. Fig. 8 Port block diagram (3) P o r t P P W M o u t p u t e n a b l e b i t P W M o u t p u t P o r t P D a t a b u s P o r t l a t c h D i r e c t i o n r e g i s t e r D a t a b u s P o r t l a t c h D i r e c t i o n r e g i s t e r S e r i a l I O i n p u t o u t p u t c o m p a r i s o n s i g n a l c o n t r o l b i t S e r i a l I O i n p u t o u t p u t c o m p a r i s o n s i g n a l o u t p u t I n t e r r u p t i n p u t I n t e r r u p t i n p u t

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS PRELIMINARY Notice: This is not a final specification. Some parametric limits are subject to change. © 2000 MITSUBISHI ELECTRIC CORP. New publication, effective Feb. 2000. Specifications subject to change without notice. Notes regarding these materials

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  • Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non-flammable material or (iii) prevention against any malfunction or mishap. HEAD OFFICE: 2-2-3, MARUNOUCHI, CHIYODA-KU, TOKYO 100-8310, JAPAN LQFP48-P-77-0.50 – Weight(g) JEDEC CodeEIAJ Package Code Lead Material Cu Alloy 48P6Q-A Plastic 48pin 75 7mm body LQFP 0.1 0.2 Symbol Min Nom Max A b c D E H E L y Dimension in Millimeters H D 0.225 ––I2 1.0 ––M D 7.4 ––M E 7.4 8°0° 0.1 1.0 0.650.50.35 9.29.08.8 9.29.08.8 0.5 7.17.06.9 7.17.06.9 0.1750.1250.105 0.270.220.17 1.4 1.7 e e E H E 48 37 H D D M D M E A F y Recommended Mount Pad A1 A2 L Detail F Lp c Lp 0.45 0.6 0.25 0.75 0.08 x A3 e b x M PACKAGE OUTLINE

Rev. Rev. No. date

0.1 First Edition 2/3/00

REVISION HISTORY M37516F8HP DATA SHEET (1/1) Revision Description