M37510E1156FP

M37510M6 MITSUBISHI | Alldatasheet

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Technical content

DESCRIPTION

The 7510 group is the 8-bit microcomputer based on the 740 fam- ily core technology. This microcomputer is equipped with added functions such as a dot matrix type LCD controller/driver built in a contrast controller and UART.

FEATURES

(at 8.0 MHz oscillation frequency) (includes key-on wake up) Built-in an LCD contrast controller (capable of 32-step contrast adjustment) l 2 Clock generating circuit (Connect to external ceramic resonator or quartz-crystal.) l Power source voltage l Power dissipation (at 8.0 MHz oscillation frequency) (at 32 kHz oscillation frequency and 3.0 V power source voltage) (at 32 kHz oscillation frequency and 3.0 V power source voltage) APPLICATION Cellular radio telephones, business telephones, facsimiles, and other portable equipment that need a large capacity of LCD dis- play.

7510 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS PIN CONFIGURATION (TOP VIEW) Package type : 176P6D-A 176-pin plastic-molded QFP NC : No connect 133NC 134NC M37510M6-XXXFP SEG 65 SEG 64 135 136 SEG 63 SEG 62 137 138 SEG 61 SEG 60 139 140 SEG 59 SEG 58 141 142 SEG 57 SEG 56 143 144 SEG 55 SEG 54 145 146 SEG 53 SEG 52 147 148 SEG 51 SEG 50 149 150 SEG 49 SEG 48 151 152 SEG 47 SEG 46 153 154 SEG 45 SEG 44 155 156 SEG 43 SEG 42 157 158 SEG 41 SEG 40 159 160 SEG 39 SEG 38 161 162 SEG 37 SEG 36 163 164 SEG 35 SEG 34 165 166 SEG 33 SEG 32 167 168 SEG 31 SEG 30 169 170 SEG 29 SEG 28 171 172 SEG 27 SEG 26 173 174 NC NC 175 176 NC NC NC NC NC NC P12 P13 P14 P15 P16 P17 P20 P21 P22 P23 P24 P25 P26 P27 VSS XOUT XIN P50/XCOUT P51/XCIN RESET P40/INT0 P41/INT1 P42/CNTR 0 P43/CNTR 1 P44/RX D 1 P45/TX D 1 P46/SCLK1 P47/SRDY1 NC NC NC NC NC NC V SS NC NC 1NC 2NC SEG 25 SEG 24 SEG 23 SEG 22 SEG 21 SEG 20 SEG 19 SEG 18 SEG 17 SEG 16 SEG 15 SEG 14 SEG 13 SEG 12 SEG 11 SEG 10 SEG 9 SEG 8 SEG 7 SEG 6 SEG 5 SEG 4 SEG 3 SEG 2 SEG 1 SEG 0 NC NC NC COM 7 COM 6 COM 5 COM 4 COM 3 COM 2 COM 1 COM 0 VLCD VL3 VL2 NC NC 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 NC NC SEG 66 SEG 67 SEG 68 SEG 69 SEG 70 SEG 71 SEG 72 SEG 73 SEG 74 SEG 75 SEG 76 SEG 77 SEG 78 SEG 79 COM 15 COM 14 COM 13 COM 12 COM 11 COM 10 COM 9 COM 8 VCC P30/RXD 2 P31/TX D 2 P32/SCLK2 P33/SRDY2 P34 P35 P36 P37 P00 P01 P02 P03 P04 P05 P06 P07 P10 NC NC

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS M37510M6-XXXFP BLOCK DIAGRAM SEG 5 Key-on wake up CNTR 0 CNTR 1 RAMROMCPU A X Y S PS RESET 108 PC LPC H P2(8) XIN S I/O2(8) Reset input Clock generating circuit Clock input Timer 2 (8) Data bus Timer X (16) INT0, INT1 CLK I/O port P0 S I/O1(8) VSS 67 476265 I/O port P1I/O port P2I/O port P3I/O port P4 P5(2) ff 66 63 64 XOUT Clock output XCIN/P51 Sub- clock input XCOUT /P50 Sub- clock output VSSVCC (5V) (0V) (0V)

24 K bytes

(160 bytes) LCD RAM controller LCD resistor Bias controller Contrast VLCD VL3 VL2 COM 0 COM 7 COM 8 COM 14 COM 15 SEG 0 SEG 1 SEG 2 SEG 3 SEG 4 SEG 6 SEG 7 SEG 8 SEG 9 SEG 10 SEG 73 SEG 74 SEG 75 SEG 76 SEG 77 SEG 78 SEG 79 109 115 116 123 122 121 120 119 118 117 918281807978777675747372717069681006160595857565554 101 102 103 104 105 106 107 92 93 94 95 96 97 98 99 ... ... ... Timer Y (16) Timer 3 (8) Timer 1 (8) Timer

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS P44/RX D1, P45/TX D 1, P46/ SCLK1 , P47/SRDY1 Pin PIN DESCRIPTION Name Function Function except a port function VCC , VSS RESET XIN XOUT VLCD Power source Reset input Clock input Clock output LCD voltage source Apply voltage of 4.0 to 5.5 V to V CC , and 0 V to VSS (in high-speed mode). Reset input pin for active “L”. Input and output pins for the main clock generating circuit. Connect a ceramic resonator or quartz-crystal oscillator between the XIN and XOUT pins to set the oscillating frequency. If an ex- ternal clock is used, connect the clock source to the XIN pin and leave the XOUT pin open. VL2, VL3 COM 0– COM 15 SEG 0– SEG 79 LCD bias control pin Common output Segment output P00–P0 7 P10–P1 7 P20–P2 7 I/O port P0 I/O port P1 I/O port P2 P30/RX D2, P31/TX D 2, P32/ SCLK2 , P33/SRDY2 P34–P3 7 P40/INT0 P41/INT1 P42/CNTR0, P43/CNTR 1 P50/XCOUT , P51/XCIN I/O port P3 Input port P4 I/O port P4 I/O port P5 This pin is used as voltage supply input for LCD driver. Input VLCD ≤ VCC voltage. When the LCD is operated at 1/5 bias, leave these pins open. When the LCD is operated at 1/4 bias, connect these pins externally. LCD common output pins. LCD segment output pins. An 8-bit I/O port. The output structure of this port is CMOS 3-state, and the input levels are CMOS compatible. The port direction register allows each pin to be individually programmed as either input or output. A 1-bit CMOS level input port. A 7-bit I/O port with the same function as port P0. The port direction register allows each pin to be individually programmed as either input or output. A 2-bit I/O port with the same function as port P0. The port direction register allows each pin to be individually programmed as either input or output. Key input (Key-on wake-up) interrupt input pins. External interrupt input pins Timer X, Timer Y function pins External interrupt input pins Serial I/O1 function pins Serial I/O2 function pins I/O pins for the internal sub clock generating circuit. Connect an oscillator.

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS PART NUMBERING Product name M37510M6-XXXFP M37510E6-XXXFP M37510E6FP M37510E6FS Currently supported products are listed below. (P) ROM size (bytes) RAM size (bytes) Package Remarks Mask ROM version One Time PROM version One Time PROM version (blank) EPROM version 176P6D-A 160D0 24K 512 As of May 1996 Product M37510 M 6 XXX FP Package type FP: 176P6D-A package FS: 160D0 package ROM number Omitted in some types. ROM/PROM size 1 : 4096 bytes 2 : 8192 bytes 3 : 12288 bytes 4 : 16384 bytes 5 : 20480 bytes 6 : 24576 bytes 7 : 28672 bytes 8 : 32768 bytes RAM size 512 bytes The first 128 bytes and the last 2 bytes of ROM are reserved areas; they cannot be used. Memory type M : Mask ROM version E : EPROM or One Time PROM version

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS FUNCTIONAL DESCRIPTION CENTRAL PROCESSING UNIT (CPU) The 7510 group uses the standard 740 family instruction set. Re- fer to the table of 740 family addressing modes and machine instructions or the SERIES 740 <Software> User’s Manual for de- tails on the instruction set. Machine-resident 740 family instructions are as follows: The FST and SLW instruction are not available for use. The STP, WIT, MUL, and DIV instruction can be used. Fig. 1 Structure of CPU mode register CPU MODE REGISTER The CPU mode register is allocated at address 003B16. The CPU mode register contains the stack page selection bit and the internal system clock selection bit. (CPUM : address 003B16) CPU mode register Processor mode bits b1 b0 0 0 : Single-chip mode 0 1 : Do not use 1 0 : Do not use 1 1 : Do not use Stack page selection bit 0 : RAM in the zero page is used as stack area 1 : RAM in page 1 is used as stack area X COUT drivability selection bit 0 : Low drive 1 : High drive Port XC selection bit 0 : I/O port 1 : X CIN, XCOUT Main clock (XIN-XOUT ) stop bit 0 : Operating 1 : Stopped Main clock division ratio selection bit 0 : XIN/2 (high-speed mode) 1 : XIN/8 (middle-speed mode) Internal system clock selection bit 0 : XIN-XOUT selected (middle/high-speed mode) 1 : XCIN-XCOUT selected (low-speed mode)

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS MEMORY Special Function Register (SFR) Area The Special Function Register area contains registers which con- trol functions such as I/O ports and timers, and is located in the zero page area. RAM RAM is used for data storage as well for stack area. ROM The first 128 bytes and the last two bytes of ROM are reserved for device testing and the rest is user area for storing programs. Interrupt Vector Area The interrupt vector area contains reset and interrupt vectors. Zero Page This dedicated zero page addressing mode enables access to this area with only 2 bytes. Special Page This dedicated special page addressing mode enables access to this area with only 2 bytes. Fig. 2 Memory map diagram 000016 004016 00DF 16 SFR area LCD display RAM area 010016 034016 03DF 16 XXXX 16 Not used YYYY 16 ZZZZ 16 Reserved ROM area (common ROM area, 128 bytes) FF0016 FFDC 16 Interrupt vector area FFFE 16 FFFF 16 Reserved ROM area RAM ROM Special page Zero page RAM area Type name Address XXXX 16 M37510M6-XXXFP 023F 16 ROM area Type name Address YYYY 16 M37510M6-XXXFP A000 16 Address ZZZZ16 A08016 LCD display RAM area ] LCD display RAM area can reside at either zero page (addresses 004016 to 00DF16) or third page (addresses 034016 to 03DF16) by software. The third page is selected after reset.

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS Fig. 3 Memory map of special function register (SFR) 000016 000116 000216 000316 000416 000516 000616 000716 000816 000916 000A16 000B16 000C 16 000D 16 000E16 000F16 001016 001116 001216 001316 001416 001516 001616 001716 001816 001916 001A16 001B16 001C 16 001D 16 001E16 Port P0 (P0) Port P0 direction register (P0D) Port P1 (P1) Port P1 direction register (P1D) Port P2 (P2) Port P2 direction register (P2D) Port P3 (P3) Port P3 direction register (P3D) Port P4 (P4) Port P4 direction register (P4D) Port P5 (P5) Port P5 direction register (P5D) Port P0 pull-up control register (PULLP0) Port P1 pull-up control register (PULLP1) Port P2 pull-up control register (PULLP2) Port P3 pull-up control register (PULLP3) Port P4 pull-up control register (PULLP4) Port P5 pull-up control register (PULLP5) Transmit/receive buffer register 1 (TB1/RB1) Serial I/O1 status register (SIO1STS) Serial I/O1 control register (SIO1CON) UART1 control register (UART1CON) Baud rate generator 1 (BRG1) 001F 002016 002116 002216 002316 002416 002516 002616 002716 002816 002916 002A16 002B16 002C 16 002D 16 002E16 002F16 003016 003116 003216 003316 003416 003516 003616 003716 003816 003916 003A16 003B16 003C 16 003D 16 003E16 Timer X (low) (TXL) Timer X (high) (TXH) Timer Y (low) (TYL) Timer Y (high) (TYH) Timer 1 (T1) Timer 2 (T2) Timer 3 (T3) Timer X mode register (TXM) Timer Y mode register (TYM) Timer 123 mode register (T123M) Transmit/receive buffer register 2 (TB2/RB2) Serial I/O2 status register (SIO2STS) Serial I/O2 control register (SIO2CON) UART2 control register (UART2CON) Baud rate generator 2 (BRG2) LCD contrast control register (LC) LCD mode register (LM) Interrupt edge selection register (INTEDGE) CPU mode register (CPUM) Interrupt request register 1 (IREQ1) Interrupt request register 2 (IREQ2) Interrupt control register 1 (ICON1) 003F

16 Interrupt control register 2 (ICON2)

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS Timer X function I/O Timer Y function I/O Port P5 Common Segment P00–P0 7 P10–P1 7 P20–P2 7 I/O PORTS Direction Registers The 7510 group has 41 programmable I/O pins arranged in six I/O ports (ports P0 to P5). The I/O ports have direction registers which determine the input/output direction of each individual pin. Each bit in a direction register corresponds to one pin, each pin can be set to be input or output. When “0” is written to the bit corresponding to a pin, that pin be- comes an input pin. When “1” is written to that bit, that pin becomes an output pin. If data is read from a pin which is set for output, the value of the port output latch is read, not the value of the pin itself. Pins set to input are floating and can read the value of the pin itself. If a pin set to input is written to, only the port output latch is written to and the pin remains floating. Port Pull-up Control Registers The 7510 group is equipped with internal pull-ups that can be en- abled by software. Each I/O port of ports P0–P5 has an port Pi (i= 0 to 5) pull-up control register (addresses 000C 16 to 001116). Each bit of the pull-up control register controls a corresponding bit of the port. The value written to each individual bit determines whether the pull-up of the corresponding pin is either enabled or disabled. When “0” is written to the pull-up control register, the pull up on the pin is disabled. When “1” is written to the pull-up control register, the pull-up on the pin is enabled. After reset, all the pull-up control registers are initialized to “00 16”, disabling all the internal pull-ups. Fig. 4 Structure of port Pi pull-up control register Pin Name Input/Output I/O Format Port P0 Port P1 Port P2 Non-Port Function Related SFRs Port P3 Port P4 Input/output, individual bits Input Input/output, individual bits Input/output, individual bits Output Output CMOS compatible input level CMOS 3-state output CMOS compatible input level CMOS compatible input level CMOS 3-state output CMOS compatible input level CMOS 3-state output LCD common output LCD segment output Key-on wake up interrupt input Serial I/O2 function I/O External interrupt input Serial I/O1 function I/O Sub-clock generat- ing circuit I/O P30/RX D2, P31/TX D 2, P32/ SCLK2 , P33/SRDY2 P34–P3 7 P40/INT0 P41/INT1 P42/CNTR 0, P43/CNTR 1 P44/RX D1, P45/TX D 1, P46/ SCLK1 , P47/SRDY1 P50/XCOUT , P51/XCIN COM 0– COM 15 SEG 0– SEG 79 CPU mode register LCD mode register Interrupt control register 2 Serial I/O2 control register Serial I/O2 status register UART control register 2 Timer X mode register Timer Y mode register Serial I/O1 control register Serial I/O1 status register UART1 control register Ref. No. (1) (1) (2) (3) (4) (5) (6) (1) (7) (8) (9) (8) (3) (4) (5) (6) (1) Notes 1:For details of how to use double-function ports as function I/O ports, refer to the applicable sections. 2:Make sure that the input level at each pin is either 0 V or VCC during execution of the STP instruction. When an input level is at an intermediate potential, a current will flow from VCC to VSS through the input-stage gate. Input/output, individual bits Input/output, individual bits Input/output, individual bits CMOS compatible input level CMOS 3-state output CMOS compatible input level CMOS 3-state output CMOS compatible input level CMOS 3-state output Port Pi pull-up control register (PULLPi : addresses 000C16 to 001116) Pi0 pull-up Pi1 pull-up Pi2 pull-up Pi3 pull-up Pi4 pull-up Pi5 pull-up Pi6 pull-up Pi7 pull-up 0 : Disabled 1 : Enabled i = 0 to 5

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS Fig. 5 Port block diagram (1) (1) Port P0, P1, P34 to P37, P5 Direction register Port latchData bus Pull-up control (2) Port P2 Direction register Port latchData bus Pull-up control Key-on wake up input (3) Port P30, P44 Direction register Port latchData bus Pull-up control Direction register Port latchData bus Pull-up control Serial I/O input Serial I/O enable bit (4) Port P31, P45 P-channel output disable bit Serial I/O output Serial I/O enable bit (5) Port P32, P46 Direction register Port latchData bus Pull-up control Direction register Port latchData bus Pull-up control Serial clock output clock selection bit (6) Port P33, P47 Serial ready output Serial I/O mode selection bit Serial I/O enable bit SRDY output enable bit External clock input Serial I/O mode selection bit Transmit enable bit Receive enable bit Serial I/O enable bit Serial I/O synchronous Serial I/O enable bit

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS Fig. 6 Port block diagram (2) (7) Port P40 Data bus (8) Port P41, P43 Direction register Port latchData bus Pull-up control Direction register Port latchData bus Pull-up control (9) Port P42 Pulse output mode INT1 interrupt input CNTR 1 interrupt input INT0 interrupt input Timer output CNTR 0 interrupt input

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS Interrupt request generating conditionsHigh FFFD 16 INTERRUPTS A total of 15 sources can generate interrupts: 5 external, 9 inter- nal, and 1 software. Interrupt Control Each interrupt is controlled by an interrupt request bit, an interrupt enable bit, and the interrupt disable flag except for the software in- terrupt set by the BRK instruction. An interrupt is generated if the corresponding interrupt request and enable bits are “1” and the in- terrupt disable flag is “0”. Interrupt enable bits can be set or cleared by software. Interrupt request bits can be cleared by software, but cannot be set by software. The reset and BRK instruction can not be disabled with any flag or bit. The I flag disables all interrupts except for the BRK instruction in- terrupt and the reset. When several interrupts occur at the same time, the interrupts are received according to priority. Interrupt Operation When an interrupt is received, the program counter and processor status register are automatically pushed onto the stack. The inter- rupt disable flag is set to inhibit other interrupts from interfering. The corresponding interrupt request bit is cleared and the interrupt jump destination address is read from the vector table into the pro- gram counter. Notes on Use When the active edge of an external interrupt (INT0, INT1, CNTR0, or CNTR 1) is changed, the corresponding interrupt request bit may also be set. Therefore, please take following sequence; (1) Disable the external interrupt which is selected. (2) Change the active edge selection. (3) Clear interrupt request which is selected to “0”. (4) Enable the external interrupt which is selected. Table 1 Interrupt vector addresses and priority Interrupt source Priority Low FFFC 16 Remarks Reset (Note 2) INT0 INT1 Non-maskable External interrupt (active edge selectable) External interrupt (active edge selectable) Valid when serial I/O1 is se- lected Valid when serial I/O1 is se- lected Valid when serial I/O2 is se- lected Valid when serial I/O2 is se- lected External interrupt (active edge selectable) External interrupt (active edge selectable) External interrupt (valid when an “L” level is applied) Non-maskable software inter- ruptAt BRK instruction execution FFFA 16 FFF8 16 FFF6 16 FFF4 16 FFF2 16 FFF0 16 FFEE 16 FFEC 16 FFEA 16 FFE8 16 FFE6 16 FFE4 16 FFE2 16 FFE0 16 FFDC 16 FFFB 16 FFF9 16 FFF7 16 FFF5 16 FFF3 16 FFF1 16 FFEF 16 FFED 16 FFEB 16 FFE9 16 FFE7 16 FFE5 16 FFE3 16 FFE1 16 FFDD 16 Serial I/O1 reception Serial I/O1 transmission Timer X Timer Y Timer 2 Timer 3 Serial I/O2 reception Serial I/O2 transmission CNTR CNTR 1 Timer 1 Key-on wake up BRK instruction Notes 1:Vector addresses contain interrupt jump destination addresses. 2:Reset function in the same way as an interrupt with the highest priority. Vector addresses (Note 1) At reset At detection of either rising or falling edge of INT0 input At detection of either rising or falling edge of INT1 input At end of serial I/O1 data re- ception At end of serial I/O1 transfer shift or when transmission buffer is empty At timer X underflow At timer Y underflow At timer 2 underflow At timer 3 underflow At end of serial I/O2 data re- ception At end of serial I/O2 transfer shift or when transmission buffer is empty At detection of either rising or falling edge of CNTR 0 input At detection of either rising or falling edge of CNTR1 input At timer 1 underflow At falling of conjunction of in- put logic level for port P2 (at input)

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS Fig. 7 Interrupt control Fig. 8 Structure of interrupt-related registers Interrupt disable flag (I) Interrupt request Interrupt request bit Interrupt enable bit BRK instruction Reset Interrupt edge selection register (INTEDGE : address 003A16) INT0 active edge selection bit INT1 active edge selection bit Not used (return “0” when read) 0 : Falling edge active 1 : Rising edge active Interrupt request register 1 (IREQ1 : address 003C16) INT0 interrupt request bit INT1 interrupt request bit Serial I/O1 receive interrupt request bit Serial I/O1 transmit interrupt request bit Timer X interrupt request bit Timer Y interrupt request bit Timer 2 interrupt request bit Timer 3 interrupt request bit b0 b7 Interrupt request register 2 (IREQ2 : address 003D16) Serial I/O2 receive interrupt request bit Serial I/O2 transmit interrupt request bit CNTR 0 interrupt request bit CNTR 1 interrupt request bit Timer 1 interrupt request bit Key-on wake up interrupt request bit Not used (return “0” when read) Interrupt control register 1 (ICON1 : address 003E16) INT0 interrupt enable bit INT1 interrupt enable bit Serial I/O1 receive interrupt enable bit Serial I/O1 transmit interrupt enable bit Timer X interrupt enable bit Timer Y interrupt enable bit Timer 2 interrupt enable bit Timer 3 interrupt enable bit b0 b7 Interrupt control register 2 (ICON2 : address 003F16) Serial I/O2 receive interrupt enable bit Serial I/O2 transmit interrupt enable bit CNTR 0 interrupt enable bit CNTR 1 interrupt enable bit Timer 1 interrupt enable bit Key-on wake up interrupt enable bit Not used (returns “0” when read) Not used (returns “0” when read) (Do not write “1” to this bit) 0 : No interrupt request issued 1 : Interrupt request issued 0 : Interrupts disabled 1 : Interrupts enabled

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS TIMERS The 7510 group has five built-in timers: timer X, timer Y , timer 1, timer 2, and timer 3. Timer X and timer Y are 16-bit timers, whereas timer 1, timer 2, and timer 3 are 8-bit timers. All timers are down count timers. When the timer reaches “00 16”, an underflow occurs at the next count pulse and the correspond- ing timer latch is reloaded into the timer and the count is continued. When a timer underflows, the interrupt request bit cor- Fig. 9 Block diagram of Timer XCIN XIN P42/CNTR 0 P42 direction register Pulse output mode P42 latch P43/CNTR 1 CNTR 1 active edge selection bit Internal system clock selection bit CNTR 0 active edge selection bit Timer X stop control bit Timer X write control bit Timer X interrupt request Timer X operation mode bit Pulse output mode CNTR 0 interrupt request CNTR 0 active “1” edge selection bit “1” “0” “10” “11” “01” “00” “0” “1” “0” “10” “11” “01” “00” Timer Y operation mode bit Timer 1 count source selection bit “1” “0” “1” “0”Timer 2 count source selection bit Timer 3 count source selection bit Timer 3 interrupt request Timer 1 interrupt request Timer 2 interrupt request Timer 2 write control bit Timer Y interrupt request Timer Y operation mode bit CNTR 1 interrupt request Pulse width continuously measurement mode Period measurement mode Rising edge detector Falling edge detector Timer Y stop control bit Timer 1 latch (8) Timer 1 (8) Timer 2 latch (8) Timer 2 (8) Timer 3 latch (8) Timer 3 (8) “1” “0” “11” “01” “00” “10” Timer XL latch (8) Timer XL (8) Timer XH latch (8) Timer XH (8) Timer YL latch (8) Timer YL (8) Timer YH latch (8) Timer YH (8) SQ Q T “0” “1”

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS responding to that timer is set to “1”. Read and write operation on 16-bit timer must be performed for both high and low-order bytes. When reading a 16-bit timer, read the high-order byte first. When writing to a 16-bit timer, write the low-order byte first. The 16-bit timer cannot perform the correct op- eration when reading during the write operation, or when writing during the read operation. Timer X Timer X is a 16-bit timer that can be selected in one of four modes and can be controlled the timer X write by setting the timer X mode register. Timer mode The timer counts f(X IN)/16 (or f(XCIN)/16, if the selected system clock φ is f(XCIN)/2). Pulse output mode Each time the timer underflows, a signal output from the CNTR pin is inverted. Except for this, the operation in pulse output mode is the same as in timer mode. When using a timer in this mode, set the corresponding port P4 2 direction register to output mode. Event counter mode The timer counts signals input through the CNTR 0 pin. Except for this, the operation in event counter mode is the same as in timer mode. Pulse width measurement mode The count source is f(X IN)/16 (or f(XCIN)/16, if the selected system clock φ is f(XCIN)/2). If CNTR0 active edge selection bit is “0”, the timer counts while the input signal of CNTR0 pin is at “H”. If it is “1”, the timer counts while the input signal of CNTR0 pin is at “L”. Timer X Write Control If the timer X write control bit is “0”, when the value is written in the address of timer X, the value is loaded in the timer X and the latch at the same time. If the timer X write control bit is “1”, when the value is written in the address of timer X, the value is loaded only in the latch. The value in the latch is loaded in timer X after timer X underflows. If the value is written in latch only, unexpected value may be set in the high-order counter when the writing in high-order latch and the underflow of timer X are performed at the same timing. Note on CNTR 0 Interrupt Active Edge Selection CNTR 0 interrupt active edge depends on the CNTR0 active edge selection bit. Fig. 10 Structure of timer X mode register Timer X write control bit 0 : Write data in latch and timer 1 : Write data in latch only Not used (Always write “0” ) Timer X operation mode bits b5 b4 0 0 : Timer mode 0 1 : Pulse output mode 1 0 : Event counter mode 1 1 : Pulse width measurement mode CNTR 0 active edge selection bit 0 : Count at rising edge in event counter mode Start from “H” output in pulse output mode Measure “H” pulse width in pulse width measurement mode Falling edge active for CNTR 0 interrupt 1 : Count at falling edge in event counter mode Start from “L” output in pulse output mode Measure “L” pulse width in pulse width measurement mode Rising edge active for CNTR 0 interrupt Timer X stop control bit 0 : Count start 1 : Count stop Timer X mode register (TXM : address 002716)

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS Timer Y Timer Y is a 16-bit timer that can be selected in one of four modes. Timer mode The timer counts f(X IN)/16 (or f(XCIN)/16, if the selected system clock φ is f(XCIN)/2). Period measurement mode CNTR 1 interrupt request is generated at rising/falling edge of CNTR 1 pin input signal. Simultaneously, the value in timer Y latch is reloaded in timer Y and timer Y continues counting down. Except for the above-mentioned, the operation in period measurement mode is the same as in timer mode. The timer value just before the reloading at rising/falling of CNTR pin input signal is retained until the timer Y is read once after the reload. The rising/falling timing of CNTR 1 pin input signal is found by CNTR 1 interrupt. Event counter mode The timer counts signals input through the CNTR 1 pin. Except for this, the operation in event counter mode is the same as in timer mode. Pulse width HL continuously measurement mode CNTR 1 interrupt request is generated at both rising and falling edges of CNTR1 pin input signal. Except for this, the operation in pulse width HL continuously measurement mode is the same as in period measurement mode. Note on CNTR 1 Interrupt Active Edge Selection CNTR 1 interrupt active edge depends on the CNTR1 active edge selection bit. However, in pulse width HL continuously measure- ment mode, CNTR 1 interrupt request is generated at both rising and falling edges of CNTR1 pin input signal regardless of the set- ting of CNTR1 active edge selection bit. Fig. 11 Structure of timer Y mode register Not used (return “0” when read) Timer Y operation mode bits b5 b4 0 0 : Timer mode 0 1 : Period measurement mode 1 0 : Event counter mode 1 1 : Pulse width HL continuously measurement mode CNTR 1 active edge selection bit 0 : Count at rising edge in event counter mode Measure the falling edge to falling edge period in period measurement mode Falling edge active for CNTR 1 interrupt 1 : Count at falling edge in event counter mode Measure the rising edge to rising edge period in period measurement mode Rising edge active for CNTR 1 interrupt Timer Y stop control bit 0 : Count start 1 : Count stop Timer Y mode register (TYM : address 002816)

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS Timer 1, Timer 2, Timer 3 Timer 1, timer 2, and timer 3 are 8-bit timers. The count source for each timer can be selected by timer 123 mode register. The timer latch value is not affected by a change of the count source. How- ever, because changing the count source may cause an inadvertent count down of the timer. Therefore, rewrite the value of timer whenever the count source is changed. Timer 2 Write Control If the timer 2 write control bit is “0”, when the value is written in the address of timer 2, the value is loaded in the timer 2 and the latch at the same time. If the timer 2 write control bit is “1”, when the value is written in the address of timer 2, the value is loaded only in the latch. The value in the latch is loaded in timer 2 after timer 2 underflows. Note on Timer 1 to Timer 3 When the count source of timer 1 to 3 is changed, the timer count- ing value may be changed large because a thin pulse is generated in count input of timer. If the count source of timer 2 or timer 3 is connected to timer 1 output, when timer 1 is written, the counting value of timer 2 or timer 3 may be changed large because a thin pulse is generated in timer 1 output. Therefore, set the value of timer in the order of timer 1 , timer 2 and timer 3 after the count source selection of timer 1 to 3. Fig. 12 Structure of timer 123 mode register Not used (Always write “0” ) Timer 2 write control bit 0 : Write data in latch and timer 1 : Write data in latch only Timer 2 count source selection bit 0 : Timer 1 output 1 : XIN/16 (or XCIN/16 when system clock f = XCIN/2) Timer 3 count source selection bit 0 : Timer 1 output 1 : XCIN/32 Timer 1 count source selection bit 0 : XIN/16 (or XCIN/16 when system clock f = XCIN/2) 1 : XCIN/32 Not used (return “0” when read) Timer 123 mode register (T123M : address 002916)

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICR OCOMPUTERS Data bus Receive buffer Address 001816 003016 Receive buffer full flag (RBF) Receive interrupt request (RI) Serial I/O control register Receive shift register Shift clock Clock control circuit Clock control circuitFalling-edge detector Serial I/O synchronous clock selection bit Frequency division ratio 1/(n+1) Baud rate generator Address 001C16 003416 Shift clock Transmit shift register Transmit buffer register Transmit interrupt source selection bit Transmit shift completion flag (TSC) Transmit interrupt request (TI) Transmit buffer empty flag (TBE) Serial I/O status registerAddress 001816 Data bus F/F P44/RX D 1 P30/RX D 2 P46/SCLK1 P32/SCLK2 f(XIN) P47/SRDY1 P33/SRDY2 P45/TX D 1 P31/TX D 2 Contents in are for serial I/O2. Address 001A16 003216 Address 001916 003116 BRG count source selection bit 003016 SERIAL I/O The 7510 group has two built-in serial I/O channels (serial I/O1 and serial I/O2). Both serial I/O ports are functionally identical. Serial I/O can be used as either clock synchronous or asynchro- nous (UART) serial I/O. A dedicated timer (baud rate generator) is also provided for baud rate generation. Clock Synchronous Serial I/O Mode Clock synchronous serial I/O mode can be selected by setting the mode selection bit of the serial I/O control register (addresses 001A 16 and 003216) to “1”. For clock synchronous serial I/O, the transmitter and the receiver must use the same clock. If an internal clock is used, transfer is started by a write signal to the TB/RB (addresses 001816 and 003016). Fig. 13 Block diagram of clock synchronous serial I/O Fig. 14 Operation of clock synchronous serial I/O function D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7D 0 D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7D 0 Internal clock f Transfer shift clock (1/2 to 1/2048 of the internal clock, or an external clock) Serial output TX D Serial input RX D Receive enable signal SRDY Write signal to receive/transmit buffer TBE = 0 TBE = 1 TSC = 0 RBF = 1 TSC = 1 Overrun error (OE) detection The transmit interrupt (TI) can be selected to occur either when the transmit buffer has emptied (TBE = 1) or after the transmit shift operation has ended (TSC = 1), by setting the transmit interrupt source selection bit (TIC) of the serial I/O control register. If data is written to the transmit buffer when TSC = 0, the transmit clock is generated continuously and serial data is output continuously from the TX D pin. The receive interrupt (RI) is set when the receive buffer full flag (RBF) becomes “1”. Notes 1 : 2 : 3 :

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS Asynchronous Serial I/O (UART) Mode Clock asynchronous serial I/O mode (UART) can be selected by clearing the serial I/O mode selection bit of the serial I/O control register to “0”. Eight serial data transfer formats can be selected, and the transfer formats used by a transmitter and receiver must be identical. The transmit and receive shift registers each have a buffer, but the two buffers have the same address in memory. Since the shift register cannot be written to or read from directly, transmit data is written to the transmit buffer, and receive data is read from the receive buffer. The transmit buffer can also hold the next data to be transmitted, and the receive buffer can hold a char- acter while the next character is being received. Fig. 15 Block diagram of UART serial I/O Fig. 16 Operation of UART serial I/O function Data bus Receive buffer Receive buffer full flag (RBF) Receive interrupt request (RI) Serial I/O control register Receive shift register Clock control circuit P44/RX D 1 P30/RX D 2 Address 001A16 003216 Address 001816 003016 UART control register Address 001B16 003316 SP detectorPE FE 7 bits 8 bits Character length selection bit OE P46/SCLK1 P32/SCLK2 f(XIN) P45/TX D 1 P31/TX D 2 Baud rate generator Address 001C16 003416 1/4 BRG count source selection bitFrequency division ratio 1/(n+1) Serial I/O synchronous clock selection bit Character length selection bit Transmit shift register Transmit buffer register Transmit interrupt source selection bit Transmit shift completion flag (TSC) Transmit interrupt request (TI) Serial I/O status registerAddress Data bus Contents in are for serial I/O2. 001816 003016 Transmit buffer empty flag (TBE) Address 001916 003116 ST detector ST/SP/PA generator D 0 D 1 TBE = 1 SP ST D 0 D 1ST SP TSC = 1 ] TBE = 0TBE = 0 TSC = 0 TBE = 1 1 start bit 7 or 8 data bits 1 or 0 parity bit 1 or 2 stop bit(s) ] Generated at 2nd bit in 2-stop-bit mode RBF = 0 D 0 D 1 RBF = 1 SP ST D 0 D 1ST SP RBF = 1 Transmit or receive clock Transmit buffer write signal Serial output TX D Receive buffer read signal Serial input RX D Error flag detection occurs at the same time that the RBF flag becomes “1” (at 1st stop bit, during reception). The transmit interrupt (TI) can be selected to occur when either the TBE or TSC flag becomes “1”, depending on the setting of the transmit interrupt source selection bit (TIC) of the serial I/O control register. The receive interrupt (RI) is set when the RBF flag becomes “1”. After data is written to the transmit buffer when TSC = 1, 0.5 to 1.5 cycles of the data shift cycle is necessary until changing to TSC = 0. Notes 1 : 2 : 3 : 4 :

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS Serial I/O Control Register SIO1CON (001A 16), SIO2CON (003216) The serial I/O control register consists of eight control bits for the serial I/O function. UART Control Register UART1CON (001B 16), UART2CON (003316) The UART control register consists of four control bits (bits 0 to 3) which are valid when asynchronous serial I/O is selected and set the data format of an data transfer. One bit in this register (bit 4) is always valid and sets the output structure of the P4 5/TX D 1 (P31/ TX D2) pin. Serial I/O Status Register SIO1STS (001916), SIO2STS (003116) The read-only serial I/O status register consists of seven flags (bits 0 to 6) which indicate the operating status of the serial I/O function and various errors. Three of the flags (bits 4 to 6) are valid only in UART mode. The receive buffer full flag (bit 1) is cleared to “0” when the receive buffer is read. If there is an error, it is detected at the same time that data is transferred from the receive shift register to the receive buffer, and the receive buffer full flag is set. Writing to the serial I/O status reg- ister clears all the error flags OE, PE, FE, and SE (bit 3 to bit 6, respectively). Writing “0” to the serial I/O enable bit SIOE (bit 7 of the serial I/O control register) also clears all the status flags, in- cluding the error flags. All bits of the serial I/O status register are initialized to “0” at reset, but if the transmit enable bit (bit 4) of the serial I/O control register has been set to “1”, the transmit shift completion flag (bit 2) and the transmit buffer empty flag (bit 0) become “1”. Transmit Buffer Register/Receive Buffer Register TB1/RB1 (001816), TB2/RB2 (003016) The transmit buffer register and the receive buffer register are lo- cated at the same address. The transmit buffer register is write-only and the receive buffer register is read-only. If a character bit length is 7 bits, the MSB of data stored in the re- ceive buffer register is “0”. Baud Rate Generator BRG1 (001C 16), BRG2 (003416) The baud rate generator determines the baud rate for serial trans- fer. The baud rate generator divides the frequency of the count source by 1/(n+1), where n is the value written to the baud rate generator.

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS Transmit buffer empty flag (TBE) 0 : Buffer full 1 : Buffer empty Receive buffer full flag (RBF) 0 : Buffer empty 1 : Buffer full Transmit shift completion flag (TSC) 0 : Transmit shift in progress 1 : Transmit shift completed Overrun error flag (OE) 0 : No error 1 : Overrun error Parity error flag (PE) 0 : No error 1 : Parity error Framing error flag (FE) 0 : No error 1 : Framing error Summing error flag (SE) 0 : (OE) U (PE) U (FE) = 0 1 : (OE) U (PE) U (FE) = 1 Not used (returns “1” when read) b7 Serial I/O status register (SIO1STS : address 001916) (SIO2STS : address 003116) BRG count source selection bit (CSS) 0 : f(XIN) 1 : f(XIN) divided by 4 Serial I/O synchronous clock selection bit (SCS) 0 : BRG output divided by 4 when clock synchronous serial I/O is selected, BRG output divided by 16 when UART is selected. 1 : External clock input when clock synchronous serial I/O is selected, external clock input divided by 16 when UART is selected. S RDY output enable bit (SRDY ) 0 : P47 P33 pin operates as ordinary I/O pin 1 : P47 P33 pin operates as SRDY output pin Transmit interrupt source selection bit (TIC) 0 : Interrupt when transmit buffer has emptied 1 : Interrupt when transmit shift operation is completed Transmit enable bit (TE) 0 : Transmit disabled 1 : Transmit enabled Receive enable bit (RE) 0 : Receive disabled 1 : Receive enabled Serial I/O mode selection bit (SIOM) 0 : Asynchronous serial I/O (UART) 1 : Clock synchronous serial I/O Serial I/O enable bit (SIOE) 0 : Serial I/O disabled (pins P4 4 to P47 P30 to P33 operate as ordinary I/O pins) 1 : Serial I/O enabled (pins P44 to P47 P30 to P33 operate as serial I/O pins) b7 Serial I/O control register (SIO1CON : address 001A16) (SIO2CON : address 003216) Character length selection bit (CHAS) 0 : 8 bits 1 : 7 bits Parity enable bit (PARE) 0 : Parity checking disabled 1 : Parity checking enabled Parity selection bit (PARS) 0 : Even parity 1 : Odd parity Stop bit length selection bit (STPS) 0 : 1 stop bit 1 : 2 stop bits 5/TXD 1 P-channel output disable bit (POFF) P31/TX D 2 P-channel output disable bit 0 : CMOS output (in output mode) 1 : N-channel open-drain output (in output mode) Not used (return “1” when read) b7 UART control register (UART1CON : address 001B16) (UART2CON : address 003316) Contents in are for serial I/O2. Fig. 17 Structure of serial I/O control registers

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS LCD CONTROLLER/DRIVER The 7510 group has a built-in Liquid Crystal Display (LCD) control- ler/driver consisting of the following. l A 160-byte LCD display RAM l Segment drivers l Common drivers l A timing generator l A built-in bias resistor l A timing controller l An LCD mode register l An LCD contrast control register l An LCD contrast controller A maximum of eighty segment output pins (SEG 0–SEG 79) and six- teen common output pins (COM0–COM 15) can be used to control an external LCD display controller. Fig. 18 Block diagram of LCD controller/driver LCDCK count source selection bit LCD display RAM address selection bit SEG 0 LCD display RAM SEG 1 SEG 78 SEG 79 VLCD VL2 VL3 VSS COM 0 COM 1 COM 7 LCD contrast control register address 0037 7 0

70 LCD mode register

LCDCK division ratio selection bit LCDCK count source selection bitLCD drive timing selection bit LCD enable bit LCDCK Timing controller Contrast controller Common driver Bias controller Bias resistor Common driverSegment driverSegment driverSegment driverSegment driver Bit selectorBit selectorBit selectorBit selector 004016, 009016 or 034016, 039016 004116, 009116 or 034116, 039116 008E16, 00DE16 or 038E16, 03DE16 008F16, 00DF16 or 038F16, 03DF16 LCD contrast control enable bit f(XCIN)/16 f(XIN)/1024 Data bus COM 8 COM 9 COM 15 LCD clock generator

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS LCD Controller/Driver Function The controller/driver reads the display data, performs bias and duty ratio control, and outputs the correct LCD timing signals on the segment and common pins according to the data in LCD dis- play RAM. LCD Mode Register LM (003916) The LCD mode register is an 8-bit register. This register is used to match the characteristics of the controller/driver to the LCD panel used. Table 2 Maximum number of display pixels for each duty ratio Duty ratio Maximum number of display pixels Note:Prior to executing an STP instruction, the LCD must be disabled by clearing the bit 3 of the LCD mode register to “0”. Fig. 19 Structure of LCD mode register 8 5 80 dots (16 characters (5 5 7 dots/1 character) + cursor) 5 1 line 11 5 80 dots (16 characters (5 5 10 dots/1 character) + cursor) 5 1 line 16 5 80 dots (16 characters (5 5 7 dots/1 character) + cursor) 5 2 line Duty ratio selection bits b1 b0 0 0 : 1/8 duty (pins COM0 – COM 7) 0 1 : 1/8 duty (pins COM8 – COM 15) 1 0 : 1/11 duty (pins COM0 – COM 10) 1 1 : 1/16 duty (pins COM0 – COM 15) LCD display RAM address selection bit 0 : Third page 1 : Zero page LCD enable bit 0 : Turn off 1 : Turn on LCD drive timing selection bit 0 : Type-A 1 : Type-B LCDCK division ratio selection bits b6 b5 0 0 : Clock input 0 1 : Clock input/2 1 0 : Clock input/4 1 1 : Clock input/8 LCDCK count source selection bit 0 : f(X IN) /1024 1 : f(XCIN) /16 LCD mode register (LM : address 003916)

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS LCD Display RAM The 7510 group has LCD display RAM apart from user RAM at addresses 004016 to 043F16. The LCD display RAM consists of 160 bytes. The memory space for the LCD display RAM can be selected as zero page addresses 0040 16 to 00DF16 or third page addresses 034016 to 03DF16, by setting the LCD display RAM ad- dress selection bit. When the LCD display RAM is at zero page, the addresses 0040 to 00DF16 of user RAM can not be used. When the LCD display RAM is at third page, the addresses 034016 to 03DF16 of user RAM can not be used. After reset, the LCD display RAM is set to third page. Writing “1” to a bit of the LCD display RAM activates the corre- sponding pixel on the LCD panel and writing “0” to the bit turns the pixel off. Note:The data of user RAM at the same addresses with the LCD display RAM (addresses 004016 to 00DF16 or 034016 to 03DF16) is retained. Therefore, user RAM can be used effectively by switching the LCD display RAM address. Fig. 20 LCD display RAM map and example of a display pattern for 1/16 duty operation 1 1 101 COM 0 COM 1 COM 2 COM 3 COM 4 COM 5 COM 6 COM 7 COM 8 COM 9 COM 10 COM 11 COM 12 COM 13 COM 14 COM 15 1000 01110111110111010001 00101110 1101100100001001000010001 1000100100 1010100100001001000010001 1000100100 1010100100001000111010001 1111100100 1000100100001000000110001 1000100100 1000100100001000000110001 1000100100 1000101110001001111001110 1000101110 1111100000000000000000000 000000000011 1000100110111111111100100 1111111110 110110100 00001100000 100 1000010001 10 0100001000101111000100 1000010001 10 0100110001000000100100 1111011110 1000100001001000000100100 1000010000 1000101001001001000100100 1000010000 1000100110001000111001110 1000010000 0000000000000000000000000 111100000 SEG 0 SEG 1 SEG 2 SEG 3 SEG 4 SEG 5 SEG 6 SEG 7 SEG 8 SEG 9 SEG 10 SEG 11 SEG 12 SEG 13 SEG 14 SEG 15 SEG 16 SEG 17 SEG 18 SEG 19 SEG 20 SEG 21 SEG 22 SEG 23 SEG 24 034016 034116 034216 034316 034416 034516 034616 034716 034816 034916 034A16 034B16 034C 16 034D 16 034E16 034F16 035016 035116 035216 035316 035416 035516 035616 035716 035816 038616 038716 038816 038916 038A16 038B16 038C 16 038D 16 038E16 038F16 03D6 16 03D7 16 03D8 16 03D9 16 03DA 16 03DB 16 03DC 16 03DD 16 03DE 16 03DF 16 039016 039116 039216 039316 039416 039516 039616 039716 039816 039916 039A16 039B16 039C 16 039D 16 039E16 039F16 03A016 03A116 03A216 03A316 03A416 03A516 03A616 03A716 03A816 At third page selection 004016 004116 004216 004316 004416 004516 004616 004716 004816 004916 004A16 004B16 004C 16 004D 16 004E16 004F16 005016 005116 005216 005316 005416 005516 005616 005716 005816 008616 008716 008816 008916 008A16 008B16 008C 16 008D 16 008E16 008F16 00D6 16 00D7 16 00D8 16 00D9 16 00DA 16 00DB 16 00DC 16 00DD 16 00DE 16 00DF 16 009016 009116 009216 009316 009416 009516 009616 009716 009816 009916 009A16 009B16 009C 16 009D 16 009E16 009F16 00A016 00A116 00A216 00A316 00A416 00A516 00A616 00A716 00A816 At zero page selection SEG 70 SEG 71 SEG 72 SEG 73 SEG 74 SEG 75 SEG 76 SEG 77 SEG 78 SEG 79 LSB MSB LSB MSB LCD display RAM map

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS Bias Control and Time Division Control The LCD controller/driver has built-in bias resistor and supports 1/ 4 bias or 1/5 bias. The bias setting is made by either floating pins V L2 and VL3 (1/5 bias) or shorting them together externally (1/4 bias). The number of common pins driven is determined by the duty ratio selected. Bits 0 and 1 of the LCD mode register are used to set the duty ratio. Contrast Controller The contrast controller is a circuit generating 32 steps of voltages using the voltage applied to the V LCD pin as the reference voltage. The voltage generated varies depending on the values given to bit 0–bit 4 with the LCD contrast control register. When bit 7 of the LCD contrast control register is set to “1”, the voltage generated by the contrast controller is applied to V L5. Given below is the relation between the values set to bit 0–bit 4 of LCD contrast control regis- ter and the voltages applied to V L5. Voltage applied to VL5 = Voltage applied to the VLCD pin 5 (n+33)/64 Where: n = Value set to bit 0–bit 4 of the LCD contrast control register (in decimal values) Duty ratio Duty ratio selection bit Bit 1 Bit 0 Common pins used COM 0–COM 7 COM 8–COM 15 COM 0–COM 10 COM 0–COM 15 When the contrast controller is used, it becomes possible to apply 32 steps of voltage to VL5 from 1/2 VLCD through VLCD . Conse- quently, 32 steps of contrast adjustment by the software becomes possible. Note:Supply power to the contrast controller from an external source through the VLCD pin. Also, when bit 7 of the LCD contrast control register is set to “0”, V LCD pin is coupled directly to VL5 (the contrast controller and VL5 become separated). In this case, perform contrast adjustment using an external circuit. Note:For all duty ratios, the unused common pins output the non-select waveform. Fig. 22 Structure of LCD contrast control register LCD Drive Timing The LCD controller/driver supports both type-A and type-B drive timing. The desired type is selected by setting the LCD drive timing selec- tion bit (bit 4 of the LCD mode register). If the LCD drive timing selection bit is set to “0”, type-A is selected, and if this bit is set to “1”, type-B is selected. After reset, type-A is selected for the drive timing. The frame frequency can be determined by the following equation: Frame frequency = Fig. 21 Example of circuit at 1/5 and 1/4 bias Table 3 Time division control LCDCK count source frequency LCDCK division ratio 5 duty ratio VL5 R VL4 R VL3 R VL2 R VL1 R VL2 VL3 Contrast controller “0” “1” LCD contrast control enable bit Variable resistance for brightness control Open VLCD 1/5 bias Variable resistance for brightness control VL5 R VL4 R VL3 R VL2 R VL1 R VL2 VL3 Contrast controller “0” “1” LCD contrast control enable bit External connection VLCD 1/4 bias LCD contrast control register (LC : address 003716) VLCD level selection bit Not used (returns “0” when read) LCD contrast control enable bit 0 : Built-in LCD contrast controller is not used 1 : Built-in LCD contrast controller is used. b7 b0

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS 1 frame OFF OFF OFFON ON OFF LCDCK COM 7 VL5 VL4 VL3 VL2 VL1 VSS COM 6 VL5 VL4 VL3 VL2 VL1 VSS SEG 0 – COM 7 VL5 VL4 VL3 VL2 VL1 VSS VL1 VL2 VL3 VL4 VL5 SEG 0 VL5 VL4 VL3 VL2 VL1 VSS SEG 0 – COM 6 VL5 VL4 VL3 VL2 VL1 VSS VL1 VL2 VL3 VL4 VL5 Fig. 23 1/8 duty, 1/5 bias, type-A LCD wave diagram

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS Fig. 24 1/8 duty, 1/5 bias, type-B LCD wave diagram 1 frame OFFON LCDCK COM 7 COM 6 SEG 0 – COM 7 SEG 0 SEG 0 – COM 6 VL5 VL4 VL3 VL2 VL1 VSS VL1 VL2 VL3 VL4 VL5 OFF VL5 VL4 VL3 VL2 VL1 VSS VL5 VL4 VL3 VL2 VL1 VSS VL5 VL4 VL3 VL2 VL1 VSS 1 frame OFFON OFFON OFF OFF VL5 VL4 VL3 VL2 VL1 VSS VL1 VL2 VL3 VL4 VL5

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS KEY-ON WAKE UP The 7510 group contains a key-on wake up interrupt function. The key-on wake up interrupt function is one way of returning from a power down state caused by the STP or WIT instruction. This interrupt is generated by applying “L” level to any pin of port P2 and the microcomputer is returned to the normal operating state. If a key matrix is connected to port P2 0 to P23 as shown in Figure 25, the microcomputer can be returned to a normal state by pressing any one of the keys. Fig. 25 Block diagram of port P2, and example of wired at used key-on wake up Port P2x (X = 0 to 7) “L” level output Port P27 latch Port P2 direction register bit 7 = “1” P27 output Key-on wake up input interrupt request Port P2 input read circuit ] P-channel transistor for pull-up ] ] CMOS output buffer ] ]] Port P26 latch Port P2 direction register bit 6 = “1” P26 output ] ]] Port P25 latch Port P2 direction register bit 5 = “1” P25 output ] ]] PULLP2 register bit 4 Port P24 latch Port P2 direction register bit 4 = “1” P24 output ] ]] PULLP2 register bit 3 Port P23 latch Port P2 direction register bit 3 = “0” 3 input ] ]] PULLP2 register bit 2 Port P22 latch Port P2 direction register bit 2 = “0” P22 input ] ]] PULLP2 register bit 1 Port P21 latch Port P2 direction register bit 1 = “0” P21 input ] ]] PULLP2 register bit 0 Port P20 latch Port P2 direction register bit 0 = “0” P20 input ] ]] PULLP2 register bit 6 PULLP2 register bit 7 PULLP2 register bit 5

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS RESET CIRCUIT To reset the microcomputer, RESET pin should be held at “L” level for 2 µ s or more. Then RESET pin is returned to “H” level (the power source voltage should be between 2.5 V and 5.5 V, and XIN oscillation width is stable), reset is released. In order to give the X IN clock time to stabilize, internal operation does not begin until after about 8000 XIN clock cycles are complete. After the reset is completed, the program starts from the address contained in ad- dress FFFD 16 (high-order) and address FFFC16 (low-order). Make sure that the reset input voltage is less than 0.5 V for VCC of 3.0 V at f(XIN) = 8.0 MHz. Fig. 26 Example of reset circuit Fig. 27 Internal status of microcomputer after reset Power source voltage 0V Poweron 3.0V Reset input voltage 0V 0.5V VCC RESET VSS 7510 groupf(XIN) = 8.0MHz 0.1mF M51953AL 10000000001916(13) Serial I/O1 status register 0016001116(12) Port P5 pull-up control register 0016001016(11) Port P4 pull-up control register 0016000E16(9) Port P2 pull-up control register 0016000D 16(8) Port P1 pull-up control register 0016000C 16(7) Port P0 pull-up control register 0016000B16(6) Port P5 direction register 0016000916(5) Port P4 direction register 0016000716(4) Port P3 direction register 0016000516(3) Port P2 direction register 0016000316(2) Port P1 direction register 0016000116(1) Port P0 direction register 0016000F16(10) Port P3 pull-up control register 0016001A16(14) Serial I/O1 control register 11100000001B16(15) UART1 control register FF16002016(16) Timer X (low) FF16002116(17) Timer X (high) FF16002216(18) Timer Y (low) FF16002316(19) Timer Y (high) FF16002416(20) Timer 1 0116002516(21) Timer 2 FF16002616(22) Timer 3 0016002716(23) Timer X mode register 0016002816(24) Timer Y mode register 0016002916(25) Timer 123 mode register 10000000003116(26) Serial I/O2 status register 0016003216(27) Serial I/O2 control register 11100000003316(28) UART2 control register 0016003716(29) LCD contrast control register 0016003916(30) LCD mode register 0016003A16(31) Interrupt edge selection register 01001100003B16(32) CPU mode register 0016003C 16(33) Interrupt request register 1 0016003D 16(34) Interrupt request register 2 0016003E16(35) Interrupt control register 1 0016003F16(36) Interrupt control register 2 55555 1 55(PS)(37) Processor status register Contents of address FFFD 16(PCH )(38) Program counter Contents of address FFFC 16(PCL) The contents of all other registers and RAM are undefined after reset, so they must be initialized by software. 5 : Undefined Note : Register contentsAddress

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS Fig. 28 Reset sequence about 8000 clock cycles RESET Internal reset f(XIN) and f(f) are in the relationship : f(XIN) = 8.f(f) A question mark (?) indicates an undefined status that depens on the previous status. Notes 1 : 2 : SYNC Data Address f XIN Reset address from vector table ? ? FFFC FFFD AD H , ADL ? ? ? AD L AD H

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS CLOCK GENERATING CIRCUIT The 7510 group has two built-in oscillation circuits. An oscillation circuit can be formed by connecting a resonator between XIN and XOUT (XCIN and XCOUT ). Use the circuit constants in accordance with the resonator manufacturer’s recommended values. No exter- nal resistor is needed between X IN and XOUT since a feed-back resistor exists on-chip. However, an external feed-back resistor is needed between X CIN and XCOUT . Immediately after power on, only the XIN oscillation circuit starts oscillating, and XCIN and XCOUT pins function as I/O port. The pull- up resistor of XCIN and XCOUT pins must be made invalid to use the XCIN oscillating circuit. Frequency Control Middle-speed mode The internal clock φ is the frequency of X IN divided by 8. After reset, this mode is selected. High-speed mode The internal clock φ is half the frequency of X IN. Low-speed mode The internal clock φ is half the frequency of X CIN. Note:If you switch the mode between middle/high-speed and low-speed, both of XIN and XCIN oscillation must be stabilized. The sufficient time is required for the XCIN oscillation to stabilize, especially imme- diately after power-on and at returning from stop mode. The mode must be switched on condition that f(X IN) > 3f(XCIN). Low-power consumption mode In low-speed mode, a low-power consumption operation can be entered by stopping the main clock X IN. To stop the main clock, set bit 5 of the CPU mode register to “1”. When the main clock XIN is restarted, the program must allow enough time for oscillation to stabilize. In low-power consumption mode, the X CIN-XCOUT drive perfor- mance can be reduced, allowing lower power consumption (8 µ A or less with XCIN = 32 kHz). To reduce the XCIN-XCOUT drive per- formance, clear bit 3 of the CPU mode register to “0”. At reset or when the STP instruction is executed, this bit is set to “1” and strong drive is selected to help the oscillation to start. Oscillation Control Stop mode If the STP instruction is executed, the internal clock φ stops at an “H” level. Timer 1 is set to “FF 16” and timer 2 is set to “0116”. Either XIN or XCIN divided by 16 is input to timer 1, and the output of timer 1 is connected to timer 2. The bits of the timer 123 mode register are cleared to “0” except for bit 4. The timer 1 and timer 2 interrupt enable bits must be set to dis- abled (“0”), so a program must set these bits before executing a STP instruction. Oscillation restarts at reset or when an external interrupt is received, but the internal clock φ is not supplied to the CPU until timer 2 underflows. This allows time for the clock circuit oscillation to stabilize. Wait mode If the WIT instruction is executed, the internal clock φ stops at an “H” level. X IN and XCIN are the same state with that before the ex- ecution of the WIT instruction. The internal clock restarts if a reset occurs or when an interrupt is received. Since the oscillator does not stop, normal operation can be started immediately after the clock is restarted. Fig. 29 Ceramic resonator circuit Fig. 30 External clock input circuit XCIN XCOUT C CIN C COUT R d R f XIN XOUT C IN C OUT XCIN XCOUT XIN XOUT Open Open External oscillator or pulse External oscillator 2.5V VSS VCC VSS

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS STP instruction Main clock stop bit Middle/High-speed mode High-speed mode or Low-speed mode Main clock division ratio selection bit Middle-speed mode Timing f (Internal clock) SQ RWIT instruction QS R STP instruction XIN XOUT Port XC selection bit Internal system clock selection bit Low-speed mode (Note 1) Timer 1 count source selection bit Timer 2 count source selection bit “1” “0” “0” “1” Timer 2 XCIN XCOUT “1” “0” Reset Interrupt disable flag I Interrupt request QS R 1/41/2 1/2 Timer 1 Note : When using the low-speed mode, set the port XC selection bit to “1”. Fig. 31 System clock generating circuit block diagram

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS Fig. 32 State transitions of system clock Low power consumption mode (f =16kHz) CM7 = 1 (32kHz selected) CM6 = 0 (High-speed) CM5 = 1 (XIN stopped) CM4 = 1 (32kHz oscillating) CM 6 “1” “0” CM 4 “0” “1” CM 6 “1” “0” Switch the mode by the allows shown between the mode blocks. (Do not switch between the mode directly without an allow.) The main clock must be oscillated (CM5 : 1fi 0) before the switching from the low-speed mode to middle/high-speed mode (CM7 : 1fi 0). The all modes can be switched to the stop mode or the wait mode and return to the source mode when the stop mode or the wait mode is ended. Timer and LCD operate in the wait mode. When the stop mode is ended, a delay of approximately 2ms is automatically generated by timer 1 and timer 2 in middle/high-speed mode. When the stop mode is ended, a delay of approximately 0.25s is automatically generated by timer 1 and timer 2 in low-speed mode. The example assumes that 8.0MHz is being applied to the XIN pin and 32kHz to the XCIN pin f indicates the internal clock. CPU mode register (CPUM : address 003B16) CM 4 : Port XC selection bit 0 : I/O port 1 : XCIN, XCOUT CM 5 : Main clock (XIN-XOUT ) stop bit 0 : Operating 1 : Stopped CM 6 : Main clock division ratio selection bit 0 : XIN/2 (high-speed mode) 1 : XIN/8 (middle-speed mode) CM 7 : Internal system clock selection bit 0 : XIN-XOUT selected (middle/high-speed mode) 1 : XCIN-XCOUT selected (low-speed mode) Notes 1 : 2 : 3 : 4 : 5 : 6 : Reset CM 4 “1” “0” CM 4 “1” “0” CM 6 “1” “0” CM 4 “1” “0” CM 7 “1” “0” CM 6 “1” “0” CM 7 “1” “0” CM 6 “1” “0” CM 5 “0” “1” CM 6 “1” “0” CM 5 “1” “0” CM 5 “1” “0” CM 6 “1” “0” CM 5 “1” “0” High-speed mode (f = 4.0MHz) CM 7 = 0 (8.0MHz selected) CM 6 = 0 (High-speed) CM 5 = 0 (XIN oscillating) CM 4 = 1 (32kHz oscillating) CM6 “1” “0” Middle-speed mode (f =1MHz) CM 7 = 0 (8.0MHz selected) CM 6 = 1 (Middle-speed) CM 5 = 0 (XIN oscillating) CM 4 = 1 (32kHz oscillating) Middle-speed mode (f =1MHz) CM 7 = 0 (8.0MHz selected) CM 6 = 1 (Middle-speed) CM 5 = 0 (XIN oscillating) CM 4 = 0 (32kHz stopped) High-speed mode (f = 4.0MHz) CM 7 = 0 (8.0MHz selected) CM 6 = 0 (High-speed) CM 5 = 0 (XIN oscillating) CM 4 = 0 (32kHz stopped) Low-speed mode (f =16kHz) CM 7 = 1 (32kHz selected) CM 6 = 1 (Middle-speed) CM 5 = 0 (XIN oscillating) CM 4 = 1 (32kHz oscillating) Low-speed mode (f = 16kHz) CM 7 = 1 (32kHz selected) CM 6 = 0 (High-speed) CM 5 = 0 (XIN oscillating) CM 4 = 1 (32kHz oscillating) Low power consumption mode (f =16kHz) CM7 = 1 (32kHz selected) CM6 = 1 (Middle-speed) CM5 = 1 (XIN stopped) CM4 = 1 (32kHz oscillating)

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS NOTES ON PROGRAMMING Processor Status Register The contents of the processor status register (PS) after a reset are undefined, except for the interrupt disable flag (I) which is “1”. Af- ter a reset, initialize flags which affect program execution. In particular, it is essential to initialize the index X mode (T) and the decimal operation mode (D) flag because of their effect on calcu- lations. Interrupts The contents of the interrupt request bits do not change immedi- ately after they have been written. After writing to an interrupt request register, execute at least one instruction before performing a BBC or BBS instruction. Decimal Calculations To calculate in decimal notation, set the decimal operation mode flag (D) to “1”, then execute the ADC or the SBC instruction. Only the ADC and the SBC instruction yield proper decimal results. Af- ter executing the ADC or SBC instruction, execute at least one instruction before executing the SEC, the CLC, or the CLD instruc- tion. In decimal mode, the values of the negative (N), overflow (V), and zero (Z) flag are invalid. The carry flag can be used to indicate whether a carry or borrow has occurred. Initialize the carry flag before each calculation. Clear the carry flag before the ADC instruction and set the flag before the SBC in- struction. Timers If a value n (between 0 and 255) is written to a timer latch, the fre- quency division ratio is 1/(n+1). Multiplication and Division Instructions The index X mode (T) and the decimal mode (D) flag do not affect the MUL and DIV instruction. The execution of these instructions does not change the contents of the processor status register. Ports The contents of the port direction registers cannot be read. The following cannot be used: l the data transfer instruction (LDA, etc.) l the operation instruction when the index X mode flag (T) is “1” l the addressing mode which uses the value of a direction register as an index l the bit-test instruction (BBC or BBS, etc.) to a direction register l the read-modify-write instruction (ROR, CLB, or SEB, etc.) to a direction register Use instructions such as LDM and STA, etc., to set the port direc- tion registers. Serial I/O In clock synchronous serial I/O, if the receive side is using an ex- ternal clock and it is to output the S RDY signal, set the transmit enable bit, the receive enable bit, and the SRDY output enable bit to “1”. Serial I/O continues to output the final bit from the T X D pin after transmission is completed. Instruction Execution Time The instruction execution time is obtained by multiplying the fre- quency of the internal clock φ by the number of cycles needed to execute an instruction. The number of cycles required to execute an instruction is shown in the list of machine instructions. In high-speed mode, the frequency of the internal clock φ is half of the X IN frequency. In middle-speed mode, the frequency of the internal clock φ is one eighth the XIN frequency. DATA REQUIRED FOR MASK ORDERS The following are necessary when ordering a mask ROM produc- tion: 1. Mask ROM Order Confirmation Form 2. Mark Specification Form 3. Data to be written to ROM, in EPROM form (three identical copies)

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS PROM Programming Method The built-in PROM of the blank One Time PROM version and built- in EPROM version can be read or programmed with a general-purpose PROM programmer using a special programming adapter. Set the address of PROM programmer in the user ROM area. The PROM of the blank One Time PROM version is not tested or screened in the assembly process and following processes. To en- sure proper operation after programming, the procedure shown in Figure 33 is recommended to verify programming. Package 176P6D-A Name of Programming Adapter PCA4738F-176A Fig. 33 Programming and testing of One Time PROM version Programming with PROM Programmer The screening temperature is far higher than the storage temperature. Never expose to 150°C exceeding 100 hours. Caution : Screening (Caution) (150°C for 40 hours) Verification with PROM Programmer Functional check in target device

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS ABSOLUTE MAXIMUM RATINGS Symbol VCC VI VI VI VI VO VO VO Pd Topr Tstg Parameter Power source voltage Input voltage P0 0–P0 7, P10–P1 7, P20–P2 7, P30–P3 7, P41–P4 7, P50, P51 Input voltage P40 Input voltage VLCD Input voltage RESET, XIN, XCIN Output voltage P00–P0 7, P10–P1 7, P20–P2 7, P30–P3 7, P41–P4 7, P50, P51, XOUT Output voltage SEG0–SEG 79, COM 0–COM 15 Output voltage XCOUT Power dissipation Operating temperature Storage temperature Conditions Retings –0.3 to 7.0 –0.3 to VCC +0.3 –0.3 to 13 –0.3 to VCC +0.3 –0.3 to VCC +0.3 –0.3 to VCC +0.3 –0.3 to VLCD –0.3 to VCC 300 –20 to 85 –40 to 125 Unit V V V V V V V V mW All voltage are based on VSS . Output transistors are cut off. Ta = 25°C RECOMMENDED OPERATING CONDITIONS (VCC = 4.0 to 5.5 V, Ta = –20 to 85°C, unless otherwise noted) Symbol VCC VLCD VSS VIH VIH VIH VIL VIL VIL Σ IOH(peak) Σ IOL(peak) Σ IOH(avg) Σ IOL(avg) IOH(peak) IOL(peak) IOH(avg) IOL(avg) f(CNTR 0) f(CNTR 1) f(XIN) f(XCIN) Parameter Power source voltage Power source voltage for LCD driver Power source voltage “H” input voltage P0 0–P0 7, P10–P1 7, P20–P2 7, P30–P3 7, P40–P4 7, P50, P51 “H” input voltage RESET, XIN “H” input voltage XCIN “L” input voltage P00–P0 7, P10–P1 7, P20–P2 7, P30–P3 7, P40–P4 7, P50, P51 “L” input voltage RESET , XIN “L” input voltage XCIN “H” total peak output current (Note 1) P00–P07, P10–P17, P20–P27, P30–P37, P41–P47, P50, P51 “L” total peak output current P00–P07, P10–P17, P20–P27, P30–P37, P41–P47, P50, P51 “H” total average output current P00–P07, P10–P17, P20–P27, P30–P37, P41–P47, P50, P51 “L” total average output current P00–P07, P10–P1 7, P20–P27, P30–P37, P41–P47, P50, P51 “H” peak output current (Note 2) P00–P07, P10–P1 7, P20–P27, P30–P37, P41–P47, P50, P51 “L” peak output current P00–P07, P10–P1 7, P20–P27, P30–P37, P41–P47, P50, P51 “H” average output current (Note 3) P00–P07, P10–P17, P20–P27, P30–P37, P41–P47, P50, P51 “L” average output current P00–P07, P10–P17, P20–P27, P30–P37, P41–P47, P50, P51 Timer X, Timer Y input frequency (at 50% duty) Main clock input oscillation frequency (Note 4) Sub-clock input oscillation frequency (Note 4, 5) High-speed mode f(φ) ≥ 2.5 MHz Middle-speed mode 1.0 MHz ≤ f(φ) < 2.5 MHz Low-speed mode f(φ) ≤ 650 kHz Limits Min. 4.0 3.0 2.5 0.8VCC 0.8VCC Typ. 5.0 5.0 5.0 32.768 Max. 5.5 5.5 5.5 V CC VCC VCC 2.5 0.2VCC 0.2VCC 0.4 –80 –40 –10 2.6 8.0 Unit V V V V V V V V V V V mA mA mA mA mA mA mA mA MHz MHz kHz Notes 1:The total output current is the sum of all the currents flowing through all the applicable ports. The total average current is an average value mea- sured over 100 ms. The total peak current is the peak value of all the currents. 2:The peak output current is the peak current flowing in each port. 3:The average output current is an average value measured over 100 ms. 4:The oscillating frequency has a 50% duty cycle. 5:In low-speed mode, the sub-clock input oscillation frequency must be used on condition that f(XCIN) < f(XIN)/3.

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS Parameter “H” output voltage P00–P0 7, P10–P1 7, P20–P2 7, P30–P3 7, P41–P4 7, P50, P51 “L” output voltage P00–P0 7, P10–P1 7, P20–P2 7, P30–P3 7, P41–P4 7, P50, P51 Hysteresis INT0, INT1, CNTR0, CNTR1 Hysteresis SCLK1 , SCLK2 , RXD 1, RX D 2 Hysteresis RESET “H” input current P0 0–P0 7, P10–P1 7, P20–P2 7, P30–P3 7, P41–P4 7, P50, P51 “H” input current RESET , P40 “H” input current XIN “H” input current XCIN “L” input current P00–P0 7, P10–P1 7, P20–P2 7, P30–P3 7, P41–P4 7, P50, P51 “L” input current RESET, P40 “L” input current XIN “L” input current XCIN RAM hold voltage LCD bias resistance (Note) COM on-resistance with V L5 output from COM COM on-resistance with VL4 output from COM COM on-resistance with VL1 output from COM COM on-resistance with VL0 output from COM SEG on-resistance with VL5 output from SEG SEG on-resistance with VL3 output from SEG SEG on-resistance with VL2 output from SEG SEG on-resistance with VL0 output from SEG Power source current ELECTRICAL CHARACTERISTICS (VCC = 4.0 to 5.5 V, Ta = –20 to 85°C, unless otherwise noted) Symbol VOH VOL VT+–VT– VT+–VT– VT+–VT– IIH IIH IIH IIH IIL IIL IIL IIL VRAM R bias R COM5 R COM4 R COM1 R COM0 R SEG5 R SEG3 R SEG2 R SEG0 ICC Test conditions IOH = –10 mA IOL = 10 mA VI = VCC VI = VCC VI = 2.5 V VI = 0 V Pull-ups “off” V CC = 5 V, VI = 0 V Pull-ups “on” V CC = 3 V, VI = 0 V Pull-ups “on” V I = VSS VI = VSS VI = VSS With clock stopped IO = –0.1 mA IO = ±0.1 mA IO = ±0.1 mA IO = 0.1 mA IO = –0.1 mA IO = ±0.1 mA IO = ±0.1 mA IO = 0.1 mA In high-speed mode, VCC = 5 V Output transistors are isolated. In low-speed mode, V CC = 3 V f(XIN) = stopped f(XCIN) = 32 kHz Low-power consumption mode Output transistors are isolated. In low-speed mode, V CC = 3 V f(XIN) = stopped f(XCIN) = 32 kHz (in wait mode) Low-power consumption mode Output transistors are isolated. All oscillation are stopped. (in stop mode) Output transistors are isolated. f(XIN) = 8.0 MHz f(XIN) = 5.0 MHz Ta = 25°C Ta = 85°C Limits Min. VCC –2.0 –30 2.0 Typ. 0.4 0.5 0.5 4.0 2.0 –70 –25 –4.0 –2.0 6.4 4.0 4.5 0.1 Max. 2.0 5.0 5.0 –5.0 –140 –45 –5.0 5.5 0.5 4.5 4.5 0.5 0.5 6.5 6.5 0.5 8.0 9.0 1.0 Unit V V V V V µA µA µA µA µA µA µA µA µA µA V kΩ kΩ kΩ kΩ kΩ kΩ kΩ kΩ kΩ mA mA µA µA µA µA Note:This is the value of bias resistance for one stage.

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS LCD CONTRAST CONTROLLER CHARACTERISTICS (VCC = 4.0 to 5.5 V, Ta = –20 to 85°C, unless otherwise noted) Symbol V CCH Parameter Resolution Accuracy Iinearity Maximum output voltage (Note) Test conditions V CC = 5.0 V, VLCD = VCC Limits Min. 4.9 Typ. Max. 2.0 ±0.5 VLCD Unit Bits LSB V Note:When the value in the LCD contrast control register (address 003716) is “9F16”.

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS Symbol tw(RESET) tc(XIN) twH(X IN) twL(XIN) tc(CNTR) twH(CNTR) twH(INT) twL(CNTR) twL(INT) tc(SCLK1 ) tc(SCLK2 ) twH(S CLK1 ) twH(S CLK2 ) twL(SCLK1 ) twL(SCLK2 ) tsu(RXD 1–SCLK1 ) tsu(RXD 2–SCLK2 ) th(SCLK1 –R XD 1) th(SCLK2 –R XD 2) TIMING REQUIREMENTS 1 (VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85°C, unless otherwise noted) Parameter Reset input “L” pulse width External clock input cycle time External clock input “H” pulse width External clock input “L” pulse width CNTR 0, CNTR1 input cycle time CNTR 0, CNTR1 input “H” pulse width INT0, INT1 input “H” pulse width CNTR 0, CNTR1 input “L” pulse width INT0, INT1 input “L” pulse width Serial I/O1 clock input cycle time (Note) Serial I/O2 clock input cycle time (Note) Serial I/O1 clock input “H” pulse width (Note) Serial I/O2 clock input “H” pulse width (Note) Serial I/O1 clock input “L” pulse width (Note) Serial I/O2 clock input “L” pulse width (Note) Serial I/O1 input set up time Serial I/O2 input set up time Serial I/O1 input hold time Serial I/O2 input hold time Limits Min. 125 200 800 800 370 370 370 370 220 220 100 100 Typ. Max. Unit µ s ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Note:When f(φ) = 4 MHz and bit 6 of address 001A16 or 003216 is “1” (clock synchronous). Divide this value by four when f(φ) = 4 MHz and bit 6 of address 001A 16 or 003216 is “0” (clock asynchronous). Symbol tw(RESET) tc(XIN) twH(X IN) twL(XIN) tc(CNTR) twH(CNTR) twH(INT) twL(CNTR) twL(INT) tc(SCLK1 ) tc(SCLK2 ) twH(S CLK1 ) twH(S CLK2 ) twL(SCLK1 ) twL(SCLK2 ) tsu(RXD 1–SCLK1 ) tsu(RXD 2–SCLK2 ) th(SCLK1 –R XD 1) th(SCLK2 –R XD 2) TIMING REQUIREMENTS 2 (VCC = 3.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85°C, unless otherwise noted) Parameter Reset input “L” pulse width External clock input cycle time External clock input “H” pulse width External clock input “L” pulse width CNTR 0, CNTR1 input cycle time CNTR 0, CNTR1 input “H” pulse width INT0, INT1 input “H” pulse width CNTR 0, CNTR1 input “L” pulse width INT0, INT1 input “L” pulse width Serial I/O1 clock input cycle time (Note) Serial I/O2 clock input cycle time (Note) Serial I/O1 clock input “H” pulse width (Note) Serial I/O2 clock input “H” pulse width (Note) Serial I/O1 clock input “L” pulse width (Note) Serial I/O2 clock input “L” pulse width (Note) Serial I/O1 input set up time Serial I/O2 input set up time Serial I/O1 input hold time Serial I/O2 input hold time Limits Min. 500 200 200 500 230 230 230 230 2000 2000 950 950 950 950 400 400 200 200 Typ. Max. Unit µ s ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Note:When f(φ) = 1 MHz and bit 6 of address 001A16 or 003216 is “1” (clock synchronous). Divide this value by four when f(φ) = 1 MHz and bit 6 of address 001A 16 or 003216 is “0” (clock asynchronous).

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS SWITCHING CHARACTERISTICS 1 (VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85°C, unless otherwise noted) Symbol twH(S CLK1 ) twH(S CLK2 ) twL(SCLK1 ) twL(SCLK2 ) td(SCLK1 –TX D 1) td(SCLK2 –TX D 2) tv(SCLK1 –TX D 1) tv(SCLK2 –TX D 2) tr(SCLK1 ) tf(SCLK1 ) tr(SCLK2 ) tf(SCLK2 ) tr(CMOS) tf(CMOS) Parameter Serial I/O1 clock output “H” pulse width Serial I/O2 clock output “H” pulse width Serial I/O1 clock output “L” pulse width Serial I/O2 clock output “L” pulse width Serial I/O1 output delay time (Note 1) Serial I/O2 output delay time (Note 1) Serial I/O1 output valid time (Note 1) Serial I/O2 output valid time (Note 1) Serial I/O1 clock output rise time Serial I/O1 clock output fall time Serial I/O2 clock output rise time Serial I/O2 clock output fall time CMOS output rise time (Note 2) CMOS output fall time (Note 2) Test conditions C L = 100 pF Limits Min. tc(SCLK1 )/2–30 tc(SCLK2 )/2–30 tc(SCLK1 )/2–30 tc(SCLK2 )/2–30 –30 –30 Typ. Max. 140 140 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns Notes 1: When bit 4 of the UART control register (address 001B16 or 003316) is “0”. 2: XOUT pin is excluded. Fig. 34 Circuit for measuring output switching characteristics (1) Fig. 35 Circuit for measuring output switching characteristics (2) Note:When bit 4 of the UART contronl register (address 001B16 or 003316) is “1” (N-channel open-drain output), and bit 7 of the serial I/O con- trol register (address 001A 16 or 003216) is “1”. SWITCHING CHARACTERISTICS 2 (VCC = 3.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85°C, unless otherwise noted) Symbol twH(S CLK1 ) twH(S CLK2 ) twL(SCLK1 ) twL(SCLK2 ) td(SCLK1 –TX D 1) td(SCLK2 –TX D 2) tv(SCLK1 –TX D 1) tv(SCLK2 –TX D 2) tr(SCLK1 ) tf(SCLK1 ) tr(SCLK2 ) tf(SCLK2 ) tr(CMOS) tf(CMOS) Parameter Serial I/O1 clock output “H” pulse width Serial I/O2 clock output “H” pulse width Serial I/O1 clock output “L” pulse width Serial I/O2 clock output “L” pulse width Serial I/O1 output delay time (Note 1) Serial I/O2 output delay time (Note 1) Serial I/O1 output valid time (Note 1) Serial I/O2 output valid time (Note 1) Serial I/O1 clock output rise time Serial I/O1 clock output fall time Serial I/O2 clock output rise time Serial I/O2 clock output fall time CMOS output rise time (Note 2) CMOS output fall time (Note 2) Test conditions C L = 100 pF Limits Min. tc(SCLK1 )/2–50 tc(SCLK2 )/2–50 tc(SCLK1 )/2–50 tc(SCLK2 )/2–50 –30 –30 Typ. Max. 350 350 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns Notes 1:When bit 4 of the UART control register (address 001B16 or 003316) is “0”. 2:X OUT pin excluded. 100pF CMOS output Measurement output pin 100pF N-channel open-drain output Measurement output pin 1kW

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS TIMING DIAGRAM tc(XIN) twL(X IN)twH(X IN) tw(RESET) twL(INT)twH(INT) twL(CNTR)twH(CNTR) tc(CNTR) tc(SCLK1 ), tc(SCLK2 ) 0.8VCC CNTR 0, CNTR1 0.2VCC 0.2VCC 0.8VCC 0.8VCC INT0, INT1 0.2VCC RESET 0.8VCC XIN 0.2VCC 0.2VCC SCLK1 0.8VCC SCLK2 tsu(RXD 1 – SCLK1 ) tsu(RXD 2 – SCLK2 ) td(SCLK1 – TXD 1), td(SCLK2 – TXD 2) tv(SCLK1 – TX D 1), tv(SCLK2 – TX D 2) th(SCLK1 – RX D 1), th(SCLK 2 – RX D 2) tf twL(S CLK1 ), twL(S CLK2 ) twH(S CLK1 ), twH(S CLK2 ) R X D 1 R X D 2 TX D 1 TX D 2 tr 0.8VCC 0.2VCC

Rev. Rev. No. date

1.0 First Edition 980110

REVISION DESCRIPTION LIST 7510 GROUP DATA SHEET (1/1) Revision Description

© 1998 MITSUBISHI ELECTRIC CORP. New publication, effective Jan. 1998. Specifications subject to change without notice. Notes regarding these materials

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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER