M37477M4

M37477M4 MITSUBISHI | Alldatasheet

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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

DESCRIPTION

The 7477/7478 group is the single-chip microcomputer designed with CMOS silicon gate technology. The single-chip microcomputer is useful for business equipment and other consumer applications. In addition to its simple instruction set, the ROM, RAM, and I/O addresses are placed on the same memory map to enable easy programming. In addition, built-in PROM type microcomputers with built-in elec- trically writable PROM, and additional functions equivalent to the mask ROM version are also available. 7477/7478 group products are shown noted below. The 7477 and the 7478 differ in the number of I/O ports, package outline, and clock generating circuit only. Version Mask ROM version One Time PROM version (Built-in PROM type microcomputers) Mask ROM version One Time PROM version (Built-in PROM type microcomputers) PROM version (Built-in PROM type microcomputer) Product M37477M4-XXXSP/FP M37477M8-XXXSP/FP M37477E8SP/FP M37477E8-XXXSP/FP M37478M4-XXXSP/FP M37478M8-XXXSP/FP M37478E8SP/FP M37478E8-XXXSP/FP M37478E8SS

FEATURES

l The minimum instruction execution time l Power source voltage CC – 2.0MHz oscillation frequency) l Power dissipation in normal mode l Subroutine nesting l Programmable I/O ports 20 (7478 group) 8 channels (7478 group) PIN CONFIGURATION (TOP VIEW)

APPLICATIONS

Audio-visual equipment, VCR, Tuner, Office automation equipment Note :The only differences between the 32P4B package prod- uct and the 32P2W-A package product are package shape and absolute maximum ratings. 16 17 M37477M4-XXXSP M37477M8-XXXSP M37477E8-XXXSP P17/SRDY P16/SCLK P15/TXD P14/RXD P13/T1 P12/T0 P11 P10 P23/IN3 P22/IN2 P21/IN1 P20/IN0 VREF XIN XOUT VSS P07 P06 P05 P04 P03 P02 P01 P00 P41 P40 P33/CNTR 1 P32/CNTR 0 P31/INT1 P30/INT0 RESET V CC Outline 32P4B 16 17 M37477M4-XXXFP M37477M8-XXXFP M37477E8-XXXFP P17/SRDY P16/SCLK P15/TXD P14/RXD P13/T1 P12/T0 P11 P10 P23/IN3 P22/IN2 P21/IN1 P20/IN0 V REF X IN XOUT VSS P07 P06 P05 P04 P03 P02 P01 P00 P41 P40 P33/CNTR 1 P32/CNTR 0 P31/INT1 P30/INT0 RESET VCC Outline 32P2W-A

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER PIN CONFIGURATION (TOP VIEW) Note :The only differences between the 42P4B package product and the 56P6N-A package product are package shape, ab- solute maximum ratings and the fact that the 56P6N-A package product has an AVSS pin. P52 P07 P06 P05 P04 P03 P02 P01 P00 P43 P42 P41 P40 P33/CNTR 1 P32/CNTR 0 P31/INT1 P53 P16/SCLK P15/TXD P14/RXD P13/T1 P12/T0 P11 P10 P27/IN7 P26/IN6 P25/IN5 P24/IN4 P23/IN3 P22/IN2 P21/IN1 P30/INT0 P20/IN0 VREF VSS P51/XCOUT P50/XCIN VCC XIN XOUT VSS AV SS NC NC NC NC NC NC P17/SRDY RESET NC NC NC NCNC NC M37478M4-XXXFP M37478M8-XXXFP M37478E8-XXXFP Outline 56P6N-A P52 P07 P06 P05 P04 P03 P02 P01 P00 P43 P42 P41 P40 P33/CNTR 1 P32/CNTR 0 P31/INT1 P53 P16/SCLK P15/TXD P14/RXD P13/T1 P12/T0 P11 P10 P27/IN7 P26/IN6 P25/IN5 P24/IN4 P23/IN3 P22/IN2 P21/IN1 M37478M4-XXXSP M37478M8-XXXSP M37478E8-XXXSP M37478E8SS P30/INT0 P51/XCOUT P50/XCIN VCC P20/IN0 VREF XIN XOUT VSS P17/S RDY RESET Outline 42P4B 42S1B-A (Window)

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER M37477M4-XXXSP/FP BLOCK DIAGRAM V CC (2) P3(4) P1(8) P0(8) CNTR CNTR INT

1 INT

V SS (4) Clock generating circuit Clock inputX IN Clock outputX OUT ResetinputRESET (P)ROM8192bytes S I/O(8) PWM control A-D converter Program counterPC H(8) Program counterPC L(8) RAM192bytes Stack pointerS(8) Processor status registerPS(8) 8-bit Arithmetic and logical unit Index registerY(8) Index registerX(8) Accumu- latorA(8) Instruction register(8)Instruction decoder Control signal Timer 1 (8) Timer 2(8)Timer 3 (8) Timer 4 (8) I/O port Input port V REF Reference voltage input Input port I/O port I/O port (Note (Note Data bus Notes 1 : 16384 bytes for M37477M8/E8-XXXSP/FP 2 : 384 bytes for M37477M8/E8-XXXSP/FP

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER M37478M4-XXXSP BLOCK DIAGRAM 19 20 XCIN Sub-clock input XCOUT Sub-clock output 25 22 21 VCC 181 42 24 23 33 32 31 30 29 28 27 26 10 11 12 13 14 15 16 17 2 3 4 5 6 7 8 9 41 40 39 38 37 36 35 34 CNTR 0CNTR 1XCIN XCOUT INT1 INT0 VSS P2(8) Clock generating circuit Main clock input XIN Main clock output XOUT Reset input RESET (P)ROM 8192 bytes S I/O(8) PWM control A-D converter Program counter PC H (8) Program counter PC L(8) RAM 192 bytes Stack pointer S(8) Processor status register PS(8) 8-bit Arithmetic and logical unit Index register Y(8) Index register X(8) Accumu- lator A(8) Instruction register(8) Instruction decoder Control signal Timer 1(8) Timer 2(8) Timer 3(8) Timer 4(8) I/O port P4 Input port P3 VREF Reference voltage inputInput port P2 I/O port P1 I/O port P0 (Note 1)(Note 2) Notes 1 : 16384 bytes for M37478M8/E8-XXXSP, M37478E8SS 2 : 384 bytes for M37478M8/E8-XXXSP, M37478E8SS Input port P5 Data bus

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER 18 19 28 23 22 VCC 1552 49 26 25 38 37 36 35 33 32 31 30 7 8 9 10 11 12 13 14 53 54 55 2 3 4 5 6 48 47 46 43 42 41 40 39 CNTR 0CNTR 1XCIN XCOUT INT1 INT0 51 21 VSS AV SS P2(8) Clock generating circuit Reset input RESET (P)ROM 8192 bytes S I/O(8) PWM control A-D converter Program counter PC H (8) Program counter PC L(8) RAM 192 bytes Stack pointer S(8) Processor status register PS(8) 8-bit Arithmetic and logical unit Index register Y(8) Index register X(8) Accumu- lator A(8) Instruction register(8) Instruction decoder Control signal Timer 1(8) Timer 2(8) Timer 3(8) Timer 4(8) I/O port P4 Input port P3 VREF Reference voltage inputInput port P2 I/O port P1 I/O port P0 (Note 1)(Note 2) Notes 1 : 16384 bytes for M37478M8/E8-XXXFP 2 : 384 bytes for M37478M8/E8-XXXFP Input port P5 Data bus XCIN Sub-clock input XCOUT Sub-clock output Main clock input XIN Main clock output XOUT M37478M4-XXXFP BLOCK DIAGRAM

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Basic machine-language instructions Instruction execution time Clock input oscillation frequency Memory size Input/Output port Serial I/O Timers A-D converter Subroutine nesting Interrupt Clock generating circuit Power source circuit Power dissipation Input/Output characters Operating temperature range Device structure Package M37477M4 M37478M4 M37477M8/E8 M37478M8/E8 P0, P1 P3, P5 ROM RAM (P)ROM RAM I/O Input Input I/O FUNCTIONS OF 7477/7478 GROUP Functions 0.5µs (The minimum instructions, at 8 MHz oscillation frequency) 8 MHz (max.) 8192 bytes 192 bytes 16384 bytes 384 bytes 8-bit 5 2 8-bit 5 1 (4-bit 5 1 for the 7477 group) 4-bit 5 2 (Port P5 is not included in the 7477 group) 4-bit 5 1 (2-bit 5 1 for the 7477 group) 8-bit 5 1 8-bit timer 5 4 8-bit 5 1 (8 channels) (8-bit 5 1 (4 channels) for the 7477 group) 96 (max.) 192 (max.) 5 external interrupts, 7 internal interrupts, 1 software interrupt Built-in circuit with internal feedback resistor (a ceramic or a quartz- crystal oscillator) 2.7 to 4.5V (at 2.2V CC –2.0MHz oscillation frequency), 4.5 to 5.5V (at 8MHz oscillation frequency) 35mW (at 8MHz oscillation frequency) –5 to 10mA (P0, P1, P4 : CMOS tri-states) –20 to 85°C CMOS silicon gate 32-pin shrink plastic molded DIP 32-pin plastic molded SOP 42-pin shrink plastic molded DIP 56-pin plastic molded QFP 42-pin ceramic DIP Parameter M37477M4, M37478M4 M37477M8/E8, M37478M8/E8 Input/Output voltage Output current M37477M4/M8/E8-XXXSP M37477M4/M8/E8-XXXFP M37478M4/M8/E8-XXXSP M37478M4/M8/E8-XXXFP M37478E8SS

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Input/ Output PIN DESCRIPTION Pin Name Functions Power source Analog power source Reset input Clock input Clock output Reference voltage input I/O port P0 I/O port P1 Input port P2 Input port P3 I/O port P4 Input port P5 Input Input Output Input I/O I/O Input Input I/O Input Notes 1 : AV SS for M37478M4/M8/E8-XXXFP . 2 : Only P20–P2 3 (IN0–IN3) 4-bit for the 7477 group. 3 : Only P40 and P41 2-bit for the 7477 group. 4 : This port is not included in the 7477 group. Apply voltage of 2.7 to 5.5V to VCC , and 0V to VSS . Ground level input pin for A-D converter. Same voltage as VSS is applied. To enter the reset state, the reset input pin must be kept at “L” for 2µ s or more (under normal VCC conditions). These are I/O pins of internal clock generating circuit for main clock. To control generating frequency, an external ceramic or a quartz crystal oscillator is connected between the X IN and XOUT pins. If an external clock is used, the clock source should be connected the XIN pin and the XOUT pin should be left open. Feedback resistor is connected between XIN and XOUT . Reference voltage input pin for A-D converter. Port P0 is an 8-bit I/O port. The output structure is CMOS output. When this port is selected for input, pull-up transistor can be connected in units of 1-bit and a key on wake up function is provided. Port P1 is an 8-bit I/O port. The output structure is CMOS output. When this port is selected for input, pull-up transistor can be connected in units of 4-bit. P1 2 and P13 are in common with timer output pins T0 and T1. P14, P15, P16 and P17 are in common with serial I/O pins RX D, TXD, SCLK____ and SRDY , respectively. Port P2 is an 8-bit input port. This port is in common with analog input pins IN0 to IN7. Port P3 is a 4-bit input port. P30, P31 are in common with external interrupt input pins INT0, INT1, and P32, P33 are in common with timer input pins CNTR 0, CNTR1. Port P4 is a 4-bit I/O port. The output structure is CMOS output, When this port is selected for input, pull-up transistor can be connected in units of 4-bit. Port P5 is a 4-bit input port and pull-up transistor can be connected in units of 4-bit. P50, P51 are in common with input/output pins of clock for clock function XCIN, XCOUT . When P50, P51 are used as XCIN, XCOUT , connect a ceramic or a quartz crystal oscillator between XCIN and XCOUT . If an external clock input is used, connect the clock input to the XCIN pin and open the XCOUT pin. Feedback resistor is connected between XCIN and XCOUT pins. VCC , VSS AV SS (Note 1) RESET XIN XOUT VREF P00 – P07 P10 – P17 P20 – P27 (Note 2) P30 – P33 P40 – P43 (Note 3) 0 – P53 (Note 4)

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER CPU Mode Register The CPU mode register is allocated at address 00FB16. This register contains the stack page selection bit. FUNCTIONAL DESCRIPTION Central Processing Unit (CPU) The 7477/7478 group uses the standard 740 family instruction set. Refer to the table of 740 family addressing modes and machine in- structions or the SERIES 740 <Software> User’s Manual for details on the instruction set. Machine-resident 740 family instructions are as follows: The FST and SLW instruction cannot be used. The MUL, DIV, WIT, and STP instruction can be used. Fig. 1 Structure of CPU mode register CPU mode register (Address 00FB16) b7 b0 Stack page selection bit (Note 1) 0 : In page 0 area 1 : In page 1 area These bits must always be set to “0”. P50, P51/XCIN, XCOUT selection bit (Note 2) 0 : P50, P51 1 : XCIN, XCOUT Notes 1 : In the M37477M4-XXXSP/FP, M37478M4-XXXSP/FP, set this bit to “0”. 2 : In the 7477 group, set this bit to “0”. XCOUT drive capacity selection bit (Note 2) 0 : Low 1 : High Clock (XIN-XOUT ) stop bit (Note 2) 0 : Oscillates 1 : Stops Internal system clock selection bit (Note 2) 0 : X IN-XOUT selected (normal mode) 1 : XCIN-XCOUT selected (low-speed mode)

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MEMORY

• Special Function Register (SFR) Area The special function register (SFR) area contains the registers relating to functions such as I/O ports and timers.
• RAM RAM is used for data storage as well as a stack area.
• ROM ROM is used for storing user programs as well as the interrupt vector area. Fig. 2 Memory map
• Interrupt Vector Area The interrupt vector area is for storing jump destination ad- dresses used at reset or when an interrupt is generated.
• Zero Page Zero page addressing mode is useful because it enables access to this area with fewer instruction cycles.
• Special Page Special page addressing mode is useful because it enables ac- cess to this area with fewer instruction cycles. RAM (192 bytes) for M37477M8/E8 M37478M8/E8 SFR area Not used Interrupt vector area 000016 00FF 16 01BF 16 C000 16 E000 16 FF00 16 FFE8 16 FFFF 16 Zero page Special page ROM (16K bytes) for M37477M8/E8 M37478M8/E8 ROM (8K bytes) for M37477M4 M37478M4 RAM (192 bytes) for M37477M4 M37477M8/E8 M37478M4 M37478M8/E8 00BF 16 010016

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Fig. 3 SFR (Special Function Register) memory map 00C0 16 00C1 16 00C2 16 00C3 16 00C4 16 00C5 16 00C6 16 00C7 16 00C8 16 00C9 16 00CA 16 00CB 16 00CC 16 00CD 16 00CE 16 00CF 16 00D0 16 00D1 16 00D2 16 00D3 16 00D4 16 00D5 16 00D6 16 00D7 16 00D8 16 00D9 16 00DA 16 00DB 16 00DC 16 00DD 16 00DE 16 00DF 16 00E016 00E116 00E216 00E316 00E416 00E516 00E616 00E716 00E816 00E916 00EA 16 00EB 16 00EC 16 00ED 16 00EE 16 00EF 16 00F016 00F116 00F216 00F316 00F416 00F516 00F616 00F716 00F816 00F916 00FA 16 00FB 16 00FC 16 00FD 16 00FE 16 00FF16 Port P0 Port P0 direction register Port P1 Port P1 direction register Port P2 Port P3 Port P4 Port P4 direction register Port P5 (Note 1) Edge polarity selection register Input latch register A-D control register A-D conversion register P0 pull-up control register P1–P5 pull-up control register (Note 2) Transmit/receive buffer register Serial I/O status register Serial I/O control register UART control register Baud rate generator Timer 1 Timer 2 Timer 3 Timer 4 Timer FF register Timer 12 mode register Timer 34 mode register Timer mode register 2 CPU mode register Interrupt request register 1 Interrupt request register 2 Interrupt control register 1 Interrupt control register 2 Notes 1 : This address is not used in the 7477 group. 2 : This address is allocated P1–P4 pull-up control register for the 7477 group.

1 interrupt request is generated. CNTR 1 pin by setting bit 4 in the edge polarity selection register. can be set and reset with a program. ority. Figure 5 shows interrupts control. Table 1. Interrupt vector address and priority. external, seven internal, and one software sources. Interrupts are vectored interrupts with priorities shown in Table 1. set to the register, the interrupt is activated on the rising edge.

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Fig. 5 Interrupt control Fig. 4 Structure of registers related to interrupt Interrupt request bit Interrupt enable bit Interrupt disable flag I BRK instruction Reset Interrupt request b7 b0 Edge polarity selection register (EG) (Address 00D416) INT0 edge selection bit INT1 edge selection bit CNTR 0 edge selection bit CNTR 1 edge selection bit 0 : Falling edge 1 : Rising edge CNTR 0/CNTR 1 interrupt selection bit 0 : CNTR0 1 : CNTR1 INT1 source selection bit (at power-down state) 0 : P31/INT1 1 : P00 – P07 “L” level (for key-on wake-up) Nothing is allocated (The value is undefined at reading) b7 b0 Interrupt request register 1 (Address 00FC16) Timer 1 interrupt request bit Timer 2 interrupt request bit Timer 3 interrupt request bit Timer 4 interrupt request bit Nothing is allocated (The value is undefined at reading) Serial I/O receive interrupt request bit Serial I/O transmit interrupt request bit A-D conversion completion interrupt request bit b7 b0 Interrupt control register 1 (Address 00FE16) Timer 1 interrupt enable bit Timer 2 interrupt enable bit Timer 3 interrupt enable bit Timer 4 interrupt enable bit Nothing is allocated (The value is undefined at reading) Serial I/O receive interrupt enable bit Serial I/O transmit interrupt enable bit A-D conversion completion interrupt enable bit b7 b0 Interrupt request register 2 (Address 00FD16) INT0 interrupt request bit INT1 interrupt request bit Nothing is allocated (The value is undefined at reading) CNTR 0 or CNTR1 interrupt request bit 0 : No interrupt request 1 : Interrupt requested b7 b0 Interrupt control register 2 (Address 00FF16) INT0 interrupt enable bit INT1 interrupt enable bit Nothing is allocated (The value is undefined at reading) CNTR 0 or CNTR1 interrupt enable bit 0 : Interrupt disable 1 : Interrupt enabled

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER TIMER The 7477/7478 group has four timers; timer 1, timer 2, timer 3, and timer 4. A block diagram of timer 1 through 4 is shown in Figure 6. Timer 1 can be operated in the timer mode, event count mode, or pulse output mode. Timer 1 starts counting when bit 0 in the timer 12 mode register (address 00F8 16) is set to “0”. The count source can be selected from the f(XIN) divided by 16, f(XCIN) divided by 16, f(XCIN), or event input from P32/CNTR 0 pin. Do not select f(XCIN) as the count source in the 7477 group. When bit 1 and bit 2 in the timer 12 mode register are “0”, f(XIN) divided by 16 or f(XCIN) divided by 16 is selected. Selection between f(XIN) and f(XCIN) is done by bit 7 in the CPU mode register (ad- dress 00FB16). When bit 1 in the timer 12 mode register is “0” and bit 2 is “1”, f(XCIN) is selected. And, when bit 1 in the timer 12 mode register is “1”, an event input from the CNTR0 pin is se- lected. Event inputs are selected depending on bit 2 in the edge polarity selection register (address 00D4 16). When this bit is “0”, the inverted value of CNTR0 input is selected; when the bit is “1”, CNTR 0 input is selected. When bit 3 in the timer 12 mode register is set to “1”, the P12 pin becomes timer output T0. When the direction register of P12 is set for the output mode at this time, the timer 1 overflow divided by 2 is output from T Please set the initial output value in the following procedure. À Set “1” to bit 0 of the timer 12 mode register. (Timer 1 count stop.) \ Set “1” to bit 0 of the timer mode register 2. ´ Set the output value to bit 0 of the timer FF register. ˆ Set the count value to the timer 1. ˜ Set “0” to bit 0 of the timer 12 mode register. (Timer 1 count start.) Timer 2 can only be operated in the timer mode. Timer 2 starts counting when bit 4 in the timer 12 mode register is set to “0”. The count source can be selected from the divide by 16, divide by 64, divide by 128, or divide by 256 frequency of f(X IN) or f(XCIN), and timer 1 overflow. Do not select f(XCIN) as the count source in the 7477 group. When bit 5 in the timer 12 mode register is “0”, any of the divide by 16, divide by 64, divide by 128, or divide by 256 frequency of f(X IN) or f(XCIN) is selected. The divide ratio is selected according to bit 6 and bit 7 in the timer 12 mode register, and selection between f(X IN) and f(XCIN) is made according to bit 7 in the CPU mode register. When bit 5 in the timer 12 mode reg- ister is “1”, timer 1 overflow is selected as the count source. Timer 3 can be operated in the timer mode, event count mode, or PWM mode. Timer 3 starts counting when bit 0 in the timer 34 mode register (address 00F9 16) is set to “0”. The count source can be selected from the f(XIN) divided by 16, f(XCIN) divided by 16, f(XCIN), timer 1 or timer 2 overflow, or an event input from P33/CNTR 1 pins according to the statuses of bit 1 and bit 2 in the timer 34 mode register, bit 6 in the timer mode reg- ister 2 (address 00FA 16) and bit 7 in the CPU mode register. Do not select f(XCIN) as the count source in the 7477 group. Note, however, that if timer 1 overflow or timer 2 overflow is selected for the count source of timer 3 when timer 1 overflow is selected for the count source of timer 2, timer 1 overflow is always selected re- gardless of the status of bit 6 in the timer mode register 2. Event inputs are selected depending on bit 3 in the edge polarity selec- tion register. When this bit is “0”, the inverted value of CNTR 1 input is selected; when the bit is “1”, CNTR1 input is selected. Timer 4 can be operated in the timer mode, event count mode, pulse output mode, pulse width measuring mode, or PWM mode. Timer 4 starts counting when bit 3 in the timer 34 mode register is set to “0” when bit 6 in this register is “0”. When bit 6 is “1”, the pulse width measuring mode is selected. The count source can be selected from timer 3 overflow, f(X IN) divided by 16, f(XCIN) divided by 16, f(XCIN), timer 1 or timer 2 overflow, or an event input from P33/CNTR 1 pin according to the statuses of bit 4 and bit 5 in the timer 34 mode register, bit 6 in the timer mode register 2, and bit 7 in the CPU mode register. Do not select f(X CIN ) as the count source in the 7477 group. Note, however, that if timer 1 overflow or timer 2 overflow is selected for the count source of timer 4 when timer 1 overflow is selected for the count source of timer 2, timer 1 overflow is always selected regardless of the status of bit 6 in the timer mode register 2. Event inputs are selected depending on bit 3 in the edge polarity selection register. When this bit is “0”, the inverted value of CNTR 1 input is selected; when the bit is “1”, CNTR1 input is selected. When bit 7 in the timer 34 mode register is set to “1”, the P13 pin becomes timer output T1. When the direction register of P13 is set for the output mode at this time, the timer 4 overflow divided by 2 is output from T 1 when bit 7 in the timer mode register 2 is “0”. Please set the initial output value in the following procedure. À Set “1” to bit 3 of the timer 34 mode register. (Timer 4 count stop.) \ Set “1” to bit 1 of the timer mode register 2. ´ Set the output value to bit 1 of the timer FF register. ˆ Set the count value to the timer 4. ˜ Set “0” to bit 3 of the timer 34 mode register. (Timer 4 count start.) (1) Timer mode Timer performs down count operations with the dividing ratio being 1/(n+1). Writing a value to the timer latch sets a value to the timer. When the value to be set to the timer latch is nn 16, the value to be set to a timer is nn16, which is down counted at the falling edge of the count source from nn16 to (nn16-1) to (nn16-2) to ...0116 to 0016 to FF16. At the falling edge of the count source immediately after timer value has reached FF16, value (nn16-1) obtained by subtract- ing one from the timer latch value is set (reloaded) to the timer to continue counting. At the rising edge of the count source immedi- ately after the timer value has reached FF 16, an overflow occurs and an interrupt request is generated. (2) Event count mode Timer operates in the same way as in the timer mode except that it counts input from the CNTR 0 or CNTR1 pin. (3) Pulse output mode In this mode, duty 50% pulses are output from the T 0 or T1 pin. When the timer overflows, the polarity of the T0 or T1 pin output level is inverted. (4) Pulse width measuring mode The 7477/7478 group can measure the “H” or “L” width of the CNTR 0 or CNTR1 input waveform by using the pulse width mea- suring mode of timer 4. The pulse width measuring mode is selected by writing “1” to bit 6 in the timer 34 mode register. In the pulse width measuring mode, the timer counts the count source while the CNTR 0 or CNTR1 input is “H” or “L”. Whether the CNTR0 input or CNTR1 input to be measured can be specified by the sta- tus of bit 4 in the edge polarity selection register; whether the “H”

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER width or “L” width to be measured can be specified by the status of bit 2 (CNTR0) and bit 3 (CNTR1) in the edge polarity selection reg- ister. (5) PWM mode The PWM mode can be entered for timer 3 and timer 4 by setting bit 7 in the timer mode register 2 to “1”. In the PWM mode, the P1 pin is set for timer output T1 to output PWM waveforms by setting bit 7 in the timer 34 mode register to “1”. The direction register of 3 must be set for the output mode before this can be done. In the PWM mode, timer 3 is counting and timer 4 is idle while the PWM waveform is “L”. When timer 3 overflows, the PWM wave- form goes “H”. At this time, timer 3 stops counting simultaneously and timer 4 starts counting. When timer 4 overflows, the PWM waveform goes “L”, and timer 4 stops and timer 3 starts counting again. Consequently, the “L” duration of the PWM waveform is de- termined by the value of timer 3; the “H” duration of the PWM waveform is determined by the value of timer 4. When a value is written to the timer in operation during the PWM mode, the value is only written to the timer latch, and not written to the timer. In this case, if the timer overflows, a value one less the value in the timer latch is written to the timer. When any value is written to an idle timer, the value is written to both the timer latch and the timer. In this mode, do not select timer 3 overflow as the count source for timer 4. INPUT LATCH FUNCTION The 7477/7478 group can latch the P30/INT0, P31/INT1, P32/ CNTR 0, and P33/CNTR 1 pin level into the input latch register (ad- dress 00D616) when timer 4 overflows. The polarity of each pin latched to the input latch register can be selected by using the edge polarity selection register. When bit 0 in the edge polarity selection register is “0”, the in- verted value of the P3 0/INT0 pin level is latched; when the bit is “1”, the P30/INT0 pin level is latched as it is. When bit 1 in the edge polarity selection register is “0”, the in- verted value of the P3 1/INT1 pin level is latched; when the bit is “1”, the P31/INT1 pin level is latched as it is. When bit 2 in the edge polarity selection register is “0”, the inverted value of the 2/CNTR 0 pin level is latched; when the bit is “1“, the P32/CNTR 0 pin level is latched as it is. When bit 3 in the edge polarity selec- tion register is “0”, the inverted value of the P3 3/CNTR 1 pin level is latched; when the bit is “1”, the P33/CNTR 1 pin level is latched as it is.

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Fig. 6 Block diagram of timer 1 through 4 Timer 1 latch (8) Timer 1 (8) Timer 2 latch (8) Timer 2 (8) Timer 3 latch (8) Timer 3 (8) Timer 4 latch (8) Timer 4 (8) Data bus T12M 2 T12M 0 T12M 1 TM2 0 1/2 1/8 EG 2 Port latch T12M 3 T12M 6 T12M 7 T12M 5 T12M 4 TM2 6 T34M 1 T34M 2 T34M 0 T34M 4 T34M 5 F/F TM2 1TM2 7EG 3 EG 2 T34M 3 T34M 6 EG 4 Port latch XCIN (Note) XIN P32/CNTR 0 P12/T0 P32/CNTR 1 P13/T1 T34M 7 P33/CNTR 1 P32/CNTR 0 P31/INT1 P30/INT0 EG 1 EG 0 ( Select gate : At reset, shaded side is connected.) Note : The 7477 group does not have XCIN input. Timer 1 interrupt request Timer 2 interrupt request Timer 3 interrupt request Timer 4 interrupt request C D3 Q3 D2 Q2 D1 Q1 D0 Q0 EG CM 7

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Fig. 7 Structure of timer mode registers Timer 12 mode register (T12M) (Address 00F816) Timer 1 count stop bit 0 : Count start 1 : Count stop Timer 1 count source selection bit 0 : Internal clock (Note 1) 1 : P32/CNTR 0 external clock Timer 1 internal clock source selection bit (Note 2) 0 : f(XIN) divided by 16 or f(XCIN) divided by 16 1 : f(XCIN) P12/T0 port output selection bit 0 : P12 port output 1 : Timer 1 overflow divided by 2 Timer 2 count stop bit 0 : Count start 1 : Count stop Timer 2 count source selection bit 0 : Internal clock 1 : Timer 1 overflow Timer 2 internal clock source selection bits (Note 3) 00 : f(XIN) divided by 16 or f(XCIN) divided by 16 01 : f(XIN) divided by 64 or f(XCIN) divided by 64 10 : f(XIN) divided by 128 or f(XCIN) divided by 128 11 : f(XIN) divided by 256 or f(XCIN) divided by 256 b7 b0 Timer mode register 2 (TM2) (Address 00FA16) Timer 1 overflow FF set enable bit 0 : Set disable 1 : Set enable Timer 4 overflow FF set enable bit 0 : Set disable 1 : Set enable Nothing is allocated (The value is undefined at reading) Timer 3, timer 4 count overflow signal selection bit 0 : Timer 1 overflow 1 : Timer 2 overflow Timer 3, timer 4 function selection bit 0 : Normal mode 1 : PWM mode b7 b0 Timer 34 mode register (T34M) (Address 00F916) Timer 3 count stop bit 0 : Count start 1 : Count stop Timer 3 count source selection bits (Note 3) 00 : f(XIN) divided by 16 or f(XCIN) divided by 16 01 : f(XCIN) 10 : Timer 1 overflow or timer 2 overflow 11 : P33/CNTR 1 external clock Timer 4 count stop bit 0 : Count start 1 : Count stop Timer 4 count source selection bits (Note 3) 00 : Timer 3 overflow 01 : f(XIN) divided by 16 or f(XCIN) divided by 16 10 : Timer 1 overflow or timer 2 overflow 11 : P33/CNTR 1 external clock Timer 4 pulse width measuring mode selection bit 0 : Timer mode 1 : Pulse width measuring mode P13/T1 port output selection bit 0 : P13 port output 1 : Timer 4 overflow divided by 2 or PWM output b7 b0 Notes 1 : f(XIN) divided by 16 in the 7477 group. 2 : The 7477 group does not use this bit (bit 2). Set this bit to “0”. 3 : Do not select f(XCIN) as the count source in the 7477 group.

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER SERIAL I/O Serial I/O can be used as either clock synchronous or asynchro- nous (UART) serial I/O. A dedicated timer (baud rate generator) is also provided for baud rate generation. Clock Synchronous Serial I/O Mode Clock synchronous serial I/O mode can be selected by setting the mode selection bit of the serial I/O control register to “1”. For clock synchronous serial I/O, the transmitter and the receiver must use the same clock. If an internal clock is used, transfer is started by a write signal to the transmit or receive buffer.Fig. 8 Clock synchronous serial I/O block diagram Fig. 9 Operation of clock synchronous serial I/O function Transfer shift clock (1/8 to 1/8192 of the internal clock, or an external clock) Serial output TxD Serial input RxD Receive enable signal SRDY Write signal to receive/transmit buffer D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7 D 7 TBE = 0 TBE = 1 TSC = 0 RBF = 1 TSC = 1 Overrun error (OE) detection Notes 1 : The transmit interrupt request (TI) can be selected to occur either when the transmit buffer has emptied (TBE = 1) or after the transmit shift operation has ended (TSC = 1), by setting the transmit interrupt source selection bit (TIC) of the serial I/O control register. 2 : If data is written to the transmit buffer when TSC = 0, the transmit clock is generated continuously and serial data is output continuously from the TxD pin. 3 : The receive interrupt request (RI) is set when the receive buffer full flag (RBF) becomes “1”. Data bus Data bus Receive buffer register Clock control circuit Serial I/O control register Fall detect Serial I/O status register F/F 1/4 1/4 Transmit shift completion flag (TSC) Transmit interrupt request (TI) Transmit buffer empty flag (TBE) Receive buffer full flag (RBF) Receive interrupt request (RI) Serial I/O synchronous clock selection bit (SCS) Frequency dividing ratio 1/(n+1) P16 P14 Shift clock P15P17 Clock control circuit Receive shift register Transmit shift register Transmit buffer register TXD SRDY SCLK R XD f(XIN) SRDY Address 00E016 Address 00E216 Address 00E016 Address 00E116 Address 00E416 CSS TE RE SIOE Baud rate generator TIC Shift clock

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER buffers have the same address in memory. Since the shift register cannot be written to or read from directly, transmit data is written to the transmit buffer, and receive data is read from the receive buffer. The transmit buffer can also hold the next data to be trans- mitted, and the receive buffer can hold a character while the next character is being received. Asynchronous Serial I/O (UART) Mode Clock asynchronous serial I/O mode (UART) can be selected by clearing the serial I/O mode selection bit of the serial I/O control register to “0”. Eight serial data transfer formats can be selected, and the transfer formats used by a transmitter and receiver must be identical. The transmit and receive shift registers each have a buffer, but the two Fig. 10 UART serial I/O block diagram Fig. 11 Operation of UART serial I/O function Receive buffer register Clock control circuit Serial I/O control register Baud rate generator Serial I/O status register Transmit shift completion flag (TSC) Transmit interrupt request (TI) Transmit buffer empty flag (TBE) Receive buffer full flag (RBF) Receive interrupt request (RI) Frequency dividing ratio 1/(n+1) P14 P15P16 Receive shift register Transmit shift register Transmit buffer register TXD SCLK R XD f(XIN) Address 00E016 Address 00E216 Address 00E016 Address 00E116 7-bit UART control register ST/SP/PA generation Serial I/O synchronous clock selection bit OE SP detection8-bit PE FE ST detection Address 00E316 Character length selection bit Data bus Data bus RE TE TIC ST D 0 D 1 SP ST D 0 D 1 SP Transmit or receive clock Transmit buffer write signal Serial output TxD Receive buffer read signal Serial input RxD TBE=0 TSC=0 TBE=0 TBE=1 RBF=0 RBF=1 RBF=1 TSC=1 1 start bit 7 or 8 data bits 1 or 0 parity bit 1 or 2 stop bit(s) ST D 0 D 1 SP ST D 1 SP ]Generated at 2nd bit in 2-stop-bit mode Notes 1 : Error flag detection occurs at the same time that the RBF flag becomes “1” (at 1st stop bit during reception). 2 : The transmit interrupt (TI) can be selected to occur when either the TBE or TSC flag becomes “1,” depending on the setting of the transmit interrupt source selection bit (TIC) of the serial I/O control register. 3 : The receive interrupt (RI) is set when the RBF flag becomes “1”. TBE=1 D 0

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Serial I/O Control Register SIOCON The serial I/O control register consists of eight control bits for the serial I/O function. UART Control Register UARTCON The UART control register consists of four control bits (bits 0 to 3) which are valid when asynchronous serial I/O is selected and set the data format of a data transfer. Serial I/O Status Register SIOSTS The read-only serial I/O status register consists of seven flags (bits 0 to 6) which indicate the operating status of the serial I/O function and various errors. Three of the flags (bits 4 to 6) are valid only in selected UART. The receive buffer full flag (bit 1) is cleared to “0” when the receive buffer is read. If there is an error, it is detected at the same time that data is transferred from the receive shift register to the receive buffer, and the receive buffer full flag is set. Writing to the serial I/O status register clears all the error flags OE, PE, FE, and SE(bit 3 to bit 6, respectively). Writing “0” to the serial I/O enable bit SIOE (bit 7 of the serial I/O control register) also clears all the status flags, in- cluding the error flags. All bits of the serial I/O status register are initialized to “0” at reset, but if the transmit enable bit (bit 4) of the serial I/O control register has been set to “1”, the transmit shift completion flag (bit 2) and the transmit buffer empty flag (bit 0) become “1”. Transmit Buffer/Receive Buffer TB/RB The transmit buffer and the receive buffer are located at the same address. The transmit buffer is write-only and the receive buffer is read-only. If a character bit length is 7 bits, the MSB of data stored in the receive buffer is “0”. Baud Rate Generator BRG The baud rate generator determines the baud rate for serial trans- fer. The baud rate generator divides the frequency of the count source by 1/(n+1), where n is the value written to the baud rate generator.

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Fig. 12 Structure of serial I/O control registers b7 b0 Transmit buffer empty flag (TBE) 0 : Buffer full 1 : Buffer empty Receive buffer full flag (RBF) 0 : Buffer empty 1 : Buffer full Transmit shift completion flag (TSC) 0 : Transmit shift in progress 1 : Transmit shift completed Overrun error flag (OE) 0 : No error 1 : Overrun error Parity error flag (PE) 0 : No error 1 : Parity error Framing error flag (FE) 0 : No error 1 : Framing error Summing error flag (SE) 0 : (OE)U(PE)U(FE)=0 1 : (OE)U(PE)U(FE)=1 Not used (returns “1” when read) Serial I/O status register (SIOSTS: address 00E116) Serial I/O synchronous clock selection bit (SCS) 0 : BRG output divided by 4 (when clock synchronous serial I/O is selected) BRG output divided by 16 (when UART is selected) 1 : External clock input (when clock synchronous serial I/O is selected ) External clock input divided by16 (when UART is selected) b7 b0Serial I/O control register (SIOCON: address 00E216) BRG count source selection bit (CSS) 0 : f(XIN)divided by 4 1 : f(XIN)divided by16 SRDY output enable bit (SRDY) 0 : P17 pin operates as ordinary I/O pin 1 : P17 pin operates as SRDY output pin Transmit interrupt source selection bit (TIC) 0 : Interrupt when transmit buffer has emptied. 1 : Interrupt when transmit shift operation is completed. Transmit enable bit (TE) 0 : Transmit disabled 1 : Transmit enabled Receive enable bit (RE) 0 : Receive disabled 1 : Receive enabled Serial I/O mode selection bit (SIOM) 0 : Asynchronous serial I/O (UART) 1 : Clock synchronous serial I/O Serial I/O enable bit (SIOE) 0 : Serial I/O disabled (pins P14 to P17 operate as ordinary I/O pins) 1 : Serial I/O enabled (pins P14 to P17 operate as serial I/O pins) b7 b0UART control register (UARTCON: address 00E3 16) Character length selection bit (CHAS) 0 : 8 bits 1 : 7 bits Not used (returns “1” when read) Parity enable bit (PARE) 0 : Parity checking disabled 1 : Parity checking enabled Parity selection bit (PARS) 0 : Even parity 1 : Odd parity Stop bit length selection bit (STPS) 0 : 1 stop bit 1 : 2 stop bits

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Fig. 14 Structure of A-D control register A-D control register (Address 00D916) Analog input selection bits 000 : IN0 001 : IN1 010 : IN2 011 : IN3 100 : IN4 101 : IN5 110 : IN6 111 : IN7 b7 b0 Note : Do not select IN4 to IN7 in the 7477 group. (Note) This bit must be set to “0”. Nothing is allocated (The value is undefined at reading) A-D conversion end bit 0 : Under conversion 1 : End conversion

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER The key on wake up interrupt is common with the INT1 interrupt. When EG 5 is set to “1”, the key on wake up function is selected. However, key on wake up cannot be used in the normal operating state. When the microcomputer is in the normal operating state, both key on wake up and INT 1 are invalid. KEY ON WAKE UP “Key on wake up” is one way of returning from a power down state caused by the STP or WIT instruction. If any terminal of port P0 has “L” level applied, after bit 5 of the edge polarity selection reg- ister (EG 5) is set to “1”, an interrupt is generated and the microcomputer is returned to the normal operating state. A key matrix can be connected to port P0 and the microcomputer can be returned to a normal state by pushing any key. Fig. 15 Block diagram of interrupt input and key on wake up circuit P33/CNTR 1 P32/CNTR 0 P30/INT0 P31/INT1 P07 P01 EG 3 Port P33 data read circuit CNTR interrupt request signal Port P32 data read circuit EG 0 Port P30 data read circuit INT0 interrupt request signal Port P31 data read circuit INT1 interrupt request signal CPU halt state signal Port P0 data read circuit EG 1 EG 5 P00 Pull-up control register Direction register Pull-up control register Direction register Pull-up control register Direction register EG 2 Noise eliminating circuit 1/2XCIN (P50) XIN CM 7 ( Select gate: At reset, shaded side is connected.). Note: The 7477 group does not have XCIN input. EG 4 Noise eliminating circuit

7477 group. Bit 6 is not used. are undefined at reset, it is necessary to set initial values. Figure 18. It starts the program from the address formed by using The internal initializations following reset are shown in Figure 17. reset is cleared when timer 4 overflows. Notes 1 : Frequency relation of XIN and f is f(XIN)=2·f.

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER I/O PORTS (1) Port P0 Port P0 is an 8-bit I/O port with CMOS outputs. As shown in Figure 2, P0 can be accessed as memory through zero page address 00C0 16. Port P0’s direction register allows each bit to be programmed individually as input or output. The direction register (zero page address 00C1 16) can be programmed as input with “0”, or as output with “1”. When in the output mode, the data to be output is latched to the port latch and output. When data is read from the output port, the output pin level is not read, only the latched data of the port latch is read. Therefore, a previously output value can be read correctly even though the output voltage level has been shifted up or down. Port pins set as input are in the high impedance state so the signal level can be read. When data is written into the input port, the data is latched only to the output latch and the pin still remains in the high impedance state. Following the execution of STP or WIT instruction, key matrix with port P0 can be used to generate the interrupt to bring the microcom- puter back in its normal state. When this port is selected for input, pull-up transistor can be connected in units of 1-bit. (2) Port P1 Port P1 has the same function as port P0. P1 2 – P17 serve dual functions, and the desired function can be selected by the program. When this port is selected for input, pull-up tran- sistor can be connected in units of 4-bit. (3) Port P2 Port P2 is an 8-bit input port. In the 7477 group, this port is 0 – P23, a 4-bit input port. This port can also be used as the analog voltage input pins. (4) Port P3 Port P3 is a 4-bit input port. (5) Port P4 Port P4 is a 4-bit I/O port and has basically the same func- tions as port P0. In the 7477 group, this port is P4 0 and P41, a 2-bit I/O port. When this port is selected for input, pull-up transistor can be connected in units of 4-bit . (6) Port P5 Port P5 is a 4-bit input port and pull-up transistor can be con- nected in units of 4-bit. P5 0 and P51 are shared with clock generating circuit input/output pins. The 7477 group does not have this port. (7) INT 0 pin (P30/INT0 pin) This is an interrupt input pin, and is shared with port P30. When “H” to “L” or “L” to “H” transition input is applied to this pin, the INT 0 interrupt request bit (bit 0 of address 00FD16) is set to “1”. (8) INT1 pin (P31/INT1 pin) This is an interrupt input pin, and is shared with port P31. When “H” to “L” or “L” to “H” transition input is applied to this pin, the INT 1 interrupt request bit (bit 1 of address 00FD16) is set to “1”. (9) Counter input CNTR0 pin (P32/CNTR 0 pin) This is a timer input pin, and is shared with port P32. When this pin is selected to CNTR0 or CNTR1 interrupt input pin and “H” to “L” or “L” to “H” transition input is applied to this pin, the CNTR 0 or CNTR1 interrupt request bit (bit 2 of ad- dress 00FD16) is set to “1”. (10) Counter input CNTR1 pin (P33/CNTR 1 pin) This is a timer input pin, and is shared with port P33. When this pin is selected to CNTR0 or CNTR1 interrupt input pin and “H” to “L” or “L” to “H” transition input is applied to this pin, the CNTR 0 or CNTR1 interrupt request bit (bit 2 of ad- dress 00FD16) is set to “1”.

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Fig. 19 Block diagram of ports P0, P10–P1 3 Direction register Port latch Interrupt control circuit Tr1 Port P0 Data bus Port P0 Tr2 Port P13 Data bus T34M 7 Data bus Tr3 Port P12 Data bus T12M 3 Port P11 Tr4 Data bus Tr5 Data bus Port P10 Ports P10 – P13 Tr1 to Tr5 are pull-up transistors. Pull-up control register Port latch Pull-up control register Port latch Port latch Port latch Direction register Direction register Direction register Direction register

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Fig. 20 Block diagram of ports P14 – P17 Direction register Port latch Tr6 Port P17 Data bus SIOE SIOM SRDY SRDY Tr7 Port P16 Data bus SIOM SIOE CLK output SCS SIOE Tr8 Port P15 Data bus SIOE TXD TE Tr9 Port P14 Data bus SIOE RE R XD Data bus Tr6 to Tr9 are pull-up transistors. Ports P14 – P17 CLK input Direction register Port latch Direction register Port latch Direction register Port latch Pull-up control register

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Fig. 21 Block diagram of ports P2 – P4 Data bus Multi- plexer Port P2 A-D conversion circuit Port P2 Port P3 INT0, INT1 CNTR 0, CNTR1 Data bus Port P3 Pull-up control register* Direction register Port latch * : Control in units of 4-bit (Control in units of 2-bit for the 7477 group) Tr10 Port P4 Tr10 is pull-up transistor Port P4 Data bus Data bus

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Fig. 22 Block diagram of port P5 Port P5 Pull-up control registerData bus Data bus Tr11 Port P53 Tr12 Port P52 Tr13 Port P51 Data bus CM 4 Data bus CM 4 CM 4 XCIN Tr14 Port P50 CM 4 Data bus Tr11 to Tr14 are pull-up transistors Note : The 7477 group does not have this port.

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Fig. 27 Block diagram of clock generating circuit Fig. 28 Structure of CPU mode register Q R S Q R SQ R SQ R SQ R S XIN XOUT 1/2 1/8 Reset STP instruction Reset Interrupt disable flag I Interrupt request STP instruction WIT instruction Internal clock f XCIN Timer 4Timer 3 T34M 0 T34M 1 T34M 2 XCOUT CM 6 CM 7 CM 7 Note : The 7477 group does not have XCIN input and XCOUT output. Select gate : At reset, shaded side is connected. b7 b0 CPU mode register (Address 00FB 16) These bits must always be set to “0”. Stack page selection bit (Note 1) 0 : In page 0 area 1 : In page 1 area P50, P51/XCIN, XCOUT selection bit (Note 2) 0 : P50, P51 1 : XCIN, XCOUT XCOUT drive capacity selection bit (Note 2) 0 : Low 1 : High Clock (XIN-XOUT ) stop bit (Note 2) 0 : Oscillates 1 : Stops Internal system clock selection bit (Note 2) 0 : XIN-XOUT selected (normal mode) 1 : XCIN-XCOUT selected (low-speed mode) Notes 1 : In the M37477M4, M37478M4, set this bit to “0”. 2 : In the 7477 group, set this bit to “0”.

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Notes 1 : Latency time is automatically generated upon release from the STP instruction due to the connections of timer 3 and 4. 2 : When the system clock is switched over by restarting clock oscillation, a certain wait time required for oscillation to stabilize must be inserted by the program. f(XIN) oscillation f(XCIN) stop f stop Timer operation STP instruction Interrupt (Note 1) CM 4 = 0 CM 5 = 0 CM 6 = 0 CM 7 = 0 Reset WIT instruction Interrupt f(XIN) oscillation f(XCIN) stop P50, P51 input f = f(XIN)/2 f(XIN) stop f(XCIN) stop f stop f(XIN) oscillation f(XCIN) oscillation f stop Timer operation STP instruction Interrupt (Note 1) WIT instruction Interrupt f(XIN) oscillation f(XCIN) oscillation f = f(XIN)/2 f(XIN) stop f(XCIN) stop f stop CM 4 = 0 CM 5 = 1 CM 4 = 1 (Note 2) f(XIN) oscillation f(XCIN) oscillation f stop Timer operation STP instruction Interrupt (Note 1) WIT instruction Interrupt f(XIN) oscillation f(XCIN) oscillation f = f(XCIN)/2 f(XIN) stop f(XCIN) stop f stop CM 7 = 0 (CM 5 = 0) CM 7 = 1 f(XIN) stop f(XCIN) oscillation f stop Timer operation STP instruction Interrupt (Note 1) WIT instruction Interrupt f(XIN) stop f(XCIN) oscillation f = f(XCIN)/2 f(XIN) stop f(XCIN) stop f stop CM 6 = 0 (Note 2) CM 6 = 1 CM 5 = 1 CM 5 = 1 Fig. 29 Transition of states for the system clock.

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER <An example of flow for system> Normal operationOperation on the clock function only Return from clock function Power on reset Clock X oscillation Internal system clock start (X→ 1/2→ φ ) Program start from RESET vector Normal program Operating at f(XIN) Clock for clock function XC oscillation start (CM4 = 1, CM5 = 1) Latency time for oscillation to stabilize (by program) ← Operating at f(XIN) XC clock power down (CM5 : 1→ 0) Internal clock φ source switching X→ XC (CM7 : 0→ 1) Clock X halt (XC in operation) (CM6 = 1) Internal clock halt (WIT instruction) Timer 4 (clock count) overflow Internal clock operation start (WIT instruction released) Clock processing routine ← Operating at f(XCIN) Internal clock halt (WIT instruction) Interrupts from INT0, INT1, CNTR0/CNTR 1, timer 1, timer 2, timer 3, timer 4, serial I/O, key on wake up Internal clock operation start (WIT instruction released) Program start from interrupt vector Clock X oscillation start (CM6 = 0) Latency time for oscillation to stabilize (by program) ← Operating at f(XCIN) Internal clock φ source switching (XC → X) (CM7 : 1→ 0) Normal program → Operating at f(XIN)

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER STP instruction preparation (pushing registers) Timer 3, timer 4 interrupt disable X/16 or XC /16 selected for timer 3 count source; timer 3 overflow selected for timer 4 count source Timer 3, timer 4 start counting Values set to timer 3, timer 4 that do not cause timer 4 to overflow until STP instruction is executed Interrupt for return from STP enabled Timer 4 interrupt request bit cleared Clock X and clock for clock function XC halt (STP instruction) RAM backup status Interrupts from INT0, INT1, CNTR0/CNTR 1, timer 1, timer 2, serial I/O, key on wake up Clock X and clock for clock function XC oscillation start Timer 4 overflow (X/16 or XC /16→ timer 3→ timer 4) Internal system clock start Program start from interrupt vector Normal program RAM backup function Return from RAM backup function ………

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Power source Analog power source Reset input Reset input Clock input Clock output Reference voltage input Select mode I/O port P0 Data I/O D 0–D 7 I/O port P1 Address input A4–A10 Input port P2 Address input A0–A3 Input port P3 Address input A11, A12 Select mode V PP input I/O port P4 Address input A13, A14 Input port P5 VCC ,VSS AV SS (Note 1) RESET XIN XOUT VREF P00 – P07 P10 – P17 P20 – P27 (Note 2) P30 – P33 P40 – P43 (Note 3) P50 – P53 (Note 4) Single-chip /EPROM Single-chip /EPROM Single-chip EPROM Single-chip /EPROM Single-chip /EPROM Single-chip EPROM Single-chip EPROM Single-chip EPROM Single-chip EPROM Single-chip EPROM Single-chip EPROM Single-chip EPROM Input Input Input Output Input Input I/O I/O I/O Input Input Input Input Input I/O Input Input BUILT-IN PROM TYPE MICROCOMPUTERS PIN DESCRIPTION Pin FunctionsMode Name Input/ output Apply voltage of 2.7 to 5.5 V to VCC and 0 V to VSS . Ground level input pin for A-D converter. Same voltage as VSS is applied. To enter the reset state, the reset input pin must be kept at a “L” for 2µs or more (under normal VCC conditions). Connect to VSS . These are I/O pins of internal clock generating circuit for main clock. To control generating frequency, an external ceramic or a quartz crystal oscillator is con- nected between the X IN and XOUT pins. If an external clock is used, the clock source should be connected the XIN pin and the XOUT pin should be left open. Feedback resistor is connected between XIN and XOUT . Reference voltage input pin for the A-D converter. VREF works as CE input. Port P0 is an 8-bit I/O port. The output structure is CMOS output. When this port is selected for input, pull-up transistor can be connected in units of 1-bit and a key on wake up function is provided. Port P0 works as an 8-bit data bus (D 0 to D7). Port P1 is an 8-bit I/O port. The output structure is CMOS output. When this port is selected for input, pull-up transistor can be connected in units of 4-bit. P12 and P1 3 are in common with timer output pins T0, T1. P14, P15, P16 and P17 are in common with serial I/O pins RxD, TxD, SCLK , SRDY , respectively. P11 to P17 works as the 7-bit address input (A4 to A10). P10 must be opened. Port P2 is an 8-bit input port. This port is in common with analog input pins IN0 to IN7. P20 to P23 works as the lower 4-bit address input (A0 to A3). P24 to P27 must be opened. Port P3 is a 4-bit input port. P30 and P31 are in common with external interrupt in- put pins INT0, INT1 and P32, P33 are in common with timer input pins CNTR0, CNTR1. P30, P31 works as the 2-bit address input (A11, A12). P32 works as OE input. Connect to P33 to VPP when programming or verifying. Port P4 is a 4-bit I/O port. The output structure is CMOS output. When this port is selected for input, pull-up transistor can be connected in units of 4-bit. P40 and P41 works as the higher 2-bit address input (A13, A14). P42 and P43 must be opened. Port P5 is a 4-bit input port and pull-up transistor can be connected in units of 4- bit. P50, P51 are in common with input/output pins of clock for clock function XCIN, XCOUT . When P50, P51 are used as XCIN, XCOUT , connect a ceramic or a quartz crystal oscillator between XCIN and XCOUT . If an external clock input is used, con- nect the clock input to the XCIN pin and open the XCOUT pin. Feedback resistor is connected between XCIN and XCOUT pins. Open. Notes 1 : AVSS for M37478M4/M8/E8-XXXFP . 2 :Only P20–P2 3 (IN0–IN3) 4-bit for the 7477 group. 3 :Only P40 and P41 2-bit for the 7477group. 4 :This port is not included in the 7477 group.

Table 2. Pin function in EPROM mode be connected to the XIN pin.

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Fig. 31 Pin connection in EPROM mode Fig. 32 Pin connection in EPROM mode A10 VSS CE D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 A14 A13 VPP A12 A11 VCC OE VSS : Same functions as M5L27C256 16 17 M37477E8-XXXSP/FP P17/SRDY P16/SCLK P15/TXD P14/RXD P13/T1 P12/T0 P11 P10 P23/IN3 P22/IN2 P21/IN1 P20/IN0 VREF XIN XOUT VSS P07 P06 P05 P04 P03 P02 P01 P00 P41 P40 P33/CNTR 1 P32/CNTR 0 P31/INT1 P30/INT0 RESET V CC Oscillation circuit P52 P07/D7 P06/D6 P05/D5 P04/D4 P03/D3 P02/D2 P01/D1 P00/D0 P43 P42 P41/A14 P40/A13 P33/CNTR 1/VPP P32/CNTR 0/OE P31/INT1/A12 P53 P16/SCLK /A9 P15/TXD/A8 P14/RXD/A7 P13/T1/A6 P12/T0/A5 P11/A4 P10 P27/IN7 P26/IN6 P25/IN5 P24/IN4 P23/IN3/A3 P22/IN2/A2 P21/IN1/A1 P30/INT0/A11 P20/IN0/A0 VREF /CE VSS P51/XCOUT P50/XCIN VCC XIN XOUT VSS AV SS NC NC NC NC NC NC P17/SRDY /A10 RESET NC NC NC NCNC NC M37478E8-XXXFP VCC VSS VSS A10 VSS D 7 D 6 D 5 CE D 2 D 3 D 4 D 1 D 0 A13 A14 VPP A12 A11 OE Oscillation circuit : Same functions as M5L27C256

when either the CE or OE pin is in the “H” state. Note : VIL and VIH indicate an “L” and an “H” input voltage, respectively. Table 3. I/O signal in each mode ent window with a seal (provided) when this chip is in use. However, this seal must not contact the lead pins. be taken when turning on the PROM programmer’s power. test according to the flow below before use is recommended.

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER PROGRAMMING NOTES (1) The frequency ratio of the timer is 1/(n+1). (2) The contents of the interrupt request bits are not modified im- mediately after they have been written. After writing to an interrupt request register, execute at least one instruction be- fore executing a BBC or BBS instruction. (3) To calculate in decimal notation, set the decimal mode flag (D) to “1”, then execute an ADC or SBC instruction. Only the ADC and SBC instruction yield proper decimal results. After execut- ing an ADC or SBC instruction, execute at least one instruction before executing a SEC, CLC, or CLD instruction. (4) An NOP instruction must be used after the execution of a PLP instruction. (5) Do not execute the STP instruction during A-D conversion. (6) In the 7477 group, set bit 0, bit 1, and bit 3 – bit 7 to “0” of the CPU mode register. (7) Multiply/Divide instructions The index X mode (T) and the decimal mode (D) flag do not affect the MUL and DIV instruction. The execution of these instructions does not modify the con- tents of the processor status register. DATA REQUIRED FOR MASK ORDERING Please send the following data for mask orders. (1) mask ROM confirmation form (2) mark specification form

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER M37477M4/M8/E8-XXXSP/FP ABSOLUTE MAXIMUM RATINGS Power source voltage Input voltage XIN Input voltage P00 – P07, P10 – P17, P20 – P23, P30 – P33, P40, P41, VREF , RESET Output voltage P00 – P07, P10 – P17, P40, P41, XOUT Power dissipation Operating temperature Storage temperature V CC VI VI VO Pd Topr Tstg V V V V mW –0.3 to 7 –0.3 to V CC +0.3 –0.3 to VCC +0.3 –0.3 to VCC +0.3 1000 (Note) –20 to 85 –40 to 150 Unit Symbol Parameter Ratings Conditions Ta = 25°C All voltages are based on VSS . Output transistors are cut off Note : 500mW for M37477M4/M8/E8-XXXFP RECOMMENDED OPERATING CONDITIONS (VCC = 2.7 to 5.5 V, VSS = 0 V, Ta = –20 to 85°C unless otherwise noted) Power source voltage Power source voltage “H” input voltage P00 – P07, P10 – P17, P30 – P33, RESET, XIN “H” input voltage P20 – P23, P40, P41 “L” input voltage P00 – P07, P10 – P17, P30 – P33 “L” input voltage P20 – P23, P40, P41 “L” input voltage RESET “L” input voltage X IN “H” sum output current P00 – P07, P40, P41 “H” sum output current P10 – P17 “L” sum output current P00 – P07, P40, P41 “L” sum output current P10 – P17 “H” peak output current P00 – P07, P10 – P17, P40, P41 “L” peak output current P00 – P07, P10 – P17, P40, P41 “H” average output current P00 – P07, P10 – P17, P40, P41 (Note 1) “L” average output current P00 – P07, P10 – P17, P40, P41 (Note1) 2.7 4.5 0.8 V CC

0.7 VCC

V V V V V V V V mA mA mA mA mA mA mA mA 4.5 5.5 V CC VCC

0.2 VCC

0.25 VCC

0.12 VCC

0.16 VCC

–30 –30 –10 250 500 2.2VCC –2 Symbol Parameter Limits Min. Typ. Max. Unit f(CNTR ) f(SCLK ) f(XIN) f(XIN) = 4 MHz f(XIN) = 8 MHz f(XIN) = 4 MHz f(XIN) = 8 MHz f(XIN) = 4 MHz f(XIN) = 8 MHz VCC = 2.7 to 4.5 V VCC = 4.5 to 5.5 V MHz kHz MHz MHz VCC VSS VIH VIH VIL VIL VIL VIL IOH(sum) IOH(sum) IOL(sum) IOL(sum) IOH(peak) IOL(peak) IOH(avg) IOL(avg) Timer input frequency CNTR0 (P32), CNTR1 (P33) (Note 2) Use as clock synchronous serial I/O mode Use as UART mode Clock input oscillation frequency (Note 2) Serial I/O clock input frequency S CLK (P16) (Note 2) f(XIN) = 2.2VCC – 2.0 MHz f(XIN) = 8 MHz Notes 1 :The average output current IOH (avg) and IOL (avg) are the average value during a 100ms. 2 :Oscillation frequency is at 50% duty cycle.

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Hysteresis RESET Hysteresis P16/SCLK ”H“ input current P00-P07, P10-P17 P30-P32, P40-P41 “L” input current P33 “L” input current P20 – P23 M37477M4/M8/E8-XXXSP/FP ELECTRICAL CHARACTERISTICS (VCC = 2.7 to 5.5 V, VSS = 0 V , Ta = –20 to 85°C, unless otherwise noted) –1.0 –0.35 3.6 0.5 0.3 0.5 0.3 0.5 0.3 –0.5 –0.18 3.5 1.8 7.5 0.5 0.1 –0.25 –0.08 V CC = 5 V VCC = 3 V VCC = 5 V VCC = 3 V VCC = 5 V VCC = 3 V VCC = 5 V VCC = 3 V VCC = 5 V VCC = 3 V VCC = 5 V VCC = 3 V VCC = 5 V VCC = 3 V VCC = 5 V VCC = 3 V VCC = 5 V VCC = 3 V VCC = 5 V VCC = 3 V VCC = 5 V VCC = 3 V VCC = 5 V VCC = 3 V VCC = 5 V VCC = 3 V Ta = 25°C Ta = 85°C V V V V V µ A mA µ A µ A µ A µ A µ A µ A µ A Max. Limits Symbol Parameter Min. Typ. UnitTest Conditions mA mA mA µ A VV RAM RAM retention voltage Stop all oscillation f(XIN)=8MHz f(XIN)=4MHz f(XIN)=8MHz f(XIN)=4MHz f(XIN)=8MHz f(XIN)=4MHz At normal mode, A-D conversion is not executed. At normal mode, A-D conversion is executed. At wait mode. At stop mode, f(X IN)=0, VCC =5V ICC Power source current VCC = 5 V, IOH = –5 mA VCC = 3 V, IOH = –1.5 mA VCC = 5 V, IOL = 10 mA VCC = 3 V, IOL = 3 mA VCC = 5 V VCC = 3 V VCC = 5 V VCC = 3 V use as SCLK input VI = 0 V, not use pull-up transistor V I = 0 V, use pull-up transistor VI = 0 V VI = 0 V, not use as analog input V I = 0 V (XIN is at stop mode) VI = VCC , not use pull-up transistor VI = VCC VI = VCC , not use as analog input V I = VCC , (XIN is at stop mode) VOH VOL VT+ – VT– VT+ –V T– VT+ –V T– IIL IIL IIL IIL IIH IIH IIH IIH “H” output voltage P00 – P07, P10 – P17, P40, P41 “L” output voltage 0 – P07, P10 – P17, P40, P41 Hysteresis P00 – P07, P30 – P33 “H” input current P00 – P07, P10 – P17, P30 – P32, P40, P41 “H” input current, P33 “H” input current P20 – P23 “H” input current RESET XIN, “L” input current RESET, XIN

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER M37477M4/M8/E8-XXXSP/FP A-D CONVERSION CHARACTERISTICS (VCC = 2.7 to 5.5 V, VSS = 0 V, Ta = –20 to 85°C, unless otherwise noted) Unit Symbol Parameter Test Conditions Limits 12.5 VCC VREF Resolution Absolute accuracy Conversion time Reference input voltage Ladder resistance value Analog input voltage V CC = 2.7 to 5.5 V, f(XIN) = 4 MHz VCC = 4.5 to 5.5 V, f(XIN) = 8 MHz Max.Typ.Min. TCONV VREF R LADDER VIA bits LSB µs V kΩ V

0.5 VCC

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER M37478M4/M8/E8-XXXSP/FP, M37478E8SS ABSOLUTE MAXIMUM RATINGS Power source voltage Input voltage XIN Input voltage P00 – P07, P10 – P17, P20 – P27,_____ P30 – P33, P40 – P43, P50 – P53, VREF , RESET Output voltage P00 – P07, P10 – P17, P40 – P43, XOUT Power dissipation Operating temperature Storage temperature V CC VI VI VO Pd Topr Tstg V V V V mW –0.3 to 7 –0.3 to V CC +0.3 –0.3 to VCC +0.3 –0.3 to VCC +0.3 1000 (Note) –20 to 85 –40 to 150 Unit Symbol Parameter Ratings Conditions Ta = 25°C Note :500mW for M37478M4/M8/E8-XXXFP All voltages are based on VSS . Output transistors are cut off 4.5 5.5 VCC VCC – 30 – 30 – 10 – 5 250 500 2.2VCC –2 f(CNTR ) f(SCLK ) f(XIN) f(XCIN) RECOMMENDED OPERATING CONDITIONS (VCC = 2.7 to 5.5 V, VSS = AVSS = 0 V, Ta = –20 to 85°C unless otherwise noted) 2.7 4.5

0.8 VCC

V V V V V V V V V mA mA mA mA mA mA mA mA Symbol Parameter Limits Min. Typ. Max. Unit f(XIN) = 4 MHz f(XIN) = 8 MHz f(XIN) = 4 MHz f(XIN) = 8 MHz f(XIN) = 4 MHz f(XIN) = 8 MHz VCC = 2.7 to 4.5 V VCC = 4.5 to 5.5 V MHz kHz MHz MHz kHz VCC VSS AV SS VIH VIH VIL VIL VIL VIL IOH(sum) IOH(sum) IOL(sum) IOL(sum) IOH(peak) IOL(peak) IOH(avg) IOL(avg) Timer input frequency CNTR0 (P32), CNTR1 (P33) (Note 3) Use as clock synchronous serial I/O mode Use as UART mode Main clock input oscillation frequency (Note 3) Serial I/O clock input frequency S CLK (P16) (Note 2) f(XIN) = 2.2VCC – 2.0 MHz f(XIN) = 8 MHz Sub-clock input oscillation frequency for clock function (Note 3,4) Notes 1 :It is except to use P50 as XCIN. 2 :The average output current IOH (avg) and IOL (avg) are the average value during a 100ms. 3 :Oscillation frequency is at 50% duty cycle. 4 :When used in the low-speed mode, the clock oscillation frequency for clock function should be f(XCIN) < f(XIN) / 3. Power source voltage Power source voltage Analog power source voltage “H” input voltage P0 0 – P07, P10 – P17 , P30 – P33, RESET , XIN “H” input voltage P20 – P27, P40 – P43, P50 – P53 (Note 1) “L” input voltage P00 – P07, P10 – P17, P30 – P33 “L” input voltage P20 – P27, P40 – P43, P50–P5 3 (Note 1) “L” input voltage RESET “L” input voltage X IN “H” sum output current P00 – P07, P40 – P43 “H” sum output current P10 – P17 “L” sum output current P00 – P07, P40 – P43 “L” sum output current P10 – P17 “H” peak output current P00 – P07, P10 – P17, P40 – P43 “L” peak output current P00 – P07, P10 – P17, P40 – P43 “H” average output current P00 – P07, P10 – P17, P40 – P43 (Note 2) “L” average output current P00 – P07, P10 – P17, P40 – P43 (Note 2)

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER f(XIN)=8MHz f(XIN)=4MHz f(XIN)=8MHz f(XIN)=4MHz f(XIN)=8MHz f(XIN)=4MHz M37478M4/M8/E8-XXXSP/FP, M37478E8SS ELECTRICAL CHARACTERISTICS (VCC = 2.7 to 5.5 V, VSS = AVSS = 0 V, Ta = –20 to 85°C, unless otherwise noted) –1.0 –0.35 3.6 0.5 0.3 0.5 0.3 0.5 0.3 –0.5 –0.18 3.5 1.8 7.5 0.5 0.1 V CC = 5 V , IOH = –5 mA VCC = 3 V , IOH = –1.5 mA VCC = 5 V , IOL = 10 mA VCC = 3 V , IOL = 3 mA VCC = 5 V VCC = 3 V VCC = 5 V VCC = 3 V used as SCLK input VI = 0 V, not use pull-up transistor V I = 0 V, use pull-up transistor VI = 0 V VI = 0 V, not use as analog input V I = 0 V (XIN is at stop mode) VI = VCC , not use pull-up transistor VI = VCC VI = VCC , not use as analog input V I = VCC , (XIN is at stop mode) Max. Limits Symbol Parameter Min. Typ. UnitTest Conditions At normal mode, A-D conversion is not executed. –0.25 –0.08 V V V V V µ A mA µ A µ A µ A µ A µ A µ A µ A V OH VOL VT+ – VT– VT+ –V T– VT+ –V T– IIL IIL IIL IIL IIH IIH IIH IIH VCC = 5 V VCC = 3 V VCC = 5 V VCC = 3 V VCC = 5 V VCC = 3 V VCC = 5 V VCC = 3 V VCC = 5 V VCC = 3 V VCC = 5 V VCC = 3 V VCC = 5 V VCC = 3 V VCC = 5 V VCC = 3 V VCC = 5 V VCC = 3 V VCC = 5 V VCC = 3 V VCC = 5 V VCC = 3 V VCC = 5 V VCC = 3 V VCC = 5 V VCC = 3 V VCC = 5 V VCC = 3 V VCC = 5 V VCC = 3 V Ta = 25°C Ta = 85°C Stop all oscillationVRAM RAM retention voltage At stop mode, f(XIN)=0, f(XCIN)=0, VCC =5V At wait mode. At normal mode, A-D conversion is executed. I CC Power source current At wait mode, Ta=25°C, f(XIN)=0, f(XCIN)=32kHz, low- power mode At low-speed mode, Ta=25°C, f(XIN)=0, f(XCIN)=32kHz, low-power mode, A-D conversion is not executed. “H” output voltage P00 – P07, P10 – P17, P40 – P43 “L” output voltage 0 – P07, P10 – P17, P40 – P43 Hysteresis P00 – P07, P30 – P33 Hysteresis RESET Hysteresis P16/SCLK “L” input current 0 – P07, P10 – P17, P30 – P32, P40 – P43, P50 – P53 “L” input current P33 “L” input current P20 – P27 “L” input current RESET, XIN “H” input current P00 – P07, P10 – P17, P30 – P32, P40 – P43, P50 – P53 “H” input current P33 “H” input current P20 – P27 “H” input current RESET, XIN mA mA µ A mA µ A µ A V

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Unit Symbol Parameter Test Conditions Limits 12.5 VCC VREF Resolution Absolute accuracy Conversion time Reference input voltage Ladder resistance value Analog input voltage V CC = 2.7 to 5.5 V, f(XIN) = 4 MHz VCC = 4.5 to 5.5 V, f(XIN) = 8 MHz Max.Typ.Min. TCONV VREF R LADDER VIA bits LSB µs V kΩ V M37478M4/M8/E8-XXXSP/FP, M37478E8SS A-D CONVERTER CHARACTERISTICS (VCC = 2.7 to 5.5 V, VSS = AVSS = 0 V, Ta = –20 to 85°C, unless otherwise noted)

© 1997 MITSUBISHI ELECTRIC CORP. New publication, effective Dec. 1997. Specifications subject to change without notice. Notes regarding these materials

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• Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non-flammable material or (iii) prevention against any malfunction or mishap. MITSUBISHI MICROCOMPUTERS 7477/7478 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

Rev. Rev. No. date

1.0 First Edition 971226

REVISION DESCRIPTION LIST 7477/7478 GROUP DATA SHEET (1/1) Revision Description