M37471E8SS

M37470M2 MITSUBISHI | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 46

Technical content

DESCRIPTION

The 7470/7471 group is a single-chip microcomputer designed with CMOS silicon gate technology. It is housed in a 32-pin shrink plastic molded DIP. The M37471M2-XXXSP/FP is a single-chip mi- crocomputer designed with CMOS silicon gate technology. It is housed in a 42-pin shrink plastic molded DIP or a 56-pin plastic molded QFP. These single-chip microcomputer are useful for business equip- ment and other consumer applications. In addition to its simple instruction set, the ROM, RAM, and I/O addresses are placed on the same memory map to enable easy programming . The differences between the M37471M2-XXXSP and the M37471M2-XXXFP are the package outline and the power dissi- pation ability (absolute maximum ratings). The differences among M37470M2-XXXSP, M37470M4-XXXSP , M37470M8-XXXSP , M37471M2-XXXSP/FP , M37471M4-XXXSP/ FP and M37471M8-XXXSP/FP are noted below. APPLICATION Audio-visual equipment, VCR, Tuner, Office automation equipment 7470/7471 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS Type name M37470M2-XXXSP M37471M2-XXXSP/FP M37470M4-XXXSP M37471M4-XXXSP/FP M37470M8-XXXSP M37471M8-XXXSP/FP I/O ports ROM size 4096 bytes 8192 bytes 16384 bytes RAM size 128 bytes 192 bytes 384 bytes

FEATURES

l The minimum instruction execution time l Power source voltage CC –2.0 MHz oscillation frequency) l Power dissipation in normal mode l Programmable I/O ports 28(7471 group) 8-bit, 8channels (7471 group) PIN CONFIGURATION (TOP VIEW)

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS PIN CONFIGURATION (TOP VIEW) P13/T1 P12/T0 M37471M2-XXXSP M37471M4-XXXSP M37471E4-XXXSP M37471M8-XXXSP M37471E8-XXXSP M37471E8SS P53 P16/CLK P15/SOUT P14/SIN P11 P10 P27/IN7 P26/IN6 P25/IN5 P24/IN4 P23/IN3 P22/IN2 P21/IN1 P20/IN0 VREF XIN XOUT VSS P17/SRDY P52 P07 P06 P05 P04 P03 P02 P01 P00 P43 P42 P41 P40 P33/CNTR 1 P32/CNTR 0 P31/INT1 P30/INT0 P51/XCOUT P50/XIN VCC RESET Outline 42P4B 42S1B-A (Window) P06 P15/SOUT P21/IN1 P52 P07 P05 P53 P16/CLK VSS NC NC NC P17/SRDY P04 P03 P02 P01 P00 P43 P42 P41 P40 P33/CNTR 1 P32/CNTR 0 P31/INT1 P30/INT0 NC NC NC P14/SIN P13/ P11 P10 P27/IN7 P26/IN6 P25/IN5 P24/IN4 P23/IN3 P22/IN2 P20/IN0 VREF NC NC M37471M2-XXXFP M37471M4-XXXFP M37471E4-XXXFP M37471M8-XXXFP M37471E8-XXXFP Outline 56P6N-A P51/XCOUT VCC XIN XOUT VSS AV SS NC NC NC RESET NC P50/XCIN P12/T0 Note : The differences between 42P4B package type of 7471 group and 56P6N-A package type of 7471 group are package outline, power dissipation ability (absolute maximum ratings), and the provision of an AVSS pin by the 56P6N-A package type. NC : No connection

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS M37470M2-XXXSP BLOCK DIAGRAM 14 15 18 17 16 VCC 1324 23 22 21 20 19 9 10 11 12 1 2 3 4 5 6 7 8 32 31 30 29 28 27 26 25 CNTR 0CNTR 1 INT1 INT0 VSS P2(4) Clock generating circuit Clock input XIN Clock output XOUT Reset input RESET ROM 4096 bytes S I/O(8) PWM control A-D converter Program counter PC H (8) Program counter PC L(8) RAM 128 bytes Stack pointer S(8) Processor status register PS (8) 8-bit Arithmetic and logical unit Index register Y(8) Index register X(8) Accumu- lator A(8) Instruction register (8) Instruction decoder Control signal Timer 1 (8) Timer 2 (8) Timer 3 (8) Timer 4 (8) I/O port P4 Input port P3 VREF Reference voltage input I/O port P2 I/O port P1 I/O port P0 (Note 1)(Note 2) Data bus Notes 1 : 8192 bytes for M37470M4/E4-XXXSP, and 16384 bytes for M37470M8/E8-XXXSP 2 : 192 bytes for M37470M4/E4-XXXSP, and 384 bytes for M37470M8/E8-XXXSP Byte counter (4)

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS M37471M2-XXXSP BLOCK DIAGRAM 181 42 24 23 33 32 31 30 29 28 27 26 10 11 12 13 14 15 16 17 2 3 4 5 6 7 8 9 41 40 39 38 37 36 35 34 CNTR 0CNTR 1XCIN XCOUT INT1 INT0 P2(8) 19 20 XCIN Sub-clock input XCOUT Sub-clock output 25 22 VCC VSS Clock generating circuit Main clock input XIN Main clock output XOUT Reset input RESET ROM 4096 bytes S I/O(8) PWM control A-D converter Program counter PC H (8) Program counter PC L(8) RAM 128 bytes Stack pointer S(8) Processor status register PS (8) 8-bit Arithmetic and logical unit Index register Y(8) Index register X(8) Accumu- lator A(8) Instruction register (8) Instruction decoder Control signal Timer 1 (8) Timer 2 (8) Timer 3 (8) Timer 4 (8) I/O port P4 Input port P3 VREF Reference voltage input I/O port P2 I/O port P1 I/O port P0 (Note 1)(Note 2) Notes 1 : 8192 bytes for M37471M4/E4-XXXSP, and 16384 bytes for M37471M8/E8-XXXSP, M37471E8SS 2 : 192 bytes for M37471M4/E4-XXXSP, and 384 bytes for M37471M8/E8-XXXSP, M37471E8SS Input port P5 Data bus Byte counter (4)

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS M37471M2-XXXFP BLOCK DIAGRAM 18 19 28 23 22 VCC 1552 49 26 25 38 37 36 35 33 32 31 30 7 8 9 10 11 12 13 14 53 54 55 2 3 4 5 6 48 47 46 43 42 41 40 39 CNTR 0CNTR 1XCIN XCOUT INT1 INT0 51 21 VSS AV SS P2(8) Clock generating circuit Reset input RESET ROM 4096 bytes S I/O(8) PWM control A-D converter Program counter PC H (8) Program counter PC L(8) RAM 128 bytes Stack pointer S(8) Processor status register PS (8) Index register Y(8) Index register X(8) Accumu- lator A(8) Instruction register (8) Instruction decoder Control signal Timer 1 (8) Timer 2 (8) Timer 3 (8) Timer 4 (8) I/O port P4 Input port P3 VREF Reference voltage input I/O port P2 I/O port P1 I/O port P0 (Note 1)(Note 2) Notes 1 : 8192 bytes for M37471M4/E4-XXXFP, and 16384 bytes for M37471M8/E8-XXXFP 2 : 192 bytes for M37471M4/E4-XXXFP, and 384 bytes for M37471M8/E8-XXXFP Input port P5 Data bus XCIN Sub-clock input XCOUT Sub-clock output Main clock input XIN Main clock output XOUT Byte counter (4) 8-bit Arithmetic and logical unit

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS FUNCTIONS OF 7470/7471 GROUP Basic machine-language instructions Instruction execution time Clock input oscillation frequency Memory size Input/Output port Serial I/O Timers A-D converter Subroutine nesting Interrupt Clock generating circuit Power source voltage Power dissipation Input/Output characters Operating temperature range Device structure Package Input/Output voltage Output current M37470M2/M4/M8/E4/E8-XXXSP M37471M2/M4/M8/E4/E8-XXXSP M37471M2/M4/M8/E4/E8-XXXFP M37471E8SS Functions 0.5 µ s (the minimum instructions, at 8 MHz oscillation frequency) 8 MHz (max.) 4096 bytes 128 bytes 8192 bytes 192 bytes 16384 bytes 384 bytes 8-bit 5 2 8-bit 5 1 (4-bit 5 1 for 7470 group) 4-bit 5 2 (Port P5 is not included in 7470 group) 4-bit 5 1 (2-bit 5 1 for 7470 group) 8-bit 5 1 8-bit timer 5 4 8-bit 5 1 (8 channels) (8-bit 5 1 (4 channels) for M37470M2/M4/M8) 64 level max. (M37470M2, M37471M2) 96 level max. (M37470M4/E4, M37471M4/E4) 192 level max. (M37470M8/E8, M37471M8/E8) 5 external interrupts, 6 internal interrupts, 1 software interrupt Built-in circuit with internal feedback resistor (a ceramic or a quartz- crystal oscillator) 2.7 to 4.5 V (at 2.2VCC –2.0 MHz oscillation frequency), 4.5 to 5.5 V (at 8 MHz oscillation frequency) 35 mW (at 8 MHz oscillation frequency) 5 V –5 to 10 mA (P0, P1, P2, P4 : CMOS tri-states) –20 to 85°C CMOS silicon gate 32-pin shrink plastic molded DIP 42-pin shrink plastic molded DIP 56-pin plastic molded QFP 42-pin ceramic DIP ROM RAM ROM RAM ROM RAM I/O I/O Input I/O Parameter M37470M2 M37471M2 M37470M4/E4 M37471M4/E4 M37470M8/E8 M37471M8/E8 P0, P1 P3, P5

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS Input/ Output PIN DESCRIPTION Pin Name Functions Power source voltage Analog power source Reset input Clock input Clock output Reference voltage input I/O port P0 I/O port P1 I/O port P2 Input port P3 I/O port P4 Input port P5 Input Input Output Input I/O I/O I/O Input I/O Input Notes 1 : AV SS for M37471M2/M4/M8/E4/E8-XXXFP. 2 : Only P20–P23 (IN0–IN3) 4-bit for 7470 group. 3 : Only P40 and P41 2-bit for 7470 group. 4 : This port is not included in 7470 group. Apply voltage of 2.7 to 5.5 V to VCC , and 0 V to VSS . Ground level input pin for A-D converter. Same voltage as VSS is applied. To enter the reset state, the reset input pin must be kept at “L” for 2 µ s or more (under normal VCC conditions). These are I/O pins of internal clock generating circuit for main clock. To control generating frequency, an external ceramic or a quartz-crystal oscillator is connected between the X IN and XOUT pins. If an external clock is used, the clock source should be connected the XIN pin and the XOUT pin should be left open. Feedback resistor is connected between XIN and XOUT . Reference voltage input pin for the A-D converter. Port P0 is an 8-bit I/O port. The output structure is CMOS output. When this port is selected for input, pull-up transistor can be connected in units of 1-bit and a key on wake up function is provided. Port P1 is an 8-bit I/O port. The output structure is CMOS output. When this port is selected for input, pull-up transistor can be connected in units of 4-bit. P1 2, P13 are in common with timer output pins T0, T1, P14, P15, P16, P17 are in common with serial I/O pins SIN, SOUT , CLK, SRDY , respec- tively. The output structure of SOUT and SRDY can be changed to N-channel open drain output. Port P2 is an 8-bit I/O port. The output structure is CMOS output. When this port is selected for input, pull-up transistor can be connected in units of 4-bit. This port is in common with analog input pins IN 0–IN7. Port P3 is a 4-bit input port. P30, P31 are in common with external interrupt input pins INT0, INT1, and P32, P33 are in common with timer input pins CNTR 0, CNTR1. Port P4 is a 4-bit I/O port. The output structure is CMOS output. When this port is selected for input, pull-up transistor can be connected in units of 4-bit. Port P5 is a 4-bit input port and pull-up transistor can be connected in units of 4-bit. P50, P51 are in common with input/output pins of clock for clock function XCIN, XCOUT . When P50, P51 are used as XCIN, XCOUT , connect a ceramic or a quartz-crystal oscillator between XCIN and XCOUT . If an external clock input is used, connect the clock input to the XCIN pin and open the XCOUT pin. Feedback resistor is connected between XCIN and XCOUT pins. VCC , VSS AV SS (Note 1) RESET XIN XOUT VREF P00–P0 7 P10–P1 7 P20–P2 7 (Note 2) P30–P3 3 P40–P4 3 (Note 3) P50–P5 3 (Note 4)

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS FUNCTIONAL DESCRIPTION Central Processing Unit (CPU) The 7470/7471 group uses the standard 740 family instruction set. Refer to the table of 740 family addressing modes and machine in- structions or the SERIES 740 <Software> User’s Manual for details on the instruction set. Machine-resident 740 family instructions are as follows: The FST and SLW instruction cannot be used. The MUL, DIV, WIT, and STP instruction can be used. CPU Mode Register The CPU mode register is allocated at address 00FB16. This register contains the stack page selection bit. Fig. 1 Structure of CPU mode register These bits must always be set to “0”. P50, P51/XCIN, XCOUT selection bit (Note 2) 0 : P50, P51 1 : XCIN, XCOUT XCOUT drive capacity selection bit (Note 2) 0 : Low 1 : High Clock (XIN-XOUT ) stop bit (Note 2) 0 : Oscillates 1 : Stops Internal system clock selection bit (Note 2) 0 : X IN-XOUT selected (normal mode) 1 : XCIN-XCOUT selected (low-speed mode) CPU mode register (Address 00FB16) b7 b0 Stack page selection bit (Note 1) 0 : In page 0 area 1 : In page 1 area 1 : In the M37470M2, M37470M4/E4, M37471M2, M37471M4/E4, set this bit to “0”. 2 : In the 7470 group, set this bit to “0”. Notes

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS MEMORY

• Special Function Register (SFR) Area The special function register (SFR) area contains the registers relating to functions such as I/O ports and timers.
• RAM RAM is used for data storage as well as a stack area.
• ROM ROM is used for storing user programs as well as the interrupt vector area.
• Interrupt Vector Area The interrupt vector area is for storing jump destination ad- dresses used at reset or when an interrupt is generated.
• Zero Page Zero page addressing mode is useful because it enables access to this area with fewer instruction cycles.
• Special Page Special page addressing mode is useful because it enables ac- cess to this area with fewer instruction cycles. Fig. 2 Memory map RAM (192 bytes) for M37470M8/E8 M37471M8/E8 SFR area Not used Interrupt vector area 000016 Zero page Special page RAM (128 bytes) for M37470M2 M37471M2 ROM (16K bytes) for M37470M8/E8 M37471M8/E8 ROM (8K bytes) for M37470M4/E8 M37471M4/E8 ROM (4K bytes) for M37470M2 M37471M2 RAM (192 bytes) for M37470M4/E4 M37470M8/E8 M37471M4/E4 M37471M8/E8 Not used 007F16 00BF 16 00FF16 010016 01BF 16 C000 16 E00016 F00016 FF0016 FFEA 16 FFFF 16

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS Fig. 3 SFR (Special Function Register) memory map 00C0 16 00C1 16 00C2 16 00C3 16 00C4 16 00C5 16 00C6 16 00C7 16 00C8 16 00C9 16 00CA 16 00CB 16 00CC 16 00CD 16 00CE 16 00CF 16 00D0 16 00D1 16 00D2 16 00D3 16 00D4 16 00D5 16 00D6 16 00D7 16 00D8 16 00D9 16 00DA 16 00DB 16 00DC 16 00DD 16 00DE 16 00DF 16 00E016 00E116 00E216 00E316 00E416 00E516 00E616 00E716 00E816 00E916 00EA 16 00EB 16 00EC 16 00ED 16 00EE 16 00EF 16 00F016 00F116 00F216 00F316 00F416 00F516 00F616 00F716 00F816 00F916 00FA 16 00FB 16 00FC 16 00FD 16 00FE 16 00FF16 Port P0 Port P0 direction register Port P1 Port P1 direction register Port P2 Port P2 direction register Port P3 Port P4 Port P4 direction register Port P5 (Note 1) Edge polarity selection register Input latch register A-D control register A-D conversion register P0 pull-up control register P1–P5 pull-up control register (Note 2) Timer 1 Timer 2 Timer 3 Timer 4 Timer FF register Timer 12 mode register Timer 34 mode register Timer mode register 2 CPU mode register Interrupt request register 1 Interrupt request register 2 Interrupt control register 1 Interrupt control register 2 Notes 1 : This address is not used in the 7470 group. 2 : This address is allocated P1–P4 pull-up control register for the 7470 group. Serial I/O mode register Serial I/O register Serial I/O counter Byte counter

external, six internal, and one software sources. Interrupts are vectored interrupts with priorities shown in Table 1. set to the register, the interrupt is activated on the rising edge. 1 interrupt request is generated. CNTR 1 pin by setting bit 4 in the edge polarity selection register. can be set and reset with a program. ority. Figure 5 shows interrupts control. Table 1. Interrupt vector address and priority

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS Fig. 5 Interrupt control Fig. 4 Structure of registers related to interrupt b7 b0 Edge polarity selection register (EG) (Address 00D416) INT0 edge selection bit INT1 edge selection bit CNTR 0 edge selection bit CNTR 1 edge selection bit 0 : Falling edge 1 : Rising edge CNTR 0/CNTR 1 interrupt selection bit 0 : CNTR0 1 : CNTR1 INT1 source selection bit (at power-down state) 0 : P31/INT1 1 : P00–P07 “L” level (for key-on wake-up) Nothing is allocated (The value is undefined at reading) b7 b0 Interrupt request register 1 (Address 00FC16) Timer 1 interrupt request bit Timer 2 interrupt request bit Timer 3 interrupt request bit Timer 4 interrupt request bit Nothing is allocated (The value is undefined at reading) Serial I/O transmit interrupt request bit A-D conversion completion interrupt request bit b7 b0 Interrupt control register 1 (Address 00FE16) Timer 1 interrupt enable bit Timer 2 interrupt enable bit Timer 3 interrupt enable bit Timer 4 interrupt enable bit Nothing is allocated (The value is undefined at reading) Serial I/O receive interrupt enable bit A-D conversion completion interrupt enable bit b7 b0 Interrupt request register 2 (Address 00FD16) INT0 interrupt request bit INT1 interrupt request bit Nothing is allocated (The value is undefined at reading) CNTR 0 or CNTR1 interrupt request bit 0 : No interrupt request 1 : Interrupt requested b7 b0 Interrupt control register 2 (Address 00FF16) INT0 interrupt enable bit INT1 interrupt enable bit Nothing is allocated (The value is undefined at reading) CNTR 0 or CNTR1 interrupt enable bit 0 : Interrupt disable 1 : Interrupt enabled Interrupt request bit Interrupt enable bit Interrupt disable flag I BRK instruction Reset Interrupt request

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS TIMER The 7470/7471 group has four timers; timer 1, timer 2, timer 3, and timer 4. A block diagram of timer 1 through 4 is shown in Figure 6. Timer 1 can be operated in the timer mode, event count mode, or pulse output mode. Timer 1 starts counting when bit 0 in the timer 12 mode register (address 00F8 16) is set to “0”. The count source can be selected from the f(XIN) divided by 16, f(XCIN) divided by 16, f(XCIN), or event input from P32/CNTR 0 pin. Do not select f(XCIN) as the count source in the 7470 group. When bit 1 and bit 2 in the timer 12 mode register are “0”, f(XIN) divided by 16 or f(XCIN) divided by 16 is selected. Selection between f(XIN) and f(XCIN) is done by bit 7 in the CPU mode register (address 00FB 16). When bit 1 in the timer 12 mode register is “0” and bit 2 is “1”, f(XCIN) is selected. And, when bit 1 in the timer 12 mode register is “1”, an event input from the CNTR0 pin is selected. Event inputs are selected depending on bit 2 in the edge polarity selection register (address 00D4 16). When this bit is “0”, the in- verted value of CNTR0 input is selected; when the bit is “1”, CNTR 0 input is selected. When bit 3 in the timer 12 mode register is set to “1”, the P12 pin becomes timer output T0. When the direction register of P12 is set for the output mode at this time, the timer 1 overflow divided by 2 is output from T Please set the initial output value in the following procedure. À Set “1” to bit 0 of the timer 12 mode register. (Timer 1 count stop.) \ Set “1” to bit 0 of the timer mode register 2. ´ Set the output value to bit 0 of the timer FF register. ˆ Set the count value to the timer 1. ˜ Set “0” to bit 0 of the timer 12 mode register. (Timer 1 count start.) Timer 2 can only be operated in the timer mode. Timer 2 starts counting when bit 4 in the timer 12 mode register is set to “0”. The count source can be selected from the divide by 16, divide by 64, divide by 128, or divide by 256 frequency of f(X IN) or f(XCIN), and timer 1 overflow. Do not select f(XCIN) as the count source in the 7470 group. When bit 5 in the timer 12 mode register is “0”, any of the divide by 16, divide by 64, divide by 128, or divide by 256 frequency of f(X IN) or (XCIN) is selected. The divide ratio is se- lected according to bit 6 and bit 7 in the timer 12 mode register, and selection between f(X IN) and f(XCIN) is made according to bit 7 in the CPU mode register. When bit 5 in the timer 12 mode reg- ister is “1”, timer 1 overflow is selected as the count source. Timer 3 can be operated in the timer mode, event count mode, or PWM mode. Timer 3 starts counting when bit 0 in the timer 34 mode register (address 00F9 16) is set to “0”. The count source can be selected from the f(XIN) divided by 16, f(XCIN) divided by 16, f(XCIN), timer 1 or timer 2 overflow, or an event input from P33/CNTR 1 pin according to the statuses of bit 1 and bit 2 in the timer 34 mode register, bit 6 in the timer mode reg- ister 2 (address 00FA 16) and bit 7 in the CPU mode register. Do not select f(XCIN) as the count source in the 7470 group. Note, however, that if timer 1 overflow or timer 2 overflow is selected for the count source of timer 3 when timer 1 overflow is selected for the count source of timer 2, timer 1 overflow is always selected re- gardless of the status of bit 6 in the timer mode register 2. Event inputs are selected depending on bit 3 in the edge polarity selec- tion register. When this bit is “0”, the inverted value of CNTR 1 input is selected; when the bit is “1”, CNTR1 input is selected. Timer 4 can be operated in the timer mode, event count mode, pulse output mode, pulse width measuring mode, or PWM mode. Timer 4 starts counting when bit 3 in the timer 34 mode register is set to “0” when bit 6 in this register is “0”. When bit 6 is “1”, the pulse width measuring mode is selected. The count source can be selected from timer 3 overflow, f(X IN) divided by 16, f(XCIN) divided by 16, f(XCIN), timer 1 or timer 2 overflow, or an event input from P33/CNTR 1 pin according to the statuses of bit 4 and bit 5 in the timer 34 mode register, bit 6 in the timer mode register 2, and bit 7 in the CPU mode register. Do not select f(X CIN ) as the count source in the 7470 group. Note, however, that if timer 1 overflow or timer 2 overflow is selected for the count source of timer 4 when timer 1 overflow is selected for the count source of timer 2, timer 1 overflow is always selected regardless of the status of bit 6 in the timer mode register 2. Event inputs are selected depending on bit 3 in the edge polarity selection register. When this bit is “0”, the inverted value of CNTR 1 input is selected; when the bit is “1”, CNTR1 input is selected. When bit 7 in the timer 34 mode register is set to “1”, the P13 pin becomes timer output T1. When the direction register of P13 is set for the output mode at this time, the timer 4 overflow divided by 2 is output from T 1 when bit 7 in the timer mode register 2 is “0”. Please set the initial output value in the following procedure. À Set “1” to bit 3 of the timer 34 mode register. (Timer 4 count stop.) \ Set “1” to bit 1 of the timer mode register 2. ´ Set the output value to bit 1 of the timer FF register. ˆ Set the count value to the timer 4. ˜ Set “0” to bit 3 of the timer 34 mode register. (Timer 4 count start.) (1) Timer mode Timer performs down count operations with the dividing ratio being 1/(n+1). Writing a value to the timer latch sets a value to the timer. When the value to be set to the timer latch is nn 16, the value to be set to a timer is nn16, which is down counted at the falling edge of the count source from nn16 to (nn16-1) to (nn16-2) to ...0116 to 0016 to FF16. At the falling edge of the count source immediately after timer value has reached FF16, value (nn16-1) obtained by subtracting one from the timer latch value is set (reloaded) to the timer to continue counting. At the rising edge of the count source immediately after the timer value has reached FF 16, an overflow occurs and an interrupt request is generated.

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS (2) Event count mode Timer operates in the same way as in the timer mode except that it counts input from the CNTR 0 or CNTR1 pin. (3) Pulse output mode In this mode, duty 50% pulses are output from the T 0 or T1 pin. When the timer overflows, the polarity of the T0 or T1 pin output level is inverted. (4) Pulse width measuring mode The 7470/7471 group can measure the “H” or “L” width of the CNTR 0 or CNTR1 input waveform by using the pulse width mea- suring mode of timer 4. The pulse width measuring mode is selected by writing “1” to bit 6 in the timer 34 mode register. In the pulse width measuring mode, the timer counts the count source while the CNTR 0 or CNTR1 input is “H” or “L”. Whether the CNTR0 input or CNTR1 input to be measured can be specified by the sta- tus of bit 4 in the edge polarity selection register; whether the “H” width or “L” width to be measured can be specified by the status of bit 2 (CNTR 0) and bit 3 (CNTR1) in the edge polarity selection reg- ister. (5) PWM mode The PWM mode can be entered for timer 3 and timer 4 by setting bit 7 in the timer mode register 2 to “1”. In the PWM mode, the P1 pin is set for timer output T1 to output PWM waveforms by setting bit 7 in the timer 34 mode register to “1”. The direction register of 3 must be set for the output mode before this can be done. In the PWM mode, timer 3 is counting and timer 4 is idle while the PWM waveform is “L”. When timer 3 overflows, the PWM waveform goes “H”. At this time, timer 3 stops counting simultaneously and timer 4 starts counting. When timer 4 overflows, the PWM wave- form goes “L”, and timer 4 stops and timer 3 starts counting again. Consequently, the “L” duration of the PWM waveform is deter- mined by the value of timer 3; the “H” duration of the PWM waveform is determined by the value of timer 4. When a value is written to the timer in operation during the PWM mode, the value is only written to the timer latch, and not written to the timer. In this case, if the timer overflows, a value one less the value in the timer latch is written to the timer. When any value is written to an idle timer, the value is written to both the timer latch and the timer. In this mode, do not select timer 3 overflow as the count source for timer 4. INPUT LATCH FUNCTION The 7470/7471 group can latch the P30/INT0, P31/INT1, P32/ CNTR 0, and P33/CNTR 1 pin level into the input latch register (ad- dress 00D616) when timer 4 overflows. The polarity of each pin latched to the input latch register can be selected by using the edge polarity selection register. When bit 0 in the edge polarity se- lection register is “0”, the inverted value of the P3 0/INT0 pin level is latched; when the bit is “1”, the P30/INT0 pin level is latched as it is. When bit 1 in the edge polarity selection register is “0”, the in- verted value of the P3 1/INT1 pin level is latched; when the bit is “1”, the P31/INT1 pin level is latched as it is. When bit 2 in the edge polarity selection register is “0”, the inverted value of the P32/ CNTR 0 pin level is latched; when the bit is “1”, the P32/CNTR 0 pin level is latched as it is. When bit 3 in the edge polarity selection register is “0”, the inverted value of the P3 3/CNTR 1 pin level is latched; when the bit is “1”, the P33/CNTR 1 pin level is latched as it is.

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERSMITSUBISHI MICROCOMPUTERS Fig. 6 Block diagram of timer 1 through 4 Timer 1 latch (8) Timer 1 (8) Timer 2 latch (8) Timer 2 (8) Timer 3 latch (8) Timer 3 (8) Timer 4 latch (8) Timer 4 (8) Data bus T12M 2 T12M 0 T12M 1 TM2 0 1/2 1/8 EG 2 Port latch T12M 3 T12M 6 T12M 7 T12M 5 T12M 4 TM2 6 T34M 1 T34M 2 T34M 0 T34M 4 T34M 5 F/F TM2 1TM2 7EG 3 EG 2 T34M 3 T34M 6 EG 4 Port latch XCIN (Note 1) XIN P32/CNTR 0 P12/T0 P33/CNTR 1 P13/T1 T34M 7 P33/CNTR 1 P32/CNTR 0 P31/INT1 P30/INT0 EG 1 EG 0 Timer 1 interrupt request Timer 2 interrupt request Timer 3 interrupt request Timer 4 interrupt request C D3 Q3 D2 Q2 D1 Q1 D0 Q0 EG CM 7 ( Select gate : At reset, shaded side is connected.) Note 1 : The 7470 group does not haveXCIN input.

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS Fig. 7 Structure of timer mode registers Timer 1 count stop bit 0 : Count start 1 : Count stop Timer 1 count source selection bit 0 : Internal clock (Note 1) 1 : P32/CNTR 0 external clock Timer 1 internal clock source selection bit (Note 2) 0 : f(XIN) divided by 16 or f(XCIN) divided by 16 1 : f(XCIN) P12/T0 port output selection bit 0 : P12 port output 1 : Timer 1 overflow divided by 2 Timer 2 count stop bit 0 : Count start 1 : Count stop Timer 2 count source selection bit 0 : Internal clock 1 : Timer 1 overflow Timer 2 internal clock source selection bits (Note 3) 00 : f(XIN) divided by 16 or f(XCIN) divided by 16 01 : f(XIN) divided by 64 or f(XCIN) divided by 64 10 : f(XIN) divided by 128 or f(XCIN) divided by 128 11 : f(XIN) divided by 256 or f(XCIN) divided by 256 b7 b0 Timer 1 overflow FF set enable bit 0 : Set disable 1 : Set enable Timer 4 overflow FF set enable bit 0 : Set disable 1 : Set enable Nothing is allocated (The value is undefined at reading) Timer 3, timer 4 count overflow signal selection bit 0 : Timer 1 overflow 1 : Timer 2 overflow Timer 3, timer 4 function selection bit 0 : Normal mode 1 : PWM mode b7 b0 Timer 3 count stop bit 0 : Count start 1 : Count stop Timer 3 count source selection bits (Note 3) 00 : f(XIN) divided by 16 or f(XCIN) divided by 16 01 : f(XCIN) 10 : Timer 1 overflow or timer 2 overflow 11 : P33/CNTR 1 external clock Timer 4 count stop bit 0 : Count start 1 : Count stop Timer 4 count source selection bits (Note 3) 00 : Timer 3 overflow 01 : f(XIN) divided by 16 or f(XCIN) divided by 16 10 : Timer 1 overflow or timer 2 overflow 11 : P33/CNTR 1 external clock Timer 4 pulse width measuring mode selection bit 0 : Timer mode 1 : Pulse width measuring mode P13/T1 port output selection bit 0 : P13 port output 1 : Timer 4 overflow divided by 2 or PWM output b7 b0 1 : f(XIN) divided by 16 in the 7470 group. 2 : The 7470 group does not use this bit (bit 2). Set this bit to “0”. 3 : Do not select f(XCIN) as the count source in the 7470 group. Timer mode register 2 (TM2) (Address 00FA16) Timer 12 mode register (T12M) (Address 00F816) Timer 34 mode register (T34M) (Address 00F916) Notes

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS SERIAL I/O The block diagram of serial I/O is shown in Figure 8. In the serial I/O mode, the receive ready signal (SRDY ), synchronous input/out- put clock (CLK), and the serial I/O (SOUT , SIN) pins are used as P17, P16, P15, and P14, respectively. The serial I/O mode register (address 00DC16) is an 8-bit register. Bit 2 of this register is used to select a synchronous clock source. When this bit is “0”, an external clock from P1 6 is selected. When this bit is “1”, an internal clock is selected. The internal clock can be selected from among the divide by 8, di- vide by 16, divide by 32, divide by 512 frequency of the oscillator frequency f(X IN) or f(XCIN ). Do not select f(XCIN ) as the count source in the 7470 group. The divide ratio is selected according to bit 0 and bit 1 in the serial I/O mode register, and selection be- tween f(X IN) and f(XCIN ) is mode according to bit 7 in the CPU mode register. Bits 3 and 4 decide whether parts of P1 will be used as a serial I/O or not. When bit 3 is “1”, P1 6 becomes an I/O pin of the syn- chronous clock. When an internal synchronous clock is selected, the clock is output from P1 6. If the external synchronous clock is selected, the clock is input to P16. And P15 will be a serial output. T o use P14 as a serial input, set the direction register bit which corresponds to P14, to “0”. For more information on the direction register, refer to the I/O pin sec- tion. Fig. 8 Block diagram of serial I/O 1/2 1/4 XCIN (Note 1) XIN CM 7 Counter 1/2 1/4 1/64 SM 1 SM 0 SM 5 SM 2 Sync. circuit Serial I/O counter (3) Byte counter (4) Serial I/O register (8) Data bus CLK input CLK output SIN SOUT S R SCSM 6 Serial I/O interrupt request Note 1 : The 7470 group does not have XCIN input. SA RDY SRDY Q ( Select gate : At reset, shaded side is connected.)

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS Bit 4 determines if P17 is used as an output pin for the receive ready signal (bit 4=“1”, SRDY ) or used as a normal I/O pin (bit 4=“0”). When the P1 7 pin is used as the SRDY output pin, output signal can be selected between SRDY signal and SARDY signal by using bit 5 in the serial I/O mode register. The SRDY signal is driven “L” by a signal written into the serial I/O register to inform that the de- vice is ready to receive. Then, the S RDY signal is driven “H” on the first falling edge of the transfer clock. The SA RDY signal is driven “H” by a signal written into the serial I/O register, and driven “L” on the last rising edge of the transfer clock. The function of serial I/O differs depending on the clock source; external clock or internal clock. Internal Clock – The serial I/O counter is set to 7 when data is stored in the serial I/O register. At each falling edge of the transfer clock, serial data is output to P1 5. During the rising edge of this clock, data can be input from P14 and the data in the serial I/O register will be shifted 1 bit. Data is output starting with the LSB. After the transfer clock has counted 8 times, the serial I/O register will be empty and the transfer clock will remain at a high level. At this time the interrupt request bit will be set. External Clock – If an external clock is used, the interrupt request bit will be set after the transfer clock has counted 8 times but the transfer clock will not stop. Due to this reason, the external clock must be controlled from the outside. Timing diagrams are shown in Figure 9. Fig. 9 Serial I/O timing D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7 Synchronous clock Transfer clock Serial I/O register write signal Serial I/O output SOUT Serial I/O input SIN Interrupt request bit set Receive ready signal SRDY

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS Fig. 10 Structure of serial I/O mode register BYTE SPECIFY MODE The serial I/O has a byte specify mode that allows one specific byte data to be selected for transmission or reception when serial I/O circuits of two or more microcomputers are connected to send or receive data through one bus. The data to be sent or received can be specified by writing a value into the byte counter. The value written in the byte counter is decremented by one each time eight cycles of transfer clock are input. When the value in the byte counter becomes “0”, serial transmission/reception is done by the next eight cycles of transfer clock. When the value in the byte counter is not “0”, the output on the S OUT pin is driven “H” by the falling edge of the first transfer clock pulse to inhibit transmission/ reception. Serial I/O interrupt requests are generated only when serial trans- mission/reception is done after the value in the byte counter is decremented to “0”. When the SA RDY signal output is selected, the SA RDY signal is driven “L” by the last rising edge of the transfer clock after the value in the byte counter is decremented to “0”. Note that in the byte mode, an external clock must be used as the sync. clock for the purpose of the mode. b7 b0 Serial I/O mode register (SM) (Address 00DC 16) Synchronous clock selection bit 0 : External clock 1 : Internal clock Internal clock selection bits 00 : f(X IN) or f(XcIN) divided by 8 01 : f(XIN) or f(XcIN) divided by 16 10 : f(XIN) or f(XcIN) divided by 32 11 : f(XIN) or f(XcIN) divided by 512 Serial I/O port selection bit 0 : Normal I/O port 1 : SOUT , CLK pins Note :Do not select f(XCIN) as the count source in the 7470 group. Serial I/O byte specify mode selection bit 0 : Normal mode 1 : Byte specify mode SRDY signal output selection bit 0 : Normal I/O port 1 : SRDY signal output pin SRDY signal selection bit 0 : SRDY signal 1 : SARDY signal P15/SOUT, P17/SRDY output structure selection bit 0 : CMOS output 1 : N-channel open drain output

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS Fig. 12 Structure of A-D control register A-D control register (Address 00D916) Note : Do not select IN4 to IN7 in the 7470 group. This bit must be set to “0”. Nothing is allocated (The value is undefined at reading) A-D conversion end bit 0 : Under conversion 1 : End conversion Analog input selection bits 000 : IN0 001 : IN1 010 : IN2 011 : IN3 100 : IN4 101 : IN5 110 : IN6 111 : IN7 (Note) VREF connection selection bit 0 : VREF is separated 1 : VREF is connected

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS KEY ON WAKE UP “Key on wake up” is one way of returning from a power down state caused by the STP or WIT instruction. If any terminal of port P0 has “L” level applied, after bit 5 of the edge polarity selection regis- ter (EG 5) is set to “1”, an interrupt is generated and the microcomputer is returned to the normal operating state. A key matrix can be connected to port P0 and the microcomputer can be returned to a normal state by pushing any key. The key on wake up interrupt is common with the INT 1 interrupt. When EG 5 is set to “1”, the key on wake up function is selected. However, key on wake up cannot be used in the normal operating state. When the microcomputer is in the normal operating state, both key on wake up and INT 1 are invalid. Fig. 13 Block diagram of interrupt input and key on wake up circuit P33/CNTR 1 P32/CNTR 0 P30/INT0 P31/INT1 P07 P01 EG 3 Port P33 data read circuit CNTR interrupt request signal Port P32 data read circuit EG 0 Port P30 data read circuit INT0 interrupt request signal Port P31 data read circuit INT1 interrupt request signal CPU halt state signal Port P0 data read circuit EG 1 EG 5 P00 Pull-up control register Direction register Pull-up control register Direction register Pull-up control register Direction register EG 2 Noise eliminating circuit 1/2XCIN (P50) XIN CM 7 EG 4 Noise eliminating circuit ( Select gate: At reset, shaded side is connected.) Note : The 7470 group does not have XCIN input.

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS RESET CIRCUIT The 7470/7471 group are reset according to the sequence shown in Figure 15. It starts the program from the address formed by us- ing the content of address FFFF 16 as the high order address and the content of the address FFFE16 as the low order address, when the RESET pin is held at “L” level for no less than 2 µs while the power voltage is in the recommended operating condition and then returned to “H” level. The internal initializations following reset are shown in Figure 16. Example of reset circuit is Figure 14. Immediately after reset, timer 3 and timer 4 are connected, and counts the f(X IN) divided by 16. At this time, FF16 is set to timer 3, and 0716 is set to timer 4. The reset is cleared when timer 4 overflows. Fig. 15 Timing diagram at reset Fig. 14 Example of reset circuit Fig. 16 Internal state of microcomputer at reset RESET V CC 7470/7471 group Notes 1 : Frequency relation of XIN and f is f(XIN)=2·f. 2 : The mark “?” means that the address is changeable depending upon the previous state. 00, S 00, S-1 00, S-2 FFFE AD H ,AD L PC H PC L PS AD L XIN f RESET Internal Address Data SYNC 32768 counts of f(XIN) Reset address from the vector table RESET ? ? FFFF AD H (1) Port P0 direction register (C116) … (2) Port P1 direction register (C316) … (3) Port P2 direction register (C516) … (4) Port P4 direction register (C916) … (5) P0 pull-up control register (D016) … (6) P1–P5 pull-up control register (Note 1)(D116) … (7) Edge selection register (EG) (D416) … (8) A-D control register (D9 16) … (9) Serial I/O mode register (SM) (DC16) … (10) Timer 12 mode register (T12M) (F816) … (11) Timer 34 mode register (T34M) (F916) … (12) Timer mode register 2 (TM2) (FA16) … (13) CPU mode register (CM) (FB16) … (14) Interrupt request register 1 (FC16) … (15) Interrupt request register 2 (FD16) … (16) Interrupt control register 1 (FE16) … (17) Interrupt control register 2 (FF16) … (18) Program counter (PC H ) … (PCL) … (19) Processor status register (PS) … 0016 0016 00 00 00 0 0 0 0 00 0 0 00 1 0 0 0 00 00 0000 000 00 0 000 000 00 0 000 000 0016 0016 0016 0016 1 : This address is allocated P1–P4 pull-up control register for 7470 group. Bit 6 is not used. 2 : Since the contents of both registers other than those listed above (including timers and the serial I/O register) are undefined at reset, it is necessary to set initial values. Address Contents of address FFFF 16 0016 Contents of address FFFE 16 Notes

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS I/O PORTS (1) Port P0 Port P0 is an 8-bit I/O port with CMOS outputs. As shown in Figure 2, P0 can be accessed as memory through zero page address 00C0 16. Port P0’s direction register allows each bit to be programmed individually as input or output. The direction register (zero page address 00C1 16) can be programmed as input with “0”, or as output with “1”. When in the output mode, the data to be output is latched to the port latch and output. When data is read from the output port, the output pin level is not read, only the latched data of the port latch is read. There- fore, a previously output value can be read correctly even though the output voltage level has been shifted up or down. Port pins set as input are in the high impedance state so the signal level can be read. When data is written into the input port, the data is latched only to the output latch and the pin still remains in the high impedance state. Following the ex- ecution of STP or WIT instruction, key matrix with port P0 can be used to generate the interrupt to bring the microcomputer back in its normal state. When this port is selected for input, pull-up transistor can be connected in units of 1-bit. (2) Port P1 Port P1 has the same function as port P0. P1 2–P1 7 serve dual functions, and the desired function can be selected by the program. When this port is selected for input, pull-up tran- sistor can be connected in units of 4-bit. (3) Port P2 Port P2 has the same function as port P0. In the 7470 group, this port is P2 0–P2 3, a 4-bit I/O port. This port can also be used as the analog voltage input pins. When this port is se- lected for input, pull-up transistor can be connected in units of 4-bit. (4) Port P3 Port P3 is a 4-bit input port. (5) Port P4 Port P4 is a 4-bit I/O port and has basically the same func- tions as port P0. In the 7470 group, this port is P4 0 and P41, a 2-bit I/O port. When this port is selected for input, pull-up transistor can be connected in units of 4-bit . (6) Port P5 Port P5 is a 4-bit input port and pull-up transistor can be con- nected in units of 4-bit. P5 0 and P51 are shared with clock generating circuit input/output pins. The 7470 group does not have this port. (7) INT 0 pin (P30/INT0 pin) This is an interrupt input pin, and is shared with port P30. When “H” to “L” or “L” to “H” transition input is applied to this pin, the INT 0 interrupt request bit (bit 0 of address 00FD16) is set to “1”. (8) INT1 pin (P31/INT1 pin) This is an interrupt input pin, and is shared with port P31. When “H” to “L” or “L” to “H” transition input is applied to this pin, the INT 1 interrupt request bit (bit 1 of address 00FD16) is set to “1”. (9) Counter input CNTR0 pin (P32/CNTR 0 pin) This is a timer input pin, and is shared with port P32. When this pin is selected to CNTR0 or CNTR1 interrupt input pin and “H” to “L” or “L” to “H” transition input is applied to this pin, the CNTR 0 or CNTR1 interrupt request bit (bit 2 of ad- dress 00FD16) is set to “1”. (10) Counter input CNTR1 pin (P33/CNTR 1 pin) This is a timer input pin, and is shared with port P33. When this pin is selected to CNTR0 or CNTR1 interrupt input pin and “H” to “L” or “L” to “H” transition input is applied to this pin, the CNTR 0 or CNTR1 interrupt request bit (bit 2 of ad- dress 00FD16) is set to “1”.

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS Fig. 17 Block diagram of ports P0, P10–P1 3 Direction register Port latch Interrupt control circuit Port P0 Data bus Port P0 Port P13 Data bus T34M 7 Data bus Port P12 Data bus T12M 3 Port P11 Data bus Ports P10–P13 Port latch Port latch Port latch Port P10 Data bus Port latch Direction register Pull-up control register Direction register Pull-up control register Direction register Direction register Tr1 Tr2 Tr3 Tr4 Tr5 Tr1–Tr5 are pull-up transistors

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS Fig. 18 Block diagram of ports P14–P1 7 Port latch Port P17 Data bus SRDY Port P16 Data bus CLK output Port P15 Data bus Port P14 Data bus Data bus Ports P14–P17 CLK input Port latch Port latch Port latch Direction register Direction register Direction register Direction register Pull-up control register SIN SOUT SM 3 SM 2 SM 3 SM 7 SM 7 SM 4 Tr6 Tr6–Tr9 are pull-up transistors Tr7 Tr8 Tr9

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS Multi- plexerA-D conversion circuit Port P3 INT0, INT1 CNTR 0, CNTR1 Data bus Port P3 Pull-up control register* Direction register Port latch * : Control in units of 4-bit (Control in units of 2-bit for 7470 group) Port P4 Port P4 Data bus Data bus Pull-up control register* Direction register Port latch * : Control in units of 4-bit Port P2 Port P2 Data bus Data bus Tr10 Tr11 Tr10–Tr11 are pull-up transistors Fig. 19 Block diagram of ports P2–P4

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS Fig. 20 Block diagram of port P5 Pull-up control register Port P5 Data bus Data bus Port P53 Port P52 Port P51 Data bus CM 4 Data bus CM 4 CM 4 XCIN Port P50 CM 4 Data bus Note : 7470 group does not have this port. Tr12–Tr15 are pull-up transistors Tr12 Tr13 Tr14 Tr15

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS Fig. 25 Block diagram of clock generating circuit Fig. 26 Structure of CPU mode register Q R S Q R SQ R SQ R SQ R S XIN XOUT 1/2 1/8 Reset STP instruction Reset Interrupt disable flag I Interrupt request STP instruction WIT instruction Internal clock f XCIN Timer 4Timer 3 T34M 0 T34M 1 T34M 2 XCOUT CM 6 CM 7 CM 7 (Note 1) Notes 1 : Refer to Timer 3 of [Figure 6 Block diagram of timer 1 through 4] 2 : 7470 group does not have XCIN input and XCOUT output. Select gate : At reset, shaded side is connected b7 b0 CPU mode register (Address 00FB16) These bits must always be set to “0”. Stack page selection bit (Note 1) 0 : In page 0 area 1 : In page 1 area Nothing is allocated (The value is undefined at reading) 0, P51/XCIN, XCOUT selection bit (Note 2) 0 : P50, P51 1 : XCIN, XCOUT XCOUT drive capacity selection bit (Note 2) 0 : Low 1 : High Clock (XIN-XOUT ) stop bit (Note 2) 0 : Oscillates 1 : Stops Internal system clock selection bit (Note 2) 0 : X IN-XOUT selected (normal mode) 1 : XCIN-XCOUT selected (low-speed mode) Notes 1 : In the M37470M2, M37470M4/E4, M37471M2, M37471M4/E4, set this bit to “0”. 2 : In the 7470 group, set this bit to “0”.

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS Notes 1 :Latency time is automatically generated upon release from the STP instruction due to the connections of timer 3 and 4. 2 :When the system clock is switched over by restarting clock oscillation, a certain wait time required for oscillation to stabilize must be inserted by the program. f(XIN) oscillation f(XCIN) stop f stop Timer operation STP instruction Interrupt (Note 1) CM 4 = 0 CM 5 = 0 CM 6 = 0 CM 7 = 0 Reset WIT instruction Interrupt f(XIN) oscillation f(XCIN) stop P50, P51 input f = f(XIN)/2 f(XIN) stop f(XCIN) stop f stop f(XIN) oscillation f(XCIN) oscillation f stop Timer operation STP instruction Interrupt (Note 1) WIT instruction Interrupt f(XIN) oscillation f(XCIN) oscillation f = f(XIN)/2 f(XIN) stop f(XCIN) stop f stop CM 4 = 0 CM 5 = 1 CM 4 = 1 (Note 2) f(XIN) oscillation f(XCIN) oscillation f stop Timer operation STP instruction Interrupt (Note 1) WIT instruction Interrupt f(XIN) oscillation f(XCIN) oscillation f = f(XCIN)/2 f(XIN) stop f(XCIN) stop f stop CM 7 = 0 (CM 5 = 0) CM 7 = 1 f(XIN) stop f(XCIN) oscillation f stop Timer operation STP instruction Interrupt (Note 1) WIT instruction Interrupt f(XIN) stop f(XCIN) oscillation f = f(XCIN)/2 f(XIN) stop f(XCIN) stop f stop CM 6 = 0 (Note 2) CM 6 = 1 CM 5 = 1 CM5 = 1 Fig. 27 Transition of states for the system clock

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS Power on reset Clock X oscillation Internal system clock start (X→ 1/2→ φ ) Program start from RESET vector Normal program ← Operating at f(XIN) Clock for clock function XC oscillation start (CM4 = 1, CM5 = 1) Latency time for oscillation to stabilize (by program) ← Operating at f(XIN) XC clock power down (CM5 : 1→ 0) Internal clock φ source switching X→ XC (CM7 : 0→ 1) Clock X halt (XC in operation) (CM6 = 1) Internal clock halt (WIT instruction) Timer 4 (clock count) overflow Internal clock operation start (WIT instruction released) Clock processing routine ← Operating at f(XCIN) Internal clock halt (WIT instruction) Interrupts from INT 0, INT1, CNTR0/CNTR 1, timer 1, timer 2, timer 3, timer 4, serial I/O, key on wake up Internal clock operation start (WIT instruction released) Program start from interrupt vector Clock X oscillation start (CM6 = 0) Latency time for oscillation to stabilize (by program) ← Operating at f(XCIN) Internal clock φ source switching (XC → X) (CM7 : 1→ 0) Normal program → Operating at f(XIN) <An example of flow for system> Normal operationOperation on the clock function only Return from clock function

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS STP instruction preparation (pushing registers) Timer 3, timer 4 interrupt disable X/16 or XC /16 selected for timer 3 count source; timer 3 overflow selected for timer 4 count source Timer 3, timer 4 start counting Values set to timer 3, timer 4 that do not cause timer 4 to overflow until STP instruction is executed Interrupt for return from STP enabled Timer 4 interrupt request bit cleared Clock X and clock for clock function XC halt (STP instruction) RAM backup status Interrupts from INT0, INT1, CNTR0/CNTR 1, timer 1, timer 2, serial I/O, key on wake up Clock X and clock for clock function XC oscillation start Timer 4 overflow (X/16 or XC /16→ timer 3→ timer 4) Internal system clock start Program start from interrupt vector Normal program RAM backup function Return from RAM backup function ………

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS Power source voltage inputs 2.7 to 5.5 V to VCC and 0 V to VSS . Ground level input pin for A-D converter. Same voltage as VSS is applied. To enter the reset state, the reset input pin must be kept at a “L” for 2 µs or more (under normal VCC conditions). Connect to VSS . These are I/O pins of internal clock generating circuit for main clock. To control generating frequency, an external ceramic or a quartz-crystal oscillator is con- nected between the X IN and XOUT pins. If an external clock is used, the clock source should be connected the XIN pin and the XOUT pin should be left open. Feedback resistor is connected between XIN and XOUT . Reference voltage input pin for the A-D converter. VREF works as CE input. Port P0 is an 8-bit I/O port. The output structure is CMOS output. When this port is selected for input, pull-up transistor can be connected in units of 1-bit and a key on wake up function is provided. Port P0 works as an 8-bit data bus (D 0–D 7). Port P1 is an 8-bit I/O port. The output structure is CMOS output. When this port is selected for input, pull-up transistor can be connected in units of 4-bit. P12, P13 are in common with timer output pins T0, T1. P14, P15, P16, P17 are in common with serial I/O pins SIN, SOUT , CLK, SRDY , respectively. The output structure of SOUT and SRDY can be changed to N-channel open drain output. P11–P17 works as the 7-bit address input (A4–A10). P10 must be opened. Port P2 is an 8-bit input port. This port is in common with analog input pins IN0–IN7. P20–P2 3 works as the lower 4-bit address input (A0–A3). P24–P2 7 must be opened. Port P3 is a 4-bit input port. P30, P31 are in common with external interrupt input pins INT0, INT1 and P32, P33 are in common with timer input pins CNTR0, CNTR1. P30, P31 works as the 2-bit address input (A11, A12). P32 works as OE input. Connect to P33 to VPP when programming or verifying. Port P4 is a 4-bit I/O port. The output structure is CMOS output. When this port is selected for input, pull-up transistor can be connected in units of 4-bit. P40, P41 works as the higher 2-bit address input (A13, A14). P42, P43 must be opened. Port P5 is a 4-bit input port and pull-up transistor can be connected in units of 4- bit. P50, P51 are in common with input/output pins of clock for clock function XCIN, XCOUT . When P50, P51 are used as XCIN, XCOUT , connect a ceramic or a quartz- crystal oscillator between XCIN and XCOUT . If an external clock input is used, con- nect the clock input to the XCIN pin and open the XCOUT pin. Feedback resistor is connected between XCIN and XCOUT pins. Open. Power source Analog power source Reset input Reset input Clock input Clock output Reference voltage input Select mode I/O port P0 Data input/output D0–D7 I/O port P1 Address input A4–A10 I/O port P2 Address input A 0–A3 Input port P3 Address input A11, A12 Select mode V PP input I/O port P4 Address input A13, A14 Input port P5 VCC ,VSS AV SS (Note 1) RESET XIN XOUT VREF P00–P0 7 P10–P1 7 P20–P2 7 (Note 2) P30–P3 3 P40–P4 3 (Note 3) P50–P5 3 (Note 4) Single-chip /EPROM Single-chip /EPROM Single-chip EPROM Single-chip /EPROM Single-chip EPROM Single-chip EPROM Single-chip EPROM Single-chip EPROM Single-chip EPROM Single-chip EPROM Single-chip EPROM Input Input Output Input Input I/O I/O I/O Input I/O Input Input Input I/O Input Input BUILT-IN PROM TYPE MICROCOMPUTERS PIN DESCRIPTION Pin FunctionsMode Name Input/ Output Notes 1 : AVSS for M37471M2/M4/M8/E4/E8-XXXFP. 2 : Only P20–P23 (IN0–IN3) 4-bit for the 7470 group. 3 : Only P40 and P41 2-bit for the 7470 group. 4 : This port is not included in the 7470 group.

Table 2. Pin function in EPROM mode

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS Fig. 29 Pin connection in EPROM mode Fig. 30 Pin connection in EPROM mode : Same functions as M5L27256 P06 P15/SOUT P21/IN1 P52 P07 P05 P53 P16/SCLK VSS NC NC NC P17/SRDY P04 P03 P02 P01 P00 P43 P42 P41 P40 P33/CNTR 1 P32/CNTR 0 P31/INT1 P30/INT0 NC NC NC P14/SIN P13/ P11 P10 P27/IN7 P26/IN6 P25/IN5 P24/IN4 P23/IN3 P22/IN2 P20/IN0 VREF NC NC M37471E4-XXXFP M37471E8-XXXFP P51/XCOUT VCC XIN XOUT VSS AV SS NC NC NC RESET NC P50/XCIN P12/T0 D 4 D 3 D 2 D 1 D 0 A14 A13 VPP OE A12 A11CE D 5 D 6 D 7 VSS A10 VCC VSS A10 VSS CE D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 A14 A13 VPP A12 A11 VCC OE VSS : Same functions as M5L27256 16 17 M37470E4-XXXSP M37470E8-XXXSP P17/SRDY P16/CLK P15/SOUT P14/SIN P13/ P11 P10 P23/IN3 P22/IN2 P21/IN1 P20/IN0 VREF XIN XOUT VSS P07 P06 P05 P04 P03 P02 P01 P00 P41 P40 P33/CNTR 1 P32/CNTR 0 P31/INT1 P30/INT0 RESET VCC P12/T0

Note : VIL and VIH indicate a “L” and “H” input voltage, respectively. Table 3. I/O signal in each mode either the CE or OE pin is in the “H” state.

• M37470E4, M37471E4 When using a PROM programmer, the address range should be between 6000 16 and 7FFF16. Addresses 000016 to 5FFF16 can- not be written to or read from correctly.
• M37470E8, M37471E8 When using a PROM programmer, the address range should be between 4000 16 and 7FFF16. When data is written between ad- dresses 000016 and 7FFF16, fill addresses 000016 to 3FFF16 with FF16. Erasing Data can only erased on the M37471E8SS ceramic package, which includes a window. To erase data on this chip, use an ultra- violet light source with a 2537 Angstrom wave length. The minimum radiation power necessary for erasing is 15W·s/cm NOTES ON HANDLING (1) Sunlight and fluorescent light contain wave lengths capable of erasing data. For ceramic package types, cover the transpar- ent window with a seal (provided) when this chip is in use. However, this seal must not contact the lead pins. (2) Before erasing, the glass should be cleaned and stains such as finger prints should be removed thoroughly. If these stains are not removed, complete erasure of the data could be pre- vented. (3) Since a high voltage (12.5 V) is used to write data, care should be taken when turning on the PROM programmer’s power. (4) For the programmable microcomputer (shipped in One Time PROM version), Mitsubishi does not perform PROM write test and screening in the assembly process and following pro- cesses. To improve reliability after write, performing write and test according to the flow below before use is recommended. Writing with PROM programmer Verify test with PROM programmer Function check in target device Screening (Caution) (Leave at 150°C for 40 hours)

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS PROGRAMMING NOTES (1) The frequency ratio of the timer is 1/(n+1). (2) The contents of the interrupt request bits are not modified im- mediately after they have been written. After writing to an interrupt request register, execute at least one instruction be- fore executing a BBC or BBS instruction. (3) To calculate in decimal notation, set the decimal mode flag (D) to “1”, then execute an ADC or SBC instruction. Only the ADC and SBC instruction yield proper decimal results. After execut- ing an ADC or SBC instruction, execute at least one instruction before executing a SEC, CLC, or CLD instruction. (4) An NOP instruction must be used after the execution of a PLP instruction. (5) Do not execute the STP instruction during A-D conversion. (6) In the M37470, set bit 0, bit 1, and bit 3–bit 7 to “0” of the CPU mode register. (7) Multiply/Divide instructions The index X mode (T) and the decimal mode (D) flag do not affect the MUL and DIV instruction. The execution of these instructions does not modify the con- tents of the processor status register. DATA REQUIRED FOR MASK ORDERING Please send the following data for mask orders. (1) mask ROM confirmation form (2) mark specification form

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS M37470M2/M4/M8-XXXSP, M37470E4/E8-XXXSP ABSOLUTE MAXIMUM RATINGS Power source voltage Input voltage XIN Input voltage P00–P0 7, P10–P1 7, P20–P2 3, P30–P3 3, P40, P41, VREF , RESET Output voltage P00–P0 7, P10–P1 7, P20–P2 3, P40, P41, XOUT Power dissipation Operating temperature Storage temperature V CC VI VI VO Pd Topr Tstg V V V V mW –0.3 to 7 –0.3 to VCC +0.3 –0.3 to VCC +0.3 –0.3 to VCC +0.3 1000 –20 to 85 –40 to 150 Unit Symbol Parameter Ratings Conditions Ta = 25°C All voltages are based on VSS . Output transistors are cut off. RECOMMENDED OPERATING CONDITIONS (VCC = 2.7 to 5.5 V, VSS = 0 V, Ta = –20 to 85°C unless otherwise noted) Power source voltage Power source voltage “H” input voltage P00–P07, P10–P1 7, P30–P3 3, RESET , XIN “H” input voltage P20–P23, P40, P41 “L” input voltage P00–P0 7, P10–P1 7, P30–P3 3 “L” input voltage P20–P23, P40, P41 “L” input voltage RESET “L” input voltage X IN “H” sum output current P00–P0 7, P40, P41 “H” sum output current P10–P1 7, P20–P2 3 “L” sum output current P00–P0 7, P40, P41 “L” sum output current P10–P1 7, P20–P2 3 “H” peak output current P00–P0 7, P10–P1 7, P20–P2 3, P40, P41 “L” peak output current P00–P0 7, P10–P1 7, P20–P2 3, P40, P41 “H” average output current P00–P0 7, P10–P1 7, P20–P2 3, P40, P41 (Note 2) “L” average output current P00–P0 7, P10–P1 7, P20–P2 3, P40, P41 (Note 2) 2.7 4.5 0.8V CC 0.7VCC V V V V V V V V mA mA mA mA mA mA mA mA 4.5 5.5 V CC VCC 0.2VCC 0.25VCC 0.12VCC 0.16VCC –30 –30 –10 2.2VCC – 2.0 Symbol Parameter Limits Min. Typ. Max. Unit f(CNTR ) f(CLK ) f(XIN) f(XIN) = 4 MHz f(XIN) = 8 MHz f(XIN) = 4 MHz f(XIN) = 8 MHz VCC = 2.7 to 4.5 V VCC = 4.5 to 5.5 V MHz MHz MHz V CC VSS VIH VIH VIL VIL VIL VIL IOH(sum) IOH(sum) IOL(sum) IOL(sum) IOH(peak) IOL(peak) IOH(avg) IOL(avg) Timer input frequency CNTR0 (P32), CNTR 1 (P33) (Note 1) Clock input oscillation frequency (Note 1) Serial I/O clock input frequency SCLK (P16) (Note 1) f(XIN) = 2.2VCC –2.0 MHz f(XIN) = 8 MHz Notes 1 : Oscillation frequency is at 50% duty cycle. 2 : The average output current IOH (avg) and IOL (avg) are the average value during a 100 ms.

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS M37470M2/M4/M8-XXXSP, M37470E4/E8-XXXSP ELECTRICAL CHARACTERISTICS (VCC = 2.7 to 5.5 V, VSS = 0 V, Ta = –20 to 85°C, unless otherwise noted) –1.0 –0.35 –1.0 –0.35 3.6 5.5 0.5 0.3 0.5 0.3 0.5 0.3 –0.5 –0.18 –0.5 –0.18 3.5 1.8 7.5 0.5 0.1 –0.25 –0.08 –0.25 –0.08 V CC = 5 V VCC = 3 V VCC = 5 V VCC = 3 V VCC = 5 V VCC = 3 V VCC = 5 V VCC = 3 V VCC = 5 V VCC = 3 V VCC = 5 V VCC = 3 V VCC = 5 V VCC = 3 V VCC = 5 V VCC = 3 V VCC = 5 V VCC = 3 V VCC = 5 V VCC = 3 V VCC = 5 V VCC = 3 V VCC = 5 V VCC = 3 V VCC = 5 V VCC = 3 V VCC = 5 V VCC = 3 V Ta = 25°C Ta = 85°C V V V V V µ A mA µ A µ A mA µ A µ A µ A µ A µ A Max. Limits Symbol Parameter Min. Typ. UnitTest Conditions mA mA mA µ A VV RAM RAM retention voltage Stop all oscillation f(XIN)=8 MHz f(XIN)=4 MHz f(XIN)=8 MHz f(XIN)=4 MHz f(XIN)=8 MHz f(XIN)=4 MHz At normal mode, A-D conversion is not executed. At normal mode, A-D conversion is executed. At wait mode. At stop mode, f(X IN)=0, VCC =5 V ICC Power source current VCC = 5 V, IOH = –5 mA VCC = 3 V, IOH = –1.5 mA VCC = 5 V, IOL = 10 mA VCC = 3 V, IOL = 3 mA VCC = 5 V VCC = 3 V VCC = 5 V VCC = 3 V use as CLK input VOH VOL VT+ – VT– VT+ –V T– VT+ –V T– IIL IIL IIL IIL IIH IIH IIH IIH “H” output voltage P00–P07, P10–P1 7, P20–P2 3, P40, P41 “H” input current RESET, XIN “L” output voltage P00–P0 7, P10–P1 7, P20–P2 3, P40, P41 Hysteresis P00 – P07, P30 – P33 Hysteresis RESET Hysteresis P16/CLK “L” input current P00–P07, P10–P1 7, P30–P3 2, P40–P4 1 “L” input current P33 “L” input current P20–P2 3 “L” input current RESET, XIN “H” input current P00–P0 7, P10–P1 7, P30–P3 2, P40, P41 “H” input current P33 “H” input current P20–P2 3 VI = 0 V, not use pull-up transistor VI = 0 V, use pull-up transistor VI = 0 V VI = 0 V, not use as analog input, not use pull-up transistor VI = 0 V, not use as analog input, use pull-up transistor VI = 0 V (XIN is at stop mode) VI = VCC , not use pull-up transistor VI = VCC V I = VCC , not use as analog input, not use pull-up transistor VI = VCC , (XIN is at stop mode)

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS A-D CONVERTER CHARACTERISTICS (VCC = 2.7 to 5.5 V, VSS = 0 V, Ta = –20 to 85°C, f(XIN)=4 MHz, unless otherwise noted) Unit Symbol Parameter Test Conditions Limits ±0.9 12.5 V CC VREF Resolution Non-linearity error Differential non-linearity error Zero transition error Full-scale transition error Conversion time Reference input voltage Ladder resistance value Analog input voltage V CC = VREF = 5.12 V, IOL (sum) = 0 mA VCC = VREF = 3.072 V, IOL (sum) = 0 mA VCC = VREF = 5.12 V VCC = VREF = 3.072 V VCC = 2.7 to 5.5 V, f(XIN) = 4 MHz VCC = 4.5 to 5.5 V, f(XIN) = 8 MHz 0.5VCC Max.Typ.Min. V OT VFST tCONV VREF R LADDER VIA bits LSB LSB LSB LSB µs V kΩ V

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS M37471M2/M4/M8-XXXSP/FP, M37471E4/E8-XXXSP/FP, M37471E8SS ABSOLUTE MAXIMUM RATINGS Power source voltage Input voltage XIN Input voltage P00–P0 7, P10–P1 7, P20–P2 7, P30–P3 3, P40–P43, P50–P53, VREF , RESET Output voltage P00–P0 7, P10–P1 7, P20–P2 7, P40–P4 3, XOUT Power dissipation Operating temperature Storage temperature V CC VI VI VO Pd Topr Tstg V V V V mW –0.3 to 7 –0.3 to VCC +0.3 –0.3 to VCC +0.3 –0.3 to VCC +0.3 1000 (Note 1) –20 to 85 –40 to 150 Unit Symbol Parameter Ratings Conditions Ta = 25°C Note 1 : 500 mW for M37471M2/M4/M8-XXXFP. All voltages are based on VSS . Output transistors are cut off. 4.5 5.5 VCC VCC 0.2VCC 0.25VCC 0.12VCC 0.16VCC – 30 – 30 – 10 – 5 2.2VCC – 2.0 f(CNTR ) f(CLK ) f(XIN) f(XCIN) RECOMMENDED OPERATING CONDITIONS (VCC = 2.7 to 5.5 V, VSS = AVSS = 0 V, Ta = –20 to 85°C unless otherwise noted) 2.7 4.5 0.8VCC 0.7VCC V V V V V V V V V mA mA mA mA mA mA mA mA Symbol Parameter Limits Min. Typ. Max. Unit f(XIN) = 4 MHz f(XIN) = 8 MHz f(XIN) = 4 MHz f(XIN) = 8 MHz VCC = 2.7 to 4.5 V VCC = 4.5 to 5.5 V MHz MHz MHz kHz V CC VSS AV SS VIH VIH VIL VIL VIL VIL IOH(sum) IOH(sum) IOL(sum) IOL(sum) IOH(peak) IOL(peak) IOH(avg) IOL(avg) Timer input frequency CNTR0 (P32), CNTR 1 (P33) (Note 3) Main clock input oscillation frequency (Note 3) Serial I/O clock input frequency SCLK (P16) (Note 3) f(XIN) = 2.2VCC – 2.0 MHz f(XIN) = 8 MHz Sub-clock input oscillation frequency for clock function (Note 3, 4) Notes 1 : It is except to use P50 as XCIN. 2 : The average output current IOH (avg) and IOL (avg) are the average value during a 100 ms. 3 : Oscillation frequency is at 50% duty cycle. 4 : When used in the low-speed mode, the clock oscillation frequency for clock function should be f(XCIN) < f(XIN) / 3. Power source voltage Power source voltage Analog power source voltage “H” input voltage P0 0–P0 7, P10–P1 7, P30–P3 3, RESET, XIN “H” input voltage P20–P2 7, P40–P4 3, P50–P5 3 (Note 1) “L” input voltage P00–P07, P10–P17, P30–P33 “L” input voltage P20–P2 7, P40–P4 3, P50–P5 3 (Note 1) “L” input voltage RESET “L” input voltage X IN “H” sum output current P00–P0 7, P40–P4 3 “H” sum output current P10–P1 7, P20–P2 7 “L” sum output current P00–P0 7, P40–P4 3 “L” sum output current P10–P1 7, P20–P2 7 “H” peak output current P00–P0 7, P10–P1 7, P20–P2 7, P40–P4 3 “L” peak output current P00–P0 7, P10–P1 7, P20–P2 7, P40–P4 3 “H” average output current P00–P0 7, P10–P1 7, P20–P2 7, P40–P4 3 (Note 2) “L” average output current P00–P0 7, P10–P1 7, P20–P2 7, P40–P4 3 (Note 2)

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS mA mA µ A mA µ A V VCC = 5 V VCC = 3 V VCC = 5 V VCC = 3 V VCC = 5 V VCC = 3 V VCC = 5 V VCC = 3 V VCC = 5 V VCC = 3 V VCC = 5 V VCC = 3 V VCC = 5 V VCC = 3 V VCC = 5 V VCC = 3 V VCC = 5 V VCC = 3 V VCC = 5 V VCC = 3 V VCC = 5 V VCC = 3 V VCC = 5 V VCC = 3 V VCC = 5 V VCC = 3 V VCC = 5 V VCC = 3 V VCC = 5 V VCC = 3 V VCC = 5 V VCC = 3 V Ta = 25°C Ta = 85°C f(XIN)=8 MHz f(XIN)=4 MHz f(XIN)=8 MHz f(XIN)=4 MHz f(XIN)=8 MHz f(XIN)=4 MHz M37471M2/M4/M8-XXXSP/FP, M37471E4/E8-XXXSP/FP, M37471E8SS ELECTRICAL CHARACTERISTICS (VCC = 2.7 to 5.5 V, VSS = AVSS = 0 V, Ta = –20 to 85°C, unless otherwise noted) –1.0 –0.35 –1.0 –0.35 3.6 0.5 0.3 0.5 0.3 0.5 0.3 –0.5 –0.18 –0.5 –0.18 3.5 1.8 7.5 0.5 0.1 V CC = 5 V, IOH = –5 mA VCC = 3 V, IOH = –1.5 mA VCC = 5 V, IOL = 10 mA VCC = 3 V, IOL = 3 mA VCC = 5 V VCC = 3 V VCC = 5 V VCC = 3 V Max. Limits Symbol Parameter Min. Typ. UnitTest Conditions At normal mode, A-D conversion is not executed. –0.25 –0.08 –0.25 –0.08 V V V V V µ A mA µ A µ A mA µ A µ A µ A µ A µ A V OH VOL VT+ – VT– VT+ –V T– VT+ –V T– IIL IIL IIL IIL IIH IIH IIH IIH Stop all oscillationVRAM RAM retention voltage Stop all oscillation VCC = 5 V At wait mode. At normal mode, A-D conversion is executed. I CC Power source current At wait mode, XIN = 0 Hz, XCIN = 32 kHz, XCOUT is low-power mode, Ta=25°C At low-speed mode, Ta=25°C, f(XIN)=0, f(XCIN)=32 kHz, XCOUT drive capacity is low, A-D conversion is not executed. “H” output voltage P00–P0 7, P10–P1 7, P20–P2 7, P40–P4 3 “L” output voltage P00–P0 7, P10–P1 7, P20–P2 7, P40–P4 3 Hysteresis P00–P0 7, P30–P3 3 Hysteresis RESET Hysteresis P16/CLK “L” input current P00–P0 7, P10–P1 7, P30–P3 2, P40–P4 3, P50–P5 3 “L” input current P33 “L” input current RESET , XIN “H” input current P00–P0 7, P10–P17, P30–P32, P40–P43, P50–P53 “H” input current P33 “H” input current P20–P2 7 VI = 0 V, not use pull-up transistor VI = 0 V, use pull-up transistor VI = 0 V used as CLK input V I = 0 V, not use as analog input, not use pull-up transistor VI = 0 V, not use as analog input, use pull-up transistor VI = 0 V (XIN is at stop mode) VI = VCC , not use pull-up transistor VI = VCC VI = VCC , not use as analog input, not use pull-up transistor VI = VCC , (XIN is at stop mode) “L” input current P20–P2 7 “H” input current RESET, XIN

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS A-D CONVERTER CHARACTERISTICS (VCC = 2.7 to 5.5 V, VSS =AV SS = 0 V , Ta = –20 to 85°C, f(XIN) = 4 MHz, unless otherwise noted) Unit Symbol Parameter Test Conditions Limits ±0.9 12.5 V CC VREF Resolution Non-linearity error Differential non-linearity error Zero transition error Full-scale transition error Conversion time Reference input voltage Ladder resistance value Analog input voltage V CC = VREF = 5.12 V, IOL (sum) = 0 mA VCC = VREF = 3.072 V, IOL (sum) = 0 mA VCC = VREF = 5.12 V VCC = VREF = 3.072 V VCC = 2.7 to 5.5 V, f(XIN) = 4 MHz VCC = 4.5 to 5.5 V, f(XIN) = 8 MHz 0.5VCC Max.Typ.Min. V OT VFST tCONV VREF R LADDER VIA bits LSB LSB LSB LSB µs V kΩ V

© 1998 MITSUBISHI ELECTRIC CORP. New publication, effective Jan. 1998. Specifications subject to change without notice. Notes regarding these materials

• These materials are intended as a reference to assist our customers in the selection of the Mitsubishi semiconductor product best suited to the customer’s application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Mitsubishi Electric Corporation or a third party.
• Mitsubishi Electric Corporation assumes no responsibility for any damage, or infringement of any third-party’s rights, originating in the use of any product data, diagrams, charts or circuit application examples contained in these materials.
• All information contained in these materials, including product data, diagrams and charts, represent information on products at the time of publication of these materials, and are subject to change by Mitsubishi Electric Corporation without notice due to product improvements or other reasons. It is therefore recommended that customers contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for the latest product information before purchasing a product listed herein.
• Mitsubishi Electric Corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use.
• The prior written approval of Mitsubishi Electric Corporation is necessary to reprint or reproduce in whole or in part these materials.
• If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited.
• Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for further details on these materials or the products contained therein. Keep safety first in your circuit designs!
• Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non-flammable material or (iii) prevention against any malfunction or mishap. MITSUBISHI MICROCOMPUTERS 7470/7471 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

Rev. Rev. No. date

1.0 First Edition 980110

REVISION DESCRIPTION LIST 7470/7471 GROUP DATA SHEET (1/1) Revision Description