M37410M3

M37410M3 MITSUBISHI | Alldatasheet

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M37410M3-XXXFP,M37410M4-XXXFP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

DESCRIPTION

The M37410M3-XXXFP is a single-chip microcomputer de- PIN CONFIGURATION (TOP VIEW) signed with CMOS silicon gate technology. It is housed in a 80-pin plastic molded QFP. This single-chip microcomputer eseeee? is useful for business equipment and other consumer ap- segeeee 5 In addition to its simple instruction set, the ROM, RAM, and SRRSUSSRRRASBSERAREI V/O addresses are placed on the same memory map to en- Seine ee EE com, able easy programming. some OC = g0m This microcomputer is also suitable for applications which Senin Be ve require controlling LCDs. ‘Aver Cl FA Eleva The differences among the M37410M3-XXXFP, the rant al s acs Bee M37410M4-XXXFP and the M37410M6-XXXFP are noted perp 3 ls below. The following explanations apply to the M37410M3- P5y/PWMI = (7 8 ial P2, XXXFP. Specification variations for other chips are noted Pee & Bape accordingly. pevent, (a 3 fe} Po, PoQ/INTy = [i i= P0, Type name “ROMsie | ——«#RAM size P3y/Sapr = fa) Po, M37410M4-XXXFP | 8192 bytes | __256 bytes Pau Su — im Po. M37410M6-XXXFP | 12288 bytes 256 bytes Fe RETIN ATE RETERIIELS Sed geghteadicecece? FEATURES ey °° © Number of basic instructions:-- sreeeeeeeneeeeneees 6Q © Memory size Outline 80P6S ROM sees 6144 bytes (M37410M3-XXXFP) 8192 bytes (M37410M4-XXXFP) 12288 bytes (M37410M6-XXXFP) RAM i rrrrsseeer--- 492 bytes (M37410M3-XXXFP) 256 bytes (M37410M4-XXXFP, @ LCD controller/driver (1/2, 1/3 bias, 1/2, 1/3, 1/4 duty) M37410M6-XXXFP) Segment outputsseceseeesceeeeessseesssssectsseseeeesanees BG @ Instruction execution time (minimum instructions) COMMON OUtPUt sesssserrsereetseeeettetetetetetetttettetets eee at high-speed mode verre 1s @ Two clock generating circuits at low-speed mode ---:----+++-+++++1 vee bus (One is for main clock, the other is for clock function) @ Single power supply (Xp) =8MH2z costintiiasiiensenee §.5~5.5V APPLICATION $(Xipg) = 2MHZ ooo oroeeoreeeeeeeerereeeeeeeeeeeeees 2.5—6.5V Audio-visual equipment, © Power dissipation Remote control, normal operation mode (at 8MHz frequency) Camera coseeenstenstenneeeneees SOMW (Veo=5V, Typ.) low-speed operation mode (at 32kHz frequency for clock function) +*:+-++-----+--54uW (Voo=3V, Typ.) @ RAM retention voltage (stop mode) sesseettnnaeeunneeeeesnseesssseeess DOVES Vpayy S5.5V © Subroutine nesting ree B6levels (Max.) © Interrupts “= 10types, Svectors © 8-bit timer so (3 when used as serial 1/O) © Programmable 1/0 ports (Ports PO, P1, P2, P3, P§) sere nesses 6) © Input port (Port P4) seoessececeeceeeeeeeenenseneennsnesee \\ © A-D converter :-+--ss- er ereeeseseeeeeeeee Bobit, Bchannel \\ — SS = MITSUBISHI 2-368 Ate

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M37410M3-X XXFP,M37410M4-X XXFP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER FUNCTIONS OF M37410M3-XXXFP urbe taste scons @ : Instruction execution time Z __| 1s (minimum instructions, at 8MHz frequency), _ Clock frequency 8MHz (at Vec=5V10%) om e1atopes (M37410M3-XXXFP- bytes ~ ma te2byes e192byed ; MarsioMeome swees Mamary sco 2ssoves Te2étes M7 10M6-XRKP raaeeones me 2sbones Taito depiay to tabvtes - : po. Pi. 2,P3,p5 [v0 Bix Input/Output port inpu bitX1 (port P4 are in common with SEG) _ ea {C0 epi Pri : OM LCD output 4 bIXY Sonal vO 7 soi S-bit timerX4 . _ 16-bit timerX1 (combination of two 6-bit timers) _ Bias - 172 1/3 las selectable Leo contotortrver — [D¥ytale VS VA ay etegapie Common output 4 Segment output _ 24 (SEGiz~SEGzs are in common with port P4 and analog input pins Nr~INe) ‘Subroutine nesting 96 (max) — Toe extemal tors, woe tne fora Soval VO eo pt A-D interrupt, key on wake up, one software interrupt Clock generating circuit _ ‘Two built-in circuits (ceramic or quartz crystal oscillator ) Operating temperate ange =20~78t Devco scure —_—_ MOS sien gate Package 80-pin plastic molded QFP- SSS MITSUBISHI 2-370 ae

M37410M3-XXXFP,M37410M4-XXXFP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER en TTT PIN DESCRIPTION Input’ Functions Pin Name ouput unction Vee, ‘Supply voltage Power supply inputs 5V+10% to Voc, and OV to Vss. Vss CNVss | CNVss This fs connect to Vas. RESET Reset input | Input To enter the reset state, the reset input pin must be kept at a “L” for more than 168 (under norma! Voc conditions). If more time is needed for the crystal oscillator to stabilize, this “L” condition should be main- tained forthe required time. Xin Clock input Input | These are 1/0 pins of internal clock generating circuit for main clock. To control generating frequency, an + — extemal coramic oF a quartz crystal oscilator is connected between the Xn and Xour pins. Han external Xour —_| Clack output Output clock is used, the clock source should be connected the Xw pin and the Xour pin should be let open AVss _| Voltage input for A-D ‘This is GND input pin for the A-O converter Vee Reference voltage Input | This is reference voltage input pin for the A-D converter. | input | PO ~PO; | 1/0 port PO vo Port PO is an 8-bit I/O port with directional registers allowing each 1/0 bit to be individually programmed as | input or output. At reset, this por is set to input mode. The output structure is CMOS output PIg~P1z | 1/0 port Pt vo | Port Pt is an -bit I/O port and has basically the same functions as port PO, but the output structure is N-ch open drain. P2o~P2; | 1/0 port P2 v0 | Port P2 is an -bit 1/0 port and has basically the same functions as port PO and also works as the Key on wake up function with mask option P3y~P3, | 0 port PS VO | Port P3is an8-bitI/0 port and has basically the same functions as port Pt. When serial 1/0 is used, PS), 6, Ps, and Px work as Saov, CLK, Sour. and Sw pins, respectively. Also Pp, Pa, PQ}, and Pap work as | timer 4 overflow signal divided by 2 output pin (T), INT2 pin, Xcw and Xcour pins, respectively. SEG,2/P43 | Segment output Output | SEGi2~SEG;; work as input port P4 and also used by 2-bit unit as LCD segment output. s ‘“Anput port P4 | , SEG,5/P4 Input P5o9~P5z | 1/0 port PS 110 | Port P5 is an 8-bit I/O port and has basically the same function as P1. Pp, P51, P52 and PS, are in common with INT5, timer3 input, timerS input and A-D trigger input respectively. PSx~PS; are also in common with | PwMo~PWM3. Vir~Ves | Vottage input for Lcd | Input | These are voltage input pins for LCD. Supply voltage as OV=VisVi25VisSVec: O~VisV Is supplied to Leb. COMo~ | Common output Output | These are LCD common output pins. At 1/2 duty, COM; and COMs pins are not used. At 1/3 duty, COM; is COM; not used. SEGo~ ‘Segment output Output These are LCD segment output pins. SEG SEGw/INy_| Segment output VO | SEGje~SEGzs work as analog input pins INr~INo- s /Analog input SEGyp~SEGia are used by 2-bit unit and SEG2~SEGz3 by 4-bit unit. SEGr/INy { i % MITSUBISHI 2-371

M37410M3-XXXFP,M37410M4-XXXFP M37410M6-XXXFP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER BASIC FUNCTION BLOCKS SFFF i, are vector addresses used for reset and interrupts (see interrupts chapter). Addresses 0000;¢ to OOFF;. are MEMORY the zero page address area. By using zero pege addres- A memory map for the M37410M3-XXXFP is shown in sing mode, this area can also be accessed with 2 bytes. Figure1. Addresses 2800, to 3FFF;, are assigned for the | The use of these addressing methods will greatly reduce built-in ROM area which consists of 6144 bytes. Addresses _the object size required. 2000;. to 3FFF\\, are assigned for the built-in ROM area The RAM, I/O port, timer, etc. addresses are already which consists of 8192 bytes for M37410M4-XXXFP. assigned for the zero page. Addresses 0000;¢ to OOBFi¢ Addresses 1000,_ to 3FFF,. are assigned for the built-in are assigned for the built-in RAM which consists of 192 ROM area which consists of 12288 bytes for M37410M6- bytes. Addresses 000015 to OOBF ig and 0100i¢ to 013F 16 are XXXFP. Addresses 3F00;. to 3FFFi5 are a special address assigned for the built-in RAM which consists of 256 bytes area (special page). By using the special page addressing _ for M37410M4-XXXFP and M37410M6-XXXFP. This RAM is mode of JSR instruction, subroutines addressed on this used as the stack during subroutine calls and interrups, in Page can be called with only 2 bytes. Addresses 3FF4,. to addition to data storage. + 0000. Decimal | e ° (192 bytes) 7 Q0E1y [Pot PO fagtstor™ |

7 E25

aM | O0BF 6 my 0063, || / ooes,,,rotr2 | Zo ey ACD) | 0008 / 00€ 5,6 | net | / oorsef 00046 228 ooe7ef Coes: [Popa | ‘RAM | 00E 9:5 (64 bytes) | 01" 256 OOEA| Pon pa tore. § O1SFie ka \\ Cy a M37410M6 Not used \\ OED» “XXXFP \\ OEE 5 { 200046 ri \\ 00F 0.6 | Sinmmean easter | | 2800, \\ OOF tre | \\ OOF 316 | | 3F00r6 \\ OOF 46 ROM { \\ OOF S15 for Yor (6144 bytes) | \\ OOF 7.5 woratoms |) artiows fos Special | \\ oF ee POOP M37410M3 Page | aera, \\ 00F 8,5 call Tie3aiNT: | OOF Bie INryarkesonwatewe\\ —OOFCy—{ Timer 4 latch ‘| [Rdgross & | SeiivOatme2 \\ OOFD,9| Timer S latch | [aagess | int, \\\\ OOFE ss ( aFeF., L_Agsreseni | RESET OFF 16383 | Fig. 1 Memory map

M37410M3-X X XFP,M37410M4-XXXFP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER eee CENTRAL PROCESSING UNIT (CPU) INDEX REGISTER X (X) The CPU consists of 6 registers and is shown in Figure2. The index register X is an 8-bit register. In the index regis- ter X addressing mode, the value of the OPERAND added ACCUMULATOR (A) to the contents of the index register X specifies the real The 8-bit accumulator (A) is the main register of the micro- address. When the T flag in the processor status register is computer, Date operations such as data transfer, input/out- _set to "1", the index register X itself becomes the address put, etc., is executed mainly through the accumulator. for the second OPERAND. INDEX REGISTER Y (Y) The index register Y is an 8-bit register. In the index regis- ter Y addressing mode, the value of the OPERAND added to the contents of the index register Y specifies the real address. 7 0 7 o Z S | Carry tlag | Index rodisterx | | ! —— Zero tiag 0 \\ 7 | | L____— interrupt disabie tlag __— Decimal mode tag 7 o Break flag | Index x mode flag 15. 7 0

5 Overtiow flag

Note : PC, uses 6 bits only. Fig. 2. Register structure i a MITSUBISHI Ae 2-373

M37410M3-XXXFP,M37410M4-XXXFP M37410M6-XX XFP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER ——— eee STACK POINTER (S) flag will be set to “0”. If the result is not zero, the zero flag The stack pointer is an 8-bit register that contains the will be set to “1”. address of the next location in the stack. It is mainly used —_ 3, Interrupt disable flag (1) during interrupts and subroutine calls. The stack pointer is This flag is used to disable all interrupts This is accom- not automatically initialized after reset and should be initial- plished by setting the flag to “1”. When an interrupt is ized by the program using the TXS instruction. accepted, this flag is automatically set to"1” to prevent from When an interrupt occurs, the higher 8-bit of the program other interrupts until the current interrupt is completed. The counter is pushed into the stack first, the stack pointer is SEI and CLI instructions are used to set and clear this flag, decremented, and then the lower 8-bits of the program respectively. counter is pushed into the stack, Next the contents of the Processor status register is pushed into the stack. When 4. Decimal mode flag (D) the return from interrupt instruction (RTI) is executed, the The decimal mode flag is used to define whether addition Program counter and processor status register data is pop- and subtraction are executed in binary or decimal. If the ped off the stack in reverse order from above. decimal mode flag is set to “1", the operations are ex- The accumulator is never pushed into the stack automati- —ecuted in decimal, if the flag is “O", the operations are ex- cally, so @ push accumulator instruction (PHA) is provided —ecuted in binary. Decimal correction is automatically ex- to execute this function. Restoring the accumulator to its ected. The SED and CLD instructions are used to set and Previous value is accomplished by the pop accumulator in- lear this flag, respectively. struction (PLA) . It is executed in the revese order of the PHA instruction. 5. Break flag (B) The contents of the processor status register (PS) are — When the BRK instruction is executed, the same operations pushed and popped to and from the stack with the PHP —_are performed as in an interrupt. The address of the inter- and PLP instructions, respectively. tupt vector of the BRK instruction is the same as that of the During a subroutine call, only the program counter is iowest priority interrupt. The contents of the B flag can be Pushed into the stack. Therefore, any registers that should checked to determine which condition caused the interrupt. not be destroyed should be pused into the stack manually. lf the BRK instruction caused the interrupt, the B flag will To retum from a subroutine call, the RTS instruction is be “1”, otherwise, it will be"0” used. 6. Index X mode flag (T) PROGRAM COUNTER (PC) When the T flag is “1", operations between memories are The 16-bit program counter consists of two 8-bit registers executed directly, without passing through the accumulator. PCy, and PC. The program counter is used to indicate the Operations between memories involving the accumulator address of the next instruction to be executed are executed when the T flag is “0” (i.e., operation results PCy is used 6 bits. between memories 1 and 2 are stored in the accumulator) : The address of memory 1 is specified by the contents of . PROCESSOR STATUS REGISTER (PS) the index register X, and that of memory 2 is specified by The 8-bit PS is composed entirely of flags used to indicate _the normal addressing mode. The SET and CLT instructions the condition of the processor immediately after an opera- _are used to set and clear the T flag, respectively. tion. Branch operations can be performed by testing the Carry flag (C) , Zero flag (Z), Overflow fag (V) or the 7. Overtlow flag (V) Negative flag (N) . Each bit of the register is explained —_The overflow flag functions when one byte is added or sub- below. tracted as a singed binary number. When the result ex- ceeds +127 or —128, the overflow flag is set to “1”. When 1. Carry flag (C) the BIT instruction is executed, bit 6 of the memory location The carry flag contains the carry or borrow generated by _is input to the V flag. The overflow flag is clear by the CLV the Arithmetic and Logical operation Unit (ALU) im- instruction and there is no set instruction. mediately after an operation. It is also changed by the shift and rotate instructions. The set carry (SEC) and clear carry 8, Negative flag (N) (CLC) instructions allow direct access for setting clearing The negative flag is set whenever the result of a data trans- this flag. fer or operation is negative (bit 7 is “1"). Whenever the BIT instruction is executed, bit 7 of the memory location is input 2. Zero flag (Z) to the N flag. There are no instructions for directly setting or This flag is used to indicate if the immediated operation clearing the N flag generated a zero result or not. If the result is zero, the zero

M37410M3-X XXFP,M37410M4-XXXFP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER SE INTERRUPT ‘The interrupt request bits are set when the following condi- The M37410M3-XXXFP can be interrupted from ten sources; tions occur: INT;, Timer 2 or Serial /O, INTs or Key on wake up, INT, (1) When the INT,, INTz or INT; pins go from “H” to “L” or or Timer 3, Timer 6 or A-D, and BRK instruction "L" to“H" “Key on wake up” can only be used at power down state by (2). When the levels any pin of P2 goes “L"(at power down STP instruction or WIT instruction. When one of the P2 is mode) “L", an interrupt occurs. (3) When the contents of timer 2, timer 3, timer 6 or the These interrupts are vectored and their priorities are shown counter of serial 1/O goes “0” in Table 1. Reset is included in this table since it has the When the two interrupt requests, which are the same prior- same function as an interrupt. ity and are at the same sampling, the priority process is When an interrupt is accepted, the contents of certain reg- processed by interrupt request distinguish register 1 and 2. isters are pushed into specified locations, as discussed in These request bits can be clear by a program but can not the stack pointer section, and the interrupt disable flag (1) __be set. The interrupt enable bit can be set and clear by a is set, and the program jumps to the address specified by program. Since the BRK instruction interrupt and the timer6 the interrupt vector, and the interrupt request bit of the in- or A-D, interrupt have the same vectored address, the con- terrupt control register or timer control register is cleared _tents of the B flag must be checked to determine if the automatically. The reset interrupt is the highest priority in _ BRK instruction caused the interrupt or if timer 6 or A-D terrupt and can never be inhibited. Except for the reset in- generated the interrupt. terrupt, all interrupts are inhibited when the interrupt dis- Table 1. Interrupt vector address and priority. able flag is set to “1", Ail of the other interrupts can further be controlled individually via the interrupt control register ——_ierupt_} _ Priory Vector adoress

1 RESET 1 SFFF 16, SFFEi6

shown in Figure 3. An interrupt is accepted when the inter- at a an it 4 1 2 16 BFF 16 rupt enable bit and the interrupt request bit are both “1 “Serial v0 ortimer? [3 | 3FFBie, OF FAyg and the interrupt disable flag is “0 INT, or key on wake up 4 1 SFFS:0. SFB: INTe or timer 3 5 3FF7;6, 3FFE16, Timer 6 or A-D (BRK) 6 3EFS:6, 3FF 46 2 2 imerupt request istingush register 1 (OOEBg adcross) B17: Seria /0 nierupt request Dt

16 Serial 0 itorupt ena bit

BUS © Timer 2 interrupt request bi

4 Timer 2 nterupt enable bt

B3 INTs interrupt request bt

2 INT, interrupt ensble Bit

———— Bt | Timer 3 wterupt request Dt Myo wet Oe er ress) 7 ° BNO Teer interrupt enable bt Invert request disinguin register 2 (OOF, acaress)

45 INTs inteupt request it

4 INT, interept nadie it

| Lu t3 | AD iterup cequest Bt LS f8t2 | AD mtr enste bit BAT Ter 6 interupt request bit _ 10 Timer 6 ntrupt enable ot Lo

7 Interrupt contl register (OOFE, adaress)

7 of lec conto’ agiter 17 INT, interrupt request BS INT, terrupt enable Bt BS INT, or Key on wake up iterupt request bit ; | BIA INT, of Koy on woke Up intrupt enable bit -<G— itl 13 = |NT, or timer 3 tart cequest it TOQhk= iL =INT, oF timer 3 sntrrpt enable it | a Bit! : Timer 6 oF A-D interrupt request bit LqQe=— [BAO : Timer 8 of A-D interrupt enabie it | 7 2 “Timer can! register (OOFF « Adcess)

1847 Seni /O or tmer 2 menus aquest bt

{U6 : Seni /0 or mer 2 interupt erable bt | terug Inarupt sabe ag! L pese | Fig. 3. Interrupt control lan nn i

4 MITSUBISHI

M37410M3-XXXFP,M37410M4-XXXFP M37410M6-XXXFP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER eee TIMER register must be set to “0” (prohibition). And also bit 4 of The M37410M3-XXXFP has six timers; timer 1, timer 2, tim- _the interrupt request distinguish register! must be set to er 3, timer 4, timer 5 and timer 6. “1". For more details on the STP instruction, refer to the A block diagram of timer1 through 6 is shown in Figure 4. oscillation circuit section. The count source for timer 1 through 3 can be selected by using bit 2, 3, 4 and 5 of the timer control register (address OOFF,s), as shown in Figure 5. All of the timers are down count timers and have 8-bit latches. When a timer reaches “0” and the next count pulse is input to a timer, the con- tents of the reload latch are loaded into the timer. The divi- sion ratio of the timer is 1/(n+1), where n is the contents of timer latch. Timer 2, 3 and 6 has interrupt generating functions. The timer interrupt request bit which is in the interrupt disting- uish register 1 or 2 (located at addresses O0EB,, and 00F0,¢ respectively) is set at the next count pulse after the timer reaches “0” (see interrupt section). The starting and stopping of timert is controlled by bit 7 of the interrupt distinguish register 2, timer 3 by bit 6 of the in terrupt distinguish register 2 and timer 4 by bit 3 of timer 4, 5 and 6 mode register (00F8,, address). If the correspond- ing bit is “O". the timer starts counting, and the correspond- ing bit is “1”, the timer stops. The timer4 overflow signal di- vided by 2 can be outputed from port P33 by setting the bit 4 of the serial I/O mode register (0OF6,¢ address) to “1”. Timer 5 and 6 work as timer mode, event counter mode and PWM mode by changing the contents of bit 5 and bit 6 of the timer 4, 5 and 6 mode register. (1) Timer Mode This mode is the 16-bit timer, and the count source is $/4. When the bit 6 of PWM control register (00F3,, address) is “1", the timer6 overflow singnal divided by 2 is output from NT, pin (common with P52). (2) Event Counter Mode The count source is input from the CNT; pin. The count de- cremented each time the input goes from “L” to "H”, (3) PWM Mode As shown in Figure 7, the output wave is controlled by the contents of the timer latch of timer 5 and 6. PWM output can choose among PWMO, PWM1, PWM2 and PWMS by bit 0, bit 1, bit 2 and bit 3 of PWM control reg- ister. When the count value-of all timers, from timer 1 to timer 6, are read, be careful not to change the input source. When the count source is inputed from the external pin, the minimum pluse width should be 8s. After a STP instruction is executed, timer 2, timer 1, and the clock (¢divided by 4) are connected in series (regardless of the status of bit 2 through 5 of the timer control register). This state is canceled if timer2 interrupt request bit is set to. “1", or if the system is reset. Before the STP instruction is executed, bit 7 of the interrupt request distinguish register2 (timert count stop bit), bit 5 of the interrupt request dis- tinguish registert, and bit 6 and bit 7 of the timer control SSS

M37410M3-X XXFP,M37410M4-XXXFP M37410M6-XXXFP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER EE Data bus Xen _ [| iF, Cea overow tag AS > overtiow OG —-$ +s ire Lepck = 5 Select gate : at reset, shaded side is connected, Cary | ' & Timer 2 interrupt request bit IF2. Interrupt request distinguish register 2 mer ian TM. Timer control register TC! Timer 4 5,6 mode register WC | PWM control register a SM _: Serial 1/0 mode register = Timer 3 interrupt request bit PS,/CNT, [4 TI PS0/Scux 6-4 A Praca Serial 1/0 interrupt request bit a) , SS, SM: SMs SM ial P3s/Sour > Pl Sw age I Cae} P3;/Snov —] & | ae | Tes Timer 4 tatch (8) | Overtiow flag S ia P3,/T 4 ts Timer latch (8) PS/CNTs “a. =oon D TT wd a oe > i Wo poll D> L_timer6(@)__ J Timer i interrupt P5./PWMO q 8 we, {7} : P5S./PWM1 J WC, P5_/PWM2 q WC; PS,/PWM3 qd Fig. 4 Block diagram of timer 1 through 6 | a MITSUBISHI 2-377 oateee

M37410M3-XXXFP,M37410M4-XXXFP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER 2 ° Timer control register (Address OOFF,_) Processor mode bit 00 : Single-chip mode . | 01 : Not used | 10: Not used | 11: Not used } | Timer 1 count source selection bit 0: Bdivided by 4

1 Clock for clock function (Xcin)

Timer 2 count source selection bit 0: Timer 1 overtiow

12 Clock for clock function (Xem)

Timer 3 count source selection bit 00: pdivided by 4 01 : Timer 2 overtiow 10: CNT, input Serial 1/0 or timer 2 interrupt enable bit 0 : Interrupt inhibit 1: Interrupt enable Serial 1/0 or timer 2 interrupt request bit 0: No interrupt request 1: With interrupt request Fig. 5 Structure of timer contro} register 7 ° Timer 4,5,6 mode register (Address 00F 8,4) | | \\_INT, input polarity selection bit | | 0: Interrupt request by falling edge | 1: Interrupt request by rising edge | INT? input polarity selection bit | 0: Interrupt request by falling edge | 1 : interrupt request by rising edge -—— INT, input polarity selection bit 0 : Interrupt request by falling edge | 1: Interrupt request by rising edge | Timer 4 count stop bit ©: Count start 1: Count stop 0: No timer 4 overtiow L 1: With timer 4 overtiow

1 Timer 5,6 mode bit

00 : Timer mode 01 : Event counter rode 10 : Pulse width measurement mode (count source ¢/4) 11 : Pulse width measurement mode (count source is overflow of timer 4) Timer 5,6 count stop bit 0: Count start 1: Count stop Fig. 6 Structure of timer 4,5,6 mode register SSS

M37410M3-XXXFP,M37410M4-XXXFP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER SSS PWM Figure 6 shows the structure of timer 4,5,6 mode register, M37410M3-XXXFP has a pulse width modulated (PWM) Figure 7 shows the PWM rectangular wave form and Figure ‘output control circuit connecting with timer5 and timer6. 8 shows the structure of PWM control register. 7 oO PWM wave form 1 timer 6|0" timer 5 PWM control register timer 5+timer 6 (00F3;s address) P5,/PWMO selection bit 0: PS. | 1 PWMO Fig. 7 PWM rectangular wave form | pou ail selection bit | ? Bat P5./PWM2 selection bit 0: PSs 1? PWM2 P5,/PWM3 selection bit 0: PS; | 1 PWM3 0: PSs 1:si6 Timer 1 overtiow flag P52/ONT2 selection bit 0: PS, TECNT: Fig. 8 Sturcture of PWM control register i TTT EEIIEIIEIEIIIEIEIIIISISSSS SSS MITSUBISHI ae 2378

M37410M3-XXXFP,M37410M4-XXXFP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER SERIAL VO (11), the internal clock ¢ divided by 4 becomes the clock. The block diagram of serial I/O is shown in Figure 9. In the _Bits 2 and 3 decide whether parts of P3 will be used as a serial I/O mode the receive ready signal (Sgoy), synchro- serial 1/O or not. When bit 2 is “1”, P3g becomes an 1/O pin nous input/output clock (CLK). and the serial 1/0 (Sour, of the synchronous clock. When an internal synchronous Sww) pins are used as P3;, P35, PSs, and P3,, respectively. clock is selected, the clock is output from P36. If the exter- The serial 1/0 mode register (address 00F6;,) is an 8-bit _nal synchronous clock is selected, the clock is input to P3s. register. Bit 1 and 0 of this register is used to select a syn- And P3, will be a serial output and P3, will be a serial in- chronous clock source. When these bits are (00) or (01), put. To use P3, as a serial input, set the directional register an external clock from P3¢ is selected. When these bits are _bit which corresponds to P3,, to “0”. For more information (10), the overflow signal divided by two from timer 3 be- _on the directional register, refer to the /O pin section comes the synchronous clock. Therefore, changing the tim- _To use the serial 1/0, bit 2 needs to be set to “1”, if it is “0” er period will change the transfer speed. When the bits are P3g will function as a normal 1/O. Bit 3 determines if P3; is Divider Internal clock # From internal clock _ divided by 4 or NY ti 2 of CNT, input Pa Cg me FOF NTH ne Interrupt request y Prescaler (Agureve OOFB.) distinguish register 1 pre DU Interrupt request ae Cpt [r= distinguish register La HD Transfer clock oe moe tall «| pete ma O [ty | babs J COLT T Ticino (Address 00F 6.) 00: 2] extemal cloak 10 : Timer 3 overflow signal divided by 2 11: Timing ¢ divided by 4 '_—— Serial 1/0 port selection bit (P3s, P35) 0: Normal 1/0 port 1: Serial 1/0 port Spov signal output selection bit (P3;) 0: Normal 1/0 port 1: Spoy signal output pin i | Fig. 9 Block diagram of serlal I/O MITSUBISHI 2380 ate

M37410M3-X XXFP,M37410M4-XXXFP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER OO used as an output pin for the receive data ready signal (bit the LSB. After the transfer clock has counted 8 times, the 3="1", Spoy) or used as a nomal I/O pin (bit 3="0"). serial /O register will be empty and the transfer clock will The function of serial 1/O differs depending on the clock remain at a high level. At this time the interrupt request bit source; externa! clock or internal clock. will be set. Internal Clock ~ The Saoy signal becomes “H" during External Clock — If an external clock is used, the interrupt transmission or while dummy data is stored in the serial /O _ request bit will be set after the transfer clock has counted 8 register. After the falling edge of write signal, the Saoy sig- _ times but the transfer clock will not stop. Due to this nal becomes low signaling that the M37410M3-XXXFP is reason, the external clock must be controlled from the out- ready to receive the external serial data. The Smpy signal side. The external clock should not exceed 250kHz at a goes “H” at the next falling edge of the transfer clock. The duty cycle of 50%. When the external clock is chosen, the serial I/O counter is set to 7 when data is stored in the se- P35 pin must be held at “H” level while the serial 1/0 is not rial 1/0 register. At each falling edge of the transfer clock, used. serial data is output to P33. During the rising edge of this Timing diagrams are shown in Figure 10, and connection clock, data can be input from P3, and the data in the serial between two M37410M3-XXXFP's are shown in Figure 11. V/O register will be shifted 1 bit. Data is output starting with Srremenesse"* TLE LL LL LI LL LL) | \\ 1 Serial 1/0 register write \\ \\ signal : i Sevaivo cos G3 9 Ce) 0 OD 3 OE i { Serial 1/0 input J t Su _X_ XXX XXX) Receivable signal Ee Al ee Interrupt request bit set Fig. 10 Serial 1/0 timing | ee i MITSUBISHI 2-381 Jes

M37410M3-XXXFP,M37410M4-XXXFP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER OO ‘Sending side Receiving side Serial WO mode register = Serial mode register P3, — P3, Set the drectiona syncvanaus coc Sethe drectona register for P3; pin PB5 P36 register for P3, pin ~ | ~ P35 P3, Fig. 11. Example of serial 1/0 connection 7 0 ‘Serial /O mode register (SM) (00F6,_ address) | Symetronous clock selection bit 00: | x | 2 } exer! lock 10 : Timer 3 overtiow signal divided by 2

11 Timing # divided by 4

| —-— Serial I/O port selection bit (P35, P3_) | 0 : Normal 1/0 port | | 1: Serial 1/0 port | —— Saoy signat output selection bit (P3;) | | 0: Normal 1/0 port 1: Saoy signal output pin ———— T/P33 selection bit 0: Normal 1/0 por tt Xcm- Xcour/P3p, P3; selection bit 0 = Normal I/O port 1: Kem: Xcour Lneystom clock operation bt 0: HALT

1 Operation

INT, input evel Note : We say the unsystem clock, which is not chosen as the system clock of Xw-Xour Of Xcw-Xcour- Fig. 12 Structure of serial 1/0 mode register MITSUBISH 2382 Pe

M37410M3-XXXFP,M37410M4-XXXFP M37410M6-XXXFP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER NTRS LCD CONTROLLER/DRIVER duty ratio is 1/(n+1). The M37410M3-XXXFP has internal LCD controllers and Address 00C0;5~ 00CBy¢ is the designated RAM for the drivers. A Block Diagram of LCD circuit is shown in Figure LCD disptay. When 1s’ are written to these addresses, the 15. The terminals for LCD consist of 4 common-pin and 24 corresponding segments of the LCD display panel are segment-pin, SEG,2~ SEGis are in common with input P4. turned on. A map of the LCD display RAM is shown in Fi- Also SEGs~SEGzy are in common with INo~IN7.These are gure 13. selected by bit 3~7 of the LCD segment control register © The ON/OFF function for the LCD controller is controlled (Q0F4,¢ address). Two biases (1/2 and1/3) can also be _by bit 3 of the LCD mode register (LM3). When this bit is selected. When bit 2 of the LCD mode register is “1", 1/2 “1” all the segments of the LCD are turned on. When this bias is selected, When bit 2 is “O", 1/3 bias is selected. _ bit is “O” all the segments are turned off. 1,1/2,1/3, of 1/4 duty cycle can also be selected. When _—The structure of the LCD mode register is shown in Figure bits 0 and 1 of the LCD mode register (LMo, LM;) isn, the 14. Bit 7 o jo | o = T T (00F5,¢ address) ov fats 2 rif Duty ratio selection bit Hehe | 00 1/1 ey cs [7 t7 i? He ete 6 [6 | 01 : 1/2 duty es [ulin 10 | 10 1121/4 duty je | 13 | 13 12 | 12 | 12 Bias selection bit c7 15 15 | 15] 15 | 14 | 14 | 14 | 14 0:1/3 bias ce |wiwly 16 | 16 | 1 51/2 bias ig [19/19 peers ie | 18 | LD turn on bit ca | 2 | 21 | 21 | 21 | 20 | 20 | 20| 20 | | 0: Of [ce | 23 | 23 | 23 | 23 | 22 | 22 | 22 | 22 | | 1:00 os = 2 2 @# = 2 | ———— Xour/SYNG selection bit 2222 3 2 3 z | 0: Xour 8 888 38 8 8 8 | 1 sync 00 | Xin/16- ‘Number in data memory area indicates corresponding segment. OT: Xy/4 10 : Xcww/2 (back to Xw/16) Fig. 13 Map of RAM for LCD segment 11: Kery/2 (back to Xw/4) External A-D start enable bit 0: tohibit 1: Enable Fig. 14 Structure of LCD mode register | MITSUBISHI — i te 2-388

M37410M3-X XXF P,M37410M4-XXXFP M37410M6-XXXFP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER x El __. g ° oR “fH é B 08 +|_tay 08 e | 2 ge 08 ancl ; _ : OF oe | =28 OF =] os - 33) <2 a [fe ral ge ye) of 3 hp 7 ko gZ Kye or ; Loge W313 of 3 é as Ke He] s-—4--- --- ° | + --- <-- mn 3 2 a Bs | 2 Ce a 29 oN] Stes a8 8 2? a 2 8}. EF —O9 — ate o_o ( = a = =e > ° ii Fig. 15 Block diagram of LCD control circuit | Se 2-384 fe IESH ELECTRIC

M37410M3-X XXFP,M37410M4-XXXFP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER A-D CONVERTER 7 0 The A-D converter circuit is shown in Figure 16. The analog i Segment contro! register input ports of the A-D converter (INo~IN7) are in common (00F 445 address) with the segment output ports. ; The segment control register is located at address 00F4,.. Analog put selection bit One of the eight analog inputs is selected by bits 0, 1 and or : ne w : He 2 of this register. The IN pins, not to use as analog input, GIO:INe 110 iN, uses as LCD segment output. ON INs 111: IN; Bit 0, 1 and 2, and corresponding to analog input pin is SEG,5~SEGio/INo~INs selection bit shown in Figure 17. A-D conversion is accomplished by first | 0: INo~IN5 selecting bit 0 and 1 of the A-D control register (address i 1: SEGp5~SEGz0 Q0F2,6) for the source of Vacr. And also the analog input | JN Ne se bit pin is chosen by the analog input select bit of the segment | SEG ena "Na. INs selection bit control register. A-D conversion starts by writing a dummy | 1 sec, + SEGrs data to the A-D register (address O0EF,g) or changing the | input level from SIG pin “H” to “L”. When A-D conversion is L______ s€4,, S€@,6/INe, IN; selection bit finished, an interrupt is generated. After A-D interrupt is 1 Ne IN accepted, the result of A-D conversion can be read from + SEG, SEGie the A-D register. SEG, SEG,2/P4a, Pay selection bit 0: Pa, Pay 1: SEG,3, SEGy2 SEG5, SEG,4/P4p, P4, selection bit 0: Pao, Pay 1: SEGis, SEG Fig. 17 Structure of segment control register ‘Segment control register (00F 4,5 address) A-D control +0 circuit ‘A-D control register NO 4 § (00F2\\5 address) wo 4 Ls Yee np sleten E 1: On WO | H Siecessve = approximation Ny 4 3 register “ |_| é (QDEF; address) 0: Vaee pin Ns 4 3 1 Vee INeO) 4 | $ i sO 4 | fuss ° Veo i vnae® bye | Fig. 16 A-D converter circuit MITSUBISHI 2-385 ooteee

M37410M3-XXXFP,M37410M4-XXXFP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER SSeS KEY ON WAKE UP ‘As shown in Figure 19, if the key matrix of active “L” to in- “Key on wake up” is one way of returning from a power _put port P2 is constructed, the microcomputer is returned to down state caused by the STP or WIT instruction. normal operating state by the key push. Refer to the sec- ‘When the key on wake up option of port P2 is designated _tion of interrupt how to use the key on wake up function. In and key on wake up interrupt enable bit (IC,) is setto“1", order to enter the power down state generated by the STP if the key on wake up option pin of port P2 has “L” level or WIT instruction at the interrupt disable flag (1) is “0” and applied, key on wake up interrupt is generated and the {Cz is “1”, the input designated as key on wake up by op- microcomputer is returned to the normal operating state. tion in port P2 must be all “H”. ‘When the bit 4 of PWM control register (address 00F3;,) is set to “1”, the pulse shown in Figure 18 is outputed from P5s pin. Timer 1 and Timer 2 count P5,/SIG pin ~ Lf Key on wake up input Stand-by release Fig. 18 Output from the SIG pin at wake up from the stop state

9 MITSUBISHI

M37410M3-X XXFP,M37410M4-XXXFP M37410M6-XXXFP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER SE LEE TTT LLY se on wate up resister ea! (O0EE, address) Grectchal register P2; os [|] D> e{ 1 nese t> Option ' 1 ' ' ' 1 ee Srectonal register Peat 72 data asf] D> Option Port P2g p Grectional register Pl (Note) FL > Option Port Pe Note : Pull-up transistor (mask option) Fig. 19 Block diagram of port P2 and example of wired at used key on wake up i | i i MITSUBISH! — oeteee 2-387

M37410M3-XXXFP,M37A1 OMe ea NEe 37410M6-XXXFP SINGLE-CHIP 8:BIT_ CMOS MICROCOMPUTER RESET CIRCUIT then returned to “H” level. The M37410M3-XXXFP is reset according to the sequence The internal initializations following reset are as shown in shown in Figure 22. It starts the program from the address Figure 20 regardless of the status before reset (including formed by using the content of address 3FFF,¢ as the high stop mode or wait mode) order address and the content of the address 3FFE;. as the An example of the reset circuit is shown in Figure 21 low order address, when the RESET pin is held at “L" level When the power on reset is used, the RESET pin must be for no less than 16 4s while the power voltage is between input “H” after the oscillation of Xjy-Xour becomes stable. 4 and 5.5V and the crystal oscillator oscillation is stable and (1) Pat PO directional register (00) (Ety)= [Og (2) Pat Pt rections register (01) (E5y)~[ Oe | (3) Pon Pe directional register (02) (E5u)~| Oe 8) Port P3 directional register (03) (E96) | | 16) Ieraptequest distinguish register 1 (EB.)~-[ we —_—| M37410M3-XXXFP (6) PWM conta register (#3 | Jofo|o[o]o]o\\0! (8) Segment conral register ——_(F&gh~ [010000 -[-[- — “ 8.00 mode register (ru [ Oe (1% Interrupt control register (IM) {FE,6): iz O06 ~ | (8 AD conta eit wo TLL | Lele) (6 Prcestr stats register EFEEo iE] A Progam counter (Pon) | Saeco] iatate unde ttveetiseacaioey ecb! Fig. 21. Example of reset clrcult Fig. 20 Internal state of microcomputer at reset | a _ MITSUBISHI 2-388 Jae

M37410M3-XXXFP,M37410M4-XXXFP M37410M6-XXXFP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER ow) UU JS °}iUii_ Js ote > iiagtiting dag $ -afane AY RESET Internal RESET + SYNC Reset address trom Data C2 XPEuX PX PSX ADLAD) ‘mevesorsane 32~48 clock cycles Note 1: Frequency relation of (Xm) and gis (Xiu) =16- ¢. 2: The mark “?” means that the address is change- able depending upon the previous state. Fig. 22 Timing diagram at reset i

M37410M3-XXXFP,M37410M4-XXXFP M37410M6-XXXFP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER VO PORTS up to Vis. Just after the reset, this becomes high- (1) Port PO impedance state. Port PO is an 8-bit I/O port with CMOS outputs and —_(9)._ Common output(COMy~COMs) pull-up transistor options available. As shown in Figure These port provides output drive and control for the 1, PO can be accessed as memory through zero page LCD common lines. At reset, this outputs the level of address O0EQ;s. Port PO's directional register allows Vis. each bit to be programmed individually as input or out- 0) Power Supply for LCD(Vi1~Via) put. The directional register (zero page address Supplies power to the LCD terminals. 00E1,¢) can be programmed as input with “O", or as (Il) INT; output with “1”. When in the output mode, the data to The INT, pin is an interrupt input pin. The INT, inter- be output is latched to the port register and output. rupt request bit (bit 7 of address OOFE;,) is set to “1” When data is read from the output port, the output pin when the input level of this pin changes from “H” to “L” level is not read, only the latched data of the port reg- (or “L" to "H"). This input level is read in the bit 7 of ister is read. Therefore, a previously output value can serial 1/O mode register (addresss 00F6,.) be read correctly even though the output voltage level (12) INT2(P3,/INT2) has been shifted up or down. Port pins set as input are The INT? pin is an interrupt input pin common with P3, in the high impedance state so the signal level can be When P3,'s directional register is set for input (“0”), read, When data is written into the input port, the data this pin can be used as an interrupt input. The INT. in- is latched only to the output register and the pin still terrupt request bit (bit 3 of address 00EB,.) is auto- remains in the high impedance state matically set to “1” when the input level of this pin (2) Port P1 changes from “H” to “L" (or from “L" to “H") Port P1 has the same function as PO but the output — (18) INTs(P59/INTs) structure is N-ch open drain. The INT, pin is an interrupt input pin common with PSg, (3) Port P2 The other functions are the same as INT. Port P2 has the same function as PO. Following the ex- ecution of STP or WIT instruction, key matrix with port P2 can be used to generate the interrupt to bring the microcomputer back in its normal state. The pin to be used as the key on wake up must be with key on wake up option and its value in directional register must be “or (4) Port P3 Port P3 has the same functions PO except that part of 3 is common with the serial 1/0, output of timerd, clock oscillation of timer clock and interrupt input. The output is N-channel open drain. When P3y and P3, pins are used for Xcin input, pull-up is inhibited (5) Port P4 Port P4 is an 4-bit input port which can be used as a segment output port. At reset, this port is pull-up to Vis. Just after the reset, this port becomes high-impedance state. When port P4 is used as input port, the pull-up option to these pins are inhibits. (6) Port PS Port P5 has the same functions as PO except that part of P5 is common with the counter input pin, SIG pin, and PWM output pin. The output is N-channel open drain output. (7) Segment output(SEGo~SEG;) These ports drive and control the LCD segments. At reset, these output the level of Vis. (8) Analog input(INo~IN;) This is a port for an analog input of A-D converter. This i can be used as the segment output. At reset, it is pull- i i | eee i

M37410M3-X X XFP,M37410M4-X XXFP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER LOO Oe vi Vss Port PO se Veo > ] £ ne q Cop O > Por PO q Veo Tr1 is pull-up transistor at input (mask option) Port Pt © Tr2(mask option) [econ nave] 5 4 > Data bus L> | Petr q Vss Tr2 is pull-up transistor at input (mask option) Port P2 Veo Veo v : | mask option q ve SNe 1S les 6 Data bus rT> on 2 { b Vss. Tr3 is pull-up transistor (mask option) Veo Port Pe, PSo Ne pism | ly “J nask option Data bus Port P32, PB r—— . ia — a Intemupt conto ccut Tr4 is pull-up transistor (mask option) i Fig. 23 Block diagram of ports PO~P2, P3, and P5p Bn MITSUBISHI 2. — 391 ee "

M37410M3-XXXFP,M37410M4-X XXFP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Port P35, P3;, P33, P34, P3s, Ps, PS, Veo P5,, P52, P53, P5,, PSs, Ne | a Port Pp, P3;, P33, P3,, P3s, PSs. Y Ves P37, P5,, P52, PSs, PSs, PSs, ‘Tr5 is pull-up transistor (mask option) Port P4( SEG,s~SEGi2) re OO Port P4(SEG;;~SEG,2) Tr6 is only conducted at RESET=“L". Tr7 is pull -up transistor (mask option) Fig. 24 Block diagram of Port P3, P4, P5;, P52, PSs, P54, P5s, PSs, P57 Analog input IN (SEGzs~SEGie) va FES Sve A-D converter circuit ¥ Anaiog input IN. > ( ) TrB is only couducted at RESET="L" RESET < - O_ RESET i Fig. 25 Block diagram of analog input port IN, INT;, RESET 2-300 te MTSUESH ELECTRIC

M37410M3-XXXFP,M37410M4-XXXFP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Xen Xcour oO oO LMs SMe ) >—{ » Ms Xin Xour (e) oO IF 2; LD Timer Uneyatem clock Ten source ‘operation SM selection TMz i infernal system { | le clock source [> Timing ¢ ‘Ms selection LMs. LMs (Internal Clock) oe ae sre wr al stp instwetion “tion ct Reset Inerrpt p— disable INT, interrupt enable (Titi vo une et oi INTs or key on wake up interupt enable (Titer nes arp oade INT; or timed intaupt request CT] Tiere A mre Timer6 or A-D interrupt request fl Fig. 28 Block diagram of clock generating circult MITSUBISHI 234 ote

M37410M3-XXXFP,M37410M4-XXXFP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER —___ SSS Si=0 SM.=0 tMs=0 wit A LMe=0 c wit BMHZ oscliaton Por MHfNNormal mode]] LMs="1"—"0" Figt-speea moce Jot te cstan 2kHz stop fui ectan I osctation | easton gestop 32kHz stop f LMs="0"-91" ]] s2kHz ze | Timers, kt | saad ti LCD action Jrterupt ga 500kHz If Hi 2MH2 iterupt LLED action STP instruction STP instruction Interrupt ‘interrupt aMitz stop Interrupt Interrupt TP instruction STP inetruction wit B o wit WIT tin — sprcttuctio 8MHz stop ‘8MHz oscillation sont oecilshon JBMHz oscilation| Mento" 8MH2 osciltion ‘32kH2 oscillation ¢=stop 32kHz oscillation S2kHz oscillation g=stop Timers, ¢=500kHz =" ~ g=2MHz Timers, . TO Len action Frrerupt H I oS ierrupt L_LED action @ G x G ". KA ES) oN Ne SOLE ON, CLE DWN. wn MV, WMO IN. wy wit E ‘STP Sry ae fosinctod a a '32kHz oscillation |8MiH2 oscillation top p stop [S2kHz oscillatior 32kHz stop Timers, 9=16kHz stop Led action Tisterrupt Ul Taterrupt SG wr Ff | yoste ow _ Trock mode PaSMUtoTGw-speedpMstUctiCN Ce stop {32kHz oscillation| mode stop emi stop okie stop Timer, LCD i na ‘stop ; Text | [L_sction Winerupt 2 Wiriorrupt eed The case of example clock Xay=8MH2, clock Kons kHz Note: Atthe end of STP instruction, wait time eccurs automaticaly by connection of timers 1 and 2 and changing system clack. This time is set by program, When SMe and unaystom clock is operated, wat time necessary by program uni osiaion becomes stable Return to the normal mode once in cate changed Io the low-speed mode frm the normal mode sito return othe high-speed mode once incase changed to he low-speed mode ram the high-speed made i Fig. 29 Transition of states for the system clock ! i MITSUBISHI eee 2396

M37410M3-X XXFP,M37410M4-XXXFP M37410M6-XXXFP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER PROGRAMMING NOTES (8) When LCD trun-on bit (bit 3 of address 00F5,¢) of the (1) The frequency ratio of the timer is 1/(n+1). LCD mode register is “1”, don't stop the timers or count (2) The count value of timers 1, 2, 3, 4 can be read at an source for timers. arbitrary timing when the timing ¢ divided by 4 or timer _(9)_ After switching the serial 1/O transfer clock, initialize overflow is input to these timers. If Xo or CNT; input the serial I/O counter (write to address 00F7;¢). is input to these timers, the value of timer 1, 2, 3, 4 0) To use an external clock as the serial 1/O transfer must be read only when the input of timers is not clock, initialize the serial I/O counter when the external changing or the timer count is stopped. clock is “H” level. ‘Also the count value of timers 5, 6 which are used in _{Il)_ To use the P3 and P3, pins as the 1/0 pins of the the event counter mode must be read when the exter- clock for clock function, do not use the pull-up resistors nal input is at the “L” level. When timers 5, 6 are used by option. in the timer mode, the count value of these timers can- not be read. DATA REQUIRED FOR MASK ORDERING (3) Even though the BBC and BBS instructions are ex- _ Please send the following data for mask orders. ecuted after the interrupt request bits are modified (by (1) mask ROM confirmation form the program), those insructions are only valid for the (2) mark specification form contents before the modification. Also, at least one in- (3) ROM data +. 3. eer EPROM Ssets sturction cycle must be used (such as a NOP) be- Write the following option on the mask ROM confirmation tween the modification of the interrupt request bits and form the execution of the BBC and BBS instructions. + Port PO pull-up transistor bit (4) © After the ADC and SBC instructions are executed (in * Port P1 pull-up transistor bit decimal mode), one instruction cycle (such as a + Port P2 pull-up transistor bit NOP) is needed before the SEC, CLC, or CLD in- —* Port P3 pull-up transistor bit structions are executed. + Port P4 pull-up transistor bit @ In decimal mode, the negative (N), overflow (V) and * ‘Port PS pull-up transistor bit zero (Z) flags are invalidated. * Port P2 key on wake up {5) A NOP instruction must be used after the exection of a PLP instruction. (6) © The timer 1 and timer 2 must be set the necessary value immediately before the execution of a STP in- struction. Also the following conditions must be satisfied: * Timer 1 count stop bit is set to “0” + Timer 2 interrupt enable bit is set to “1” + Timer 2 interrupt request bit is set to “0” + Serial I/O or timer 2 interrupt enable bit is set to “0” * Serial 1/0 or timer 2 interrupt request bit is set to “0” @ To restart oscillation when it is stopped by STP in- struction or unsystem clock operation bit, wait for a specified time which is needed for the oscillator to stabilize. (7) Some instructions can be used to write contents of the timer control register, the interrupt control register and interrupt request distinguish register 1, 2. If the SEB or CLB instruction or a set of instruction that acts as the SEB or CLB instruction (for instance, LDA TC+SE8 7, A+STA TC) is used, an interrupt request which is input during execution of these instructions may be cleared. Therefore, these instructions should be used onty when ' there is no problem even if such an interrupt request is | cleared. Usually, the LDM or STA instruction is used | Use the LDA instruction (IMM, T=1) to write to inter- | rupt cause recognition register 2 only when A-D inter- | rupt or timer 6 interrupt is used. | = MITSUBISHI 2-396 aE

M37410M3-XXXFP,M37410M4-XXXFP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER eee ABSOLUTE MAXIMUM RATINGS Z ~ Parameter Conditions Ratings [unt] Supply vonage LT =0.3~7 Supply voltage forLCDViy~Wis_ Sei 08 VeotH 0.3 | input voltage PQy~PO;, P2p~P2y, Pp, P3s, | | w Pay~PAy, INo~INr, Vac Xn Lo -0.3~Vec+0.3 v Input voltage CNVss =0.3-7 y, Input voltage INT, RESET, Plo~PIr, ‘Output voltage PO;~PO;, P2o~P2}, Pp, P3y, Output voRage P1e~P I>, PG;~PQ;, P&y~P5, <a 3=0 Vv Pa Power dissipation ie _ 300 mw ‘Operating temperature = 20~75 c Tstg Oo =~ |e RECOMMENDED OPERATING CONDITIONS (vcc=2.5~5.5V, Vss=0V, Ta=—20~75T, unless otherwise noted) ‘Symbol Parameter ‘Conditions wn a ~ {(Xq)= 8 MHz High-speed mode 45 Vee ‘Supply voltage (Note 1} 1(Xiu)= 8 MHz Normal mode or los 55 1(Xw)= 2 MHz High-speed mode (Note 2 ) ° “ “H® input voltage ~P0o~PO;, P3p, P3;, P4y~Pas, Vw ___Xn, CNVss (Note 3) _ _ 0.7Vec) Vee ve Vin “HF input voltage _P2s~P2, OO ee Vin “HT input voltage Plo~Pty, P5~P5r. Sm _ '0.%ec| | 10 v “H" input voltage P32~P3;, Pg, INTs, INTz, INTs, Ve NTs, CNTs, SIG, CLK 0-BVce J v View “H" input voltage RESET, Xow _ _ . 0. 85Vcc) 10 v =U input voltage PO:~PO;, Pte~P ty, Pb, PS, va PP, PSi~P5, Sin ° 0-25Vec} “L input voltage P2g~P2z, P32~P3z, PSp, INT: Ve INTa, INTs, CNTs, CNTs, SIG, CLK _ ° 0.2Vec V “Linput wotage RESET. Xw. Kom _ ° 0. 15Vec.__V lon “HT output current PO)~PQ;, P2o~P2y, Xour (Note 4 ) _ =1 | ma =L" output current PO)~PO;, P2~P2r, Poo~P3, low P5o~P5z, Xour, PWMO~PWM3, 1 mA ___T. Sour. CLK, Spov, SIG (Note 5) _ | Veo™ i lou “L’ output current Ple~P17 (Note 6 ) oY oma _ ee Os - | 20 | (Xin) Clock oscillating frequency a 0.2 8.2 | MHz f(Xcy)__ | Clock oscillating trequency for clock function [30 | 50) kHz Note 1 : When only maintaining the RAM data, minimum value of Vcc is 2V. 2. We say the high-speed mode, when the system clock is chosen Xiw/4, and the low-speed mode, when the system clock is chosen Xww/16. 3: When P3, is used as Xew, Vix and Vy of P3; is 0.85VccSVinSVcc and OSV_ S0-15Voc. 4.1 The total lowipeak) of port PO, P2 and Xour is less than 35mA. 5. The total loxcpeak of port PO, P2, P3 and PS is less than 32mA. 6 : The total peak current of lo. of port P1 is less than 80mA and the average current of total Io, of port P1 is less than 40mA.

M37410M3-X XXFP,M37410M4-XXXFP M37410M6-XXXFP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER ELECTRICAL CHARACTERICS (v.s=0v, ta=—20~75€, unless otherwise noted) a [Min [typ | Max | Vom | “Wr output votage POy~PO,, P2.~P2; Veo=BVitow=—O.Sma a Voo=3V, y= —0. 3A ee ee Vow | -¥ etput wotage ou Yee Ve low= 0.3m py Voo=3V, lon —0, IMA Ld “ouput vltage PO)~PO;, PA~P2, P=, Vom lomima Cod Vou P5e~PSr, T, Sour, CLK, an V Vo | -L-eutputvottage Pto~Pty Voc SV. qu Z0mA [oe | Yee 5¥. ton = 10a on | Voc=5V, lor=0. 3mA { [oT Vou | *L*eutput votage Xour | Moo 8V. toe O.3mA ° cp otage Nov ‘Yeo=2V, k=O. 1a [| Vou, | Peters NT, IN INTs GOK ENT, TWee=sv T4—Vr | CNTs, SIG, Sy, P20~P2) Xen Voo=3V Poet Y { ~ Voe=5V 2 /ey—Vr~ | Hysteresis RESET 4 VreTWr- | Hy Voo=3¥ { [Yo v Voc™5V_ 0.5 Ve —Vr- — | ee eee ee oe “Ep cont POy~P, Plo=Ph, P2a-Pos, PPh, Veo=5V Vi=OV f | | te Pég~P4s, PSy~P57! without pull-up Ty, (Note 1), = uA se mgt. INT, RESET Xa Veo=3V_Wi=0V —3 1 “HE input current POg~POr, P2s~P2), PS, PS), Voc=5V_Vi=5V 5 “” Po Pr INo~IN7, Xin. Kerns CNV Veo=3V_Vi=3V _ | 3 “Fpl coment (Pig~Piy, PPS, PPER wiht pulp Ty, lie INT, INT, NT, CNT, veto 10 | wa _ ONT, SIG, RESET, Su CLK | . Pleup Te, POy~PO>, Pre~Pt>, Ple~P2r, Voo=5v, VO 7[ 1%) 3% i P39~PS), Pay~ PAs, P5y~P5; Voc=v,ViEOV -2 8 | seem _[ovruinsemee con~cove hese ee} jh} a | ee ~ OtherGom,sea [Veomsv TT Rs ‘Output impedanos SEGo~SEGz3 pins are opened. Veo=3V_ ___. __ 3 | 10%) =8MHz High-speed mode Vec=5V_ | _ ci el a operation (%q)=8MHz Normal mode Vec=3V_— | 8 Xen) =32kHz, Voo=3V 18 36 lee ‘supply current v- — tT ta | | wah mage %p)=8MHz Normal mode Vee=3V | | tOXon)=32KH2, Voo=3V ee ee A | at stop mode TBC a1] o6 | ‘Vaam | RAM retention voltage 2 p56 | v | Note 1: Also the same when each port is used as INT2, INTs, CNT), CNT2, SIG, Sy and Xcin, respectively. i 2-308 fe MIeSH ELECTRIC

M37410M3-XXXFP,M37410M4-XXXFP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER EE eee A-D CONVERTER CHARACTERISTICS (Vcc=5v, Vss=AVss= 0 V, Ta=25, 1(Xm)= 8 MHz, unless otherwise noted) I Units rameter est condi L__.. | —— [Reson oo - 8 | bits. —_ Vec=Vursev Non-linearity. oro _ Vee=Vner=3, 0720 — | +2 tsB | 7 Veo=Veer=5.12V £0.9 Voo™Vaner=5. 12V 2 Vor Zero transition error _ Vee Veere3 OV - + Z| +s Voc=Vaer=5. 120 6 Vest Futscale Nransiton error _ Veo™=Vaer=3. 072 : T 10 “sB Veo=2.5~5. 5V High-speed mode OAK) te Conversion ume _ Vec™=2.5~5.5V Normal mode OK) _ “s | Veer =5V [io | 25 Iner__| Reference input corot a Poss] ™ In ‘Analog port input current | ¥w=0~Vec [a [0] na Viv | Analog input tage SSSCSC*~*~CS*~S~S Wes || Veo | V Vaer | Reterence input voltage ce es | nS Poe 2-388