M37409M2

M37409M2 MITSUBISHI | Alldatasheet

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Technical content

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

DESCRIPTION

The M37409M2-XXXSP is a single-chip microcomputer de- PIN CONFIGURATION (TOP VIEW) signed with CMOS silicon gate technology. It is housed in a 52-pin shrink plastic molded DIP (flat package type also (4-0 Vee available). This single-chip microcomputer is useful for the aE «+ PO, communication application used as a slave-microcomputer. aE = PO; in addition to its simple instruction sets, the ROM, RAM, Address bus | A> Po. | and I/O addresses are placed on the same memory map to As EDP | 110 p00 bo enable easy programming. aE [=> Po. The differences between the M37409M2-XXXSP and the a [)-+ Pos M37409M2-XXXFP are the package outline and the power |v. ay cae Ere dissipation ability (absolute maximum ratings) esd contol signal FD —> = PIs | Chip select CS —+ [Ti] rN Pt, FEATURES Dp 3 [D--Pr. | © Number of basic instructions::-: 1+ rss 69 Des s Pls | io pen Pt @ Memory size ROM ores 4096 bytes ao x [+ Pt, RAM srsseeseceeessissesssessesees 128 bytes pata bus 2 Oe EI fo] fa] +> P15 © Instruction execution time aeg 8 jor Pe 0.8,s (minimum instructions at 10MHz frequency) nant P= P tr samt © Single power supply (Xi) =10MHz “=~ 5VE10% od Boece mane © Power dissipation UART clock CLK + 2] + TxDs Transmit output normal operation mode (at 10MHz frequency) -- 50mW. ONVss j++ CTS, Transmit © Subroutine nesting =. 64 levels (Max.) Reset input RESET —* [2] — RxO2 Receive input @ Interrupts: eetteseeerens 10 types Clock input Xw—> Bl [i] —+ 1.02 Transmit output © B-bit timers soseesesesuneeesisseesesteneensereneenee J Clock output Xour Bi] a) + CTS, ere input © UART (Full-duplex) :<----eeeeee3 channels Timing output o-B = RxD, Receive input © Communication registers Outline 52P4B Access flag ---sssss setters - 192 bits IPC* semaphore register: seseereseeeereess TaD itX T gee IPC mode register" seresceeeeeeeeenseseeee BEDOK aiateettet ett IPC error register -- seeseeeeeeeee 8-bitX4 trrtrpe papi ages © Programmable 1/0 ports 7 EEE os; (Ports PO, P1, CTS;~CTS3) srereeeeeeeeee dG PO; + fa Fl px, © Bus interface Po, [=] C) =) —+ TxD, Address bus -----ssssssseessieeesssseeesessnseeesssseeeesssee yor Bis cts. Data bus sncsrnnnennennnnnnneeninien ve Ma7409M2-xxXEP aonb APPLICATION ho 3" Office automation equipment Ms <8 O O om Xour As fl— RESET

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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER FUNCTIONS OF M37409M2-XXXSP ‘Number of basic instructions ee c) - OO instruction execution time (0.818 (minimum instructions, at 1OMH2 frequency) Clock frequency Tomi ~~ TOM 4096 bytes _ a | POo~PO, vo 8-bitX1 (System bus 1/0) Input/Output ports Pie~Ptz vo B-bitX1 (Local bus 1/0, System bus input) — CTS\\~CTS: vo 1-bitX3 (Common with UART transmit control input) ~ Romy Input B-bitXT : : Z RD, WR, CS Input T-bit<3 : ART _ . 3 (with programmable baud rate generator) Timer ~ - 8-bitX1 (with B-bit prescaler) interrupt ‘System bus (IPCMO) interrupt 1, UART interrupt 6, Timer interrupt 1, Collision inter- Collision detect register 8-biX1 - ‘Subroutine nesting ~ 64 levels (max.) : ‘Supply voltage 5v+10%6 a at operation SOmW Power dissipation at wall mode Sm — - Operating temperature range . =W~70C Device structure ‘CMOS silicon gate process ~ Package [[ma7409M2-XxxSP ‘52-pin shrink plastic molded DIP _ Z ee

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER PIN DESCRIPTION | Inpuy Pn | N Funet in Jame go unctions Veo. ‘Supply voltage | Power supply inputs SV10% to Voc, and OV to Vss. Vss CNVss_— | CNVss This is usually connected to Vss. RESET | Reset input Input | To enter the reset state, the reset input pin must be kept at a “L" for more than 2us (under normal Veo | conditions). If more time is needed for the crystal oscillator to stabilize, this “L” condition should be main- | tained forthe required time Xin Cock input | Input | This chip has an internal clock generating circu To conttl generating requency, an external ceramic ora + quant enystaloscitator is connected between the Xx and Xour pins. If an external clock is used, the clock Xour | Clock output Output | source should be connected the Xw pin and the Xour pin should be left open. é | riming output Output | This is the timing output pin a | eee em P05~PO; | /0 port PO v0 | Port PO isan 8-bit 1/0 port with drectional register allowing each 1/0 bit tobe indvidualy programmed as | input or ouput. This por is connected tothe system bus only, and can not be accessed! rom the focal bus | At reset this pot becomes input mode. The output structure is CMOS output. Pron Pty [vO petes VO | Pa Pt an O18 VO pr and has bancly te sme nce a pot FO. THe po camated toe local bus and can be used as ony input port rom the systom bus. The output structre is CMOS output Ts, | UaRT ator oupa | Opa | These are UART want dal expt is ~TxD3 RxD, I UART receive input Input ‘These are UART receive data input pins. ~RxD3 GTS, | UART twanster conti | vO | These are UART transfer control signal input pins and can be used as V/O pot which have batlealy same ~CTS, | input | tuncton as port 1 CLK | UART clock input Input | This por isan extemal clock input pin for baud rate Ao~A, | Address input Input__| This port is input fr system address Do~Dr | Data input/output v0 | This port is input or output the systom data, [od Chip select Input, | System data can be read or writen by nputing “Lt ths port ia I eee on by mpwsing eine Po _ _ | | Read contol input Input | Memory or register data speciied by Ay~Ar is read trom Da~Dy by inputting “Lt this por Wie contro input Input | Data input trom Dp~D: is writen to memory oF register speciied by Ar-Ay by inputing “Lt this pod

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER BASIC FUNCTION BLOCKS MEMORY M37409M2-XXXSP has two buses; the local bus connected to the CPU of its own, and the system bus connected to the CPU of the external master computer. There are two cor- responding address area, Figure 1 shows the memory map of the local bus and the system bus, respectively The local bus has thirteen address buses and eight data buses. The address area, which is 8192 bytes, is addresses from 0000;¢ to 1FFF For this local bus area, addresses 1000;5 to 1FFFis are assigned to the built-in ROM area which consists of 4096 bytes. Addresses 1F00\\¢ to 1FFFis are a special address area (special page) . By using the special page addressing mode of the JSR instruction, subroutines addressed on this page can be called with only 2 bytes. Addresses 1FECjs to 1FFF;, are vector addresses used for the reset and inter- rupts (see interrupt chapter). Addresses 0000;¢ to OOFFi5 are the zero page address area. By using the zero page addressing mode, this area can also be accessed with 2 bytes. The use of these addressing methods will greatly re- duce the object size required. The RAM, dual port RAM, 1/O port, timer, etc., are assigned to this area. Addresses 0000;¢ to 007F;5 are assigned to the built-in RAM and consist of 128 bytes of static RAM. In addition to data storage, this RAM is used for the stack during sub- routine calls and interrupts. The system bus has eight address buses and eight data buses. The address area, which is 256 bytes, is addresses from 0046 to FF is The dual port RAM, access flag, port, IPC mode / IPC error register etc., are assigned to this area. The internal memories and registers are connected to one or both of these buses. Therefore, it is necessary, in writing programs, to know the operation of each functional block as well as to which bus the memories and registers are con- nected at what addresses a MITSUBISHI — ae aid

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Oe ERE MOS MICROCOMPUTER Decimal / 7 Girectiona 0000; 0 7 O0EI:. [Port Pr director / Teaspa aee RAM 7 00 E16 Oe OT ee reiser 0016 (128 / oe Dual-port RAM bytes) / ARTY 7 ema Zero / BIT aaa get? 0 | Access flag page 00co, 7 Access f / 00E6,5 {UARTI control register| tag / TT Sra Tatas DBse 000716) a UART? receiveliransTer 000.6 ]UART?2 mode register Fic OOEA,, JUART2 control register OOF Fie 00685 POT rene] gg, [ noma \\ avec, Tatas * [ieee ee 0200.6 \\ blr regster FO. | ora ager \\ 00ED 5 [UArrs aus ease” TRC mode egster 7 \\ 16 |UART mae es regs Dual-port RAM \\ a Faw (192 bytes) \\ O0E€ yg [UARTS contol register co, [mare over, | aATaderoTad | rarer 3 02BF \\ " fale generate Fxg | rotusea | \\ 00F 0s, [IPC mode register 0} £0, la 10006 \\ 00F 1,6 [IPC mode register! \\ 00F 2,6 |IPC mode register 2 | \\ FF ye | IPC semaphore register (re \\ 00F3,, [IPC mode register3} rec \\ 00F4, {ipo ewer register o] Address area apply to system bus «| Ragone UARTS transter = \\ OFS: JIPC error register 1 UART? wanstr a ROM —* ‘ 5 [IPC error register 2] (409 | Special | Aagress | UART! wanster, sorr,, hee = J 15 [IPC error register bytes) | Page for J Colson detect z call Address H Timer X tomo \\ * ese ‘Collision detect UARTareceve | OOFAve a \\ Tnlemupt enable UART2 receive OOF Bae [ MerUeTenabTE ‘Address L \\ Tnterrupt request UARTH receive, 00FC

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Address area apply to local bus Fig. 1 Memory map eee 2-344 9 MITSUBISHI

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER CENTRAL PROCESSING UNIT (CPU) STACK POINTER (S) The CPU consists of 6 registers and is shown in Figure 2. The stack pointer (S) is an 8-bit register that contains the address of the next location in the stack. It is mainly used ACCUMULATOR (A) during interrupts and subroutine calls. The stack pointer is The 8-bit accumulator (A) is the main register of the micro _ not automatically initialized after reset and should be initial- computer. Data operations such as data transfer, Input/Out-__ized by the program using the TXS instruction put, etc., are executed mainly through accumulator. When an interrupt occurs, the higher 8 bits of the program counter are pushed into the stack first, and then the lower 8 INDEX REGISTER X (X) bits of the program counter are pushed into the stack. After The index register X is an 8-bit register. each byte is pushed into the stack, the stack pointer is de- In the index addressing mode, the value of the OPERAND _cremented by one. Next, the contents of the processor sta- added to the contents of the register X, specifies the real tus register are pushed into the stack. When the return from address. When the T flag in the processor status register is _interrupt instruction (RTI) is executed, the program counter set to “1”, the index register X itself becomes the address are processor status register data is pulled off the stack in for the second OPERAND. reverse order from above. The Accumulator is never pushed into the stack automati- INDEX REGISTER Y (Y) cally. A Push Accumulator instruction (PHA) is provided to The index register Y is an 8-bit register. ‘execute this function. Restoring the Accumulator to its pre- In the index addressing mode, the value of the OPERAND _vious value is accomplished by the Pull Accumulator in- added to the contents of the register Y specifies the real _struction (PLA). It is executed in reverse order of the PHA address. instruction. The contents of the Processor Status Register (PS) are pushed (pulled) to (from) the stack with the PHP and PLP instructions, respectively. Only the program counter is pushed into the stack during a subroutine call. Therefore, any registers that should not be destroyed should be pushed into the stack manually. The RTS instruction is used to return from a subroutine 7 0 7 0 [| accumir Top felt fefe] Processor stats register 7 0 | | | Carry tag | register x | | | Zero tlag 7 0 Interrupt disable flag Decimal mode flag 7 0 — Break flag stack pointer —— Index X mode tlag 15 7 0 \\ | Fig. 2 Register structure a

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER eee sss an eee PROGRAM COUNTER (PC) 5. Break flag (B) The 16-bit program counter consists of two 8-bit registers When the BRK instruction is executed, the same operations PC, and PC,. The program counter is used to indicate the are performed as in an interrupt. The address of the inter- address of the next instruction to be executed rupt vector of the BRK instruction is the same as that of the lowest priority interrupt. The contents of the B flag can be PROCESSOR STATUS REGISTER (PS) checked to determine which condition caused the interrupt. The processor status register is composed entirely of flags _If the BRK instruction caused the interrupt, the break flag used to indicate the condition of the processor immediately _will be “1”, otherwise it will be “0” after an operation. Branch operations can be performed by testing the Carry flag (C), Zero flag (Z), Overtiow flag (V) 6. Index X mode flag (T) or the Negative flag (N). Each bit of the register is ex- When the T flag is “1”, operations between memories are plained below. executed directly without passing through the accumulator. Operations between memories involving the accumulator 1. Carry flag (C) are executed when the T flag is “O” (i.e., operation results The carry flag contains the carry or borrow generated by —_ between memories 1 and 2 are stored in the accumulator) the Arithmetic and Logical operation Unit (ALU) im- The address of memory 1 is specified by the contents of mediately after an operation. It also changed by the shift the index register X, and that of memory 2 is specified by and rotate instructions. The set carry (SEC) and clear carry _the normal addressing mode. The SET and CLT instructions (CLC) instructions allow direct access for setting and are used to set and clear the index X mode flag, respec- clearing this flag. tively. 2. Zero flag (Z) 7. Overflow flag (V) This flag is used to indicate if the immediate operation The overflow flag functions when one byte is added or sub- generated a zero result or not. If the result is zero, the zero _ tracted as a signed binary number. When the result ex- flag will be set to “1”. If the result is not zero, the zero flag ceeds +127 or —128, the overflow flag is set to “1”. When will be set to “0” the BIT instruction is executed, bit 6 of the memory location is input to the overflow flag. The overflow flag is reset by 3. Interrupt disable flag (1) the CLV instruction and there is no set instruction This flag is used to disable all interrupts. This is accom- Plished by setting the flag to “1”. When an interrupt, this 8. Negative flag (N) flag is automatically set to “1” to prevent other interrupts The negative flag is set whenever the result of a data trans- from interfering until the current interrupt is completed. The fer or operation is negative (bit 7 is set to “1”), Whenever SEI and CLI instructions are used to set and clear this flag, _the BIT instruction is executed, bit 7 of the memory location, respectively. is input to the negative flag. There are no instructions for directly setting or resetting the negative flag. 4. Decimal mode flag (D) The decimal mode flag is used to define whether addition and subtraction are executed in binary or decimal. If the decimal mode flag is set to “1”, the operations are ex- ecuted in decimal, if the flag is set to “0”, the operations are executed in binary. Decimal correction is automatically executed. The SED and CLD instructions are used to set and clear this flag, respectively. as SsSSSSSSSSSSSSSSSSSSSS— — MITSUBISHI ama ete

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER ee Bus Interface ter CPU, specify the address by Ap~Ar and set WR to “L”, M37409M2-XXXSP has the bus interface to operate itself and the data at Do~D> is written to the specified address. by the control signal sent from the master CPU. The master. When reading data, specify the address by Ao~Ar and set CPU can access the memories and registers located in the RD to “L”, and the contents of the specified address are system address area described below via this bus inter- output to Dp~Dy. face. The bus interface has address pins Ay to Ay, data pins Driving the CS pin to “H” puts the M37409M2-XXXSP in the Dp to Dy, and three controls signals CS, WR, and RD which _state which does not allow the read and write operations can be directly connected to TTL. from the master CPU. At this time, the outputs of Do to Dy Driving the CS pin to “L” put this microcomputer in the are in the floating state. read/write enabled state. When writing data from the mas- _Figure 3 shows the block diagram of the bus interface. Local bus 8 8 8 48 a7 8 {92 its RAM register (7) J |_ register (8) 182 bytes 8 ; pr ps 8 8 Sysiem bus 6 6 6 oO 6 cs RD OWA Ao~Ay Oo~D, Fig. 3. Block diagram of bus interface ee MITSUBISHI 2-347 Jee

Table 1. Result obtained by simultaneously accessing _“10ared By the read operation from the local bus. As for a buses - | Correct data cleared to “0”. write is made. If an access to read from one bus and an ac- fead-out resets the access flag bit. Table 2. Correspondence among each bit of dual-port RAM direction specify register, dual-port RAM and access

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER {IPC mode register, IPC error register] [Collision detect register) Local bus : address 00F0;.~00F716 Local bus : address O0FA;s System bus : address F8,¢~F Bis System bus : address FE. IPC mode registers 0~3 (IPCMO~IPCM3) and IPC error This register consists of six bits of collision detect flags registers 0~3 (ERRO~ERR3) are the 8-bit registers which (CDy~CDs), the collision interrupt enable bit, and collision can be set by the user without restriction. IPC mode regis- _interrupt request bit. The collision detect flags are set when ters 0~3 are used to specify the mode setting such as _an access to read is performed by the system bus on the UART {rom the external master CPU via the system bus. same address on the dual port RAM to which the local bus IPC error registers 0~3 are used to indicate the error found _is writing data. These flags indicate that the data read by on the local CPU to the outside via the system bus. On the the master CPU may be incorrect. When these flags are system bus, IPC mode registers 0~3 and IPC error regis- _set, a collision detect interrupt request occurs. ters 0~3 share four bytes of the same address, with the Each collision flag corresponds to each 32 bits of the dual former being for write only and the latter for read only. On port RAM. The flag bit corresponding to the address at the local bus, the former is for read only and the latter is for _ which access competition occurred is set. The relationship both read and write. between the flag bits and the dual port RAM is shown in The data written from the system bus to IPC mode registers Table 3. These flags can be read from both buses. All bits 0~3 can be read from the local bus only. If an access to _are cleared when read from the system bus or at reset read or write is performed from the system bus on IPC The collision interrupt enable bit can be read/written from mode register O/IPC error register 0, an interrupt request the local bus. When it is read from the system bus, “0” is (IPCMO) is caused. always output. The collision interrupt request bit can be When IPC error registers 0~3 are accessed for read from —_read only from the local bus. Only “0” can be written. the system bus, orily the bits which are found “1” are reset by hardware. When these registers are read from the local Table 3. Correspondence between collision detect flag bus, their values remain unchanged. If an access to read is and dual-port RAM performed by the system bus between the read cycle and —_[Gotision detect | _ Duat-pot RAM write cycle of the local bus when IPC error registers 0~3 | flag ___| Local bus address | System bus address are accessed from the local bus by a read-modify-write in- | _CDo 0200;¢~021F io 005~1F ie struction, the hardware reset signal for the bit which is cD: 0220;6~023F 16. _2016~3Fie found “1” by the system bus continues until the local CPU C2 0240;6~025F io __ A016 5F ie fetches a next instruction. CPs 026010027 Fre S01 7E sg __ cD. __ 0280;6~029F 16 80:6~9F 16 [IPC semaphore register] SPs Ser OR Ate Bre Local bus : address 00F9i¢ System bus : address FF is 5 5 This register is for handshaking with the master CPU and Collision detect consists of block semaphore flags (BSO~ BS5) and the register ready flag (RDY). BSO~BSS can be read/written from both the focal and system buses. RDY can be read/written from = - Colision detect the local bus and read only from the system bus. With this °9 register, all bits can be read at a time but, in a write opera- | tion, only one bit can be written at a time. The low-order _______— cotision interrupt enable bit three bits of the data to be written are used to specify to : eat ciele which register bit the data is to be written. Bit 7 is used to specify whether to write “I" or “0". At reset, all bits are Collision interrupt request bit cleared to “0” 0: No interrupt request RDY is cleared to “0” also when an access to write is per- 1 2 With interrupt request formed by the system bus on IPC mode register 0. Fig. 6 Structure of collision detect register 7 0 IPC semaphore [ror = Tos ]es.[e]os[ossfos] ocr a Oe semaphore flag rary flag Fig. § Bit structure of IPC semaphore register ee MITSUBISHI = ae oss

Table 4. Reset is also included in the table because its op- UARTS control register (address 00E6,¢, OOEA;¢, OOEE;.) or disable flag | is set, and the program jumps to the address _—register. rupt can never be inhibited, Other interrupts are disabled (see UART section). are accepted when the interrupt enable bit is “1",interrupt _ ated the interrupt. terrupt request bit can be reset with a program, but not set.

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER eee 7 0 UART1 control register (address OOE6;.) a bit 4 : CTS, pin function select bit bit 3 : UART# receive interrupt enable bit -- ~ — bit | : UAT! transmit interrupt enable bit OTS: 0 bitO: UART1 transmit enable bit UART2 control register (address OOEA;,) __ bit 4 : GTS; pin tunction select bit — bit 3: UART2 receive interrupt enable bit "7 O_ bit 0: UART2 transmit enable bit CELT TTT TJ sats conor resister (accross 008€ 4) a i bit 4 : CTS; pin function select bit — bit 3 : UARTS receive interrupt enable bit Ce = bit 1 : UART3 transmit interrupt enable bit 87 0 bit: UARTS transmit enable bit [LLL LLL [| internet request resister (aadress 00F 4) bit 7 : UART! receive interrupt request bit a | | | DEG: VART2 receive interrupt request bit | bit 5 : UARTS receive interrupt request bit |) bit3: Timer x interrupt request bit —— — | bit 2: UARTI transmit interrupt request bit | bit 1 : UART2 transmit interrupt request bit 7 9 bitO : UARTS transmit interrupt request bit | ECCI J manner nate reistr(oderess 00F8.) | bit 7 : UARTI receive interrupt enable bit ~ — no el bit 6 : UART2 receive interrupt enable bit on se bit 5 : UARTS receive interrupt enable bit —| bit 4 : IPCMO interrupt enable bit ct bit 3 : Timer X interrupt enable bit | a cq bit 2: UARTI transmit interrupt enable bit | i bit 1 | UART2 transmit interrupt enable bit | ? 9. bitO : UARTS transmit interrupt enable bit | bit 7: IPCMO interrupt enable bit i bit 6 : Timer X interrupt enable bit z 0 Collision detect register (address OOF Ay.) bit 7 : Colision interrupt request bit C) C) C) UC) UJ C) CJ bit 6 : Collision interrupt enable bit CJ Interrupt request nae Interrupt disable flag | \\ Reset Fig. 7 Interrupt control ee % MITSUBISHI 2-351 ELECTRIC

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER TIMER The M37409M2-XXXSP has one timer: timer X. It has an 8- bit prescaler. Each timer or prescaler is structured with 8- 7 ° bit counter. A block diagram of timer X is shown in Figure Timer control register (Address OOFF,.) 9. Timer or prescaler is a down-counter which is reloaded T from the latch when the next clock pulse after the timer | Processor mode bit reaches zero. The division ratio is defined as 1/(n +1) 00 : Single-chip mode where n is the decimal contents of the timer latch. The tim- ore er interrupt request bit (bit 3 of the address 00FC;¢ of local a Not used address bus) is also set to “1” at this time. Timer counts the timo x oscillation frequency divided by 16 when the bit 5 of timer | ne ee or ded ot control register is “0”, and stops when “I”. The structure of 7 1 Count soos. ¥ the timer control register is shown in Figure 8. When the STP instruction is excuted, or after reset, the pre- i i enininanienaal = Interrupt disable scaler and timer latch are set to FFs and 0116, respective- 1 interrupt enable ly. Also, when the STP instruction is executed, the oscilla- ‘poo tor’s frequency (divided by 16) will become the counting Se nnnterupttequest source. This state will be released when the timer X inter- + With interrupt request rupt request bit is set to “1”, or after a reset. For more de- tails on the STP instruction, refer to the oscillation circuit section, Fig. 8 Structure of timer controi register pee ( Local bus FFye Ole Reset STP instruction Timer X count control bit (bit 5 of address OOFFy.) Fig. 9 Timer X block diagram 2-382 te MisussH ELECTRIC

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER UART , [Receive operation] The M37409M2-XXXSP contains three channels of UART'S Setting the receive enable bit (bit 2 of the UART1 control (UARTI(i=1, 2, 3). Functionally, they are all equal and can register) to “1” puts the system in the receive enable state be separately operated. Each channel has three pins (TxDi When there is no input of receive data, “H” is input to RxD, (transmit output), RxDi(receive input), and CTSi (clear to pin. When the falling edge is input to RxD, pin and “L” in- send) and contains the receive (transmit) shift register, the put ig detected twice consecutively by sampling with the receive (transmit) buffer register, the UARTi mode register, clock having a frequency 16 times the baud rate, the start the UARTi control register, the UARTi status register, and bit ig triggered. Then, sampling is performed three time in the baud rate generating divider. It also has aCLK pin (the the middle of the start bit. When “L” is detected twice or input pin of the external clock for baud rate generation) more, the receive operation begins, capturing the data bits which is shared by three channels. An interrupt can be into the receive shift register. If “L” has not been detected generated on each channel at receive and transmit inde- twice or more, start bit detection begins. again. When the Pendently. Figure 10 shows the UARTi block diagram. Be- gata bits and parity bit have been captured into the receive cause the differences between the channels are only pin shit register and the stop bit is detected, the receive data numbers and internal addresses, the following description is transferred from the receive shift register to the receive uses UART1 for reference. butfer register, setting the receiver ready flag (bit 1 of the UARTI status register). If a parity error occurred, the parity error flag is set. The framing error flag is set when the first stop bit is found “L”. If the previous data has not been read out of the receive buffer register, the overrun error flag is set, clearing the previous data. The receiver ready flag is reset when the receive buffer register is read. Each error flag can be reset by writing “1” to the error flag reset bit (bit 7 of the UART1 control register). Any of these errors does not affect the receive operation. The data bit, the par- ity bit, and the stop bit are sampled three times in the mid- dle of them each. When “L" or “H” is detected twice or more, “0” or “I” is determined respectively. Each time a receive operation has been completed, setting the receiver, ready flag, the UART1 receive interrupt re- quest bit (bit 7 of the interrupt request register) is set. An interrupt is acknowledged when the two UARTt receive in- terrupt enable bits (bit 3 of the UART1 control register and bit 7 of the interrupt enable register) are both “I”, and the interrupt disable flag | is “0”. The UART1 receive interrupt request bit is reset when a UART1 receive interrupt is ack- nowledged Setting the receive enable bit (bit 2 of the UART1 control register) to “0” puts the system in the receive stopped state. At this time, the receiver ready flag is “0” (ready), the receive shift register is in the stopped state, and the start bit detection is stopped. oS MITSUBISHI — ae on 58

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER [Transmit operation] for writing data. The immediately preceding data is trans- When the send data is written to the transmit buffer regis- _ferred from the transmit buffer register to the transmit shift ter, the start bit, parity bit, and stop bit are added to the —_register. Every time the start bit is output from TxD, pin, this data, which is transferred to the transmit shift register. The _flag is set. Every time the transmitter ready flag is set, the transmit shift register begins shift when it becomes enable UART1 transmit interrupt request bit (bit 2 of the interrupt for transmission, sending the serial data to TxD, pin. For request register) is set. An interrupt is acknowledged when the description of the transmit enable state, see Table 5. two UART1 transmit interrupt enable bits (bit 3 of the In the transmit enable state, each time transmission of the UART1 control register and bit 2 of the interrupt enable stop bit of the serial data being transmitted has been com- _register) are both “I” and the interrupt disable flag 1 is “0”. pleted, it is checked whether the next data has been writ- Note that an interrupt occurs only in the transmit ready ten to the transmit buffer register. If the data is found writ _ state. ten, transmission of the next data begins. If the data is Bit 6 of the UART1 control register initializes the UART1 found not written, TxD; pin is held at “H” until the next transmit side. When this bit “0”, the transmit side is in the transmit data is written, setting the transmitter empty flag. _ initial state. When the transmit enable state is cleared during transmis- sion, the transmission is stopped after completing the trans- mission of the transmit data so far written to the transmit able 6. _Bit and pin states when transmission is enable butter register. TSE, | OTS] TE: — : UARTI tanemit enable bit When the transmitter ready flag (bit 0 of the UART1 status [| 0 x CTSE, : CTS; pin function selection bit register) is “1°, it indicates that the transmit buffer is ready 1 L] CTS, : CFS; pin input level Local bus RxD! {| 8 Receive butter |__| Receive shitt Start bit detection register register circuit af baud rate | | — | | crsoi | cTsoi | CTSi re] Transmit control 1, ‘TxDi register register ~~ Fig. 10 UARTI block diagram 2-384 ale MISESH ELECTRIC

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER [UARTi divider for baud rate generator) Table 6. Baud rate calculation This is an 8-bit programmable divider which generates the [x | BA: Catculation baud rate for the UARTIi receive or transmit operation. 0 ° ‘baud te (bps) = (Xin) When the setting value is Ne (0 to 255), the divide ratio _ pane rake PSN 32(Nowt1) becomes 1/(Non-+1). There are three count sources; Xiu | | 1 Pave rate (ops) = clock divided by 2, Xi clock divided by 32, and the exter- $12(Nen+1) nal clock. Choose sources by bits 4 and 5 of the UARTi po | baud rate (008) Fenn) mode register. Table 6 shows the baud rate calculation for ae EX; : Glock selection bit for baud rate generator each bit combination. BR; __: Divide ratio selection bit for baud rate generator When the external clock is used, the frequency of the input clock must be below 1.6MHz. Writing to the baud rate generating divider must be performed when bits 2 and 6 of the UARTI control register are both “0”. eee Local bus 8 8 Baud rate register i Baud rate counter i BRGI EXi ) ~~ setcion gee: Comecte oak Sie} — J colored at reset BRI Fig. 11 Baud rate generating circuit MITSUBISHI ate ELECTRIC 2-365

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER I 7 0 7 0 EC lc ee a — Parity enable bit | L_— Transmit enabie bit 0: Parity disable | \\ | 0; Transmit disable 1: Perity enable \\ 1: Transmit enable | 0: Odd party | 0: interrupt disable i} rit ___. --— Character length select bit | | : Receive enable bit | 0: 7-bit | eee ena | eae | 0 Racene dart , L— stap bit ona setet bit ' { Receive enable | 1: 2estop bit 0: Disable \\ —_-- ~~ Baud rate generating prescaier [ 1: Enable | divide ratio select bit oo | — TSI pin function setect bit | 0: Xw clock divided by2 | Senne | 1! Xyy clock divided by 32 VO port t Baud rate erating 1: CTS pin Baus rate gen Bas | Synchronous clock select bit L. ——— G¥Si output data select bit Oe Internal clock 0 *L" output Eo ETS pin VO select bit [ gransmit side iitiatize bit 0: Input 0: Initialize 1: Output | 1: Transmit enable (error tag reset selection bit 7 0 0: Reset disable — 1: Error flag reset Eel Tron fr ffn] wn na | | | | | | | Transmitter ready flag | | 1: Transmit buffer empty —— Receiver ready flag | 0 : Receive butter empty | | 1 cab eter al transmitter empty flag 0 nit data tor transmit ; | 1: No data for transmit | | ; L ——— Parity error tag | | 0: No error | 1 Error Overrun error flag 0: No error 1: er - —— Framing error tag | 0: No error 1: error ome vow Fig. 12 Structure of registers related to UARTi a MITSUBISHI

2386 Pere

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER (CTSi_ pin] © CTSi output data select bit : CTSOi The CTSi pin can be used as the 1-bit I/O port when bit 4 When this bit is “0”, “L” is output. When it is "I", “H” is of the UARTI control register (CTSEi) is "0". In this case, output. the input/output direction can be determined by bit 7 of the © Transmit side initialize bit : MRi UARTi mode register (CTSDi) and the output data can be When this bit is “0”, the transmit side is initialized. set by bit 5 of the UARTI control register (CTSOi). Addi- @ Error flag reset select bit : ERSTi tionally, the input level can be known by bit 7 of the UARTi Setting this bit to “I” resets all error flags. When this bit status register (CTSi) is read, “0” is always read. [UARTi mode register) [UARTi status register] © Parity enable bit : PENi © Transmitter ready flag : TxRDYi Setting this bit to “I” adds a parity bit to the transmit When this flag is “1”, it indicates that the transmit buffer data. In a receive operation, this. bit is used for parity register is empty and ready for writing transmit data. evaluation © Receiver ready flag : RxRDYi © Parity select bit : EVNi When this flag is “I”, it indicates that the receive buffer This bit specifies the parity bit to be generated in a register is holding receive data, When the receive but- transmit operation and the parity bit to be evaluated in a fer register is read, it is cleared. receive operation. Depending on the content of this bit, @ Transmitter empty flag : TEMPi the number of 1's in data is made even or odd. When this flag is “I", it indicates that neither the trans- | @ Character length select bit : CHLI mit shift register nor the transmit buffer register holds This bit specifies the character length of data. the data to be transmitted. @ Stop bit length select bit : STi @ Parity error flag : PEi This bit specifies the stop bit length. This bit is set to "I" when the parity of the received @ Baud rate generating prescaler divide ratio select bit : data is different from the parity which was set. BRI © Overrun error flag : ORI When this bit is “0", the signal obtained by dividing Xw When this flag is “1”, it indicates that, before the data in clock by 2 becomes the count source of the baud rate the receive buffer register is read, the next data is divider, When this bit is “I”, the signal is obtained by di- transterred from the receive shift register to the receive viding the clock by 32 buffer register and the previous data is lost. @ Baud rate generating synchronous clock selection bit : @ Framing error flag : FEI EXi This flag is set to "I" when the stop bit is found “L” This bit specifies baud rate synchronous clock. When when data is transferred from the receive shift register this bit is “1”, external clock is input from the CLK pin. to the receive buffer register. _ © CTS pin 1/0 select bit : CTSDi © CTSi pin input level flag : CTSi When this bit is “0”, the CTSi pin is the input pin. When the input level of the CTSi pin is “L”, “0" is read; When this bit is “I”, the pin is the output pin. To use the when it is “H", “1” is read CTSi pin as the CTSi input, set “0”. [UARTi control register] © Transmit enable bit : TEi Setting this bit to “1” enables a transmit operation. © Transmit interrupt enable bit : TIEi When this bit is “I”, the interrupt in a transmit operation is enabled © Receive enable bit : REI Setting this bit to “I” enables a receive operation. © Receive interrupt enable bit : RIEI When this bit is “1”, the interrupt in a receive operation is enabled © CTSi pin function select bit ! CTSEi When this bit is “I", the CTSi pin becomes the CTSi input

9 MITSUBISHI 2-357

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Eee RESET CIRCUIT mended operating condition and the crystal oscillator The M37409M2-XXXSP is reset according to the sequence _ oscillation is stable and then returned to “H” level. The in- shown in Figure 14. It starts the program from the address _ ternal initializations following reset are shown in Figure 15 formed by using the content of address 1FFFi_ as the high and 16. order address and the content of the address 1FFE;. as the An example of the reset circuit is shown in Figure 13. low order address, when the RESET pin is held at “L”" level When the power on reset is used, the RESET pin must be for more than 2)s while the power voltage is in the recom- _held "L” until the oscillation of Xiv-Xour becomes stable. : Power on MSTA0OM2- f XXXSP iw RESET Voc | yy 22| 52 ae ov 0.6v M437A0M2- XxXSP a Me 1 ‘Supply voltage — detection LA pe setection circuit i} 1 I i} ! 1 xk! i ! ! sca L_-----3 Fig. 13 Example of reset circuit \\ , ||| -- oY é --4--- -- AESET pedo (POX XY OEE Data L ED ED GD ED EDC) CD. ea Zelock cycles) Note 1: Frequency relation of f(x) and gis (Xm) =4-4 2: The mark “?" means that the address is changeable depending on the previous state Fig.14 Timing diagram at reset eee 2-358 ate MISUESH : ELECTRIC

MITSUBISHI! MICROCOMPUTERS SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER —__SSSSSSSSSSSSSSSSSSSSSSSSSSSFS OE Local bus address VO PORTS -< (1) Port Po System bus : address F6;5 (Wy Port Ph directional register Ele) =o Port PO is an 8-bit 1/O port with CMOS output. it can 2) Dua pa RAM drecion spect egster (EZ) X X00) 0 0/0] 0. be accessed from system bus only and can not be 3) UARTS status register (€5,.)" |X 0 0/0/10 1, accessed from local bus. 4) UART1 mode register (E59) 0'X'0 01010/0/0 ‘As shown in the memory map (Figure 1), port PO can 5) UAT! contol register (Ee) Oe be accessed at system bus address F61s. Port PO has a ea,ynlelele dale directional register (address F715) which can be used ©) UART2 satus easier re ee to program each individual bit as input (“0”) or as out- 71 UART2 mode register (Ene) 0%, 0' 0,000.0) put (“1”). If the pins are programmed as output, the 8) UART2 control register (EA) = output data is latched to the port register and then out- 8) UARTS status register (ED) XX 0.001101 put. When data is read from the output port the output so) UARTS mode register teDgi='0/x10°0'0,0.0.0 pin level is not read, only the latched data in the port SSS ees register is read. This allows a previously output value to

1 UARTS contol register FE 004 :

tes te be read correctly even though the output voltage level We IPC error register 0 (Fade Ont is shifted up or down. Pins set as input are in the float- 18 IPC error register 1 Fond Oe ing state and the signal levels can thus be read. When 1M (PC error register? (F6,6) 005 data is written into the input port, the data is latched

59 IFC error register S (F0 oe only to the port latch and the pin still remains in the

it 1P6 semaphore register (Fo,) oon floating state. This port becomes input at reset : ennai (2) Port P1 Local bus : address 00E0,. 1) Collision detect register Fag Oe | System bus : address FSve {Interrupt enable register (FB x0) Me Port P1 is an 8-bit I/O port and connected to local bus, 19) Interrupt request register (FCs) OD ] It has the same function as port PO except the con- a Prescaler x (FOw| Re nected bus. ay timer x (eyy-d It’s directional register is at local bus address 00E1 16. pr yrotgtencxdatale Also port P1 can be read from system bus but the pin

2 Timer control register Sis dak rh Kaleo state is read regardless the value of the port P1 direc-

21 Access tag (C0¢~07,6) Cre tional register. 2k Processor status register a (3) Address pins . 128 Program counter (PC)-{Comens of adaress FFF! Address pins Ay~ A; are the input pins directly con- (PC.)--lContenis of adaress 1 FFE ul nected to the system bus. The 8-bit address corres- OO ponding to the system bus is input to these pins. The Since the contents of both registers other than those listed above and the RAM are undefined at reset, itis necessary 10 set initial values input level is TTL. Fig.15 Internal state of microcomputer at reset (1) (4) Data pins ig.18 Internal state of microcomputer at reso! Data pins Dp ~ D7 are the output pins directly con- nected to the system bus. The 8-bit data corresponding system bus address to the system bus is input/output on these pins. When taj ee — the CS pin is “L” and the RD pin is “L", the data pins 1) Port Po directional register A a become the output pins. When the CS pin is “L” and (2) IPC error register 0 (FB x6) Oe the WR pin is “L”, the data pins become the input pins. (3) IPC error register 1 (Es) Setting the CS pin to “H” puts pins Do~D; in the float- 4). 1G error register 2 (FAW Ce ing state. The 1/0 level is TTL. 9) IPC error register 3 (Bre)! Ose - (6) Collision detect register (FEw| Oe (2) IPG semaphore register (FF) 06 \\ (8) Access tlag (co~p7.6)-| Ce ‘Since the contents of both registers other than those listed above and the RAM are undefined at reset, its necessary to set inital values Fig.16 internal state of microcomputer at reset (2) oe MITSUBISHI 2-359 oaleee

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Port PO system bus 1 ae © Peet Po /——' } > Pon PA 7] : if BD 7 Local tus yO pots i Doan «| 4 | Fig. 17 Port PO, P1 block diagram _ MITSUBISHI 2-360 eee

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Eee CLOCK GENERATING CIRCUIT The built-in clock generating circuits are shown in Figure 18. M37409M2-XXxSP When the STP instruction is executed, the oscillation of in- x x ternal clock ¢ is stopped in the “H” state. Fa) Ar A Also, the prescaler X and timer X are loaded with FF;. and “— 0116, respectively. The oscillator (dividing by 16) is then —{Ot connected to the prescaler input. This connection is cleard =om Cour when timer X overflows or the reset is in, as discussed in + + the timer section. . The oscillator is restarted when an interrupt is accepted. _"Fig_49 External ceramic resonator circult However, the internal clock ¢ keeps its “H” level until timer X overtiows. This is because the oscillator needs a set-up period it a ceramic or a quartz crystal oscillator is used M37409M2-XxXSP When the WIT instruction is executed, the internal clock ¢ x x stops in the “H” level but the oscillator continues running. a = This wait state is cleared when an interrupt is accepted. por, Since the oscillation does not stop, the next instructions are Oh executed at once. ps To return from the stop or the wait status, the interrupt en- u--- + ---4 able bit must be set to “1” before executing STP or WIT in- struction. Especially, to return from the stop status, the tim- Fig 99 External ceramic resonator circuit er X count stop bit (bit 5 of address OOFF,,) must be set to (capacity built-in type) “0” before executing STP instruction. The circuit example using a ceramic oscillator (or a quartz crystal oscillator) is shown in Figure 19 and 20. M37409M2-XXXSP The constant capacitance will differ depending on which Xw oscillator is used, and should be set to the manufactures 3 suggested value. Ve The example of external clock uasge is shown in Figure 21. - Xiu is the input, and Xour is open. External oscillating circuit Vee Fig. 21 External clock input circuit Interrupt request BD reset Interrupt disable flag | ) > WIT instruction 4 R STP instruction STP instruction Bb: Internal clocks f BD Proscaler Timer X d | Overtiow fe) Timer X converter stop bit Xin Xour Fig. 18 Block diagram of clock generating circuit MITSUBISHI 2-3 —361 Jee

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER PROGRAMMING NOTES (1) The frequency ratio of the timer and the prescaler is 1/(n+1). (2) Even though the BBC and BBS instructions are ex- ecuted after the interrupt request bits are modified (by the program), those instructions are only valid for the contents before the modification. Also, at least one in- struction cycle must be used (such as a NOP) be- tween the modification of the interrupt request bits and the execution of the BBC and BBS instructions. (3) Change the address Ay~ Ay input and the CS input when both the RD input and WR input are “H”. (4) Registers whose values change when read, are con- nected to the system bus of the M37409M2-XXXSP. If the master CPU generates an invalid read cycle, data is not correctly transferred. (5) A NOP instruction must be used after the execution of a PLP instruction (6) After the ADC and SBC instructions are executed (in decimal mode), one instruction cycle (such as a NOP) is needed before the SEC, CLC, or CLD instructions are executed. (7) The STP instruction must be executed after setting tim- er X count enable bit to enable “0”, timer X interrupt enable bit to inhibit ("0"), and timer X interrupt request bit to no request ("0") (8) The power current is max. 10mA in DC. However, be- cause a rush current and a bus charge-discharge cur- rent flow transiently, a bypass capacitor must be con- nected between Ves and Voc. DATA REQUIRED FOR MASK ORDERING Please send the following data for mask orders. (1) mask ROM confirmation form (2) mark specification form (3) ROM data <---sssesssssseeesssssssseseeessiesssss EPROM Ssets — MITSUBISHI 2-362 Re

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER nn TFS ABSOLUTE MAXIMUM RATINGS [“symba Parameter Conditions Ratings Tam Vee ‘Supply voltage _ _ 03-7 of vi Input voltage, RESET, Xu =0.3~7 Y Input voltage, P0p~PO;, P1o~P17, Do~Dz, Ao~Ar, ~ if — v RD, WR, OS, CLK, RyDy~RyDs, With respect 10 Vss | =0.3~Vect0.3 |v - 5, ~CTS, Output transistors cut-ot _ i

7 Input voltage, CNVss _ | =0,3~13 v

V ‘Output voltage, POp~POr, PIo~PIr, Kour. #, Do~Dr, | i ° 1yD:~TsDs, OTS) ~CTSs _ | jo arWeoto9 v [Pg | Power dissipation __ Ta= Be . T000(Note 1) | mw Operating temperature __ =10~70 c Storage temperature — — =~ Note 1 : 300mW for QFP types. RECOMMENDED OPERATING CONDITIONS (Vcc = 5v+10%, Ta = —10~70C, unless otherwise noted) a °. Limite Unt sym rameter a at Veo Supply voltage 45) 5 5.5 v Vss ‘Supply voltage - 0 7 Vv “Ht” input voltage Xw, RESET, CLK, POy~PO>, i a ae 08M Vect0. v Vu 7 Plo~Pty, RxDi~PiDs, CTS)~ CTS : Sve foaland Vie “H” input voltage Ag~Ar, Do~D7, RD, WR, CS 2) Voc+0.3| V “L input voltage POo~PO;, P1o~Pt7, CLK, | Me ania —0. 0.2 v M RxD)~RxDs, CTS;~CTSs O38 Vee _ Vie “Lr input voltage Ay~Ar, Dy~Dr, RD. WA, CS -0.3 0.8 v Vie “L” input voltage RESET =0.3 0.12Vccl __V Vin “L" input voltage Xin —0.3 10. 16Vcc| v “H" output current POy~PO7, Plo~P17, $ ow Pine =10 | oma TyD\\~TDs, CTS. ~CTSs “HF output current Do~Or _ =1.0 | ma L™ output current POp~POr, Pto~PIr. $, 10 | ma TxDy~TxDs. OTS: ~CTSs - “L" output current Do~O7 =1.6 mA Note 2: The average output current loviavg) and low‘avg) are the average value of a period of 100ms 3! Total of loupeak. of ports PO, Pl, TxD;~TxD3 and CTS;~CTSs is —5S0mA Total of lon(peak), of ports PO, Pl, TxD)~TxD3 and CTS,;~CTS; is 50mA. a

9 MITSUBISHI

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER ELECTRICAL CHARACTERISTICS (vec = 5V, Ves = 0V, Ta = 25C, unless ctnerwise noted) Tine symba Parameter Test conditions ——| unt ,Pavae _ vin | yp. [Ma |" output voltage PO~POr. Pto~Pt1, & TD~TxDs, |g = | Vow | oso low=—10mA, |Vee—2 | v Von [7H exiput votage Dy~Dr a a zal as “L"eutput voltage POs PO; Pig~PIy, A THD/—THDs | lee lOma Vou “L" output voltage Do~Dy __ lo=1-6mA, . a4) ov h Input leak current Ag~Ar, RO, WA, GS, CLK Messi Ves os] 5] HA i Input leak current RESET. Xv en 5. 5) uA THsat tak curent PO,~PO,, Pig—Pi loz state Teak POrr-PO;, Ple~ Pi Ves+0.5SVoSVec—0. 5V ~5 5 uA

0 OTS CTS a __

Hysteresis RESET, CLK, RxD:~RxDs, TO 1 ys) =8~ 10M I 40 —| ma | ouputterninas {sito _ | re open wait ) red | Supply current sre opened, Soa mode] —— | others to Vss, ‘At stop mode i] 1 | C8=Vec Ta= 25 I | — un Ai stop meds | Ta= 20 MITSUBISHI 2-364 Jota

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER EEE ee TIMING REQUIREMENTS System bus (Vec=5V10%, Vss=0V. Ta=—10~70C, f(X)=5~10MH2, unless otherwise noted) Limits symbol Parameter Test conditions ee nei teuca-wn)_| Ao~Ay CS input set-up time ~ 50] ne tsuca-no) | Ao~Ar CS input set-up time ~ 50 - ns tsuio—wn) | Do~Dy input set-up time 80 ~ ns thiwn—a) | Ao~Ar OS input hold time 7 ° ne thino—ai | Ao~Ar GS input hold time Fig. 22 5 t — thiwr—o) | Do~Dy input hold time _ to ns twcwa) _| WR input "L" pulse width 200 TT A put "pulse wich ae as Local bus (vcc=5vt10%, Vss=0V, Ta=—10~70, t(Xs)=5~1OMH2, unless otherwise noted) S) J Pe i Test conditi [| _Lmits ‘Unit symbol rameter ; est conditions ne toute #)) Ple~Pty input set-up time _ bg i - ns this —ex) | Plo~PI input hold time 50 _ ne SWITCHING CHARACTERISTICS System bus (Vec=5V+10%, Ves=0V, Ta=—10~70°, 1(Xy.)=5~10MHz, unless otherwise noted) iol Pe te Test conditi Limits Unit Sym 7 arameter est conditions wm | a ni tg’ —no) | Do~Dy output delay time if _ _| 150 ns tyio—no) | Oo~Dr output effective time Fig. 22 Lo [ns tenino—0)| Do~Dy output enable time [10 ns tdisino- 0» | Do~Dr output disable time 50 ns Local bus (Vcc=5V+10%, Vss=0V, Ta=—10~70, 1(Xny)=5~TOMHz, unless otherwise noted) Symbol Paramet Test conditi | _Limnits unit moot | arameter est conditions win wax ni [tase [PnP ouputdeayime ig eT 00 Tins Do~D; Po O La) 100pF Fig. 22 Port PO, P1, Do~D, test circuit a

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER TIMING DIAGRAMS System bus write cycle t twiwed m tsuiawry AoA, GS \\ Ssucoowm Seno System bus read cycle i = ' tsuia-ro? thino-a) ‘ ! tdio-no) Idistro-0) | tenmon tio-nor | os es | obra ir tn ANNAN MM — MITSUBISHI oases Ae

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Local bus a oat" 99