M37271MF

M37271MF MITSUBISHI | Alldatasheet

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Technical content

DESCRIPTION

The M37271MF-XXXSP is a single-chip microcomputer designed with CMOS silicon gate technology. It is housed in a 52-pin shrink plastic molded DIP. In addition to their simple instruction sets, the ROM, RAM and I/O addresses are placed on the same memory map to enable easy pro- gramming. The M37271MF-XXXSP has a OSD function and a data slicer func- tion, so it is useful for a channel selection system for TV with a closed caption decoder. The features of the M37271EF-XXXSP and the M37271EFSP are similar to those of the M37271MF-XXXSP except that these chips have a built-in PROM which can be written electri- cally.

FEATURES

• Memory size
• The minimum instruction execution time
• Power dissipation (at VCC = 5.5V, 8MHz oscillation frequency, CRT on, and Data slicer on) (at VCC = 5.5V, 32kHz oscillation frequency)
• Data slicer
• OSD function (In EXOSD mode, they can be combined with 32 kinds of extra fonts) OSD mode : 16 5 20 dots EXOSD mode : 16 5 26 dots OSD mode : 14 types EXOSD mode : 6 types It can be specified by a character unit (maximum 7 kinds). Character font coloring, character background coloring It can be specified by a screen unit (maximum 7 kinds). Extra font coloring, raster coloring, border coloring OSD mode : 15 kinds (R, G, B, I) EXOSD mode : 7 kinds (R, G, B, I1, I2) Display position OSD mode : border EXOSD mode : border, extra font (32 kinds) Automatic solid space function Window function Dual layer OSD function APPLICATION TV with a closed caption decoder MITSUBISHI MICROCOMPUTERS M37271MF-XXXSP M37271EF-XXXSP, M37271EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER

M37271EF-XXXSP, M37271EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER PIN CONFIGURATION (TOP VIEW) Outline 52P4B HLF H SYNC VSYNC P40/AD4 P41/INT2 P42/TIM2 P43/TIM3 P24/AD3 P25/AD2 P01/PWM5 P02/PWM6 P17/SIN P44/INT1 P46/SCLK AV CC RVCO P52/R P53/G P54/B P55/OUT1 P04/PWM0 P05/PWM1 P10/OUT2 P11/SCL1 P12/SCL2 P13/SDA1 P14/SDA2 P15/I1 P16/I2/INT3 P30 P31 RESET P64/OSC2/XCOUT P63/OSC1/XCIN VCC P03 P26/AD1 P27 P00/PWM4 P45/SOUT P06/PWM2 P21 P22 P23 M37271MF-XXXSP M37271EF-XXXSP, M37271EFSP CV IN VHOLD CNV SS XOUT XIN V SS P07/PWM3 P20

M37271EF-XXXSP, M37271EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER FUNCTIONAL BLOCK DIAGRAM of M37271MF-XXXSP Clock input Clock output XIN XOUT Reset input AV CC VCC VSS CNV SS Pins for data slicer Clock output for OSD/ sub-clock output Input ports P63, P64 OSC1 OSC2 Clock input for OSD/ sub-clock input P1 (8) Multi-master I2C-BUS interface P3 (2) SDA1 SCL2 SCL1 SDA2 SIN SCLK SOUT SI/O (8) P6 (2) INT1 INT2 PWM6 PWM5 PWM4 PWM3 PWM2 PWM1 PWM0 P5 (4) OUT1 B G R HSYNC VSYNC OUT2 A-D converter 8-bit PWM circuit 8-bit arithmetic and logical unit Accumulator A (8) Timer 6 T6 (8) Timer 5 T5 (8) Timer 4 T4 (8) Timer 3 T3 (8) Timer 2 T2 (8) Timer 1 T1 (8) Timer count source selection circuit TIM2 TIM3 Data slicer Instruction register (8) Instruction decoder Control signal CRT circuit Processor status register PS (8) Stack pointer S (8) Index register Y (8) Index register X (8) ROM

60 K bytes

PC L (8) Progam counter PC H (8) RAM 1024 bytes Data bus Clock generating circuit 24 25 30 RESET 18 27 26 23 CV IN 22 21 20 19 V HOLD RVCO HLF 28 29 Address bus 31 14 34 35 36 37 38 39 40 10 9 8 7 41 42 43 44 45 46 47 48 33 13 12 11 17 16 15 6 5 4 3 49 50 51 52 2 1 I/O ports P30, P31 I/O port P1 I/O port P2 I/O port P0 Input ports P4 0–P46 Output port P5 Sync signal input INT3

M37271EF-XXXSP, M37271EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER 0.5 µs (the minimum instruction execution time, at 8 MHz oscillation fre- quency)

8 MHz (maximum)

7-bit 5 1 (N-channel open-drain output structure, can be used as PWM output pins) 1-bit 5 1 (CMOS input/output structure) 4-bit 5 1 (CMOS input/output structure, can be used as OSD output pin, INT input pin, serial input pin) 4-bit 5 1 (N-channel open-drain output structure, can be used as multi- master I 2C-BUS interface) 8-bit 5 1 (CMOS input/output structure, can be used as A-D input pins) 2-bit 5 1 (CMOS input/output structure) 5-bit 5 1 (can be used as A-D input pins, INT input pins, external clock input pins) 2-bit 5 1 (N-channel open-drain output structure when serial I/O is used, can be used as serial I/O pins) 4-bit 5 1 (CMOS output structure, can be used as OSD output) 1-bit 5 1 (can be used as sub-clock input pin, OSD clock input pin) 1-bit 5 1 (CMOS output structure when LC is oscillating, can be used as sub-clock output pin, OSD clock output pin) 8-bit 5 1 4 channels (8-bit resolution) 8-bit 5 7 8-bit timer 5 6 128 levels (maximum) External interrupt 5 3, Internal timer interrupt 5 6, Serial I/O interrupt 5 1, OSD interrupt 5 1, Multi-master I 2C-BUS interface interrupt 5 1, Data slicer interrupt 5 1, f(XIN)/4092 interrupt 5 1, VSYNC interrupt 5 1, A- D conversion interrupt 5 1, BRK instruction interrupt 5 1 2 built-in circuits (externally connected a ceramic resonator or a quartz- crystal oscillator) Built in Parameter Functions FUNCTIONS Number of basic instructions Instruction execution time Clock frequency Memory size Input/Output ports Serial I/O Multi-master I2C-BUS interface A-D converter PWM output circuit Timers Subroutine nesting Interrupt interval determination circuit Interrupt Clock generating circuit Data slicer ROM RAM OSD ROM OSD RAM 0–P02, P04–P07 P03 P10, P15–P17 P11–P14 P30, P31 P40–P44 P45, P46 P52–P55 P63 P64 I/O I/O I/O I/O I/O I/O Input Input Output Input Input

M37271EF-XXXSP, M37271EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER

5 V ± 10 %

165 mW typ. (at oscillation frequency fCPU = 8 MHz, fOSD = 13 MHz) 82.5 mW typ. (at oscillation frequency fCPU = 8 MHz) 0.33mW typ. (at oscillation frequency fCLK = 32 kHz, f(XIN) = stopped) 0.055 mW (maximum) –10 °C to 70 °C CMOS silicon gate process 52-pin shrink plastic molded DIP Number of display characters Dot structure Kinds of characters Kinds of character sizes Kinds of character colors Display position (horizontal, vertical) FUNCTIONS (continued) OSD function Power source voltage Power dissipation 40 characters 5 16 lines CC mode: 16 5 26 dots (character part : 16 5 20 dots) OSD mode: 16 5 20 dots EXOSD mode: 16 5 26 dots 320 kinds (In EXOSDmode, they can be combined with 32 kinds of extra fonts) CC mode: 2 kinds OSD mode: 14 kinds EXOSD mode: 6 kinds CC mode: 7 kinds (R, G, B) OSD mode: 15 kinds (R, G, B, I1) EXOSD mode: 7 kinds (R, G, B, I1, I2) 256 levels (horizontal) 5 1024 levels (vertical) Data slicer ON Data slicer OFF Data slicer OFF In high-speed mode In low-speed mode In stop mode OSD ON OSD OFF OSD OFF Operating temperature range Device structure Package

M37271EF-XXXSP, M37271EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER Apply voltage of 5 V ± 10 % (typical) to VCC and AVCC , and 0 V to VSS . This is connected to VSS . To enter the reset state, the reset input pin must be kept at a “L” for 2 µs or more (under normal VCC conditions). If more time is needed for the quartz-crystal oscillator to stabilize, this “L” condition should be maintained for the required time. This chip has an internal clock generating circuit. To control generating frequency, an external ceramic resonator or a quartz-crystal oscillator is connected between pins X IN and XOUT . If an external clock is used, the clock source should be connected to the XIN pin and the XOUT pin should be left open. Port P0 is an 8-bit I/O port with direction register allowing each I/O bit to be individually programmed as input or output. At reset, this port is set to input mode. The output structure of P0 3 is CMOS output, that of P00–P02 and P04–P07 are N-channel open-drain output. The note out of this Table gives a full of port P0 function. Pins P00–P02 and P04–P07 are also used as PWM output pins PWM4–PWM6 and PWM0– PWM3 respectively. The output structure is N-channel open-drain output. Port P1 is an 8-bit I/O port and has basically the same functions as port P0. The output structure of P10 and P15–P17 is CMOS output, that of P11–P14 is N-channel open-drain output. Pins P10, P15, P16 are also used as OSD output pins OUT2, I1, I2 respectively. The output structure is CMOS output. Pins P11–P14 are used as SCL1, SCL2, SDA1 and SDA2 respectively, when multi-master I2C-BUS interface is used. The output structure is N-channel open-drain output. P17 pin is also used as serial I/O data input pin SIN. Port P2 is an 8-bit I/O port and has basically the same functions as port P0. The output structure is CMOS output. Pins P24–P26 are also used as analog input pins AD3–AD1 respectively. Ports P30 and P31 are a 2-bit I/O port and has basically the same functions as port P0. The output structure is CMOS output. Ports P40–P46 are a 7-bit input port. P40 pin is also used as analog input pin AD4. Pins P41, P44 are also used as external interrupt input INT2, INT1. Pins P42 and P43 are also used as external clock input pins TIM2, TIM3 respectively. P45 pin is used as serial I/O data output pin SOUT . The output structure is N-channel open- drain output. P46 pin is used as serial I/O synchronizing clock input/output pin SCLK . The output struc- ture is N-channel open-drain output. Ports P52–P55 are a 4-bit output port. The output structure is CMOS output. Pins P52–P55 are also used as OSD output pins R, G, B, OUT1 respectively. PIN DESCRIPTION Pin Name Name Input/ Output Power source CNV SS Reset input Clock input Clock output I/O port P0 PWM output I/O port P1 OSD output Multi-master I2C-BUS interface Serial I/O data input I/O port P2 Analog input I/O port P3 Input port P4 Analog input External interrupt input External clock input Serial I/O data output Serial I/O synchronizing clock input/output Output port P5 OSD output V CC , AV CC , VSS. CNV SS RESET XIN XOUT P00/PWM4– P02/PWM6, P03, P04/PWM0– P07/PWM3 P10/OUT2, P11/SCL1, P12/SCL2, P13/SDA1, P14/SDA2, P15/I1, P16/I2/INT3, P17/SIN P20–P23 P24/AD3– P26/AD1, P27 P30, P31 P40/AD4, P41/INT2, P42/TIM2, P43/TIM3, P44/INT1, P45/SOUT , P46/SCLK , P52/R,P53/G, P54/B, P55/OUT1 Input Input Output I/O Output I/O Output Output Input I/O Input I/O Input Input Input Input Output I/O Output Output

M37271EF-XXXSP, M37271EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER Input Input Output Output Input Input Input Input Input Input port Clock input for OSD Clock output for OSD Sub-clock output Sub-clock input I/O for data slicer H SYNC input VSYNC input PIN DESCRIPTION (continued) P63/OSC1/ XCIN, P64/OSC2/ XCOUT CV IN VHOLD RVCO HLF H SYNC VSYNC Ports P63 and P64 are 2-bit input port. P63 pin is also used as OSD clock input pin OSC1. P64 pin is also used as OSD clock output pin OSC2. The output structure is CMOS output. P64 pin is also used as sub-clock output pin XCOUT . The output structure is CMOS output. P63 pin is also used as sub-clock input pin XCIN. Input composite video signal through a capacitor. Connect a capacitor between V HOLD and VSS . Connect a resistor between RVCO and VSS . Connect a filter using of a capacitor and a resistor between HLF and VSS . This is a horizontal synchronizing signal input for OSD. This is a vertical synchronizing signal input for OSD. Note : As shown in the memory map (Figure 3), port P0 is accessed as a memory at address 00C016 of zero page. Port P0 has the port P0 direction register (address 00C116 of zero page) which can be used to program each bit as an input (“0”) or an output (“1”). The pins programmed as “1” in the direction register are output pins. When pins are programmed as “0,” they are input pins. When pins are programmed as output pins, the output data are written into the port latch and then output. When data is read from the output pins, the output pin level is not read but the data of the port latch is read. This allows a previously-output value to be read correctly even if the output “L” voltage has risen, for example, because a light emitting diode was directly driven. The input pins are in the floating state, so the values of the pins can be read. When data is written into the input pin, it is written only into the port latch, while the pin remains in the floating state.

M37271EF-XXXSP, M37271EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER FUNCTIONAL DESCRIPTION Central Processing Unit (CPU) The M37271MF-XXXSP uses the standard 740 family instruction set. Refer to the table of 740 family addressing modes and machine in- structions or the SERIES 740 < Software > User’s Manual for details on the instruction set. Machine-resident 740 family instructions are as follows: The FST, SLW instruction cannot be used. The MUL, DIV, WIT and STP instruction can be used. CPU Mode Register The CPU mode register contains the stack page selection bit and internal system clock selection bit. The CPU mode register is allo- cated at address 00FB 16. Fig. 1. Structure of CPU mode register 11 0 0 CPU mode register (CPUM (CM) : address 00FB16) Processor mode bits b1 b0 0 0 : Single-chip mode 0 1 : 1 0 : 1 1 : Stack page selection bit (Note) 0 : Zero page 1 : 1 page Fix these bits to “1.” Note: Please beware of this bit when programming because it is set to “1” after the reset release. X COUT drivability selection bit 0 : Low drive 1 : High drive Main colock (X IN–XOUT ) stop bit 0 : Oscillating 1 : Stopped Internal system clock selection bit 0 : X IN–XOUT selected (high-speed mode) 1 : XCIN–XCOUT selected (low-speed mode) Not available

M37271EF-XXXSP, M37271EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER MEMORY Special Function Register (SFR) Area The special function register (SFR) area in the zero page contains control registers such as I/O ports and timers. RAM RAM is used for data storage and for stack area of subroutine calls and interrupts. ROM ROM is used for storing user programs as well as the interrupt vector area. RAM for OSD RAM for display is used for specifying the character codes and col- ors to display. ROM for OSD ROM for display is used for storing character data. Interrupt Vector Area The interrupt vector area contains reset and interrupt vectors. Zero Page The 256 bytes from addresses 000016 to 00FF16 are called the zero page area. The internal RAM and the special function registers (SFR) are allocated to this area. The zero page addressing mode can be used to specify memory and register addresses in the zero page area. Access to this area with only 2 bytes is possible in the zero page addressing mode. Special Page The 256 bytes from addresses FF0016 to FFFF16 are called the spe- cial page area. The special page addressing mode can be used to specify memory addresses in the special page area. Access to this area with only 2 bytes is possible in the special page addressing mode. Fig. 2. Memory map 000016 00C0 16 00FF16 0FFF 16 SFR1 area Not used FFFF 16 FFDE 16 FF0016 080016 Interrupt vector area Not used 1080016 1FFFF 16 Special page ROM (60 K bytes) RAM for OSD (Note) (1920 bytes) RAM (1024 bytes) Zero page 020016 023F16 100016 SFR2 area 053F16 Not used 030016 Not used 1567F16 1800016 Not used 1E43F 16 1000016 ROM for OSD (14464 bytes)

M37271EF-XXXSP, M37271EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER Fig. 3. Memory map of special function register 1 (SFR1) (1) 0 : “0” immediately after reset : Fix this bit to “0” ( do not write “1”) : Nothing is allocated n SFR1 area (addresses C016 to DF16) D0 16 D1 16 D2 16 D3 16 D4 16 D5 16 D6 16 D7 16 D8 16 D9 16 DA 16 DB 16 DC 16 DD 16 DE 16 DF 16 C0 16 C1 16 C2 16 C3 16 C4 16 C5 16 C6 16 C7 16 C8 16 C9 16 CB 16 CC 16 CD 16 CE 16 CF 16 CA 16 Address Port P5 (P5) OSD control register (OC) Horizontal position register (HP) Block control register 1 (BC1) Port P1 (P1) Port P1 direction register (D1) Port P3 (P3) Port P3 direction register (D3) Port P2 (P2) Port P2 direction register (D2) Register Port P0 (P0) Port P0 direction register (D0) Block control register 2 (BC2) Block control register 3 (BC3) Block control register 4 (BC4) Block control register 5 (BC5) Block control register 6 (BC6) Block control register 7 (BC7) Block control register 13 (BC13) Block control register 14 (BC14) Block control register 15 (BC15) Block control register 16 (BC16) : undefined immediately after reset ? b7 b0 Bit allocation State immediately after reset 0016 b7 b0 0016 0016 0000 000 0 0000 000 0 Port P4 (P4) Port P4 direction register (D4) OSD port control register (PF) Port P6 (P6) Block control register 8 (BC8) Block control register 9 (BC9) Block control register 10 (BC10) Block control register 11 (BC11) Block control register 12 (BC12) RI 2 I 1GBOUT1OUT2 000 0000 OC6OC7 OC4 OC5 OC2 OC3 OC0 OC1 0016 BC 11BC 12BC 13BC 14BC 15BC 16BC 17BC 18 BC 21BC 22BC 23BC 24BC 25BC 26BC 27BC 28 BC 31BC 32BC 33BC 34BC 35BC 36BC 37BC 38 BC 41BC 42BC 43BC 44BC 45BC 46BC 47BC 48 BC 51BC 52BC 53BC 54BC 55BC 56BC 57BC 58 BC 61BC 62BC 63BC 64BC 65BC 66BC 67BC 68 BC 71BC 72BC 73BC 74BC 75BC 76BC 77BC 78 BC 81BC 82BC 83BC 84BC 85BC 86BC 87BC 88 BC 91BC 92BC 93BC 94BC 95BC 96BC 97BC 98 BC 101BC 102BC 103BC 104BC 105BC 106BC 107BC 108 BC 111BC 112BC 113BC 114BC 115BC 116BC 117BC 118 BC 121BC 122BC 123BC 124BC 125BC 126BC 127BC 128 BC 131BC 132BC 133BC 134BC 135BC 136BC 137BC 138 BC 141BC 142BC 143BC 144BC 145BC 146BC 147BC 148 BC 151BC 152BC 153BC 154BC 155BC 156BC 157BC 158 BC 161BC 162BC 163BC 164BC 165BC 166BC 167BC 168 HP6HP7 HP4 HP5 HP2 HP3 HP0 HP1 0016

M37271EF-XXXSP , M37271EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DEC ODER and ON-SCREEN DISPLA Y CONTR OLLER Fig. 4. Memory map of special function register 1 (SFR2) (2) F016 F116 F216 F316 F416 F516 F616 F716 F816 F916 FA 16 FB 16 FC 16 FD 16 FE 16 FF16 E016 E116 E216 E316 E416 E516 E616 E716 E816 E916 EB 16 EC 16 ED 16 EE 16 EF 16 EA 16 Data slicer control register 1 (DSC1) Data register 3 (CD3) A-D conversion register (AD) A-D control register (ADCON) Timer 1 (TM1) Window register (WN) Clock run-in register 1 (CR1) Clock run-in register 2 (CR2) Data register 1 (CD1) Data register 2 (CD2) Caption position register (CP) Start bit position register (SP) Timer 2 (TM2) Timer 3 (TM3) Timer 4 (TM4) Timer mode register 1 (TM1) Timer mode register 2 (TM2) I2C data shift register (S0) I2C control register (S1D) I2C clock control register (S2) Interrupt request register 1 (IREQ1) Interrupt request register 2 (IREQ2) Interrupt control register 1 (ICON1) Interrupt control register 2 (ICON2) Clock run-in detect register 1 (CRD1) Clock run-in detect register 2 (CRD2) Data register 4 (CD4) CPU mode register (CPUM) b7 b0 ADIN0ADIN1ADVREF ADSTRADV TM20TM21TM22TM23TM24 TM10TM11TM12TM13TM14 CM2 TM1RTM2RTM3RTM4RCRTRVSCRADR CK0 INT1RDSRSIOR TM1ETM2ETM3ETM4ECRTEVSCE INT1EDSESIOEINT2E TM25 b7 b0 CK0 0016 ? 0 0 0?0 00 FF16 0716 FF16 0716 0 0 0 000 00 0 0 0 000 00 00 0 0 0 000 00 0 0 0 000 00 0 0 0 000 00 0 0 0 000 0 11 1 00 0 00 0 1 00 1 Sync slice register (SSL) Data slicer control register 2 (DSC2) I2C status register (S1) I2C address register (S0D) ? 00 0 0 00 0 0016 TM15TM16TM17 TM26TM27 SAD0SAD1SAD2SAD3SAD4SAD5SAD6 RBW LRBAD0AASALPINBBTRXMST BC0BC1BC2ES0ALS10 BIT SADBSEL0BSEL1 CCR0CCR1CCR2CCR3CCR4FAST MODE ACK BITACK 0016 0016 0016 0000 01? 0 1MSRINT2RIICRT56R ADE 1MSEIICET56ET56S CM0CM1CM7 CM5CM6 DSC20DSC21DSC22DSC25DSC27 DSC10DSC11DSC12DSC15DSC17 0 00 0 0 01 1SSL7 1 00 ? ? ?? ?CP0CP1CP2CP3CP4 SP0SP1SP2SP3SP4SP5SP6SP7 0016 0 00 0 0 00 0WN0WN1WN2WN3WN4WN5 CRD20CRD21CRD22CRD25CRD27 CRD25 CRD25 CRD25 1 00 1 1 1 10CR21 CR11 0 10 1 00 00 0 00 0 0 00 0CRD10CRD11CRD12CRD15CRD17 CRD15 CRD15 CRD15 1 : “1” immediately after reset : Fix this bit to “0” ( do not write “1”) : Nothing is allocated n SFR1 area (addresses E016 to FF16) Address Register : undefined immediately after reset ? Bit allocation State immediately after reset : Fix this bit to “1” ( do not write “0”) 0 : “0” immediately after reset

M37271EF-XXXSP, M37271EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER Fig. 5. Memory map of special function register 2 (SFR2) (1) 21016 21116 21216 21316 21416 21516 21616 21716 21816 21916 21A16 21B16 21C 16 21D 16 21E16 21F16 20016 20116 20216 20316 20416 20516 20616 20716 20816 20916 20B16 20C 16 20D 16 20E16 20F16 20A16 PWM mode register 1 (PN) Timer 5 (TM5) Sync pulse counter register (SYC) Data slicer control register 3 (DSC3) PWM2 register (PWM2) PWM6 register (PWM6) PWM4 register (PWM4) PWM5 register (PWM5) PWM0 register (PWM0) PWM1 register (PWM1) Interrupt interval determination register (RI) Interrupt interval determination control register (RE) Serial I/O mode register (SM) Serial I/O register (SIO) Clock source control register (CS) Extra font color register (EC) Window H register 1 (WH1) Window L register 1 (WH1) Window H register 2 (WH2) Window L register 2 (WH2) Clock run-in detect register (CRD3) Clock run-in register (CR3) Timer 6 (TM6) Border color register (FC) b7 b0 SYC0 FC2 b7 b0 0716 ?000000? 0016 0? ? ?0 0 00 PWM3 register (PWM3) PWM mode register 2 (PW) Raster color register (RC) I/O polarity control register (PC) FF16 0016 PW0PW1PW2PW3PW4PW5PW6 ENABLEPOL SYC1SYC2SYC3SYC4SYC5 DSC30DSC31DSC32DSC37 DSC35 RE0RE1RE2RE3RE4RE5INT3 POL AD/INT3 SEL RE1RE2RE3RE4RE5INT3 POL AD/INT3 SEL SM0RE1RE2RE3SM4RE5INT3 POL AD/INT3 SEL SM1SM2SM3SM5 PC0RE1RE2RE3PC4RE5INT3 POL AD/INT3 SEL PC1PC2PC3PC5PC6PC7 RE1RE2RE3RE5INT3 POL AD/INT3 SEL CS0CS4 CS1 CS2CS3CS5CS6 RC0RE1RE2RE3RC4RE5INT3 POL AD/INT3 SEL RC1RC2RC3RC5RC6RC7 RE1RE2RE3RE5INT3 POL AD/INT3 SEL FC0FC1FC3FC4 WH20WH21 WL20WL21 0? ? ?0 0 00 01 0 00 0 00 ?? ? 00 0 00 0 00 0016DSC36 DSC34 DSC33 ? 00 00 0 0 0 CRD31CRD32CRD33CRD34CRD35 0 00 00 0 0 0 1 : “1” immediately after reset : Fix this bit to “0” ( do not write “1”) : Nothing is allocated n SFR2 area (addresses 20016 to 21F16) Address Register : undefined immediately after reset ? Bit allocation State immediately after reset 0 : “0” immediately after reset

M37271EF-XXXSP, M37271EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER Fig. 6. Memory map of special function register 2 (SFR2) (2) 23016 23116 23216 23316 23416 23516 23616 23716 23816 23916 23A16 23B16 23C 16 23D 16 23E16 23F16 22016 22116 22216 22316 22416 22516 22616 22716 22816 22916 22B16 22C 16 22D 16 22E16 22F16 22A16 Vertical position register 111 (VP111) Vertical position register 116 (VP116) Vertical position register 13 (VP13) Vertical position register 17 (VP17) Vertical position register 15 (VP15) Vertical position register 16 (VP16) Vertical position register 11 (VP11) Vertical position register 12 (VP12) Vertical position register 19 (VP19) Vertical position register 110 (VP110) b7 b0 b7 b0 Vertical position register 14 (VP14) Vertical position register 112 (VP112) ?VP1 11 Vertical position register 18 (VP18) Vertical position register 115 (VP115) Vertical position register 213 (VP213) Vertical position register 214 (VP214) Vertical position register 216 (VP216) Vertical position register 23 (VP23) Vertical position register 27 (VP27) Vertical position register 25 (VP25) Vertical position register 26 (VP26) Vertical position register 21 (VP21) Vertical position register 29 (VP29) Vertical position register 210 (VP210) Vertical position register 24 (VP24) Vertical position register 212 (VP212) Vertical position register 28 (VP28) Vertical position register 215 (VP215) Vertical position register 114 (VP114) Vertical position register 113 (VP113) Vertical position register 22 (VP22) Vertical position register 211 (VP211) VP1 12VP1 13VP1 14VP1 15VP1 16VP1 17VP1 18 VP1 21VP1 22VP1 23VP1 24VP1 25VP1 26VP1 27VP1 28 VP1 31VP1 32VP1 33VP1 34VP1 35VP1 36VP1 37VP1 38 VP1 41VP1 42VP1 43VP1 44VP1 45VP1 46VP1 47VP1 48 VP1 51VP1 52VP1 53VP1 54VP1 55VP1 56VP1 57VP1 58 VP1 61VP1 62VP1 63VP1 64VP1 65VP1 66VP1 67VP1 68 VP1 71VP1 72VP1 73VP1 74VP1 75VP1 76VP1 77VP1 78 VP1 81VP1 82VP1 83VP1 84VP1 85VP1 86VP1 87VP1 88 VP1 91VP1 92VP1 93VP1 94VP1 95VP1 96VP1 97VP1 98 VP1 101VP1 102VP1 103VP1 104VP1 105VP1 106VP1 107VP1 108 VP1 111VP1 112VP1 113VP1 114VP1 115VP1 116VP1 117VP1 118 VP1 121VP1 122VP1 123VP1 124VP1 125VP1 126VP1 127VP1 128 VP1 131VP1 132VP1 133VP1 134VP1 135VP1 136VP1 137VP1 138 VP1 141VP1 142VP1 143VP1 144VP1 145VP1 146VP1 147VP1 148 VP1 151VP1 152VP1 153VP1 154VP1 155VP1 156VP1 157VP1 158 VP1 161VP1 162VP1 163VP1 164VP1 165VP1 166VP1 167VP1 168 VP2 11VP2 12 VP2 21VP2 22 VP2 31VP2 32 VP2 41VP2 42 VP2 51VP2 52 VP2 61VP2 62 VP2 71VP2 72 VP2 81VP2 82 VP2 91VP2 92 VP2 101VP2 102 VP2 111VP2 112 VP2 121VP2 122 VP2 131VP2 132 VP2 141VP2 142 VP2 151VP2 152 VP2 161VP2 162 : Nothing is allocated n SFR2 area (addresses 22016 to 23F16) Address Register : undefined immediately after reset ? Bit allocation State immediately after reset

M37271EF-XXXSP, M37271EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER Fig. 7. Internal state of processor status register and program counter at reset b7 b0 b7 b0 Register Processor status register (PS) Bit allocation State immediately after reset Program counter (PCH ) Program counter (PCL) Contents of address FFFF16 Contents of address FFFE16 : Nothing is allocated : “1” immediately after reset : undefined immediately after reset

table because its operation is similar to an interrupt. register are automatically stored into the stack. the interrupt-related registers. be set to “0” and “1” by a program. Reset is treated as a non-maskable interrupt with the highest priority. Figure 9 shows interrupt control. tected. Note that all bits are cleared to “0” at reset. An interrupt is generated by an overflow of timer 1, 2, 3 or 4. An interrupt occurs when slicing data is completed. Table 1. Interrupt vector addresses and priority

M37271EF-XXXSP, M37271EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER (9)Timer 5 · 6 interrupt An interrupt is generated by an overflow of timer 5 or 6. Their priorities are same, and can be switched by software. (10)BRK instruction interrupt This software interrupt has the least significant priority. It does not have a corresponding interrupt enable bit, and it is not af- fected by the interrupt disable flag I (non-maskable). Fig. 8. Structure of interrupt-related registers Fig. 9. Interrupt control Interrupt request bit Interrupt enable bit Interrupt disable flag I BRK instruction Reset Interrupt request Interrupt request register 1 (IREQ1: address 00FC16) Timer 1 interrupt request bit Timer 2 interrupt request bit Timer 3 interrupt request bit Timer 4 interrupt request bit OSD interrupt request bit VSYNC interrupt request bit Multi-master I2C-BUS interface interrupt request bit Timer 5 × 6 interrupt request bit 0 : No interrupt request issued 1 : Interrupt request issued Interrupt request register 2 (IREQ2: address 00FD16) INT1 interrupt request bit Data slicer interrupt request bit Serial I/O interrupt request bit INT2 interrupt request bit Fix this bit to “0.” 0 : Interrupt disabled 1 : Interrupt enabled Interrupt control register 2 ( ICON2 : address 00FF16) INT1 interrupt enable bit Data slicer interrupt enable bit Serial I/O interrupt enable bit Interrupt control register 1 ( ICON1: address 00FE16) Timer 1 interrupt enable bit Timer 2 interrupt enable bit Timer 3 interrupt enable bit Timer 4 interrupt enable bit OSD interrupt enable bit VSYNC interrupt enable bit f(XIN)/4096 interrupt request bit Multi-master I2C-BUS interface enable bit Timer 5 × 6 interrupt enable bit INT2 interrupt enable bit Timer 5 × 6 interrupt switch bit f(XIN)/4096 interrupt enable bit A-D conversion × INT3 interrupt request bit 0 : Timer 5 1 : Timer 6 A-D conversion × INT3 interrupt request bit

M37271EF-XXXSP, M37271EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER TIMERS The M37271MF-XXXSP has 6 timers: timer 1, timer 2, timer 3, timer 4, timer 5, and timer 6. All timers are 8-bit timers with the 8-bit timer latch. The timer block diagram is shown in Figure 11. All of the timers count down and their divide ratio is 1/(n+1), where n is the value of timer latch. The value is set to a timer at the same time by writing a count value to the corresponding timer latch (addresses 00F0 16 to 00F316 : timers 1 to 4, addresses 020C16 and 020D16 : timers 5 and 6). The count value is decremented by 1. The timer interrupt request bit is set to “1” by a timer overflow at the next count pulse after the count value reaches “00 16”. (1) Timer 1 Timer 1 can select one of the following count sources:

• f(XIN)/16 or f(XCIN)/16
• f(XIN)/4096 or f(XCIN)/4096
• External clock from the P42/TIM2 pin The count source of timer 1 is selected by setting bits 5 and 0 of the timer mode register 1 (address 00F4 16). Either f(XIN) or f(XCIN) is selected by bit 7 of the CPU mode register. Timer 1 interrupt request occurs at timer 1 overflow. (2) Timer 2 Timer 2 can select one of the following count sources:
• f(XIN)/16 or f(XCIN)/16
• Timer 1 overflow signal
• External clock from the P42/TIM2 pin The count source of timer 2 is selected by setting bits 4 and 1 of the timer mode register 1 (address 00F416). Either f(XIN) or f(XCIN) is selected by bit 7 of the CPU mode register. When timer 1 overflow signal is a count source for the timer 2, the timer 1 functions as an 8- bit prescaler. Timer 2 interrupt request occurs at timer 2 overflow. (3) Timer 3 Timer 3 can select one of the following count sources:
• f(XIN)/16 or f(XCIN)/16
• f(XCIN)
• External clock from the P43/TIM3 pin The count source of timer 3 is selected by setting bit 0 of the timer mode register 2 (address 00F516) and bit 6 at address 00C716. Ei- ther f(XIN) or f(XCIN) is selected by bit 7 of the CPU mode register. Timer 3 interrupt request occurs at timer 3 overflow. (4) Timer 4 Timer 4 can select one of the following count sources:
• f(XIN)/16 or f(XCIN)/16
• f(XIN)/2 or f(XCIN)/2
• f(XCIN) The count source of timer 3 is selected by setting bits 4 and 1 of the timer mode register 2 (address 00F5 16). Either f(XIN) or f(XCIN) is selected by bit 7 of the CPU mode register. When timer 3 overflow signal is a count source for the timer 4, the timer 3 functions as an 8- bit prescaler. Timer 4 interrupt request occurs at timer 4 overflow. (5) Timer 5 Timer 5 can select one of the following count sources:
• f(XIN)/16 or f(XCIN)/16
• Timer 2 overflow signal
• Timer 4 overflow signal The count source of timer 3 is selected by setting bit 6 of the timer mode register 1 (address 00F4 16) and bit 7 of the timer mode regis- ter 2 (address 00F516). Either f(XIN) or f(XCIN) is selected by bit 7 of the CPU mode register. Timer 5 interrupt request occurs at timer 5 overflow. (6) Timer 6 Timer 6 can select one of the following count sources:
• f(XIN)/16 or f(XCIN)/16
• Timer 5 overflow signal The count source of timer 6 is selected by setting bit 7 of the timer mode register 1 (address 00F416). Either f(XIN) or f(XCIN) is selected by bit 7 of the CPU mode register. When timer 5 overflow signal is a count source for the timer 6, the timer 5 functions as an 8-bit prescaler. Timer 6 interrupt request occurs at timer 6 overflow. At reset, timers 3 and 4 are connected by hardware and “FF 16” is automatically set in timer 3; “0716” in timer 4. The f(XIN) ] /16 is se- lected as the timer 3 count source. The internal reset is released by timer 4 overflow at these state, the internal clock is connected. At execution of the STP instruction, timers 3 and 4 are connected by hardware and “FF 16” is automatically set in timer 3; “0716” in timer 4. However, the f(XIN) ] /16 is not selected as the timer 3 count source. So set both bit 0 of the timer mode register 2 (address 00F516) and bit 6 at address 00C716 to “0” before the execution of the STP in- struction (f(XIN) ] /16 is selected as the timer 3 count source). The internal STP state is released by timer 4 overflow at these state, the internal clock is connected. Because of this, the program starts with the stable clock. ] : When bit 7 of the CPU mode register (CM 7) is “1,” f(XIN) be- comes f(XCIN). The structure of timer-related registers is shown in Figure 10.

M37271EF-XXXSP, M37271EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER Fig. 10. Structure of timer-related registers Timer mode register 1 (TMR1 : address 00F416) Timer 1 count source selection bit 1 0 : f(XIN)/16 or f(XCIN)/16 (Note) 1 : Count source selected by bit 5 of TMR1 Timer 2 count source selection bit 1 0 : Count source selected by bit 4 of TMR1 1 : External clock from P42/TIM2 pin Timer 1 count stop bit 0 : Count start 1 : Count stop Timer 2 count stop bit 0 : Count start 1 : Count stop Timer 2 count source selection bit 2 0 : f(X IN)/16 or f(XCIN)/16 (Note) 1 : Timer 1 overflow Timer 1 count source selection bit 2 0 : f(X IN)/4096 or f(XCIN)/4096 (Note) 1 : External clock from P42/TIM2 pin Timer 5 count source selection bit 2 0 : Timer 2 overflow 1 : Timer 4 overflow Timer 6 count source selection bit 0 : f(X IN)/16 or f(XCIN)/16 (Note) 1 : Timer 5 overflow Timer mode register 2 (TMR2 : address 00F516) Timer 3 count stop bit 0 : Count start 1 : Count stop Timer 4 count stop bit 0 : Count start 1 : Count stop Timer 5 count stop bit 0 : Count start 1 : Count stop Timer 6 count stop bit 0 : Count start 1 : Count stop Timer 5 count source selection bit 1 0 : f(X IN)/16 or f(XCIN)/16 (Note) 1 : Count source selected by bit 6 of TMR1 Timer 3 count source selection bit 0 0 : f(XIN)/16 or f(XCIN)/16 (Note) 1 0 : f(XCIN) 0 1 : 1 1 : (Bit 6 at address 00C7 16) External clock from P43/TIM3 pin Timer 4 count source selection bits b4 b1 0 0 : Timer 3 overflow 0 1 : f(X IN)/16 or f(XCIN)/16 (Note) 1 0 : f(XIN)/2 or f(XCIN)/2 (Note) 1 1 : f(XCIN) Note : Either f(XIN) or f(XCIN) is selected by bit 7 of the CPU mode register.

M37271EF-XXXSP, M37271EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER Fig. 11. Timer block diagram Timer 1 (8) CM7 TMR15 Timer 1 latch (8) TMR10 TMR12 TMR14 TMR11 TMR13 Timer 2 (8) Timer 2 latch (8) Timer 3 (8) Timer 3 latch (8) Timer 4 (8) Timer 4 latch (8) Timer 5 (8) Timer 5 latch (8) Timer 6 (8) Timer 6 latch (8) Data bus Timer 1 interrupt request Timer 2 interrupt request Timer 3 interrupt request Reset STP instruction TMR20 TMR22 TM3EL Timer 4 interrupt requestTMR24 TMR23 TMR21 TMR16 Timer 5 interrupt requestTMR27 TMR25 Timer 6 interrupt requestTMR17 TMR26 TMR21 XCIN X IN P42/TIM2 P43/TIM3 Selection gate : Connected to black colored side at reset TMR1 : Timer mode register 1 TMR2 : Timer mode register 2 TM3EL : Timer 3 count source switch bit (address 00C7 16) CM : CPU mode register Notes 1: “H” pulse width of external clock inputs TIM2 and TIM3 needs 4 machine cycles or more. 2: When the external clock source is selected, timers 1, 2, and 3 are counted at a rising edge of input signal. FF16 0716 3: In the stop mode or the wait mode, external clock inputs TIM2 and TIM3 cannot be used.

M37271EF-XXXSP, M37271EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER SERIAL I/O The M37271MF-XXXSP has a built-in serial I/O which can either trans- mit or receive 8-bit data in serial in the clock synchronous mode. The serial I/O block diagram is shown in Figure 12. The synchroniz- ing clock I/O pin (SCLK ), and data output pin (SOUT ) also function as port P4, data input pin (SIN) also functions as port P1. Bit 2 of the serial I/O mode register (address 021316) selects whether the synchronizing clock is supplied internally or externally (from the 6/SCLK pin). When an internal clock is selected, bits 1 and 0 select whether f(XIN) is divided by 8, 16, 32, or 64. To use P45/SOUT and P46/SCLK pins for serial I/O, set the corresponding bits of the port P4 direction register (address 00C916) to “0.” To use P17/SIN pin for serial I/O, set the corresponding bit of the port P1 direction register (address 00C3 16) to “0.” Fig. 12. Serial I/O block diagram The operation of the serial I/O function is described below. The func- tion of the serial I/O differs depending on the clock source; external clock or internal clock. Serial I/O shift register (8) Data bus Serial I/O interrupt request Selection gate: Connect to black colored side at reset. Synchronization circuit Frequency divider 1/81/4 1/16 SM1 SM0 Serial I/O counter (8) SM5 : LSB MSB S SM2 1/2XIN P17/SIN P45/SOUT P46/SCLK (Address 021416) XCIN CM7 1/2 Note : When the data is set in the serial I/O register (address 021416), the register functions as the serial I/O shift register. (Note) CM : CPU mode register SM : Serial I/O mode register

M37271EF-XXXSP, M37271EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER Fig. 14. Structure of serial I/O mode register Internal clock—the serial I/O counter is set to “7” during write cycle into the serial I/O register (address 021416), and transfer clock goes “H” forcibly. At each falling edge of the transfer clock after the write cycle, serial data is output from the S OUT pin. Transfer direction can be selected by bit 5 of the serial I/O mode register. At each rising edge of the transfer clock, data is input from the SIN pin and data in the serial I/O register is shifted 1 bit. After the transfer clock has counted 8 times, the serial I/O counter becomes “0” and the transfer clock stops at “H.” At this time the inter- rupt request bit is set to “1.” External clock—when an external clock is selected as the clock source, the interrupt request is set to “1” after the transfer clock has counted 8 times. However, transfer operation does not stop, so con- trol the clock externally. Use the external clock of 500kHz or less with a duty cycle of 50%. The serial I/O timing is shown in Figure 13. When using an external clock for transfer, the external clock must be held at “H” for initializing the serial I/O counter. When switching between an internal clock and an external clock, do not switch during transfer. Also, be sure to ini- tialize the serial I/O counter after switching. Notes 1:On programming, note that the serial I/O counter is set by writing to the serial I/O register with the bit managing in- structions as SEB and CLB instructions. 2: When an external clock is used as the synchronizing clock, write transmit data to the serial I/O register at “H” of the transfer clock input level. Fig. 13. Serial I/O timing (for LSB first) Serial I/O mode register (SM : address 021316) Internal synchronizing clock selection bits b1 b0 0 0 : f(X IN)/8 or f(XCIN)/8 0 1 : f(XIN)/16 or f(XCIN)/16 1 0 : f(XIN)/32 or f(XCIN)/32 1 1 : f(XIN)/64 or f(XCIN)/64 Synchronizing clock selection bit 0 : External clock 1 : Internal clock Port function selection bit 0 : P11, P13 functions as port 1 : SCL1, SDA1 Port function selection bit 0 : P12, P14 functions as port 1 : SCL2, SDA2 Transfer direction selection bit 0 : LSB first 1 : MSB first Fix these bits to “0” Synchroninzing clock Transfer clock Serial I/O register write signal Serial I/O output SOUT D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7 (Note) Serial I/O input S IN Note : When an internal clock is selected, the SOUT pin is at high-impedance after transfer is completed. Interrupt request bit is set to “1”

M37271EF-XXXSP, M37271EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER Fig. 15. PWM block diagram PN PW : PWM mode register 1 (address 020A16) : PWM mode register 2 (address 020B16) : Port P0 register (address 00C016) : Port P0 direction register (address 00C116) Selection gate : Connected to black colored side at reset. is as same contents with the others. PWM1 register (Address 020116) PWM2 register (Address 020216) PWM3 register (Address 020316) PWM4 register (Address 020416) PWM5 register (Address 020516) PWM6 register (Address 020616) ENABLE XIN PWM timing generating circuit Data bus PWM0 register (Address 020016) b7 b0 8-bit PWM circuit POL P04 PW0 D0 4 PWM0 P05 PW1 D0 5 PWM1 P06 PW2 D0 6 PWM2 P07 PW3 D0 7 PWM3 P00 PW4 D0 0 PWM4 P01 PW5 D0 1 PWM5 P02 PW6 D0 2 PWM6 Inside of

M37271EF-XXXSP, M37271EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER Fig. 16. 8-bit PWM timing (a) Pulses showing the weight of each bit 1 3 5 7 9 20 30 40 50 60 70 80 90 100 110 120 130 140 150 160 170 180 190 200 210 220 230 240 250 255 4 12 20 28 36 44 52 60 68 76 84 92 100 108 116 124 132 140 148 156 164 172 180 188 196 204 212 220 228 236 244 252 16 48 80 112 144 176 208 240 24 40 56 72 88 104 120 136 152 168 184 200 216 232 248 32 96 160 224 64 192 Bit 7 2 6 10 14 18 22 26 30 34 38 42 46 50 54 58 62 66 70 74 78 82 86 90 94 98 102 106 110 114 118 122 126 130 134 138 142 146 150 154 158 162 166 170 174 178 182 186 190 194 198 202 206 210 214 218 222 226 230 234 238 242 246 250 254 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 128 Bit 0 PWM output t = 4 ms T = 1024 ms f(XIN) = 8 MHz (b) Example of 8-bit PWM t 0016 (0) 0116 (1) 1816 (24) FF16 (255) T = 256 t

M37271EF-XXXSP, M37271EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER Fig. 17. Structure of PWM-related registers PWM count source selection bit 0 : Count source supply 1 : Count source stop PWM output polarity selection bit 0 : Positive polarity 1 : Negative polarity PWM mode register 1 (PN: address 020A 16) P04/PWM0 output selection bit 0 : P04 output 1 : PWM0 output P05/PWM1 output selection bit 0 : P05 output 1 : PWM1 output P06/PWM2 output selection bit 0 : P06 output 1 : PWM2 output P07/PWM3 output selection bit 0 : P07 output 1 : PWM3 output PWM mode register 2 (PW: address 020B16) P00/PWM4 output selection bit 0 : P00 output 1 : PWM4 output P01/PWM5 output selection bit 0 : P01 output 1 : PWM5 output P02/PWM6 output selection bit 0 : P02 output 1 : PWM6 output Fix this bit to “0.”

M37271EF-XXXSP, M37271EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER A-D control register (ADCON: address 00EF16) A-D conversion completion bit 0 : Conversion in purogress 1 : Conversion completed Analog input pin selection bits b1 b0 0 0 : P26/AD1 0 1 : P25/AD2 1 0 : P24/AD3 1 1 : P40/AD4 VCC connection selection bit 0 : OFF 1 : ON Fix this bit to “0.” A-D CONVERTER (1)A-D Conversion Register (AD) A-D conversion reigister is a read-only register that stores the result of an A-D conversion. This register should not be read during A-D conversion. (2)A-D Control Register (ADCON) The A-D control register controls A-D conversion. Bits 1 and 0 of this register select analog input pins. When these pins are not used as anlog input pins, they are used as ordinary I/O pins. Bit 3 is the A-D conversion completion bit, A-D conversion is started by writing “0” to this bit. The value of this bit remains at “0” during an A-D conversion, then changes to “1” when the A-D conversion is completed. Bit 4 controls connection between the resistor ladder and V CC . When not using the A-D converter, the resistor ladder can be cut off from the internal V CC by setting this bit to “0.” This can realize the low- power dissipation. (3)Comparison Voltage Generator (Resistor Ladder) The voltage generator divides the voltage between VSS and VCC by 256, and outputs the divided voltages to the comparator as the refer- ence voltage V ref. (4)Channel Selector The channel selector connects an analog input pin selected by bits 1 and 0 of the A-D control register to the comparator. (5)Comparator and Control Circuit The conversion result of the analog input voltage and the reference voltage “V ref” is stored in the A-D conversion register. The A-D con- version completion bit and A-D conversion interrupt request bit are set to “1” at the completion of A-D conversion. Fig. 19. A-D comparator block diagram Fig. 18. Structure of A-D control register A-D control register (address 00EF16) A-D control circuit Data bus Switch tree A-D conversion interrupt request Resistor ladder Compa- rator Channel selector A-D conversion register P26/AD1 P25/AD2 P24/AD3 P40/AD4 (address 00EE16) b7 b0 VSS VCC

Note: VREF indicates the voltage of internal VCC . rupt bit is not set to “0” automatically). ter during the A-D conversion. interrupt bit, or the occurrence of an A-D conversion interrupt. 8Read the A-D conversion register to obtain the conversion results. connection selection bit to “0” between steps 7and 8. are automatically performed. “1, ” and the comparison voltage “Vref” is input to the comparator. 3Bit 7 is determined by the comparison result as follows. result is stored in the A-D conversion register. Table 2. Expression for V

M37271EF-XXXSP, M37271EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER [LSB] [LSB] (8) Definition of A-D Conversion Accuracy The definition of A-D conversion accuracy is described below. 1Relative accuracy

• Zero transition error (V0T) The deviation of the input voltage at which A-D conversion output data changes from “0” to “1,” from the corresponding ideal A-D conversion characteristics between 0 and VREF .
• Non-linearity error The deviation of the actual A-D conversion characteristics, from the ideal A-D conversion characteristics between V 0 and V254. (V0 –1/2 5 VREF /256) 1LSB V0T = (VREF – 3/2 5 VREF /256) – V254 1LSB VFST = Non-linearity error = [LSB] [LSB]
• Differential non-linearity error The deviation of the input voltage required to change output data by “1,” from the corresponding ideal A-D conversion characteris- tics between 0 and V REF . 2Absolute accuracy
• Absolute accuracy error The deviation of the actual A-D conversion characteristics, from the ideal A-D conversion characteristics between 0 and V REF . Vn – (1LSB 5 n + V0) 1LSB [LSB]Differential non-linearity error = (Vn+1 – Vn) – 1LSB 1LSB Absolute accuracy error = 1LSB A with respect to absolute accuracy = 1LSB with respect to relative accuracy = Note: The analog input voltage “Vn” at which A-D conversion output data changes from “n” to “n + 1” (n ; 0 to 254) is as follows (refer to Figure 18). V254 – V0 254 VREF 256 [V] [V] Fig. 21. Definition of A-D conversion precision
• Full-scale transition error (VFST ) The deviation of the input voltage at which A-D conversion output data changes from “255” to “254,” from the corresponding ideal A- D conversion characteristics between 0 and V REF . Vn – 1LSBA 5 (n+1/2) 1LSB A Output data Analog input voltage (V)V0 Vn Vn+1 V254 VREF n n+1 254 255 Zero transition error (V0T) Differential non- linearity error LSB A Actual A-D conversion characteristics 1LSB A Ideal A-D conversion characteristics between V0 and V254 LSB A 1LSB Absolute accuracy Non-linearity error Full-scale transition error (VFST ) 1LSB

M37271EF-XXXSP, M37271EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER DATA SLICER The M37271MF-XXXSP includes the data slicer function for the closed caption decoder (referred to as the CCD). This function takes out the caption data superimposed in the vertical blanking interval of a composite video signal. A composite video signal which makes the sync chip’s polarity negative is input to the CV IN pin. When the data slicer function is not used, the data slicer circuit can be cut off by setting bit 0 of the data slicer control register 1 (address 00EA 16) to “0.” Also, the timing signal generating circuit can be cut off by setting bit 0 of data slicer control register 2 (address 00EB16) to “0.” These settings can realize the low-power dissipation. Fig. 22. Data slicer block diagram 100 0000101 Composite video signal Hundred of kiloohms to 1 MW Sync pulse counter register (address 020F16) Clock run-in register 2 (address 00E716) Data slicer control register 2 (address 00EB16) Data slicer control register 1 (address 00EA16) Window register (address 00E216) Clock run-in register 1 (address 00E616) Caption position register (address 00E016) Start bit position register (address 00E116) Clock run-in detect register 1 (address 00E816) Clock run-in detect register 2 (address 00E916) Interrupt request generating circuit Data slicer interrupt request Synchronizing signal counter Synchronizing separation circuit Sync slice circuit Clamping circuit Low-pass filter Timing signal generating circuit Clock run-in determination circuit Data slice line specification circuit Start bit detecting circuit Data clock generating circuit 16-bit shift register Data register 1 (address 00E416) Data register 2 (address 00E516) Sync slice register 3 (address 00E3 16) Data bus Comparator 01 0111 00 0 00 0 0 10 1 0.1mF 470W 560 pF CV IN 1mF 1 kW 200 pF 15 kW H SYNC HLF RVCO Reference voltage generating circuit VHOLD 1000 pF high-order low-order Data slicer ON/OFF Data register 4 (address 00ED16) Data register 3 (address 00EC16) Data slicer control register 3 (address 0210 16) Clock run-in detect register 3 (address 0208 16) Clock run-in register 3 (address 0209 16) External circuit Note: Make the length of wiring which is connected to VHOLD , HLF, RVCO and CVIN pin as short as possible so that a leakage current may not be generated when mounting a resistor or a capacitor on each pin.

M37271EF-XXXSP, M37271EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER 00 0 Data slicer control register 1 (DSC1: address 00EA16) Data slicer control bit 0: Data slicer stopped 1: Data slicer operating Field to be sliced data selection bit Fix this bit to “0.” Data latch completion flag for caption data in main data slice line 0: Data is not yet latched 1: Data is latched Field determination flag 00 0 H sep Vsep H sep Vsep 0 : 1 : Field of main data slice line Field for setting reference voltage b2 b1 0 0 F2 0 1 F1 1 0 F1 and F2 1 1 F1 and F2 Definition of fields 1 (F1) and 2 (F2) H sep VSYNC Vsep F1 : H sep VSYNC Vsep F2 : Data slicer control register 3 (DSC3: address 021016) Line selection bit for slice voltage 0: Main data slice line 1: Sub-data slice line Field of sub-data slice line b2 b1 0 0 F2 0 1 F1 1 0 F1 and F2 1 1 F1 and F2 Field to be sliced data selection bit Setting bit of sub-data slice line Field for setting reference voltage Fix these bits to “0.” Data slicer control register 2 (DSC2: address 00EB16) Timing signal generating circuit control bit 0: Stopped 1: Operating Reference clock source selection bit 0: Video signal 1: H SYNC signal Test bit: read-only Fix these bits to “0.” V-pulse shape determination flag 0: Match 1: Mismatch Fix this bit to “0.” Test bit: read-only Figure 23 shows the structure of the data slicer control registers. Fig. 23. Structure of data slicer control registers

M37271EF-XXXSP, M37271EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER (1) Clamping Circuit and Low-pass Filter This filter attenuates the noise of the composite video signal input from the CVIN pin. The CVIN pin to which composite video signal is input requires a capacitor (0.1 µF) coupling outside. Pull down the CV IN pin with a resistor of hundreds of kiloohms to 1 M . In addition, we recommend to install externally a simple low-pass filter using a resistor and a capacitor at the CV IN pin (refer to Figure 22). (2) Sync Slice Circuit This circuit takes out a composite sync signal from the output signal of the low-pass filter. Figure 24 shows the structure of the sync slice register. (3) Synchronizing Signal Separation Circuit This circuit separates a horizontal synchronizing signal and a vertical synchronizing signal from the composite sync signal taken out in the sync slice circuit. 1Horizontal synchronizing signal (H sep) A one-shot horizontal synchronizing signal Hsep is generated at the falling edge of the composite sync signal.

2 Vertical synchronizing signal (V

sep) As a Vsep signal generating method, it is possible to select one of the following 2 methods by using bit 7 of the sync slice register (address 00E3 16).

• Method 1 The “L” level width of the composite sync signal is measured. If this width exceeds a certain time, a Vsep signal is generated in synchronization with the rising of the timing signal immediately after this “L” level.
• Method 2 The “L” level width of the composite sync signal is measured. If this width exceeds a certain time, it is detected whether a falling of the composite sync signal exits or not in the “L” level period of the timing signal immediately after this “L” level. If a falling exists, a V sep signal is generated in synchronization with the rising of the timing signal (refer to Figure 25). Figure 25 shows a Vsep generating timing. The timing signal shown in the figure is generated from the reference clock which the timing generating circuit outputs. Reading bit 5 of data slicer control register 2 permits determinating the shape of the V-pulse portion of the composite sync signal. As shown in Figure 26, when the A level matches the B level, this bit is “0.” In the case of a mismatch, the bit is “1.” For the pins RVCO and the HLF, connect a resistor and a capacitor as shown in Figure 22. Make the length of wiring which is connected to these pins as short as possible so that a leakage current may not be generated. Note: It takes a few tens of milliseconds until the reference clock becomes stable after the data slicer and the timing signal generating circuit are started. In this period, various timing signals, H sep signals and Vsep signals become unstable. For this reason, take stabilization time into consideration when programming. Fig. 24. Structure of sync slice register Fig. 25. Vsep generating timing (method 2) Composite sync signal Timing signal V sep signal Measure “L” period A Vsep signal is generated at a rising of the timing signal immediately after the “L” level width of the composite sync signal exceeds a certain time. 00 0 Sync slice register (SSL : address 00E316) Fix these bits to “00001012” Vertical synchronizing signal (Vsep) generating method selection bit 0 : Method 1 1 : Method 2 00 1 1

M37271EF-XXXSP, M37271EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER (4) Timing Signal Generating Circuit This circuit generates a reference clock which is 832 times as large as the horizontal synchronizing signal frequency. It also generates various timing signals on the basis of the reference clock, horizontal synchronizing signal and vertical synchronizing signal. The circuit operates by setting bit 0 of data slicer control register 2 (address 00EB 16) to “1.” The reference clock can be used as a display clock for OSD function in addition to the data slicer. The H SYNC signal can be used as a count source instead of the composite sync signal. However, when the HSYNC signal is selected, the data slicer cannot be used. A count source of the reference clock can be selected by bit 1 of data slicer control register 2 (address 00EB 16). Fig. 26. Determination of V-pulse waveform Composite sync signal AB V-pulse (“L” pulse width is long, “H” pulse width is short)Bit 5 of DSC2

2 Selection of field to be sliced data

data of both fields (refer to Figure 23).

3 Specification of line to set slice voltage

4 Field determination

1 Specification of data slice line

the structure of the caption position register. Table 3. Specifying of field whose sets reference voltage

M37271EF-XXXSP, M37271EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER Time from the falling of the horizontal synchronizing signal to occurrence of the start bit 4 5 set value of the start bit position register 5 reference clock period<< Fig. 28. Structure of caption position register (6) Reference Voltage Generating Circuit and Comparator The composite video signal clamped by the clamping circuit is input to the reference voltage generating circuit and the comparator. 1Reference voltage generating circuit This circuit generates a reference voltage (slice voltage) by using the amplitude of the clock run-in pulse in line specified by the data slice line specification circuit. Connect a capacitor between the V HOLD pin and the VSS pin, and make the length of wiring as short as possible so that a leakage current may not be generated. 2Comparator The comparator compares the voltage of the composite video signal with the voltage (reference voltage) generated in the reference voltage generating circuit, and converts the composite video signal into a digital value. (7) Start Bit Detecting Circuit This circuit detects a start bit at line decided in the data slice line specification circuit. For start bit detection, it is possible to select one of the following two types by using bit 1 of the clock run-in register 2 (address 00E7 16). 1After the lapse of the time corresponding to the set value of the start bit position register (address 00E116), the first rising of the composite video signal is detected as a start bit. The time is set in bits 0 to 6 of the start bit position register (address 00E1 16) (refer to Figure 26). Set a value fit for the following conditions. Figure 29 shows the structure of the start bit position register. Time from the falling of the horizontal synchronizing signal to the last rising of the clock run-in Fig. 29. Structure of start bit position register Caption position register (CP : address 00E016) Specification main data slice line 100 Fix these bits to “1002” Start bit generating time Time from a falling of the horizontal synchronizing signal to occurrence of a start bit = 4 5 set value (“00 16” to “7F16”) 5 reference clock period Start bit position register (SP : address 00E116) DSC1 bit 7 control bit 0 : Generation of 16 pulses 1 : Generation of 16 pulses and detection of clock run-in

M37271EF-XXXSP, M37271EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER 2After a falling of the clock run-in pulse set in bits 2 to 0 of clock run- in detect register 2 (address 00E916) is detected, a start bit is detected by sampling a comparator output. A sampling clock for sampling is obtained by dividing the reference clock generated in the timing signal generating circuit by 13. Figure 31 shows the structure of clock run-in detect register 2. The contents of bits 2 to 0 of clock run-in detect register 2 and bit 1 of clock run-in register 2 are written at a falling of the horizontal synchronizing signal. For this reason, even if an instruction for setting is executed, the contents of the register cannot be rewritten until a falling of the horizontal synchronizing signal. Fig. 30. Structure of clock run-in register 2 (8) Clock run-in determination circuit This circuit sets a window in the clock run-in portion in the composite video signal, and then determinates clock run-in by counting the number of pulses in this window. Set the time from a falling of the horizontal synchronizing signal to a start of the window by bits 0 to 5 of the window register (address 00E2 16; refer to Figure 32). The window ends according to the contents of the setting of the start bit position register (refer to Figure 29). Fig. 32. Structure of window register Start bit detecting method selection bit 0 : Method 1 1 : Method 2 Clock run-in register 2 (CR2 : address 00E7 16) Fix this bit to “1” Fix these bits to “1001112” 00111 1 Fig. 31. Structure of clock run-in detect register 2 Window start time Time from a falling of the horizontal synchronizing signal to a start of the window = 4 5 set value (“00 16” to “3F16”) 5 reference clock period Window register (WN : address 00E216) Fix these bits to “0” Clock run-in pulses for sampling b2 b1 b0 0 0 0 : Not available 0 0 1 : 1st pulse 0 1 0 : 2nd pulse 0 1 1 : 3rd pulse 1 0 0 : 4th pulse 1 0 1 : 5th pulse 1 1 0 : 6th pulse 1 1 1 : 7th pulse Clock run-in detect register 2 (CRD2 : address 00E9 16) Data clock generating time Time from detection of a start bit to occurrence of a data clock = (13 + set value) 5 reference clock period

M37271EF-XXXSP, M37271EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER Fig. 33. Structure of clock run-in register 1 Fig. 36. Structure of clock run-in detect registers 1and 3 Fig. 35. Window setting Fig. 34. Structure of clock run-in register 3 For the main data slice line, the count value of pulses in the window is stored in clock run-in register 1 (address 00E616; refer to Figure 33). For the sub-data slice line, the count value of pulses in the window is stored in clock run-in register 3 (address 0209 16; refer to Figure 34). When this count value is 4 to 6, it is determined as a clock run-in. Accordingly, set the count value so that the window may start after the first pulse of the clock run-in (refer to Figure 35). The contents to be set in the window register are written at a falling of the horizontal synchronizing signal. For this reason, even if an instruction for setting is executed, the contents of the register cannot be rewritten until a falling of the horizontal synchronizing signal. For the main data slice line, reference clock is counted in the period from a falling of the clock pulse set in bits 0 to 2 of the clock run-in detect register 2 (address 00E9 16) to the next falling. The count value is stored in bits 3 to 7 of the clock run-in detect register 1 (address 00E8 16) (When the count value exceeds “1F16,” “1F16” is held). For the sub-data slice line, the count value is stored in bits 3 to 7 of the clock run-in detect register 3 (address 020816). Read out these bits after the occurence of a data slicer interrupt (refer to (11) Interrupt Request Generating Circuit). Figure 36 shows the structure of clock run-in detect registers 1 and Clock run-in count value of sub-data slice line Clock run-in register 3 (CR3 : address 020916) Data latch completion flag for caption data in sub-data slice line 0: Data is not latched yet 1: Data is latched Data slice line selection bit for interrupt request 0: Main data slice line 1: Sub-data slice line Interrupt mode selection bit 0: Interrupt occurs at end of data slice line 1: Interrupt occurs at completion of caption data latch ]When the count value in the window is 4 to 6, this is determined as a clock run-in. Horizontal synchronizing signal Composite video signal Window Clock run-in Start bit data + 16-bit data Time to be set in the window register Time to be set in the start bit position register Number of reference clocks to be counted in one clock run-in pulse period Clock run-in detect registers 1, 3 ( CRD1 : address 00E8 16) ( CRD3 : address 020816) Test bits : read-only Clock run-in count value of main-data slice line Clock run-in register 1 (CR1 : address 00E616) Fix these bits to “01012” 0101

16) and data register 1 (address 00E416), respectively. slicer interrupt (refer to (11) Interrupt Request Generating Circuit). after the occurence of a data slicer interrupt request. Table 4. Setting conditions for caption data latch completion flag bit detected in the start bit detecting circuit. Table 5. Occurence sources of interrupt request

M37271EF-XXXSP, M37271EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER Fig. 37. Sync pulse counter register Sync pulse counter register (SYC : address 020F16) Count value Count source Count time 0: HSYNC signal 1: Composite sync signal f(XIN)/213 (1024 ms, f(XIN) = 8 MHz) (12) Synchronizing Signal Counter The synchronizing signal counter counts the composite sync signal taken out from a video signal in the data slicer circuit or the vertical synchronizing signal V sep as a count source. The count value in a certain time (T time) generated by f(XIN)/213 or f(XIN)/213 is stored into the 5-bit latch. Accordingly, the latch value changes in the cycle of T time. When the count value exceeds “1F16,” “1F16” is stored into the latch. The latch value can be obtained by reading out the sync pulse counter register (address 020F 16). A count source is selected by bit 5 of the sync pulse counter register. The synchronizing signal counter is used when bit 0 of the PWM mode register 1 (address 02EA16). Figure 37 shows the structure of the sync pulse counter and Figure 38 shows the synchronizing signal counter block diagram. Fig. 38. Synchronizing signal counter block diagram Reset 5-bit counter Latch (5 bits) f(XIN)/213 Composite sync signal H SYNC signal Counter Sync pulse counter register Data bus Selection gate : connected to black colored side when reset.

Table 6. Multi-master I2C-BUS interface functions ports (SCL1, SCL2, SDA1, SDA2). face and Table 6 shows multi-master I2C-BUS interface functions. control register, the I2C status register and other control circuits.

M37271EF-XXXSP, M37271EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER (1) I2C Data Shift Register The I2C data shift register (S0 : address 00F616) is an 8-bit shift register to store receive data and write transmit data. When transmit data is written into this register, it is transferred to the outside from bit 7 in synchronization with the SCL clock, and each time one-bit data is output, the data of this register are shifted one bit to the left. When data is received, it is input to this register from bit 0 in synchronization with the SCL clock, and each time one-bit data is input, the data of this register are shifted one bit to the left. The I 2C data shift register is in a write enable status only when the ES0 bit of the I2C control register (address 00F916) is “1.” The bit counter is reset by a write instruction to the I2C data shift register. When both the ES0 bit and the MST bit of the I2C status register (address 00F816) are “1,” the SCL is output by a write instruction to the I2C data shift register. Reading data from the I2C data shift regis- ter is always enabled regardless of the ES0 bit value. Note: To write data into the I2C data shift register after setting the MST bit to “0” (slave mode), keep an interval of 8 machine cycles or more. (2) I2C Address Register The I2C address register (address 00F716) consists of a 7-bit slave ___ address and a read/write bit. In the addressing mode, the slave ad- dress written in this register is compared with the address data to be received immediately after the START condition are detected. ____ n Bit 0: Read /write bit (RBW) Not used in the 7-bit addressing mode. In the 10-bit addressing mode, the first address data to be received is compared with the contents (SAD6 to SAD0 + RBW) of the I 2C address register. The RBW bit is cleared to “0” automatically when the stop condition is detected. n Bits 1 to 7: Slave address (SAD0–SAD6) These bits store slave addresses. Regardless of the 7-bit address- ing mode and the 10-bit addressing mode, the address data trans- mitted from the master is compared with the contents of these bits. (3) I2C Clock Control Register The I2C clock control register (address 00FA16) is used to set ACK control, SCL mode and SCL frequency. n Bits 0 to 4: SCL frequency control bits (CCR0–CCR4) These bits control the SCL frequency. Refer to Table 7. n Bit 5: SCL mode specification bit (FAST MODE) This bit specifies the SCL mode. When this bit is set to “0,” the stan- dard clock mode is set. When the bit is set to “1,” the high-speed clock mode is set. n Bit 6: ACK bit (ACK BIT) This bit sets the SDA status when an ACK clock ] is generated. When this bit is set to “0,” the ACK return mode is set and make SDA “L” at the occurrence of an ACK clock. When the bit is set to “1,” the ACK non-return mode is set. The SDA is held in the “H” status at the oc- currence of an ACK clock. However, when the slave address matches the address data in the reception of address data at ACK BIT = “0,” the SDA is automatically made “L” (ACK is returned). If there is a mismatch between the slave address and the address data, the SDA is automatically made “H”(ACK is not returned). ]ACK clock: Clock for acknowledgement n Bit 7: ACK clock bit (ACK) This bit specifies a mode of acknowledgment which is an acknowl- edgment response of data transmission. When this bit is set to “0,” the no ACK clock mode is set. In this case, no ACK clock occurs after data transmission. When the bit is set to “1,” the ACK clock mode is set and the master generates an ACK clock upon comple- tion of each 1-byte data transmission.The device for transmitting address data and control data releases the SDA at the occurrence of an ACK clock (make SDA “H”) and receives the ACK bit generated by the data receiving device. Note: Do not write data into the I 2C clock control register during transmitting. If data is written during transmitting, the I2C clock generator is reset, so that data cannot be transmitted nor- mally. Fig. 40. Structure of I2C address register SAD6 SAD5 SAD4 SAD3 SAD2 SAD1 SAD0 RBW Slave address I2 C address register (S0D: address 00F716) Read/write bit

Table 7. Set values of I2C clock control register and SCL number of bits specified with these bits are transmitted. the address data is always transmitted and received in 8 bits. When ES0 = “0,” the following is performed.

• PIN = “1,” BB = “0” and AL = “0” are set (they are bits of the I2C status register at address 00F816 ).
• Writing data to the I2C data shift register (address 00F616) is dis- abled. n Bit 4: Data format selection bit (ALS) This bit decides whether or not to recognize slave addresses. When this bit is set to “0,” the addressing format is selected, so that ad- dress data is recognized. When a match is found between a slave address and address data as a result of comparison or when a gen- eral call (refer to “(5) I 2C Status Register,” bit 1) is received, trans- mission processing can be performed. When this bit is set to “1,” the free data format is selected, so that slave addresses are not recog- nized. n Bit 5: Addressing format selection bit (10BIT SAD) This bit selects a slave address specification format. When this bit is set to “0,” the 7-bit addressing format is selected. In this case, only the high-order 7 bits (slave address) of the I 2C address register (ad- dress 00F716) are compared with address data. When this bit is set to “1,” the 10-bit addressing format is selected, all the bits of the I2C address register are compared with address data. n Bits 6 and 7: Connection control bits between I 2C-BUS interface and ports (BSEL0, BSEL1) These bits controls the connection between SCL and ports or SDA and ports (refer to Figure 42). Fig. 41. Structure of I2C clock control register ACK ACK BIT FAST MODE CCR4 CCR3 CCR2 CCR1 CCR0 I2C clock control register (S2 : address 00FA16) SCL frequency control bits Refer to Table 7. SCL mode specification bit 0 : Standard clock mode 1 : High-speed clock mode ACK bit 0 : ACK is returned. 1 : ACK is not returned. ACK clock bit 0 : No ACK clock 1 : ACK clock SCL frequency (at φ = 4MHz, unit : kHz) Setting value of CCR4–CCR0 Standard clock mode Setting disabled Setting disabled Setting disabled Setting disabled Setting disabled 100 83.3 500/CCR value 17.2 16.6 16.1 High-speed clock mode Setting disabled Setting disabled Setting disabled 333 250 400(Note) 166 1000/CCR value 34.5 33.3 32.3 CCR4 CCR3 CCR2 CCR1 CCR0 Note: At 400 kHz in the high-speed clock mode, the duty is 40%. In the other cases, the duty is 50%.

M37271EF-XXXSP, M37271EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER Fig. 43. Structure of I2C control register BSEL1 BSEL0 10 BIT SAD ALS ES0 BC2 BC1 BC0 Connection control bits between I2C-BUS interface and ports b7 b6 Connection port 0 0 : None 0 1 : SCL1, SDA1 1 0 : SCL2, SDA2 1 1 : SCL1, SDA1, SCL2, SDA2 I 2C control register (S1D : address 00F916) Bit counter (Number of transmit/receive bits) b2 b1 b0 0 0 0 : 8 0 0 1 : 7 0 1 0 : 6 0 1 1 : 5 1 0 0 : 4 1 0 1 : 3 1 1 0 : 2 1 1 1 : 1 I 2C-BUS interface use enable bit 0 : Disabled 1 : Enabled Data format selection bit 0 : Addressing format 1 : Free data format Addressing format selection bit 0 : 7-bit addressing format 1 : 10-bit addressing format (5) I2C Status Register The I2C status register (address 00F816) controls the I2C-BUS inter- face status. The low-order 4 bits are read-only bits and the high- order 4 bits can be read out and written to. n Bit 0: Last receive bit (LRB) This bit stores the last bit value of received data and can also be used for ACK receive confirmation. If ACK is returned when an ACK clock occurs, the LRB bit is set to “0.” If ACK is not returned, this bit is set to “1.” Except in the ACK mode, the last bit value of received data is input. The state of this bit is changed from “1” to “0” by execut- ing a write instruction to the I 2C data shift register (address 00F616). n Bit 1: General call detecting flag (AD0) This bit is set to “1” when a general call] whose address data is all “0” is received in the slave mode. By a general call of the master device, every slave device receives control data after the general call. The AD0 bit is set to “0” by detecting the STOP condition or START con- dition. ]General call: The master transmits the general call address “00 16” to all slaves. n Bit 2: Slave address comparison flag (AAS) This flag indicates a comparison result of address data. 1In the slave receive mode, when the 7-bit addressing format is selected, this bit is set to “1” in one of the following conditions.

• The address data immediately after occurrence of a START condition agrees with the slave address stored in the high-order 7 bits of the I 2C address register (address 00F716).
• A general call is received. 2In the slave reception mode, when the 10-bit addressing format is selected, this bit is set to “1” with the following condition.
• When the address data is compared with the I2C address register (8 bits consisted of slave address and RBW), the first bytes agree. 3The state of this bit is changed from “1” to “0” by executing a write instruction to the I 2C data shift register (address 00F616). Fig. 42. Connection port control by BSEL0 and BSEL1 “0” “1” BSEL0 SCL1/P11 SCL2/P12 “0” “1” BSEL1 “0” “1” BSEL0 SDA1/P1 SDA2/P1 4 “0” “1” BSEL1 Multi-master I2C-BUS interface SCL SDA Note: When using multi-master I2C-BUS interface, set bits 3 and 4 of the serial I/O mode register (address 0213 16) to “1.”

M37271EF-XXXSP, M37271EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER n Bit 3: Arbitration lost] detecting flag (AL) In the master transmission mode, when the SDA is made “L” by any other device, arbitration is judged to have been lost, so that this bit is set to “1.” At the same time, the TRX bit is set to “0,” so that immedi- ately after transmission of the byte whose arbitration was lost is com- pleted, the MST bit is set to “0.” In the case arbitration is lost during slave address transmission, the TRX bit is set to “0” and the recep- tion mode is set. Consequently, it becomes possible to receive and recognize its own slave address transmitted by another master de- vice. ]Arbitration lost: The status in which communication as a master is disabled. n Bit 4: I 2C-BUS interface interrupt request bit (PIN) This bit generates an interrupt request signal. Each time 1-byte data is transmitted, the state of the PIN bit changes from “1” to “0.” At the same time, an interrupt request signal occurs to the CPU. The PIN bit is set to “0” in synchronization with a falling of the last clock (in- cluding the ACK clock) of an internal clock and an interrupt request signal occurs in synchronization with a falling of the PIN bit. When the PIN bit is “0,” the SCL is kept in the “0” state and clock generation is disabled. Figure 45 shows an interrupt request signal generating timing chart. The PIN bit is set to “1” in one of the following conditions.

• Executing a write instruction to the I2C data shift register (address 00F616).
• When the ES0 bit is “0”
• At reset The conditions in which the PIN bit is set to “0” are shown below:
• Immediately after completion of 1-byte data transmission (includ- ing when arbitration lost is detected)
• Immediately after completion of 1-byte data reception
• In the slave reception mode, with ALS = “0” and immediately after completion of slave address or general call address reception
• In the slave reception mode, with ALS = “1” and immediately after completion of address data reception n Bit 5: Bus busy flag (BB) This bit indicates the status of use of the bus system. When this bit is set to “0,” this bus system is not busy and a START condition can be generated. When this bit is set to “1,” this bus system is busy and the occurrence of a START condition is disabled by the START condi- tion duplication prevention function (Note). This flag can be written by software only in the master transmission mode. In the other modes, this bit is set to “1” by detecting a START condition and set to “0” by detecting a STOP condition. When the ES0 bit of the I 2C control register (address 00F916) is “0” and at reset, the BB flag is kept in the “0” state. n Bit 6:Communication mode specification bit (transfer direction specification bit: TRX) This bit decides a direction of transfer for data communication. When this bit is “0,” the reception mode is selected and the data of a trans- mitting device is received. When the bit is “1,” the transmission mode is selected and address data and control data are output onto the SDA in synchronization with the clock generated on the SCL. When the ALS bit of the I 2C control register (address 00F916) is “0” in the slave reception mode is selected, the TRX bit is set to “1” (transmit) if the least significant bit (R/W bit) of the address data trans- mitted by the master is “1.” When the ALS bit is “0” and the R/W bit is “0,” the TRX bit is cleared to “0” (receive). The TRX bit is cleared to “0” in one of the following conditions.
• When arbitration lost is detected.
• When a STOP condition is detected.
• When occurence of a START condition is disabled by the START condition duplication preventing function (Note).
• With MST = “0” and when a START condition is detected.
• With MST = “0” and when ACK non-return is detected.
• At reset n Bit 7: Communication mode specification bit (master/slave speci- fication bit: MST) This bit is used for master/slave specification for data communica- tion. When this bit is “0,” the slave is specified, so that a START condition and a STOP condition generated by the master are re- ceived, and data communication is performed in synchronization with the clock generated by the master. When this bit is “1,” the master is specified and a START condition and a STOP condition are gener- ated, and also the clocks required for data communication are gen- erated on the SCL. The MST bit is cleared to “0” in one of the following conditions.
• Immediately after completion of 1-byte data transmission when ar- bitration lost is detected
• When a STOP condition is detected.
• When occurence of a START condition is disabled by the START condition duplication preventing function (Note).
• At reset Note: The START condition duplication prevention function disables the occurence of a START condition, reset of bit counter and SCL output when the following condition is satisfied:
• a START condition is set by another master device.

tion generating timing table. for setting the MST bit and the TRX bit to “1” and the BB bit to “0”. tion/STOP condition generating timing table. Table 8. START condition/STOP condition generating timing notes the number of φ cycles.

fied, a START/STOP condition can be detected. dress communication formats is described below. ing format is selected, refer to Figure 49, (1) and (2). data but also is processed as an address data bit. Table 9. START condition/STOP condition detecting conditions notes the number of φ cycles.

M37271EF-XXXSP, M37271EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER When the first-byte address data matches the slave address, the AAS bit of the I2C status register (address 00F816) is set to “1.” After the second-byte address data is stored into the I2C data shift register (address 00F616), make an address comparison between the sec- ond-byte data and the slave address by software. When the address data of the 2 bytes matches the slave address, set the RBW bit of the I 2C address register (address 00F716) to “1” by software. This pro- cessing can match the 7-bit slave address and R/W data, which are received after a RESTART condition is detected, with the value of the I 2C address register (address 00F716). For the data transmission format when the 10-bit addressing format is selected, refer to Figure 49, (3) and (4). (10) Example of Master Transmission An example of master transmission in the standard clock mode, at the SCL frequency of 100 kHz and in the ACK return mode is shown below.

1 Set a slave address in the high-order 7 bits of the I

register (address 00F716) and “0” in the RBW bit.

2 Set the ACK return mode and SCL = 100 kHz by setting “8516” in

the I2C clock control register (address 00FA16).

3 Set “1016” in the I2C status register (address 00F816) and hold

the SCL at the “H” level.

4 Set a communication enable status by setting “4816” in the I2C

control register (address 00F916).

5 Set the address data of the destination of transmission in the high-

order 7 bits of the I2C data shift register (address 00F616) and set “0” in the least significant bit.

6 Set “F016” in the I2C status register (address 00F816) to generate

a START condition. At this time, an SCL for 1 byte and an ACK clock automatically occurs. 7 Set transmit data in the I2C data shift register (address 00F616). At this time, an SCL and an ACK clock automatically occurs.

8 When transmitting control data of more than 1 byte, repeat step

9 Set “D016” in the I2C status register (address 00F816). After this, if ACK is not returned or transmission ends, a STOP condition occurs. (11) Example of Slave Reception An example of slave reception in the high-speed clock mode, at the SCL frequency of 400 kHz, in the ACK non-return mode and using the addressing format is shown below. register (address 00F716) and “0” in the RBW bit.

2 Set the no ACK clock mode and SCL = 400 kHz by setting “2516”

in the I2C clock control register (address 00FA16). the SCL at the “H” level. control register (address 00F916).

5 When a START condition is received, an address comparison is

made. 6 •When all transmitted addresses are “0” (general call) AD0 of the I2C status register (address 00F816) is set to “1” and an interrupt request signal occurs.

• When the transmitted addresses match the address set in 1 ASS of the I2C status register (address 00F816) is set to “1” and an interrupt request signal occurs.
• In the cases other than the above AD0 and AAS of the I2C status register (address 00F816) are set to “0” and no interrupt request signal occurs. 7 Set dummy data in the I2C data shift register (address 00F616). 8 When receiving control data of more than 1 byte, repeat step 7. 9 When a STOP condition is detected, the communication ends.

Table 10 outlines the OSD functions of the M37271MF-XXXSP. ter. There are 3 display modes and they are selected by a block unit. The features of each mode are described below. Table 10. Features of each display mode Notes 1: The divide ratio of the frequency divider (the pre-divide circuit) is referred as “pre-divide ratio” hereafter. 2: The character size is specified with dot size and pre-divide ratio (refer to (3) Dote size).

M37271EF-XXXSP, M37271EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER The OSD circuit has an extended display mode. This mode allows multiple lines (16 lines or more) to be displayed on the screen by interrupting the display each time one line is displayed and rewriting data in the block for which display is terminated by software. Figure 50 shows the configuration of OSD character. Figure 51 shows the block diagram of the OSD control circuit. Figure 52 shows the structure of the OSD control register. Figure 53 shows the structure of the block control register. Fig. 50. Configuration of OSD character 16 dots 26 dots 20 dots Underline area+ Blank area+ : Displayed only in CCD mode. Blank area 26 dots 20 dots Character font 26 dots 20 dots OSD mode CC mode Extra font EXOSD mode 16 dots 16 dots 16 dots 16 dots logical sum (OR)

M37271EF-XXXSP, M37271EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER Fig. 51. Block diagram of OSD control circuit Display oscillation circuit OSC1 OSC2 H SYNC VSYNC RAM for OSD 20-bit5 40 5 16 Data bus RAM for OSD (16-bit5 205 320) + 16-bit5 265 32) Shift register 2 16-bit Shift register 1 16-bit Data slicer clock Clock for OSD Output circuit R G B I1 I2 OSD Control circuit OUT1 OUT2 Control registers for OSD (address 00CE16) (address 00CF16) (addresses 00D016 to 00DF16) (address 021616) (address 021716) (address 021816) (address 021916) (address 021B16) (addresses 021C16 to 021F16) (addresses 022016 to 023F16) OSD control register Horizontal position register Block control registers Clock source control register I/O polarity control register Raster color register Extra font color register Border color register Window H/L registers Vertical registers

2 : Shadow border is output at right and bottom side of the font. 3 : Set “00” during displaying extra fonts. Table 11. Setting value of block control registers

the same time and overlayed on each other. combinations assign the block to layer 1. register (refer to Figure 52). Note: When using the dual layer OSD, note Table 12. Table 12. Conditions of dual layer Note: For the pre-divide ratio of the layer 2, select the same as the layer 1’s ratio by bit 6 of the clock control register.

M37271EF-XXXSP, M37271EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER (2) Display Position The display positions of characters are specified in units called a “block.” There are 16 blocks, blocks 1 to 16. Up to 40 characters can be displayed in each block (refer to (6) Memory for OSD). The display position of each block can be set in both horizontal and vertical directions by software. The display position in the horizontal direction can be selected for all blocks in common from 256-step display positions in units of 4 T OSC (TOSC = oscillating cycle for OSD). The display position in the vertical direction for each block can be selected from 1024-step display positions in units of 1 T H ( TH = HSYNC cycle). Blocks are displayed in conformance with the following rules:

1 When the display position is overlapped with another block

(Figure 56, (b)), a lower block number (1 to 16) is displayed on the front.

2 When another block display position appears while one block is

displayed (Figure 56 (c)), the block with a larger set value as the vertical display start position is displayed. However, do not dis- play block with the dot size of 2T C 5 2H or 3TC 5 3H during dis- play period (]) of another block. ] In the case of OSD mode block: 20 dots in vertical from the verti- cal display start position. ] In the case of CCD or EXOSD mode block: 26 dots in vertical from the vertical display start position. Fig. 56. Display position (HR) VP12, VP22 Block 1 Block 2 (a) Example when each block is separated VP13, VP23 Block 3 (HR) VP11, VP21 VP12, VP22 Block 1 (b) Example when block 3 overlaps with block 1 (Block 3 is not displayed) (HR) VP11, VP21 VP12, VP22 (c) Example when block 3 overlaps in process of block 1 Block 1 Block 3 Note: VP1i or VP2i (i : 1 to 6) indicates the contents of vertical position registers 1i or 2i. VP11, VP21

M37271EF-XXXSP, M37271EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER The display position in the vertical direction is determined by count- ing the horizontal sync signal (HSYNC ). At this time, it starts to count the rising edge (falling edge) of HSYNC signal from after about 1 ma- chine cycle of rising edge (falling edge) of VSYNC signal. So interval from rising edge (falling edge) of VSYNC signal to rising edge (falling edge) of HSYNC signal needs enough time (2 machine cycles or more) for avoiding jitter. The polarity of HSYNC and VSYNC signals can se- lect with the I/O polarity control register (address 021716). For de- tails, refer to (15) OSD Output Pin Control. Note: When bits 0 and 1 of the I/O polarity control register (address 021716) are set to “1” (negative polarity), the vertical position is determined by counting falling edge of HSYNC signal after rising edge of VSYNC control signal in the microcomputer (re- fer to Figure 57). Fig. 57. Supplement explanation for display position The vertical position for each block can be set in 1024 steps (where each step is 1TH (TH : HSYNC cycle)) as values “0016” to “FF16” in vertical position register 1i (i = 1 to 16) (addresses 022016 to 022F16) and values “0016” to “FF16” in the vertical position register 2i (i = 1 to 16) (addresses 023016 to 023F16). The structure of the vertical posi- tion registers is shown in Figure 58. Fig. 58. Structure of vertical position registers The horizontal position is common to all blocks, and can be set in 256 steps (where 1 step is 4TC , TC being the oscillating cycle for display) as values “0016” to “FF16” in bits 0 to 7 of the horizontal position register (address 00CF16). The structure of the horizontal position register is shown in Figure 59. Fig. 59. Structure of horizontal position register When bits 0 and 1 of the I/O polarity control register (address 021716) are set to “1” (negative polarity) VSYNC signal input VSYNC control signal in microcomputer 0.25 to 0.50 [ms] ( at f(X IN) = 8MHz) Period of counting H SYNC signal (Note 1) H SYNC signal input Not count 12345 Notes 1 : Do not generate falling edge of HSYNC signal near rising edge of VSYNC control signal in microcomputer to avoid jitter. 2 : The pulse width of VSYNC and HSYNC needs 8 machine cycles or more. Vertical position register 1i (i = 1 to 16) (VP1i : addresses 022016 to 022F16) Control bits of vertical display start positions (Note) Vertical display start positions (low-order 8 bits) T H 5 (setting value of low-order 2 bits of VP2i5 16 +setting value of low-order 4 bits of VP1i5 16 +setting value of low-order 4 bits of VP1i5 16 ) Note : Set values except “0016” and “0116” to VP1i when VP2i is “0016.” Vertical position register 2i (i = 1 to 16) (VP2i : addresses 023016 to 023F16) Control bits of vertical display start positions (Note) Vertical display start positions (high-order 2 bits) T H 5 (setting value of low-order 2 bits of VP2i5 16 +setting value of low-order 4 bits of VP1i5 16 +setting value of low-order 4 bits of VP1i5 16 ) Note : The setting value synchronizes with a rising (falling) of the VSYNC . Horizontal position register (HP : address 00CF16) Control bits of horizontal display start positions Horizontal display start positions OSC 5 (setting value of high-order 4 bits5 16 +setting value of low-order 4 bits5 16 )

M37271EF-XXXSP, M37271EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER Notes 1 : 1TC (TC : OSD clock cycle divided by prescaler) gap oc- curs between the horizontal display start position set by the horizontal position register and the most left dot of the 1st block. Accordingly, when 2 blocks have different pre- divide ratios, their horizontal display start position will not match. 2 : The horizontal start position is based on the OSD clock source cycle selected for each block. Accordingly, when 2 blocks have different OSD clock source cycles, their hori- zontal display start position will not match. Fig. 60. Notes on horizontal display start position (3) Dot Size The dot size can be selected by a block unit. The dot size in vertical direction is determined by dividing HSYNC in the vertical dot size con- trol circuit. The dot size in horizontal is determined by dividing the following clock in the horizontal dot size control circuit : the clock gained by dividing the OSD clock source (data slicer clock, OSC1) in the pre-divide circuit. The clock cycle divided in the pre-divide circuit is defined as 1T C . The dot size of the layer 1 is specified by bits 6 to 3 of the block control register. The dot size of the layer 2 is specified by the following bits : bits 3 and 4 of the block control register, bit 6 of the clock source control register. Refer to Figure 53 (the structure of the block control regis- ter), refer to Figure 62 (the structure of the clock source control reg- ister). The block diagram of dot size control circuit is shown in Figure 61. Notes 1 : The pre-divide ratio = 3 cannot be used in the CC mode. 2 : The pre-divide ratio of the OSD mode block on the layer 2 must be same as that of the CC mode block on the layer 1 by bit 6 of the clock source control register. 3 : In the bi-scan mode, the dot size in the vertical direction is 2 times as compared with the normal mode. Refer to “(13) Scan Mode” about the scan mode. Fig. 61. Block diagram of dot size control circuit H SYNC 1TC 1TC Block 1 (Pre-divide ratio 1, clock source data slicer clock) 1TC 1TC 4TOSC 5 N 4TOSC’ 5 N Note 1 Note 2 Block 2 (Pre-divide ratio 2, clock source data slicer clock) Block 3 (Pre-divide ratio 3, clock source data slicer clock) Block 4 (Pre-divide ratio 3, clock source OSC1) Data slicer clock H SYNC OSC1 CS 0 Synchronization Cycle5 2circuit Cycle5 3 Pre-divide circuit Clock cycle = 1TC Horizontal dot size control circuit Vertical dot size control circuit OSD control circuit = = = =

• Data slicer clock output from the data slicer (approximately 26 MHz)
• Clock from the LC oscillator supplied from the pins OSC1 and OSC2
• Clock from the ceramic resonator or the quartz-crystal oscillator from the pins OSC1 and OSC2 This OSD clock for each block can be selected by the following bits : bit 7 of the port P3 direction register, bits 5 and 4 of the clock source control register (addresses 0216 16). A variety of character sizes can be obtained by combining dot sizes with OSD clocks. When not us- ing the pins OSC1 and OSC2 for the OSD clock I/O pins, the pins can be used as sub-clock I/O pins or port P6. Fig. 63. Block diagram of OSD selection circuit Fig. 62. Structure of clock control register

Table 13. Setting for P63/OSC1/XCIN, P64/OSC2/XCOUT data slicer clock for software debugging.

M37271EF-XXXSP, M37271EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER (5) Field Determination Display To display the block with vertical dot size of 1/2H, whether an even field or an odd field is determined through differences in a synchro- nizing signal waveform of interlacing system. The dot line 0 or 1 (re- fer to Figure 65) corresponding to the field is displayed alternately. In the following, the field determination standard for the case where both the horizontal sync signal and the vertical sync signal are nega- tive-polarity inputs will be explained. A field determination is deter- mined by detecting the time from a falling edge of the horizontal sync signal until a falling edge of the V SYNC control signal (refer to Figure 57) in the microcomputer and then comparing this time with the time of the previous field. When the time is longer than the comparing time, it is regarded as even field. When the time is shorter, it is re- garded as odd field The contents of this field can be read out by the field determination flag (bit 7 of the I/O polarity control register at address 0217 16). A dot line is specified by bit 6 of the I/O polarity control register (refer to Figure 65). However, the field determination flag read out from the CPU is fixed to “0” at even field or “1” at odd field, regardless of bit 6. Fig. 64. Structure of I/O polarity control register I/O polarity control register (PC : address 021716) H SYNC input polarity switch bit 0 : Positive polarity input 1 : Negative polarity input OUT2 output polarity switch bit 0 : Positive polarity output 1 : Negative polarity output VSYNC input polarity switch bit 0 : Positive polarity input 1 : Negative polarity input R/G/B output polarity switch bit 0 : Positive polarity output 1 : Negative polarity output I1, I2 output polarity switch bit 0 : Positive polarity output 1 : Negative polarity output OUT1 output polarity switch bit 0 : Positive polarity output 1 : Negative polarity output Display dot line selection bit (Note) Field determination flag 0 : Even field 1 : Odd field Note : Refer to Figure 65. “ ” at odd field “ ” at odd field 1 : “ ” at even field 0 : “ ” at even field

M37271EF-XXXSP, M37271EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER Fig. 65. Relation between field determination flag and display font Both HSYNC signal and VSYNC signal are negative-polarity input Field Even Odd Field determination flag(Note) Display dot line selection bit Display dot line 0 (T2 > T1) 1 (T3 < T2) When using the field determination flag, be sure to set bit 0 of the PWM mode register 1 (address 020A16) to “0.” Character ROM font configuration diagram Dot line 0 Dot line 1 Odd Dot line 0 Dot line 1 (n–1) field (Odd-numbered) 0.25 to 0.50[ms] at f(XIN) = 8 MHz CC mode · EXOSD mode 13 57 9 1 1 1 3 1 5 2 4 6 8 10 12 14 16 13 5 7 9 1 1 1 3 1 52 4 6 8 10 12 14 16 OSD mode H SYNC V SYNC and V SYNC control signal in microcom- puter Upper : V SYNC signal Lower : VSYNC control signal in micro- computer (n) field (Even-numbered) (n+1) field (Odd-numbered) When the display dot line selection bit is “0,” the “ ” font is displayed at even field, the “ ” font is displayed at odd field. Bit 7 of the I/O polarity control register can be read as the field determination flag : “1” is read at odd field, “0” is read at even field. Note : The field determination flag changes at a rising edge of the VSYNC control signal (negative-polarity input) in the microcomputer.

M37271EF-XXXSP, M37271EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER (6) Memory for OSD There are 2 types of memory for OSD : ROM for OSD (addresses 1080016 to 1567F16, 1800016 to 1E43F16) used to store character dot data (masked) and RAM for OSD (addresses 080016 to 0FFF16) used to specify the characters and colors to be displayed. The fol- lowing describes each type of memory.

11111 ROM for OSD (addresses 10800 16 to 1567F16, 1800016 to

1E43F 16) The ROM for OSD contains dot pattern data for characters to be displayed. To actually display the character code and the extra code stored in this ROM, it is necessary to specify them by writing the character code inherent to each character (code determined based on the addresses in the ROM for OSD) into the RAM for OSD. The OSD ROM of the character font has a capacity of 12800 bytes. Since 40 bytes are required for 1 character data, the ROM can stores up to 320 kinds of characters. The OSD ROM of the extra font has a capacity of 1664 bytes. Since 52 bytes are required for 1 character data, the ROM can stores up to 32 kinds of characters. Data of the character font and extra font is specified shown in Figure 66. Fig. 66. OSD character data storing form OSD ROM address of character font data AD16 AD15 AD14 AD13 AD12 AD11 AD10 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 Line number Character code Font bit “0216” to “1516” “0016” to “13F16” 0 : left font 1 : right font OSD ROM address bit Line number/character code/font bit 10 Line number Character code Font bit AD16 AD15 AD14 AD13 AD12 AD11 AD10 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 11 00 00 0216 000016 7FF016 7FF816 601C 16 600C 16 600C 16 600C 16 600C 160916 0316 0416 0516 0616 0716 0816 0A16 601C 16 7FF816 7FF016 630016 638016 61C0 16 60E016 6070161116 0B16 0C 16 0D 16 0E16 0F16 1016 603816 601C 16 600C 16 0000161516 1216 1316 1416 b0b7 b0 b7 0216 000316 000316 000316 000316 000316 000316 000316 0003160916 0316 0416 0516 0616 0716 0816 0A16 000316 000316 000316 000316 000316 000316 000316 0003161116 0B16 0C 16 0D 16 0016 0016 1016 000316 000316 000316 0003161516 1216 1316 1416 b0b7 b0b7 FFFF 16 FFFE 16 000016 0000161916 1616 1716 1816 0016 0116 FFFE 16 FFFF 16 Line number Line number Extra code Font bit “0016” to “1916” “0016” to “1F16” 0 : left font 1 : right font OSD ROM address bit Line number/extra code /font bit Extra code Line number Left font Right font Line number Data in OSD ROM Left font Right font Data in OSD ROM OSD ROM address of extra font data Character font Extra font Font bit

Table 14. Contents of OSD RAM

22222 RAM for OSD (addresses 080016 to 0FFF16)

1 specification part, and color code 2 specification part for each block. Table 14 shows the contents of the RAM for OSD. at 084016, and write the color code 2 at 082816. The structure of the RAM for OSD is shown in Figure 68. can be stored here (refer to Figure 67).

Table 14. Contents of OSD RAM (continued)

Table 15. List of access disable addresses

M37271EF-XXXSP, M37271EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER RF6 RF5 RF4 RF3 RF2 RF1 RF0 RC17 RC16 RC15 RC14 RC13 RC12 RC11 RC10 RC23 RC22 RC21 RC20RF7 b3b0b7b0b7 Blocks 1 to16 Character code Color code 1 Color code 2 Fig. 68. Structure of OSD RAM Bit RF0 RF1 RF2 RF3 RF4 RF5 RF6 RF7 RC10 RC11 RC12 RC13 RC14 RC15 RC16 RC17 RC20 RC21 RC22 RC23 Bit name Character code (Low-order 8 bits) Character code (High-order 1 bit) Control of character color R Control of character color G Control of character color B OUT1 control Flash control Underline control Italic control Control of background color R Control of background color G Control of background color B Not used Function Specification of character code in OSD ROM 0: Color signal output OFF 1: Color signal output ON 0: Character output 1: Background output 0: Flash OFF 1: Flash ON 0: Underline OFF 1: Underline ON 0: Italic OFF 1: Italic ON 0: Color signal output OFF 1: Color signal output ON Bit name Character code (Low-order 8 bits) Character code (High-order 1 bit) Control of character color R Control of character color G Control of character color B OUT1 control Control of character color I1 Not used Control of background color R Control of background color G Control of background color B Control of background color Function Specification of character code in OSD ROM 0: Color signal output OFF 1: Color signal output ON 0: Character output 1: Background output 0: Color signal output OFF 1: Color signal output ON 0: Color signal output OFF 1: Color signal output ON Bit name Character code (Low-order 8 bits) Character code (High-order 1 bit) Character color code 0 (CC0) Character color code 1 (CC1) Character color code 2 (CC2) OUT1 control Extra code 0 (EX0) Extra code 1 (EX1) Extra code 2 (EX2) Background color code 0 (BCC0) Background color code 1 (BCC1) Background color code 2 (BCC2) Extra code 3 (EX3) Function Specification of character code in OSD ROM Specification of character color 0: Character output 1: Background output Specification of extra code in OSD ROM Specification of background color Specification of extra code in OSD ROM CC mode OSD mode EXOSD mode Notes 1: Read value of bits 4 to 7 of the color code 2 is undefined. 2: For “not used” bits, the write value is read. 3: The decode value of the extra code is “EX4.”

Table 16. Correspondence table of color code 1 and color Table 17. Correspondence table of color code 2 and color put in the EXOSD mode is shown in Table 16. character background color are different depending on each mode. in the EXOSD mode is shown in Table 17. (character display area)–(character font)–(border)–(extra font).

M37271EF-XXXSP, M37271EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER (9) OUT1, OUT2 signals The OUT1, OUT2 signals are used to control the luminance of the video signal. The output waveform of the OUT1, OUT2 signals is controlled by bit 4 of the color code 1 (refer to Figure 68), bits 2 and Fig. 69. Setting value for controlling OUT1, OUT2 and corresponding output waveform 7 of the block control register (refer to Figure 53). The setting values for controlling OUT1, OUT2 and the corresponding output waveform is shown in Figure 69. OUT1 OUT2 OUT1 OUT2 OUT1 OUT2 OUT1 OUT2 OUT1 OUT2 OUT1 OUT2 OUT1 OUT2 OUT1 OUT2 Block control register OUT2 output control bit (b7) Border output control bit (b2) Output waveform OUT1 control (b4 of color code 1)

M37271EF-XXXSP, M37271EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER

44444 Extra font

There are 32 kinds of the extra fonts configured with 165 26 dots in OSD ROM. 16 kinds of these fonts can be displayed by ORed with the character font by a character unit (refer to Figure 50). For the others, only the extra font is displayed (refer to Figure 50). In only the EXOSD mode, the extra font is controlled the following : bits 7 to 5 of the color code 1, bit 3 of the color code 2, and decode value (EX4) of the character code. When the character code = “00 16” to “13F16,” EX4 is “0, ” when the character code = “14016,” EX4 is “1.” Since there is no font with the character code = “14016,” a blank is dis- played. The extra font color for each screen is specified by the extra color register. When the character font overlaps with the extra font, the color of the area becomes the ORed color of both fonts. Note : When using the extra font, set bits 7 and 6 of the OSD control register to “0” (refer to Figure 52). Fig. 70. Structure of extra font color register (10) Attribute The attributes (flash, underline, italic) are controlled to the character font. The attributes for each character are specified by the color codes 1 and 2 (refer to Figure 68). The attributes to be controlled are differ- ent depending on each mode. be selected) be selected) , extra font (32 kinds)

11111 Under line

The underline is output at the 23th and 24th dots in vertical direction only in the CC mode. The underline is controlled by bit 6 of the color code 1. The color of underline is the same color as that of the char- acter font.

22222 Flash

The parts of the character font, the underline, and the character back- ground are flashed only in the CC mode. The color signals (R, G, B, OUT1) of the character font and the underline are controlled by bit 5 of the color code 1. All of the color signals for the character font flash. However, the color signal for the character background can be con- trolled by bit 3 of the OSD control register (refer to Figure 52). The flash cycle bases on the V SYNC count.

• VSYNC cycle 5 48 ; 768 ms (at flash ON)
• VSYNC cycle 5 16 ; 256 ms (at flash OFF)

33333 Italic

The italic is made by slanting the font stored in OSD ROM only in the CC mode. The italic is controlled by bit 7 of the color code 1. The display example of the italic and underline is shown in Figure 70. In this case, 16 26 dots are used and “R” is displayed. Notes 1: When setting both the italic and the flash, the italic charac- ter flashes. 2: When the pre-divide ratio = 1, the italic character with slant of 1 dot 5 5 steps is displayed (refer to Figure 71 (c)). When the pre-divide ratio = 2, the italic character with slant of 1/2 dot 5 10 steps is displayed (refer to Figure 71 (d)). 3: The boundary of character color is displayed in italic. How- ever, the boundary of character background color is not af- fected by the italic (refer to Figure 72). 4: The adjacent character (one side or both side) to an italic character is displayed in italic even when the character is not specified to display in italic (refer to Figure 72). 5: When displaying the italic character in the block with the pre-divide ratio = 1, set the OSD clock frequency to 11 MHz to 14 MHz. Extra font color register (EC : address 021816) Extra font color R control bit 0 : No output 1 : Output Extra font color G control bit 0 : No output 1 : Output Extra font color B control bit 0 : No output 1 : Output Extra font color I1 control bit 0 : No output 1 : Output Extra font color I2 control bit 0 : No output 1 : Output

M37271EF-XXXSP, M37271EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER Fig. 72. Example of italic display Fig. 71. Example of attribute display (in CC mode) 0 0 10 0 1 0 1 Color code 1 Bit 6 Bit 7 Color code 1 Bit 6 Bit 7 Color code 1 Bit 6 Bit 7 Color code 1 Bit 6 Bit 7 (a) Ordinary (b) Underline (c) Italic (pre-divide ratio = 1) (d) Italic (pre-divide ratio = 2) 10 0 1 1 0 1 Italic on one side Italic on both sides Bit 7 of color code 1 Note : The wavy-lined is the boundary of character color

M37271EF-XXXSP, M37271EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER

55555 Border

The border is output in the OSD mode and the EXOSD mode. The all bordered (bordering around of character font) and the shadow bor- dered (bordering right and bottom sides of character font) are se- lected (refer to Figure 73) by bit 2 of the OSD control register (refer to Figure 52). The border ON/OFF is controlled by bit 2 of the block control register (refer to Figure 53). The OUT1 signal is used for border output. The border color for each screen is specified by the border color register. The horizontal size (x) of border is 1T C (OSD clock cycle divided in the pre-divide circuit) regardless of the character font dot size. The vertical size (y) different depending on the screen scan mode and the vertical dot size of character font. Notes 1 : There is no border for the extra font. 2 : The border dot area is the shaded area as shown in Figure 75. In the EXOSD mode, top and bottom of character font display area is not bordered. 3 : When the border dot overlaps on the next character font, the character font has priority (refer to Figure 76 A). When the border dot overlaps on the next character back ground, the border has priority (refer to Figure 76 B). 4 : The border is not displayed at right side of the most right dot in the display area of the 40th character (the character located at the most right of the block). Fig. 73. Example of border display Fig. 74. Horizontal and vertical size of border All bordered Shadow bordered y x 1/2H 1H, 2H, 3H 1/2H, 1H, 2H, 3H 1/2H 1H 1H Vertical dot size of character font Border dot size Scan mode Horizontal size (x) Vertical size (y) Normal scan mode Bi-scan mode 1TC (OSD clock cycle divided in pre-divide circuit)

M37271EF-XXXSP, M37271EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER Fig. 75. Border area Fig. 76. Border priority Fig. 77. Structure of border color register Border color register (FC : address 021B16) Border color R control b 0 : No output 1 : Output Border color G control bit 0 : No output 1 : Output Border color B control bit 0 : No output 1 : Output Border color I1 control bit 0 : No output 1 : Output Border color I2 control bit 0 : No output 1 : Output Character boundary B Character boundary A Character boundary B 16 dots 16 dots 20 dots OSD mode EXOSD mode 1 dot width of border 1 dot width of border 1 dot width of border 1 dot width of border Character font area 20 dots

M37271EF-XXXSP, M37271EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER (11) Multiline Display The M37271MF-XXXSP can ordinarily display 16 lines on the CRT screen by displaying 16 blocks at different vertical positions. In addi- tion, it can display up to 16 lines by using OSD interrupts. An OSD interrupt request occurs at the point at which display of each block has been completed. In other words, when a scanning line reaches the point of the display position (specified by the vertical position registers) of a certain block, the character display of that block starts, and an interrupt occurs at the point at which the scan- ning line exceeds the block. The mode in which an OSD interrupt occurs is different depending on the setting of the raster color regis- ter (refer to Figure 84).

• When bit 7 of the raster color register is “0” An OSD interrupt occurs at the end of block display in the OSD and the EXOSD mode.
• When bit 7 of the raster color register is “1” An OSD interrupt occurs at the end of block display in the CC mode. Notes 1: An OSD interrupt does not occur at the end of display when the block is not displayed. In other words, if a block is set to off display by the display control bit of the block control reg- ister (addresses 00D0 16 to 00DF16), an OSD interrupt re- quest does not occur (refer to Figure 78 (A)). 2: When another block display appeares while one block is displayed, an OSD interrupt request occurs only once at the end of the another block display (refer to Figure 78 (B)). 3: On the screen setting window, an OSD interrupt occurs even at the end of the CC mode block (off display) out of window (refer to Figure 78 (C)). Fig. 78. Note on occurence of OSD interrupt (B) (C) Block 1 (on display) Block 2 (on display) Block 3 (on display) Block 4 (on display) Block 1 (on display) Block 2 (on display) Block 3 (off display) Block 4 (off display) “OSD interrupt request” “OSD interrupt request” “OSD interrupt request” “OSD interrupt request” “OSD interrupt request” “OSD interrupt request” No “OSD interrupt request” Block 1 Block 2 “OSD interrupt request” “OSD interrupt request” “OSD interrupt request” “OSD interrupt request” Block 1 Block 2 Block 3 On display (OSD interrupt request occurs at the end of block display) Off display (OSD interrupt request does not occur at the end of block display) In CC mode Window No “OSD interrupt request” No “OSD interrupt request” (A)

on the right side of the 40th character of each block. blank output) of the character area in the CC mode.

• the character area except character code “009 16 ”
• the character area on the left and right sides of the character area except character code “00916 ” This function is turned on and off by bit 4 of the OSD control register (refer to Figure 52). Character Character font part display area OFF

Table 18. Setting for automatic solid space

• • •
• • • 009 009 When setting the character code “00516” as the character A, “00616” as the character B. (Display memory) Character to be displayed (Display screen) 1st character 2nd character(Note 1) No blank output 39th character 40th character (Note 2)( Note 1)

OSD control register (refer to Figure 52). on and off by bit 5 of the OSD control register (refer to Figure 52). Table 19. Setting for scan mode

M37271EF-XXXSP, M37271EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER Fig. 82. Structure of window L registers Fig. 81. Structure of window H registers Window L register 1 (WL1 : address 021D ) Control bits of window bottom boundary (Note) Bottom boundary position (low-order 8bits) TH 5 (setting value of low-order 2bits of WL2 5 16 +setting value of high-order 4bits of WL15 16 +setting value of low-order 4bits of WL15 16 ) Window L register 2 (WL2 : address 021F ) Control bits of window bottom boundary (Note) Bottom boundary position (high-order 2bits) TH 5 (setting value of low-order 2bits of WL2 5 16 +setting value of high-order 4bits of WL15 16 +setting value of low-order 4bits of WL15 16 ) Note : Set values fit for the following condition : (WH1+WH2)< (WL1+WL2). Window H register 1 (WH1 : address 021C ) Control bits of window top boundary (Note) Top boundary position (low-order 8bits) TH 5 (setting value of low-order 2bits of WH2 5 16 +setting value of high-order 4bits of WH15 16 +setting value of low-order 4bits of WH15 16 ) Window H register 2 (WH2 : address 021E ) Control bits of window top boundary (Note) Top boundary position (high-order 2bits) TH 5 (setting value of low-order 2bits of WH2 5 16 +setting value of high-order 4bits of WH15 16 +setting value of low-order 4bits of WH15 16 ) Note : Set values except “0016” and “0116” to the WH1 when the WH2 is “0016.” 7 0 7 0 7 0 7 0

M37271EF-XXXSP, M37271EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER (15) OSD Output Pin Control The OSD output pins R, G, B, and OUT1 can also function as ports P52, P53, P54 and P55. Set the corresponding bit of the OSD port control register (address 00CB16) to “0” to specify these pins as OSD output pins, or set it to “1” to specify it as a general-purpose port P5 pins. The OUT2, I1, and I2 can also function as port P10, P15, P16. Set the corresponding bit of the port P1 direction register (address 00C3 16) to “1” (output mode). After that, switch between the OSD output function and the port function by the OSD port control regis- ter. Set the corresponding bit to “1” to specify the pin as OSD output pin, or set it to “0” to specify as port P1 pin. The input polarity of the H SYNC , VSYNC and output polarity of signals R, G, B, I1, I2, OUT1 and OUT2 can be specified with the I/O polarity control register (address 0217 16) . Set a bit to “0” to specify positive polarity; set it to “1” to specify negative polarity (refer to Figure 64). The structure of the OSD port control register is shown in Figure 83. Fig. 83. Structure of OSD port control register

0 OSD port control register

(PF : address 00CB16) Port P15 output signal selection bit 0 : Port P15 output 1 : I1 signal output Port P16 output signal selection bit 0 : Port P16 output 1 : I2 signal output Port P52 output signal selection bit 0 : R signal output 1 : Port P52 output Port P53 output signal selection bit 0 : G signal output 1 : Port P53 output Port P54 output signal selection bit 0 : B signal output 1 : Port P54 output Port P55 output signal selection bit 0 : OUT1 signal output 1 : Port P55 output Port P10 output signal selection bit 0 : Port P10 output 1 : OUT2 signal output Fix this bit to “0.”

M37271EF-XXXSP, M37271EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER (16) Raster Coloring Function An entire screen (raster) can be colored by setting the bits 6 to 0 of the raster color register. Since each of the R, G, B, I1, I2, OUT1, and OUT2 pins can be switched to raster coloring output, 7 raster colors can be obtained. If the OUT1 pin has been set to raster coloring output, a raster color- ing signal is always output during 1 horizontal scanning period. This setting is necessary for erasing a background TV image. If the R, G, B, I1, and I2 pins have been set to output, a raster color- ing signal is output in the part except a no-raster colored character (in Figure 85, a character “1”) during 1 horizontal scanning period. This ensures that character colors are not mixed with the raster color. The structure of the raster color register is shown in Figure 84, the example of raster coloring is shown in Figure 85. Fig. 84. Structure of raster color register Fig. 85. Example of raster coloring H SYNC /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines A'A OUT1 R G B /LiteDiagLines : Character color “RED” (R) : Border color “GREEN” (G) : Background color “MAGENTA” (R and B) : Raster color “BLUE” (R and OUT1) Signals across A-A' Raster color register (RC : address 021816) Raster color R control bit 0 : No output 1 : Output Raster color G control bit 0 : No output 1 : Output Raster color B control bit 0 : No output 1 : Output Raster color I1 control bit 0 : No output 1 : Output Raster color I2 control bit 0 : No output 1 : Output Raster color OUT1 control bit 0 : No output 1 : Output Raster color OUT2 control bit 0 : No output 1 : Output OSD interrupt source selection bit 0 : Interrupt occurs at end of OSD or EXOSD block display 1 : Interrupt occurs at end of CC mode block display

M37271EF-XXXSP, M37271EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER INTERRUPT INTERVAL DETERMINATION FUNCTION The M37271MF-XXXSP incorporates an interrupt interval determi- nation circuit. This interrupt interval determination circuit has an 8-bit binary up counter as shown in Figure 86. Using this counter, it deter- mines an interval or a pulse width on the INT1 or INT2 (refer to Fig- ure 88). The following describes how the interrupt interval is determined. 1. The determination mode is selected by using bit 5 of the interrupt interval determination control register (address 0212 16). When this bit is set to “0,” the interrupt interval determination mode is se- lected; when the bit is set to “1,” the pulse width determination mode is selected. 2. The interrupt input to be determined (INT1 input or INT2 input) is selected by using bit 2 in the interrupt interval determination con- trol register (address 0212 16). When this bit is cleared to “0,” the INT1 input is selected ; when the bit is set to “1,” the INT2 input is selected. 3. When the INT1 input is to be determined, the polarity is selected by using bit 3 of the interrupt interval determination control register ; when the INT2 input is to be determined, the polarity is selected by using bit 4 of the interrupt interval determination control register. When the relevant bit is cleared to “0,” determination is made of the interval of a positive polarity (rising transition) ; when the bit is set to “1,” determination is made of the interval of a negative po- larity (falling transition). 4. The reference clock is selected by using bit 1 of the interrupt inter- val determination control register. When the bit is cleared to “0,” a µs clock is selected ; when the bit is set to “1,” a 16µs clock is selected (based on an oscillation frequency of 8MHz in either case). 5. Simultaneously when the input pulse of the specified polarity (rising or falling transition) occurs on the INT1 pin (or INT2 pin), the 8-bit binary up counter starts counting up with the selected reference clock (32 µs or 16µs). 6. Simultaneously with the next input pulse, the value of the 8-bit binary up counter is loaded into the interrupt interval determina- tion register (address 0211 16) and the counter is immediately re- set (“0016”). The reference clock is input in succession even after the counter is reset, and the counter restarts counting up from “0016”. 7. When count value “FE16” is reached, the 8-bit binary up counter stops counting. Then, simultaneously when the next reference clock is input, the counter sets value “FF 16” to the interrupt inter- val determination register. The reference clock is generated by setting bit 0 of the PWM mode register 1 to “0.”

M37271EF-XXXSP, M37271EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER Fig. 88. Setting value of interrpt interval determination control register and measuring interval Fig. 86. Block diagram of interrupt interval determination circuit Fig. 87. Structure of interrupt interval determination control register RE 5 RE i INT1 or INT2 input Count interval RE i :Bit i (i = 3, 4) of interrupt interval determination control register (address 021116) Data bus Control circuit Connected to black colored side at rest. Selection gate : (Address 021116) 32ms RE 1 16ms 8-bit binary up counter (8) Interrupt interval determination register(8) RE 0 INT1 (Note) RE 2 INT2 (Note) Note: The pulse width of external interrupt INT1 and INT2 needs 5 or more machine cycles. RE: Input interval determination control register Interrupt interval determination control register (RE : address 021216) Interrupt interval determination circuit operation control bit 0 : Stopped 1 : Operating External interrupt input pin selection bit 0 : INT1 input 1 : INT2 input INT1 pin input polarity switch bit 0 : Positive polarity input 1 : Negative polarity input INT2 pin input polarity switch bit 0 : Positive polarity input 1 : Negative polarity input Interrupt interval determination mode switch bit 0 : Interrupt interval determination mode 1 : Pulse width determination mode Reference clock control selection bit (at f(XIN) = 8MHz) 0 : 32ms 1 : 16ms INT3 pin input polarity switch bit 0 : Positive polarity input 1 : Negative polarity input A-D conversion· INT3 interrupt source selection bit 0 : INT3 interrupt 1 : A-D conversion interrupt

M37271EF-XXXSP, M37271EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER RESET CIRCUIT The M37271MF-XXXSP is reset according to the sequence shown in Figure 90. It starts the program from the address formed by using the content of address FFFF16 as the high-order address and the content of the address FFFE16 as the low-order address, when the RESET pin is held at “L” level for 2 µs or more while the power source voltage is 5 V ± 10 % and the oscillation of a quartz-crystal oscillator or a ceramic resonator is stable and then returned to “H” level. The internal state of microcomputer at reset are shown in Figures 3 to 7. An example of the reset circuit is shown in Figure 89. The reset input voltage must be kept 0.9 V or less until the power source voltage surpasses 4.5 V. Fig. 90. Reset sequence Fig. 89. Example of reset circuit XIN φ RESET Internal RESET SYNC Address Data 32768 count of XIN clock cycle (Note 3) Reset address from the vector table ? ? 01, S 01, S-101, S-2 FFFE FFFF AD H , AD L Notes 1 : f(XIN) and f(φ) are in the relation : f(XIN) = 2·f (φ). 2 : A question mark (?) indicates an undefined state that depends on the previous state. 3 : Immediately after a reset, timer 3 and timer 4 are connected in hardware. At this time, “FF16” is set in timer 3 and “0716” is set to timer 4. Timer 3 counts down with f(XIN)/16, and reset state is released by the timer 4 overflow signal. Power source voltage 0 V Reset input voltage 0 V 4.5 V 0.9 V Poweron Vcc RESET Vss M37271MF-XXXSP 3 0.1 µF M51953AL

M37271EF-XXXSP, M37271EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER Fig. 91. I/O pin block diagram (1) Ports P03, P10, P15–P17, P2, P30, P31 Data bus Direction register Port latch Data bus Direction register Port latch Data bus Direction register Port latch Ports P00–P02, P04–P07 Ports P11–P14 N-channel open-drain output Ports P00–P02, P04–P07 Note :Each port is also used as below : P0 0–P02 : PWM4–PWM6 P04–P07 : PWM0–PWM3 N-channel open-drain output Port P11-P14 Note :Each port is also used as below : P11 : SCL1 P12 : SCL2 P13 : SDA1 P14 : SDA2 CMOS output Ports P03, P10, P15–P17, P2, P30, P31 Note :Each port is also used as below : P10 : OUT2 P15 : I1 P16 : I2/INT3 P17 : SIN P24–P26 : AD3–AD1

M37271EF-XXXSP, M37271EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER N-channel open-drain output Ports SOUT , SCLK Note :Each pin is also used as below : SOUT : P45 SCLK : P46 R, G, B, OUT1 Note :Each pin is also used as below : R : P5

2 B : P54

G : P53 OUT1 : P55 CMOS output H SYNC , VSYNC Schmidt input Fig. 92. I/O pin block diagram (2) Ports P40–P44 Note :Each port is also used as below : P40 : AD4 P41 : INT2 P42 : TIM2 P43 : TIM3 P44 : INT1 H SYNC , VSYNC SOUT , SCLK R, G, B, OUT1 Data bus Direction register Internal circuit Data bus Ports P40–P4 4 Internal circuit

M37271EF-XXXSP, M37271EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER CLOCK GENERATING CIRCUIT The M37271MF-XXXSP has 2 built-in oscillation circuits. An oscilla- tion circuit can be formed by connecting a resonator between XIN and XOUT (XCIN and XCOUT ). Use the circuit constants in accordance with the resonator manufacturer’s recommended values. No exter- nal resistor is needed between X IN and XOUT since a feed-back re- sistor exists on-chip. However, an external feed-back resistor is needed between XCIN and XCOUT . When using XCIN-XCOUT as sub- clock, clear bits 5 and 4 of the clock source control register to “0.” To supply a clock signal externally, input it to the X IN (XCIN) pin and make the XOUT (XCOUT ) pin open. When not using XCIN clock, con- nect the XCIN to VSS and make the XCOUT pin open. After reset has completed, the internal clock φ is half the frequency of XIN. Immediately after poweron, both the XIN and XCIN clock start oscillating. To set the internal clock φ to low-speed operation mode, set bit 7 of the CPU mode register (address 00FB16) to “1.” Oscillation Control (1) Stop mode The built-in clock generating circuit is shown in Figure 93. When the STP instruction is executed, the internal clock φ stops at “H” level. At the same time, timers 3 and 4 are connected in hardware and “FF16” is set in the timer 3, “0716” is set in the timer 4. Select f(XIN)/16 or f(XCIN)/16 as the timer 3 count source (set both bit 0 of the timer mode register 2 and bit 6 at address 00C716 to “0” before the execu- tion of the STP instruction). And besides, set the timer 3 and timer 4 interrupt enable bits to disabled (“0”) before execution of the STP instruction. The oscillator restarts when external interrupt is accepted, however, the internal clock φ keeps its “H” level until timer 4 over- flows. Because this allows time for oscillation stabilizing when a ce- ramic resonator or a quartz-crystal oscillator is used. (2) Wait mode When the WIT instruction is executed, the internal clock φ stops in the “H” level but the oscillator continues running. This wait state is released at reset or when an interrupt is accepted (Note). Since the oscillator does not stop, the next instruction can be executed at once. Note: In the wait mode, the following interrupts are invalid. (1) V SYNC interrupt (2) OSD interrupt (3) Timers 1 and 2 interrupts using P4 2/TIM2 pin input as count source (4) Timer 3 interrupt using P43/TIM3 pin input as count source (5) Data slicer interrupt (6) Multi-master I 2C-BUS interface interrupt (7) f(XIN)/4096 interrupt (8) All timer interrupts using f(XIN)/2 or f(XCIN)/2 as count source (9) All timer interrupts using f(XIN)/4096 or f(XCIN)/4096 as count source (10) A-D conversion interrupt Fig. 93. Ceramic resonator circuit example Fig. 94. External clock input circuit example (3) Low-Speed Mode If the internal clock is generated from the sub-clock (XCIN), a low power consumption operation can be realized by stopping only the main clock XIN. To stop the main clock, set bit 6 (CM6) of the CPU mode register (00FB16) to “1.” When the main clock XIN is restarted, the program must allow enough time to for oscillation to stabilize. Note that in low-power-consumption mode the X CIN-XCOUT drivability can be reduced, allowing even lower power consumption (60µA with f (XCIN) = 32kHz). To reduce the XCIN-XCOUT drivability, clear bit 5 (CM 5) of the CPU mode register (00FB16) to “0.” At reset, this bit is set to “1” and strong drivability is selected to help the oscillation to start. When an STP instruction is executed, set this bit to “1” by soft- ware before executing. X CIN X IN C CIN M37271MF-XXXSP X COUT R f R d C COUT XOUT C IN C OUT X CIN M37271MF-XXXSP External oscillation circuit or external pulse XCOUT XIN XOUT Open Open External oscillation circuit Vcc Vss Vcc Vss

M37271EF-XXXSP, M37271EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER Fig. 95. Clock generating circuit block diagram XCIN XCOUT OSC1 oscillating mode selection bits (Notes 1, 4) Internal system clock selection bit (Notes 1, 3) Internal system clock selection bit (Notes 1, 3) Main clock (XIN–XOUT ) stop bit (Notes 1, 3) R SQ STP instruction WIT instruction R S Q Reset Interrupt disable flag I Interrupt request R SQ Reset STP instruction Timing f (Internal clock) Timer 3 count source selection bit (Notes 1, 2) “1” Timer 3 count stop bit (Notes 1, 2) Timer 4 count stop bit (Notes 1, 2) Timer 3 Timer 4 1/2 1/8 XOUTXIN “1” “0” “0” Notes 1 : The value at reset is “0.” 2 : Refer to the structure of timer mode register 2. 3 : Refer to the structure of CPU mode register (next page). 4 : Refer to the structure of clock source control register.

M37271EF-XXXSP, M37271EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER Fig. 96. State transitions of system clock Reset The example assumes that 8 MHz is being applied to the XIN pin and 32 kHz to the XCIN pin. The f indicates the internal clock. WIT instruction CM 7 : Internal system clock selection bit 0 : XIN-XOUT selected (high-speed mode) 1 : XCIN-XCOUT selected (low-speed mode) CPU mode register (Address : 00FB 16) CM 6 : Main clock (XIN–XOUT ) stop bit 0 : Oscillating 1 : Stopped 8MHz oscillating 32kHz oscillating f is stopped (“H”) Timer operating 8MHz oscillating 32kHz oscillating f(f ) = 4MHz 8MHz stopped 32kHz stopped f is stopped (“H”) 8MHz oscillating 32kHz oscillating f is stopped (“H”) Timer operating (Note 3) 8MHz oscillating 32kHz oscillating f(f ) = 16kHz 8MHz stopped 32kHz stopped f is stopped (“H”) 8MHz stopped 32kHz stopped f = stopped (“H”) 8MHz stopped 32kHz oscillating f(f ) = 16kHz 8MHz stopped 32kHz oscillating f is stopped (“H”) Timer operating (Note 3) Interrupt STP instruction Interrupt (Note 1) WIT instruction Interrupt WIT instruction Interrupt STP instruction Interrupt (Note 2) STP instruction Interrupt (Note 2) CM 7 = 1 CM 7 = 0 CM 6 = 1 CM 6 = 0 External INT, timer interrupt, or SI/O interrupt External INT Notes 1: When the STP state is ended, a delay of approximately 8ms is automatically generated by timer 3 and timer 4. 2: The delay after the STP state ends is approximately 2s. 3: When the internal clock f divided by 8 is used as the timer count source, the frequency of the count source is 2kHz. The program must allow time for 8MHz oscillation to stabilize High-speed operation start mode

M37271EF-XXXSP, M37271EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER DISPLAY OSCILLATION CIRCUIT The OSD oscillation circuit has a built-in clock oscillation circuits, so that a clock for OSD can be obtained simply by connecting an LC, a ceramic resonator, or a quartz-crystal oscillator across the pins OSC1 and OSC2. Which of the sub-clock or the OSD oscillation circuit is selected by setting bits 5 and 4 of the clock source control register (address 0216 16). ADDRESSING MODE The memory access is reinforced with 17 kinds of addressing modes. Refer to the SERIES 740 <Software> User’s Manual for details. MACHINE INSTRUCTIONS There are 71 machine instructions. Refer to the SERIES 740 <Soft- ware > User’s Manual for details. PROGRAMMING NOTES (1) The divide ratio of the timer is 1/(n+1). (2) Even though the BBC and BBS instructions are executed imme- diately after the interrupt request bits are modified (by the pro- gram), those instructions are only valid for the contents before the modification. At least one instruction cycle is needed (such as an NOP) between the modification of the interrupt request bits and the execution of the BBC and BBS instructions. (3) After the ADC and SBC instructions are executed (in decimal mode), one instruction cycle (such as an NOP) is needed before the SEC, CLC, or CLD instruction is executed. (4) An NOP instruction is needed immediately after the execution of a PLP instruction. (5) In order to avoid noise and latch-up, connect a bypass capacitor (≈ 0.1 µF) directly between the V CC pin–VSS pin, AVCC pin–VSS pin, and the VCC pin–CNVSS pin using a thick wire. Fig. 97. Display oscillation circuit AUTO-CLEAR CIRCUIT When power source is supplied, the auto-clear function can be per- formed by connecting the following circuit to the RESET pin. Fig. 98. Auto-clear circuit example RESET Vss Vcc Circuit example 1 RESET Vss Vcc Circuit example 2 Note :Make the level change from “L” to “H” at the point at which the power source voltage exceeds the specified voltage. OSC2OSC1 L C1 C2

M37271EF-XXXSP, M37271EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER PROM Programming Method The built-in PROM of the One Time PROM version (blank) and built- in EPROM version can be read or programmed with a general-pur- pose PROM programmer using a special programming adapter. Product M37271EFSP Name of Programming Adapter PCA7400 The PROM of the One Time PROM version (blank) is not tested or screened in the assembly process and following processes. To en- sure proper operation after programming, the procedure shown in Figure 99 is recommended to verify programming. Fig. 99. Programming and testing of One Time PROM version Programming with PROM programmer Screening (Caution) (150°C for 40 hours) Verification with PROM programmer Functional check in target device Caution : The screening temperature is far higher than the storage temperature. Never expose to 150°C exceeding 100 hours. DATA REQUIRED FOR MASK ORDERS The following are necessary when ordering a mask ROM produc- tion: (1) Mask ROM Order Confirmation Form (2) Mark Specification Form (3) Data to be written to ROM, in EPROM form ( 32-pin DIP Type 27C101, three identical copies)

M37271EF-XXXSP, M37271EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER 7.9 11.0 26.5 15.262 1.5 Limits Power source voltage V CC , AVCC Input voltage CNV SS Input voltage P0 0–P07, P10–P17, P20–P27, XIN, HSYNC , VSYNC , RESET, CV IN Output voltage P0 3, P10–P17, P20–P27, P30, P31, R, G, B, OUT1, SOUT , SCLK , XOUT , OSC2 Output voltage P0 0–P02, P04–P07 Circuit current R, G, B, OUT1, OUT2, P03, P15–P17, P20–P27, P30, P31 Circuit current R, G, B, OUT1, OUT2, P03, P15–P17, P20–P27, SOUT , SCLK Circuit current P1 1–P14 Circuit current P0 0–P02, P04–P07 Circuit current P3 0, P31 Power dissipation Operating temperature Storage temperature Symbol V CC , AVCC VI VI VO ABSOLUTE MAXIMUM RATINGS Conditions All voltages are based on VSS . Output transistors are cut off. Parameter –0.3 to 13 0 to 1 (Note 1) 0 to 2 (Note 2) 0 to 6 (Note 2) 0 to 1 (Note 2) 0 to 10 (Note 3) 550 –10 to 70 –40 to 125 V mA mA mA mA mA mW Min. 4.5 2.0 0.8V CC 0.7VCC Typ. 5.0 Max. 5.5 5.5 VCC VCC

0.4 VCC

0.3 VCC

0.2 VCC

Input frequency TIM2, TIM3, INT1, INT2, INT3 Input frequency S CLK Input frequency SCL1, SCL2 Input frequency Horizontal sync. signal of video signal Input amplitude video signal CV IN V V V V V V V V mA mA RECOMMENDED OPERATING CONDITIONS (Ta = –10 °C to 70 °C, VCC = 5 V ± 10 %, unless otherwise noted) Power source voltage (Note 4), During CPU, OSD, data slicer operation RAM hold voltage (when clock is stopped) Power source voltage “H” input voltage P0 P40–P46, P64, HSYNC , VSYNC , RESET, XIN, OSC1 “H” input voltage P1 1–P14 (When using I2C-BUS) “L” input voltage P0 0–P07, P10–P17, P20–P27, P30, P31, P40–P46, P63, P64 “L” input voltage SCL1, SCL2, SDA1, SDA2, (When using I2C-BUS) “L” input voltage (Note 6) P4 1–P44, P46, P16, P17, HSYNC , VSYNC ,______ RESET, XIN, OSC1 “H” average output current (Note 1) R, G, B, OUT1, OUT2, P03, P15–P17, P20–P27, P30, P31 “L” average output current (Note 2) R, G, B, OUT1, OUT2, P03, P15–P17, P20–P27, SOUT , SCLK “L” average output current (Note 2) P11–P14 “L” average output current (Note 2) P00–P02, P04–P07 “L” average output current (Note 3) P30, P31 Oscillation frequency (for CPU operation) (Note 5) XIN Oscillation frequency (for sub-clock operation) XCIN VCC , AVCC VCC , AVCC VSS VIH1 VIH2 VIL1 VIL2 VIL3 IOH IOL1 Symbol Parameter Unit fhs1 fhs2 fhs3 fhs4 VI kHz MHz kHz kHz V MHz mA mA mA MHz kHz 8.1 27.0 27.5 100 400 16.206 2.5 8.0 27.0 15.734 2.0 IOL2 IOL3 IOL4 fCPU fCLK VO IOH IOL1 IOL2 IOL3 IOL4 Pd Topr Tstg Oscillation frequency (for OSD) OSC1fOSD LC oscillating mode Ceramic oscillating mode Ta = 25 °C Unit V V V V Ratings –0.3 to 6 –0.3 to 6 –0.3 to VCC + 0.3 –0.3 to VCC + 0.3

M37271EF-XXXSP, M37271EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER mA mA mA µA V V Max. 200 100 0.4 Limits Power source current “H” output voltage R, G, B, OUT1, OUT2, P03, P15–P17, P20–P27, P30, P31 “L” output voltage R, G, B, OUT1, OUT2, SOUT , SCLK , P00–P07, P15–P17, P20–P27 “L” output voltage P30, P31 “L” output voltage P11–P14 Hysteresis RESET Hysteresis (Note 6) HSYNC , VSYNC , P41–P44, P46, P11–P14, P17 “H” input leak current RESET, P03, P10–P17, P20–P27, P30, P31, P40–P46, P63, P64, HSYNC , VSYNC “L” input leak current RESET, P00–P07, P10–P17, P20–P27, P30, P31, P40–P46, P63, P64, HSYNC , VSYNC “H” input leak current P00–P02, P04–P07 I2C-BUS·BUS switch connection resistor (between SCL1 and SCL2, SDA1 and SDA2) Min. 2.4 ELECTRIC CHARACTERISTICS (VCC = 5 V ± 10 %, VSS = 0 V, f(XIN) = 8 MHz, Ta = –10 °C to 70 °C, unless otherwise noted) ICC VOH VOL Typ. Symbol Parameter Test conditions Unit Wait mode Stop mode System operation VCC = 5.5 V, f(XIN) = 0, f(XCIN) = 32kHz, OSD OFF, Data slicer OFF, Low-power dissipation mode set (CM 5 = “0”, CM 6 = “1”) VCC = 5.5 V, f(XIN) = 8 MHz VCC = 5.5 V, f(XIN) = 0, f(XCIN) = 32kHz, Low-power dissipation mode set (CM 5 = “0”, CM 6 = “1”) VCC = 5.5 V, f(XIN) = 0, f(XCIN) = 0 VCC = 4.5 V IOH = –0.5 mA VCC = 4.5 V IOL = 0.5 mA CRT OFF Data slicer OFF CRT ON Data slicer ON VCC = 5.5 V, f(XIN) = 8 MHz 0.5 0.5 3.0 0.4 0.6 0.7 1.3 130 V T+–VT– IIZH IIZL IIZH R BS V µA µA µA Ω VCC = 4.5 V IOL = 10.0 mA VCC = 4.5 V IOL = 3 mA IOL = 6 mA VCC = 5.0 V VCC = 5.0 V VCC = 5.5 V VI = 5.5 V VCC = 5.5 V VI = 0 V VCC = 5.5 V VI = 12 V VCC = 4.5 V Notes 1:The total current that flows out of the IC must be 20 or less. 2:The total input current to IC (IOL1 + IOL2 + IOL3 ) must be 20 mA or less. 3:The total average input current for ports P30, P31 to IC must be 10 mA or less. 4:Connect 0.1 µF or more capacitor externally across the power source pins VCC –VSS and AVCC –VSS so as to reduce power source noise. Also connect 0.1 µF or more capacitor externally across the pins V CC –CNV SS . 5:Use a quartz-crystal oscillator or a ceramic resonator for the CPU oscillation circuit. When using the data slicer, use 8 MHz. 6:P16, P41–P44 have the hysteresis when these pins are used as interrupt input pins or timer input pins. P11–P14 have the hysteresis when these pins are used as multi-master I2C-BUS interface ports. P17 and P46 have the hysteresis when these pins are used as serial I/O pins. 7:When using the sub-clock, set fCLK < fCPU /3.

M37271EF-XXXSP, M37271EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER A-D CONVERTER CHARACTERISTICS (VCC = 5 V ± 10 %, VSS = 0 V, f(XIN) = 8 MHz, Ta = –10 °C to 70 °C, unless otherwise noted) Resolution Non-linearity error Differential non-linearity error Zero transition error Full-scale transition error Conversion time Reference voltage Ladder resistor Analog input current Max. ±0.9 12.5 VCC VREF bits LSB LSB LSB LSB µs V kΩ V Min. 12.25 Limits Typ. UnitTest conditionsParameterSymbol V OT VFST TCONV VREF R LADDER VIA VCC = 5.12V IOL (SUM) = 0mA VCC = 5.12V MULTI-MASTER I 2C-BUS BUS LINE CHARACTERISTICS Bus free time Hold time for START condition “L” period of SCL clock Rising time of both SCL and SDA signals Data hold time “H” period of SCL clock Falling time of both SCL and SDA signals Data set-up time Set-up time for repeated START condition Set-up time for STOP condition tBUF tHD:STA tLOW tR tHD:DAT tHIGH tF tSU:DAT tSU:STA tSU:STO Max. 1000 300 Min. 1.3 0.6 1.3 20+0.1C b 0.6 20+0.1Cb 100 0.6 0.6 Max. 300 0.9 300 µs µs µs ns µs µs ns ns µs µs Unit Standard clock mode High-speed clock mode ParameterSymbol Note: C b = total capacitance of 1 bus line Fig. 100. Definition diagram of timing on multi-master I2C-BUS Min. 4.7 4.0 4.7 4.0 250 4.7 4.0 SDA SCL p tBUF S tHD :STA tLOW tR tHD :DAT tHIGH tF tSU :DAT tSU :STA Sr p tSU :STOtHD :STA

M37271EF-XXXSP, M37271EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER PACKAGE OUTLINE

M37271EF-XXXSP, M37271EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER GZZ–SH10–44B < 5ZA0 >

740 FAMILY MASK ROM CONFIRMATION FORM

SINGLE-CHIP MICROCOMPUTER M37271MF-XXXSP MITSUBISHI ELECTRIC Mask ROM number Date : Supervisorsignature Receipt Section head signature * Customer Company name Date issued Date : TEL ( ) Note : Please fill in all items marked *. Submitted by Supervisor Issuance signature * 1. Confirmation Specify the name of the product being ordered and the type of EPROMs submitted. Three EPROMs are required for each pattern. If at least two of the three sets of EPROMs submitted contain identical data, we will produce masks based on this data. We shall assume the responsibility for errors only if the mask ROM data on the products we produce differs from this data. Thus, extreme care must be taken to verify the data in the submitted EPROMs. Checksum code for entire EPROM (hexadecimal notation) 27C101 EPROM address

0000016 Product name

ASCII code : ‘M37271MF –’0000F16 0FFFF 16 Set “FF16” in the shaded area. Write the ASCII codes that indicates the product name of “M37271MF–” to addresses 0000 (1) (2) EPROM type (indicate the type used) 0100016 OSD ROM 1E43F 16 * 2. Mark specification Mark specification must be submitted using the correct form for the type package being ordered fill out the appropriate mark specification form (52P4B for M37271MF-XXXSP) and attach to the mask ROM confirmation form. Do you set “FF16” in the shaded area ? Do you write the ASCII codes that indicates the product name of “M37271MF–” to addresses 0000 16 to 000F16 ? EPROM data check item (Refer the EPROM data and check “ ” in the appropriate box) fi Yes fi Yes l l 1080016 data ROM 60K bytes 16 to 000F16.

M37271EF-XXXSP, M37271EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER GZZ–SH10–44B < 5ZA0 > SINGLE-CHIP MICROCOMPUTER M37271MF-XXXSP MITSUBISHI ELECTRIC ‘M’= 164D 16‘3’= 33 16‘7’= 3 7 16‘2’= 3 2 16‘7’= 37 16‘1’= 3 1 16‘M’= 4D 16‘F’= 46 000016 000116 000216 000316 000416 000516 000616 000716 Address ‘–’= 162D 16FF 16FF 16FF 16FF 16FF 16FF 16FF 000816 000916 000A16 000B16 000C 16 000D 16 000E16 000F16 Address Addresses 0000016 to 0000F16 store the product name, and addresses 1080016 to 1E43F16 store the character pattern. If the name of the product contained in the EPROMs does not match the name on the mask ROM confirmation form, the ROM processing is disabled. Write the data correctly. Inputting the name of the product with the ASCII code ASCII codes ‘M37271MF-’ are listed on the right. The addresses and data are in hexadecimal notation. Inputting the character ROM Input the character ROM data to character ROM. For the character ROM data, see the next page and on. Writing the product name and character ROM data onto EPROMs

M37271EF-XXXSP, M37271EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER GZZ–SH10–44B < 5ZA0 > SINGLE-CHIP MICROCOMPUTER M37271MF-XXXSP MITSUBISHI ELECTRIC Font data must be stored in the proper OSD ROM address according to the following table. (3/4) (2)OSD ROM address of extra font data (1)OSD ROM address of character font data Line number = 0216 to 1516 Character code = 0016 to 13F16 Font bit = 0 : Left font 1 : Right font OSD ROM address bit Line number / Character code / Font bit AD16 AD15 AD14 AD13 AD12 AD11 AD10 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0

10 Font

bitLine number Character code OSD ROM address bit Line number / Extra code / Font bit AD16 AD15 AD14 AD13 AD12 AD11 AD10 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0

11 Font

bitLine number Extra code0000 Example) The font data “60” (shaded area ) of the character code “AA16” is stored in address 1 0 0 1 0 1 0 0 1 0 1 0 1 0 1 0 0 2 =1295416. 0216 0316 0416 0516 0616 0716 0816 0916 0A16 0B16 0C 16 0D 16 0E16 0F16 1016 1116 1216 1316 1416 1516 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Left font Right font Line number (1) Character code “AA16” Line number 1916 (2) Extra code “0A16” DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Left font Right font 0016 0116 0216 0316 0416 0516 0616 0716 0816 0916 0A16 0B16 0C 16 0D 16 0016 0016 1016 1116 1216 1316 1416 1516 1616 1716 1816 Line number = 0016 to 1916 Extra code = 0016 to 1F16 Font bit = 0 : Left font 1 : Right font Example) The font data “03” (shaded area ) of the extra code “0A16” is stored in address 1 1 0 0 1 0 1 0 0 0 0 0 1 0 1 0 1 2 =1941516.

M37271EF-XXXSP, M37271EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER GZZ–SH10–44B < 5ZA0 > SINGLE-CHIP MICROCOMPUTER M37271MF-XXXSP MITSUBISHI ELECTRIC 10A8016 to 10BFF16 10E8016 to 10FFF16 1128016 to 113FF16 1168016 to 117FF16 11A8016 to 11BFF16 11E8016 to 11FFF16 1228016 to 123FF16 1268016 to 127FF16 12A8016 to 12BFF16 12E8016 to 12FFF16 1328016 to 133FF16 1368016 to 137FF16 13A8016 to 13BFF16 13E8016 to 13FFF16 1428016 to 143FF16 1468016 to 147FF16 14A8016 to 14BFF16 14E8016 to 14FFF16 1528016 to 153FF16 1568016 to 17FFF16 1804016 to 183FF16 1844016 to 187FF16 1884016 to 18BFF16 18C40 16 to 18FFF16 1904016 to 193FF16 1944016 to 197FF16 1984016 to 19BFF16 19C40 16 to 19FFF16 1A040 16 to 1A3FF16 1A440 16 to 1A7FF16 1A840 16 to 1ABFF16 1AC40 16 to 1AFFF16 1B04016 to 1B3FF16 1B44016 to 1B7FF16 1B84016 to 1BBFF16 1BC40 16 to 1BFFF16 1C040 16 to 1C3FF16 1C440 16 to 1C7FF16 1C840 16 to 1CBFF16 1CC40 16 to 1CFFF16 1D040 16 to 1D3FF16 1D440 16 to 1D7FF16 1D840 16 to 1DBFF16 1DC40 16 to 1DFFF16 1E04016 to 1E3FF16 The following OSD ROM addresses must be set “FF.” There are no font data in these addresses.

M37271EF-XXXSP, M37271EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER 52P4B (52-PIN SHRINK DIP) MARK SPECIFICATION FORM

M37271EF-XXXSP, M37271EFSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER SHRINK DIP MARK SPECIFICATION FORM for one time PROM version microcomputers

© 1997 MITSUBISHI ELECTRIC CORP. New publication, effective Nov. 1997. Specifications subject to change without notice. Notes regarding these materials

• These materials are intended as a reference to assist our customers in the selection of the Mitsubishi semiconductor product best suited to the customer’s application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Mitsubishi Electric Corporation or a third party.
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• Mitsubishi Electric Corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use.
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• Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for further details on these materials or the products contained therein. Keep safety first in your circuit designs!
• Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non-flammable material or (iii) prevention against any malfunction or mishap.

Rev. Rev. No. date

1.0 First Edition 9708

2.0 Information about copyright note, revision number, release date added (last page). 971130 (1/1) Revision Description REVISION DESCRIPTION LIST M37271EF-XXXSP, M37271EFSP DATA SHEET M37271MF-XXXSP