M37267M4-XXXSP

M37267 MITSUBISHI | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 80

Technical content

M37267M4-XXXSP, M37267M6-XXXSP, M37267M8-XXXSP M37267EE-XXXSP, M37267EESP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER DESCRIPTION ‘© Programmable VO ports (Ports PO, P1, P2, P30, P31) .aremnn 26 ‘The M37267M4-XXXSP, M37267M6-XXXSP and M37267MB-XXXSP © Input ports (Ports P40-P46, P63, P64) .arccsncneeeennnnnen 9 are single-chip microcomputers designed with CMOS silicon gate © Output ports (Ports P52-PS8) svnsssnnnnnnnneneniinnnnnnnn In addition to their simple instruction sets, the ROM, RAM and YO ® LED GFiV@ POI vvennnnnnnnnnnnsnnsnnernnnnnnniannnninnne addresses are placed on the same memory map to enable easy pro-@ SCfial VO earenineninnnmninnninnnnnnnann DHX 1 channel gramming. © Multi-master !2C-BUS interface ‘.essessscssscenseeueeeneeseeraneeseeee 1 ‘The M37267M6-XXXSP has a OSD display function anda data slicer © A-D comparator (6-bit reSOlUtiON) .ccnnenenenne 4 Channels function, so itis useful for a channel selection system for TV with a © PWM output citcUlt.nisanennnnansennnsnioneennee BbIEX 7 closed caption decoder. The features of the M37267EE-XXXSP and _@ Interrupt interval determination circuit the M37267EESP are similar to those of the M37267M6-XXXSP ex- _® Power dissipation cept the following: ROM size, RAM size, kinds of character, and that In high-speed M0d€ .s.sinnneunnniinnnnnnineenenene 1OEMW these chips have a builtin PROM which can be written electrically. (at Voc = 5.5V, eMHz oscillation requency, CRT on, and Data sher on) Tho differance between M37267M4-XXXSP, M37267M6-XXXSP and In low-speed MODE ..rnsennsinnnnnnnnnnesennnenene 0.33 the M37267M8-XXXSP are the ROM size and the RAM size as shown (at Voc = 5.5V, 32kHz oscillation frequency) below. Accordingly, the following descriptions will be for the Data slicer M37267M6-XXXSP unless otherwise noted. CRT display function [po rarne [ROW sas [Rasa [Wineaterwracer] BOT} Stay charactors 34 chart 4s |Ms7z67Me-roxsP | 16 Kbytes | 096 bytes! 192Kinds | Kinds of charactetS .rocnininninnnnnnannnnns 192 KiNdS Dot StUcture nrnstntnatinnneneen CCD mode : 8X 13 dots Imsr2srme-ocsP [22K byes [7024 yes | 102 nds 8D mode 8x 10 dot lwsracTe€ 1008? [56 Kbytes |1556 byes | — 256 ana — | (heater pan: 8% 10 doin to mde) [ma7267eesP [56K bytes [1596 bytos| 256 kinds | Kinds of character $1288 ..esnsunnniennneninnernnneene 5 KINGS - (minimum dot width is 1/2 scanning line) Kinds of character colors (It can be specified by the character) maximum 7 kinds (R, G, B) Memory size screen, switching to character color is possible.) POM eecnnsessneee 16 K bytes (M37267M4-XXXSP) maximum 7 kinds (R, G, B)

24 K bytes (M37267M6-XXXSP) Kinds of raster colors (maximum 7 kinds)

32 K bytes (M37267M8-XXXSP) 2 blanking output (OUT1, OUT2)

56 K bytes (M37267EE-XXXSP, Display position

M97267EESP) Horizontal nennnnintnininnnnnnennens 128 OVOIS RAM oesncnen 896 bytes (M37267M4-XXXSP) VOMICA en nnennennnnnntnannrnieemnnnnee S12 16VOIS 960 bytes (M37267M6-XXXSP) Simultaneos display of caption and channel selection 1024 bytes (M37267M8-XXXSP) Smooth Rol-up 1536 bytes (M37267EE-XXXSP, ‘Mixing ROM for display ....nnnetmmnevninnese 3648 Bytes RAM 06 displ8Y .neoneennnsenennee 272 bytes APPLICATION The minimum instruction execution time ‘TV included a closed caption decoder nmmmnnnssinnnesnose OSHS (at 8 MHZ oscillation frequency) © Power SOUICE VOILEQE -ssinrnninstnnnnnsninnennin SW 10% © Subroutine NEStING hve 96 Kovels (maximum) — MB 6249828 0025807 55) oa eRe ELECTRIC 2-673

MITSUBISHI MICROCOMPUTERS. M37267M4-XXXSP, M37267M6-XXXSP, M37267M8-XXXSP M37267EE-XXXSP, M37267EESP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER ny PIN CONFIGURATION (TOP VIEW) Hsvnc—> Ei] [e]—> Psu Vevic—o> [2] [> Pave P4oMXR/AD4—> [3] [sJ—>PSwB PavINT2MXG—> Gi] [zs] > PSS/OUT1 PaerimanxB—> [5] fza}<+- POw/PWMO PastimaxouT—>E] 222 [a= Pospwni Povanz> Lf] RB Bl» PoPwus PauaDize GB] S33 + re perso] SSE fal<era POoPWM4—e—[T] > % % fee par Povpwms<efid S582 <= po, porpwMes~fd SES fe pivoure Priswee—4 Se fle Pivscit PavINTi—~fy SS [le PI/SCL2 PasSoureefiq BY <= PivSDA1 PasScox—ef] Fm Ba] P1y/SDA2 AVec—efgd IT [Slee Pis HiF—efy 0 % <> Pie AVCOefd I> Pos VHoL>—> Ei] v Je P30 CVin—o> [si] P31 CNVss—m [eq [sol——RESET Xin» [2 [e]<«> PevOSC2/Xcour Xour-—f fzs]+— P6s/0SC1/Xon Vss—> Veo Outline 52P4B mM 6249828 0025808 498 MM

MITSUBISHI MICROCOMPUTERS : M37267M4-XXXSP, M37267M6-XXXSP, M37267M8-XXXSP M37267EE-XXXSP, M37267EESP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONFROLLER ON SCREEN DISPLAY CONFROLLER Fn nm ne © Z 233! | Heese £3426 ery CU" Sg ge 23 | | : 88 B27 ae S Wes Bs E39 I l=oaad || eS ae i i << + 3 Ps BE 8 \\. =! ais I ee ej} = if ; =ailf5 - = = Pamlues 33 s 3 3 | Kore ls &% g 3 : é i =) iE pamuie tT 2 | i ; i FE gs Ln tg uw mm 6249828 0025809 324 <<< Jaws 2-675

M37267M4-XXXSP, M37267M6-XXXSP, M37267M8-XXXSP M37267EE-XXXSP, M37267EESP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER . and ON-SCREEN DISPLAY CONTROLLER FUNCTIONS quency) Memory size [ROM aK byes eC | ean = ae ade 9a PO0s-PO7 ‘output pins) [Pos [vO | 1-01 (CMOS inpuvoutput structure) ial E12 serial input pin) i a Ea master IC-BUS interface) [p2 | v0 | bit 4 (CMOS inputvoutput structure, can be used as A-D input pins) | [Pao.Por [vO __| 2bRx1 (CMOS inpwouputsructure) | cai all == aie ‘extemal clock input pins) can be used as serial /O pins) [PSPs [Output | 4-bit 1 (CMOS output structure, can be used as CRT output pins) | [Pes [input _|1-bitx 1 (can be used as sub-clock input pin, CRT display clock input pin) | i aad Pact sub-clock output pin, CRT display clock output pin) [Seavo wt | Muti-masterC-BUS interlace A [Timers Rmx | Interuptinterval determination creuit Pt ee CRT interrupt X 1, Multi-master 12C-BUS interface. interrupt X 1, (Xin)/4096 interrupt X 1, VSYNC interrupt X 1, BRK interrupt X 1 crystal oscillator) mm 6249828 0025810 O46 Mm oe ERE 2-676 ELECTRIC

M37267M4-XXXSP, M37267M6-XXXSP, M37267M8-XXXSP M37267EE-XXXSP, M37267EESP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER FUNCTIONS (continued) | Dataset OC™S™SOSSCCSY | Powersource voltage veto SOCOCOCOCOOCC*SY Power dissipation | In high-speed mode 0.33mW typ. (at oscillation frequency ICLxK = 32 kHz, f(XIN) = stopped) mode [wc Cid CRT display function [Dotstructure [Kinds of characters" tezkinds Cid Display poston (horizontal, vera) — mm 6249828 OO258l) T8e MM oes er

M37267M4-XXXSP, M37267M6-XXXSP, M37267M8-XXXSP M37267EE-XXXSP, M37267EESP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER PIN DESCRIPTION Input’ Output vec, Power source ‘Apply voltage of 5 V = 10 % (Iypical) to Voc and AVco, and 0 V to Vss. |AVcc, vss. [cnvss__[onvss |_| This is connected to Vss. RESET Reset input Input To enter the reset state, the reset input pin must be kept at a “L” for 2 us or more (under normal Vec conditions). if more time is needed for the quartz-crystal oscillator to stabilize, this *L" condition should be maintained for the required time. Po [Seceinput | ret | This chip has an internal clock generating circuit. To control generating frequency, an external ceramic resonator or a quartz-crystal oscilator is connected between pins XiNand Clock output Guiput | XOur. If an extemal clock is used, the clock source should be connected to the Xin pin and the XOuT pin should be left open. PooPWMé- |/O port PO Port PO is an -bit /O port with direction register allowing each V/O bit to be individually PoolPWM6, programmed as input or output. At reset, this port is set to input mode. The output structure Pos, of POs is CMOS output, that of P0o-P02 and P04~P07 are N-channel open-drain output. PouPWMO- ‘The note out of this Table gives a full of port PO function. PovrPwMs Pins PO0-P0e and P04-PO7 are also used as PWM output pins PWM4—PWM6 and PWMO— Output PWMS respectively. The output structure is N-channel open-drain output. Pto/OUTA, | /O port P1 Port P1 is an 8-bit I/O port and has basically the same functions as port PO. The output PIVvSCL1, ‘structure of P10 and P1s—-P'17 is CMOS output, that of P11-P14 is N-channel open-drain: Pt2a/SCL2, output. PraSDAl [CRT output Pins P10 is also used as CRT output pins OUT2. The output structure is CMOS output. Pts, |Muli-master Output | Pins P11-P14 are used as SCL1, SCL2, SDA1 and SDA2 respectively, when multi-master Pte, °C-BUS interface (?C-BUS interface is used. The output structure is N-channel open-drain output. Pi7/Sin [Serial VO data P17 pin is also used as serial /O data input pin Sin. input P20-P23 [VO port P2 Port P2 is an 8-bit /O port and has basically the same functions as port PO. The output P2WAD3- structure is CMOS output. P2Q/AD1, Pins P24-P26 are also used as analog input pins AD3-AD1 respectively. VO port PS Ports P30 and P31 are a 2-bit VO port and has basically the same functions as port PO. The ‘output structure is CMOS output. P4o/MXRV |inputport P4 | __—Input__| Ports P4o-P4e are a 7-bit input port and has basically the same functions as port PO. peaintar Video signal input Ports P4o-P43 are also usad as video signal input pins for mixing, MXR, MXB, MXOUT ine for CRT display respectively. Paariney [Analoginput_— | Tiput_—_| Pao pins also used as analog Input pin ADA. MXB, External interrupt Input Pins P41, P44 are also used as extemal interrupt input INT2, INT1. P4S/TIMG! | input MXOUT, Paa/NTi, [Extemal clock input| Input | Pins P42 and P43 are also used as external clock input pins TIM2, TIMS respectively. Pas/Sour, [Serial VO data P45 pin is used as serial /O data output pin Sour. The output structure is N-channel open- Pas/Scx, | output drain output. Serial VO P46 pin is used as serial /O synchronizing clock input/output pin Scux. The output struc- synchronizing clock| ture is N-channel open-drain output. input/output @® 6249828 0025812 919 MITSUBISHI 2-678 ae ELECTRIC

M37267M4-XXXSP, M37267M6-XXXSP, M37267M8-XXXSP M37267EE-XXXSP, M37267EESP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER eee eainy PIN DESCRIPTION (continued P52/R, [Output port PS Ports P52-P5s are an 4-bit output port and has basically the same functions as port PO. P5aG, The output structure is CMOS output. Beeeury [ORT ouput Pins P5c-P5s are also used as CAT output pins R, G, B, OUT respectively. The output structure is CMOS output. PevOsct/ [input por 6 | __Input__| ‘Ports Ps, PGs are a 2-bit nport and has basically the same functions as port PO. Xen, —— x ‘cour P64 pin is also used as CRT clock output pin OSC2. The output structure is CMOS output. for CRT 6s pin is also used as sub-clock output pin XcouT. The output structure is CMOS output. [suceargu | tut | Poroniabowsedes aockeptpn ¥en | VO for data slicer [Input | Input composite video signal through a capacitor. |__Input | Connect a capacitor between VHOLD and Vss. [avco | |__| Connecta resistor between RVCO and Vss. |__| Connect fiter using of a capacitor and a resistor between HLF andVss. | [Heme [Herne input [Input | This is ahorizontal synchronizing signal inputforOSD. [vere |vemeinput [Input This is averical synchronizing signalinputfor OSD. Note : As shown in the memory map (Figure 3), port PO is accessed as a memory at address 00CO1e of zero page. Port PO has the port PO direction register (address 00C'16 of zero page) which can be used to program each bit as an input (°0") or an output (*1"). The pins programmed as “1” in the direction register are output pins. When pins are programmed as "0," they are input pins. When pins are programmed as output pins, the output data are written into the port latch and then output. When data Is read from the output pins, the ‘output pin level is not read but the data of the port latch is read. This allows a previously-output value to be read correctly even if the ‘output “L" voltage has risen, for example, because a light emitting diode was directly driven. The input pins are in the floating state, so the values of the pins can be read. When data is written into the input pin, Its written only into the port latch, while the pin remains in the floating state. MITSUBISHI ELECTRIC 2-679

M37267M4-XXXSP, M37267M6-XXXSP, M37267M8-XXXSP M37267EE-XXXSP, M37267EESP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER: FUNCTIONAL DESCRIPTION CPU Mode Register Central Processing Unit (CPU) The CPU mode ragister contains the stack page selection bit and ‘The M37267M6-XXXSP uses the standard 740 family instruction set. _intamal system clock selection bit. The CPU mode register is allo- Refer to the table of 740 family addressing modes and machine in- cated at address OOF B16. structions or the SERIES 740 <Software> User's Manual for details ‘on thé instruction set. Machine-resident 740 family instructions are as follows: ‘The FST, SLW instruction cannot be used. ‘The MUL, DIV, WIT and STP instruction can be used. 7 9 CPU mode register (CPUM (CM) : address 00F B16) LET TTT Polo] LL processor mode bits b1bo 8 9 : Single-chip mode 10: } Not available Td: ‘Stack page selection bit 0: Zero page 1:1 page Fix these bits to “1.” Xcour drivability selection bit 0: Low drive 1: High drive Main colock (Xin - Xour) stop bit 0: Oscillating 1: Stopped Inte mal system clock selection bit 0 : Xiw - Xour selected (high-speed mode) 1: Xo - Xcout selected (low-speed mode) Note : Please beware of this bit when programming because it is set to “1” after the reset release. Fig. 1. Structure of CPU mode register “M@ 6249828 0025814 791 oa 2-680 ELECTRIC

M37267M4-XXXSP, M37267M6-XXXSP, M37267M8-XXXSP M37267EE-XXXSP, M37267EESP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER aS MEMORY Interrupt Vector Area Special Function Register (SFR) Area ‘The interrupt vector area contains reset and interrupt vectors. ‘The special function register (SFR) area in the zero page contains control registers such as /O ports and timers. Zero Page ‘The 256 bytes from addresses 000016 to OOFF16 are called the zero RAM age area. The intemal RAM and the special function registers (SFR) RAM is used for data storage and for stack area of subroutine calls are allocated to this area. and interrupts. ‘The zero page addressing mode can be used to specify memory and register addresses in the zero page area. Access to this area with ROM only 2 bytes Is possible in the zero page addressing mode. ROM is used for storing user programs as well as the interrupt vector area. Special Page ‘The 256 bytes from addresses FF0016 to FFFF16 are called the spe- RAM for Display cial page area. The special page addressing mode can be used to RAM for display is used for specifying the character codes and col- ‘specify memory addresses in the special page area. Access to this ors to display. area with only 2 bytes Is possible in the special page addressing mode. ROM for Display ROM for display is used for storing character data. { A A ART] _ 00C 0% Zero page LOL LL eel pene | BAM Ra Lied ed 10BFFi6| eka {ula (ote (ita (IS woreses “usresmue “warasms Swsrzsnn * 200° SER 2area__| (9648 bytes) [ratuset —| \\ {12008} SOY Mea ere O4BFI6 O4FFief Ce | stay orene| for display (Note) |_ OFE1r6| oe a eet, C00016} ek OM byes) ‘ee (82 Kbytes) / ROM vera | rte | Oa ke wsrzeme | “ren Fr O06 } “Lessor om | fm FFFFi6|_omurtvecior area 1FFFFi6 Note: Refer to Table 10. Contents of CRT display RAM. Fig. 2. Memory map — M@ 6249828 0025815 b28 oars a

MITSUBISHI MICROCOMPUTERS. M37267M4-XXXSP, M37267M6-XXXSP, M37267M8-XXXSP : M37267EE-XXXSP, M37267EESP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER, 00C016 OOEO16 00C116 OOEt18 coca [PoaPr (I o0csi6 OOESi6 oocéis [Pot P2 OOESi6 o0csi6 OOESi6 ooc6ie O0E6t6 ooc716 O0E716 oocere O0E8ie oocors O0E 916 - oocars[PotP5 OOEAI6 oocBre OOEBre oocere OoECre cocdef O0EDie OOCE:6 OOEE16 ocr ie OOEF ie o0Dore oF O16 o0D116 OOF 16 oon2te oor 26 oobare OF 316 000416 oF a6

000516 OOF S16

000616 OOF 616

coe%e OOF 16 oopAte OOFAte ope OOFBI6 00DCr6 00F Cie ooDDie OOF Die 00D Ete OOFE%6 00DF OOF Fie Fig. 3. Memory map of special function register 1 (SFR 1) . MH 6249828 0025816 Shy MM ate" 2-682 ELECTRIC

M37267M4-XXXSP, M37267M6-XXXSP, M37267M8-XXXSP M37267EE-XXXSP, M37267EESP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER as 020016 020116 020316 [PWM3 register 020516 020616 c2o7e {| Ce es o20Ar6 020B16 020016 020016 o20Ete | SSSSSSC=*'sNNNottee: Sect “O06” to address 020Et6. 020F 16 c21016 021116 [CRT input polarity register | o2i216 o21316 021416 oats PO cate [| o2t7ie PO cate PO cata [OT cata [OT oatBre PT cater | cae fT cate [ care Ld Fig. 4. Memory map of special function register 2 (SFR 2) M 6249828 0025817 4TO oe MEER 2-683

terrupts with priorties shown in Table 1. Reset is also included in the the vertical sync signal. ‘When an interrupt is accepted, is completed. 4” tected. Note that all bits are cleared to “0” at reset. request bit and an interrupt enable bit. The interrupt request bits are An interrupt is generated by an overflow of timer 1, 2, 3 or 4. the interrupt-related registers. . ‘ (V0 tunction. Reset is treated as a non-maskable interrupt with the highest priority. position register. priorities are same, and can be switched by software. fected by the interrupt disable flag | (non-maskable). Table 1. Interrupt vector addresses and priority

M37267M4-XXXSP, M37267M6-XXXSP, M37267M8-XXXSP M37267EE-XXXSP, M37267EESP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER z 2 7 ° interrupt request register 1 Interrupt request register 2 (IREQH : address 0OF C16) fo] LLL TTT] uncon ciencteey Timer 1 interrupt request bit INT1 interrupt request bit Timer 2 interrupt request bit Data slicer interrupt request bit Timer 3 interrupt request bit Serial V/O interrupt request bit Timer 4 interrupt request bit {(Xin)/4096 interrupt request bit CAT interrupt request bit INT2 interrupt request bit Verne interrupt request bit Multi: master 12C-BUS interface interrupt request bit Timer 5 «6 interrupt request bit Fix this bit to “0.” 0 : No interrupt request issued 1: Interrupt request issued 7 0 7 9o Interrupt control register 1 Interrupt control register 2 [Tol TT TTT) scan? Sterese Sores) (ICON2 : address OOFF16) ‘Timer 4 interrupt enable bit INT1 interrupt enable bit Timer 2 interrupt enable bit Data slicer interrupt enable bit Timer 3 interrupt enable bit Serial VO interrupt enable bit Timer 4 interrupt enable bit {0X1ny4096 interrupt enable bit GRT interrupt enable bit INT2 interrupt enable bit Vern interrupt enable bit Mutt-master |2C-BUS Fix this itt "0" interface interrupt enable bit Timer § - 6 interrupt enable bit Timer 5 - 6 interrupt switch bit 0: Timer 5 0: Interrupt disabled 1: Timer 6 1: Intarrupt enabled Fig, 5. Structure of interrupt-related registers Interrupt request bit Interrupt enable bit Interrupt disable flag | BAK instruction Interrupt request Reset Fig. 6. Interrupt control M@™ 6249828 0025819 223 = oars Be 2-685

M37267M4-XXXSP, M37267M6-XXXSP, M37267M8-XXXSP M37267EE-XXXSP, M37267EESP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER: a RAALUON'SCREEN DISPLAY CONTROLLER TIMERS (5) Timer 5 The M37267M6-XXXSP has 6 timers: timer 1, timer 2, timer 3, timer ‘Timer 5 can select one of the following count sources: 4, timer 5 and timer 6. All timers are 8-bit timers with the 8-bit timer © {(XIN)/16 or f(XCINV16. latch. The timer block diagram is shown in Figure 8. ‘© Timer 2 overflow signal All of the timers count down and their divide ratio is 1/(n+1), where n ‘® Timer 4 overflow signal is the value of timer latch. The value is set to a timer at the same time ‘The count source of timer 3 is selected by setting bit 6 of the timer by writing a count value to the corresponding timer latch (addresses mode register 1 (address 00F 416) and bit 7 of the timer mode regis- OOF016 to OOF 316 : timers 1 to 4, addresses 020C16 and 020Di16 : ter 2 (address O0F516). Either f(Xin) or f(Xcin) is selected by bit 7 of timers 5 and 6). the CPU mode register. ‘The count value is decremented by 1. The timer interrupt request bit Timer 5 interrupt request occurs at timer 5 overflow. is set to “1” by a timer overflow at the next count pulse after the count value reaches “0016”. (6) Timer 6 Timer 6 can select one of the following count sources: (1) Timer 1 © £(XIN)/16 oF {(XCINV16 Timer 1 can select one of the following count sources: ‘© Timer 5 overflow signal © F(XIN)/16 oF F(XCINV16 ‘The count source of timer 6 is selected by setting bit 7 of the timer ‘© f(XIN)/4096 or f(XCINV4096 mode register 1 (address 00F 416). Either f(Xin) or f(XCIN) is selected © Extemal clock from the P42/TIM2/MXB pin ‘by bit 7 of the CPU mode register. When timer 5 overflow signal is a ‘The count source of timer 1 is selected by setting bits 5 and 0 of the count source for the timer 6, the timer 5 functions as an 8-bit prescaler. timer mode register 1 (address OOF 416). Either f(Xin) or f(Xcin) Is Timer 6 interrupt request occurs at timer 6 overflow. ‘selected by bit 7 of the CPU mode register. ‘Timer 1 interrupt request occurs at timer 1 overflow. At reset, timers 3 and 4 are connected by hardware and “FF16" is automatically set in timer 3; “0716” in timer 4. The f(Xin) */16 is se- (2) Timer 2 lected as the timer 3 count source. The intemal reset is released by ‘Timer 2 can select one of the following count sources: timer 4 overflow at these state, the internal clock is connected. © £(XIN)/16 oF f(XCINV/16. At execution of the STP instruction, timers 3 and 4 are connected by ‘© Timer 1 overflow signal hardware and “FF 16” is automatically set in timer 3; 0716" in timer 4. © External clock from the P42/TIM2/MXB pin ~ ‘However, the f(Xin) */16 is not selected as the timer 3 count source. ‘The count source of timer 2 is selected by setting bits 4 and 1 of the ‘So set both bit 0 of the timer mode register 2 (address 00F516) and timer mode register 1 (address OOF 416). Either f(Xin) or (Xcin) is bit 0 at address 020F 16 to “0” before the execution of the STP in- ‘selected by bit 7 of the CPU mode register. When timer 1 overflow ‘struction (f(Xin) */16 is selected as the timer 3 count. source). The signal is a count source for the timer 2, the timer 1 functions as an 8- internal STP state is released by timer 4 overfiow at these state, the bit prescaler. internal clock is connected. Timer 2 interrupt request occurs at timer 2 overflow. Because of this, the program starts with the stable clock. 1 : When bit 7 of the CPU mode register (CM7) is “1,” (Xin) be- (3) Timer 3 comes f(XciN). ‘Timer 3 can select one of the following count sources: ‘The structure of timer-related registers is shown in Figure 7. © FOXIN)/16 oF F(XCINY16. © f(XcIN) ‘© External clock from the P4a/TIM3/MXOUT pin ‘The count source of timer 3 is selected by setting bit 0 of the timer mode register 2 (address 00F516) and bit 0 at address 020F 16. Ei- ther f(Xin) oF {(XcIN) is selected by bit 7 of the CPU mode register. ‘Timer 3 interrupt request occurs at timer 3 overflow. (4) Timer 4 ‘Timer 4 can select one of the following count sources: © £(XIN)/16 oF f(XCINV16- © f(Xiny/2 or f(Xcin)/2 © f(XcIN) ‘The count source of timer 3 is selected by setting bits 4 and 1 of the ‘timer mode ragister 2 (address O0F516). Either f(XINn) or f(XcIN) is ‘selected by bit 7 of the CPU mode register. When timer 3 overflow _ ‘signal is a count source for the timer 4, the timer 3 functions as an 8- bit prescaler. ‘Timer 4 interrupt request occurs at timer 4 overflow. aa oe MESES

M37267M4-XXXSP, M37267M6-XXXSP, M37267M8-XXXSP M37267EE-XXXSP, M37267EESP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER 7 oO 7 oO Timer mode register 1 Timer mode register 2 ' (TMI : address 00F416) (TMR2 : address OOF 516) Timer 1 count source selection bit 1 Timer 3 count source selection bit © 0 (%in)/16 or f(Xcin)/16 (Note) eto 1: Count source selected by bit 5 at of TMR1 address 020F 16) bo Timer 2 count source selection bit 1 0 0: {QKny/16 oF (XcINY/16 (Note) 0: Count source selected by bit 4 of 1 0:f(XcIn) TMAt oO 1: 1 : External clock from Pa2/TIM2/ + at Peer MRSAROUT pin MXB pin Timer 1 count stop bit ‘Timer 4 count source selection bits 0: Count start bs bt 4: Count stop 0 0: Timer 3 overtiow 0 1: f0GN)/16 or f(KcINy/16 (Note) Timer 2 count stop bit 1 0: QXiny2 or f(Xcmy2 (Note) . 0: Count start 4 1f0Kem) 1: Count stop Timer 2 count source selection bit 2 Taner & cours op kt 0 : £(XIn)/16 or f(XcIN)/16 (Note) [Count 1: Timer 1 overflow 1: Count stop Timer 4 count stop bit Timer 1 count source selection bit 2 0: Count start (0: f(Xiny/4096 or f(Xcim)/4096 (Note) 1: External clock from P42/TIM2/ 1: Count stop MXB pin Timer § count source selection bit 2 Timer § count stop bit 0: Timer 2 overflow 0: Count start 1: Timer 4 overtiow 1: Count stop Timer 6 count source selaction bit Timer 6 count stop bit 0 :fOXin)/16 oF f(XciN}/16 (Note) 0: Count start 1: Timer § overflow 1 Count stop Timer 5 count source selection bit 1 10: (QGN)/16 or f(XcINy/16 (Note) 1: Count source selected by bit 6 of TMRt Note : Either f(Xin) or (XcIn) is selected by bit 7 of the CPU mode register. Fig. 7. Structure of timer-related registers

MITSUBISHI MICROCOMPUTERS, M37267M4-XXXSP, M37267M6-XXXSP, M37267M8-XXXSP M37267EE-XXXSP, M37267EESP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER: CEL AY CONTROLLER

5 Data bus

Xcin O CM | : F ye ' x xno fa} bp} ako Ce re ees TMR12 TMAIs i p- J arte 0 > >> ey Ti uns , Reset a: = 1, timers P4sTIM3 © > pommel interrupt request TMR22 Timer 4 i : TMR23 3 : TMRIe > : Selection gate : Connected to : ups :tiermoderogeers |, || ‘TMR2 : Timer mode register 2 ‘TMRGEL : Timer 3 count source z fF (address 020F 16) cw :oPu tote ae =a | z : Le ‘Timer 6 ‘Notes 1: "H" pulse width of extemal clock inputs TIM2 and TIM3 needs 4 machine cycles or more. 2: When the extemal clock source is selected, timers 1, 2, and 3 are counted at a rising edge of input signal. 3: In the stop mode or the wait mode, extemal clock inputs TIM2 and TIMS cannot be used. Fig. 8. Timer block diagram MI 6249828 0025622 868 Mm ° 2-688 ate MESH

M37267M4-XXXSP, M37267M6-XXXSP, M37267M8-XXXSP M37267EE-XXXSP, M37267EESP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER —.] SERIAL VO ‘The M37267M6-XXXSP has a buit-in serial YO which can either rans- The operation of the serial V/O function is described below. The func- mit or receive 8-bit data in serial in the clock synchronous mode. tion of the serial VO differs depending on the clock source; extemal The serial VO block diagram is shown in Figure 9. The synchronizing _clock or intemal clock. clock VO pin (Scxx), and data output pin (Sour) also function as port P4, data input pin (Sin) also functions as port P1. Bit 2 of the serial VO mode register (address 00EB16) selects whether the synchronizing clock is supplied internally or extemally (rom the P46/SoLx pin). When an intemal clock is selected, bits 1 and 0 select whether {(Xin) Is divided by 8, 16, 32, or 64. To use Pas/Sour and P4a/Scux pins for serial VO, set the corresponding bits of the port P4 direction register (address 000916) to “0.” To use P17/SIN pin for serial VO, set the corresponding bit of the port P1 direction register (address 000316) to “0." XenO————, . [12] Databus x0 ; j cM Way Way TOP Te BS 8 oom Selection gate: Connected (CM: CPU mods ister 7 1, Serial vo PaeScxO ~ | | interupt request Ms: LSB<> MSB | Pi7SNO Serial VO shift register (8) 4 (Address 00EC1«)| | Note : When the data is set inthe serial YO register (address OOECte), the register functions as the serial /O shift register. Fig. 9. Serial VO block diagram WM 6249828 0025823 774 : a eaters ELECTRIC 2-689

M37267M4-XXXSP, M37267M6-XXXSP, M37267M8-XXXSP M37267EE-XXXSP, M37267EESP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER 7 and ON-SCREEN DISPLAY CONTROLLER a Internal clock—the serial VO counter is set to “7” during write cycle into the serial /O register (address 00EC16), and transfer clock goes *H" forcibly. At each falling edge of the transfer clock after the write 7 ° V0 cycle, serial data is output from the Sout pin. Transfer direction can Serial pode regis ter be selected by bit 5 of the serial /O mode register. At each rising lT TTT TT (SM : address OOFBe) ‘edge of the transfer clock, data is input from the Sin pin and data in L| the serial /O register is shifted 1 bit. Internal synchronizing clock Alter the transfer clock has counted 8 times, the serial /O counter Selection bits becomes *0” and the transfer clock stops at “H.” At this time the inter- 0 0:4(Xmy/8 of (Xonys rupt request bitis set to “1.” 0 1:4(Q%KmNV/16 oF (XoINyA6 External clock—when an extemal clock is selected as the clock 1° pone or tronyer source, the interrupt request is set to “1” after the transfer clock has . counted 8 times. However, transfer operation does not stop, so con- ‘Synchronizing clock selection bit trol the clock externally. Use the external clock of SOOkHz or less be rome ioe with a duty cycle of 50%. . The serial I/O timing is shown in Figure 10. When using an external Port function selection bit lock for transfer, the extemal clock must be held at “H" for initializing 0: P11, Pts functions as port the serial /O counter. When switching between an internal clock and 1:8CL1, SDA1 an extemal clock, do not switch during transfer. Also, be sure to ini- Port selection bit tialize the serial VO counter after switching. 0: Ptz, P14 functions as port 1: SCL2, SDA2 Notes 1: On programming, note that the serial /O counter is set by writing to the serial I/O register with the bit managing in- Transfer rection selection bit structions as SEB and CLB instructions. +: MB fret 2: When an extemal clock is used as the synchronizing clock, write transmit data to the serial /O register at “H’ of the Fix these bits to “012” transfer clock input level. Fig. 11. Structure of serial /O mode register syererircingooek “LE LE LE LILI LU LL Luu UU Transfer clock Serial YO register H write signal : Serial VO output 4 i_(Note) Sout Xb Xo: X od X_ds X_O« X_ Os X05 X [07 / Serial /O input ¢ + Es Gn GD 6S Gp Gp Gp Gn é Interrupt request bit is set to “1” Note : When an intemal clock is selected, the Sour pin is at high-impedance after transfer is completed. Fig. 10, Serial YO timing (for LSB first) mm 6249828 0025824 630 Mm MITSUBISHI 2-690 ELECTRIC

M37267M4-XXXSP, M37267M6-XXXSP, M37267M8-XXXSP M37267EE-XXXSP, M37267EESP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER: Data bus jwctere | LPwMo register : 1 |] Address : 020016) H

1 SOOCCCTe i

: 0 : H | PNs} Pog» DO« Pwo i as Se 4 POs Dos g- PWM! i : PW : "| PWMS register (Address : 020316) H i Pwe 1B epee P00 D0o PWM4 | PWM4 (Address : 020416) i PWe 7 i iaiileldaiiddiiiaia Sania PO: Dor g- PWMS if PWMS register (Address : 020516) : i PWs [ses Connected to black colored side when reset. PN : PWM mode register 1 (address 020A16) PW: PWM mode register 2 (address 020B16) pecs PO : Port PO register (address 00C016) Inside of; ______} is as same contents with the DO : Port PO direction register (address 00C116) Fig. 12. PWM block diagram MH 6249828 0025826 403 mm a ae 2-692 ELECTRIC

7 MITSUBISHI MICROCOMPUTERS

M37267M4-XXXSP, M37267M6-XXXSP, M37267M8-XXXSP M37267EE-XXXSP, M37267EESP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER OO DISPAY CONTROLLER ET wi i 5 iS i * Es 1S 4 1B is a a is, . iS & a : wt

3 H F :

ii |, 2B id > | : =a . Q ES a wigs, 3 lag g #3 oid? g gas 3 ig Ss : ag § ES : es ® 3 i S H z 8B sd * = Z 3S t : 8 FS R . 8: ® 3S 55 « 3 s g ® a ¢ 7st ‘ Fe = 3 a a Fy a tS 2 * . 8 5s @t Fig. 13. 8-bit PWM timing mm 6249828 002582? 347 x ee 2-0

M37267M4-XXXSP, M37267M6-XXXSP, M37267M8-XXXSP M37267EE-XXXSP, M37267EESP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER: OO ehenAhnehAecacacaea id ON SCREEN DISPLAY CONTROLLER 7 0 PWM mode register 1 PWM mode jister 2 CL LLT fefel | (PN: address 020A16) PT LLL TT (PW: aderess G20B%8) | PWM count source selection bit P04/PWMO output selection bit 0: Count source supply 0: POs output 1: Count source stop 1: PWMO output Fix these bits to “0.” P0s/PWM1 output selection bit 0: POs output 1: PWM1 output Pa cult polarity selection bit : itive polarity : P06/PWM2 output selection bit 1 : Negative poterty 0: POs output . 1: PWM2 output P07/PWM3 output selection bit 0: PO7 output 1: PWM output P00/PWM4 output selection bit 0: POo output 1: PWM4 output P01/PWMS output selection bit 0: PO: output 1: PWME output P02/PWM6 output selection bit 0: P02 output 1: PWM6 output Fix this bit to “0.” Fig, 14, Structure of PWM-related registers M@® 6249828 0025826 266

M37267M4-XXXSP, M37267M6-XXXSP, M37267M8-XXXSP M37267EE-XXXSP, M37267EESP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER A-D COMPARATOR ‘A-D comparator consists of 6-bit D-A converter and comparator. A-D 7 ° ‘comparator block diagram is shown in Figure 17. AD conte rogitr | The reference voltage “Vret’ for D-A conversion is set by low-order 5 DY: acsrees CODY) bits of the A-D control register 1 (address 00ED16) and bit 0 of the Pete raae set te A-D control register 2 (address 021416). . ‘The comparison result of the analog input voltage and the reference Spi tut votags rekeeros vtage voltage "Vee is stored in bit 5 of the A-D control register 1. 1: Input voltage > reference voltage For A-D comparison, set ‘O* to corresponding bits of the direction input pin selection bits register to use ports as analog input pins. Write the least significant rhea bit of dig value comesponding to Vret to be compared to bit 0 of the © 3: pavabe A-D control register 2. After that, write the high-order 5 bits of digital 1 Y panntvane value to the low-order 5 bits of the A-D contol register 1, and write the data for selecting analog input pins to bits 6 and 7. The voltage Fig 4g, Siructure of AD control register 2 comparison starts by writing to the A-D control register 1, and itis completed afer 16 machine cycias (NOP instruction X 6) Table 2, Relation between contents of A-D control registers and ref- erence voltage “Vret" [ets Tens Tene Tent [ero | eo | voltage "Vor po fo To Po fo To | vesves | 7 ° fo fo fo fo To [1 | 264Vec | A-D control register 2 jo | o [oo [io [4 [0 [ 3%4vec | (AD2: address 021416) po fo fo fo ta | 1 [46svec | po fo fo fi [oo | o [564 Veo | D-A converter set bits po fo fo fa fo tr [ e6svec | ome | Pp papa pa pa To [oT ei64 voc | OO pa fa fa Pa [a [oF eai6s vec | Fig. 16. Structure of A-D control register 1 Consume on ‘AD control register 1 ‘AD control registor 2 P2uAD1. ‘Analog —_— Paina] “Sesh | P4a/MXV/AD4- swe FC ————— Fig. 17. A-D comparator block diagram MITSUBISH ae ELECTRIC 2-605

M37267M4-XXXSP, M37267M6-XXXSP, M37267M8-XXXSP _ M37267EE-XXXSP, M37267EESP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER DATA SLICER ‘When the data slicer function is not used, the data slicer circuit can ‘The M37267M6-XXXSP inclides the data slicer function for the _be cut off by setting bit 0 of the data slicer control register 1 (address closed caption decoder (referred to as the CCD). This function takes O0DE%6) to “0.” Also, the timing signal generating circuit can be cut out the caption data superimposed in the vertical blanking interval of _off by satting bit 0 of data slicer control register 2 (address OODF ie) ‘a composite video signal. A composite video signal which makes _to “0.” These settings can realize the low-power dissipation. the sync chip's polarity negative is input to the CVin pin. Gonpostte i 470 seopr 1k 15k H signal | Hundred of 0.1nF—— 200 pF { Syne pulse counter [i H | register : vi] Hsync HLF] | RVCO REY : Clock run-in register 2 : Synchronizing] (address 00E716) | ee a (oor 14 Data slicer control register 2 Sreult (eddress 000FI0) Cro rool TT} filter lreult lroult To Data slicer control register.1 nn | (eddross OODE‘S Timing signal [To Toro TT} generating —-—] i circuit Data slicer ON/OFF | = ‘Window register : (address 00E216) | BPN oS [oro TLL Clock unin 1-H} Te determination FH TTT 17->-3vn0u PRek circuit mall] (OO TTT H ference [4 Clock run-in register 1 He Comparator : : voltage {address 00E616) fi ati decision [| | | ‘ 1000 pF Stout " sircutt Lf rTiti ii ao (Toor TTT TK Levene! Caption position register ‘Start bit detecting [<7 {address 00E016) [ eircuit a a CITITITT {__ }extemal circuit Stat DR outed reer ne {address O0E 116) Note: Make the length of wiring which is ( : connected to Voto, HLF, RVCO and generating circuit oo CVn pin as short as possible so that a CITT TIT Ks | leakage current may not be generated Clock run-in detect register 1} | when mounting a resistor or a (address 00E816) 4 capacitor on each pin. 16-bit shift register aaanneun high-order low, Clock run-in detect register 2| (address 00916) Data slicer interrupt Data register 2 |generating circult || ‘Sync slice register (address Q0ESt6) request {address 00E316) REREEEE VY VV VYVY¥ Data register 1 Croom «= CLEETEITI «= CELE [IIT address 006416) [| Fig. 18. Data slicer block diagram M@@ 62498248 0025830 934 2-696 oe EES

M37267M4-XXXSP, M37267M6-XXXSP, M37267M8-XXXSP M37267EE-XXXSP, M37267EESP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER: a Figure 19 shows the structure of the data slicer control register. 7 ° U ° Data slicer control register 1 , CTTPPIIT secsorcem CELE anenseger Data slicer control bit 0: Data slicer stopped Timing signal generating circuit | =

1 Data slicer operating control bit

0: Stopped Field tobe sliced data 1: Operating selection bit Reference clock source 0: Hep LI selection bit 0 : Video signal Veep ¥. 11: Hsync signal Test bit : read-only 1: Hsep u u rr Fix these bits to‘0” Field selection bit 9: Flald selected by bit 1 Vue shape determination Field determination flag Fix this bit to“0" o: tee LT LU Testbit : read-only i a a Fix thi bit to "0" Data clock generating : determination bit 0: No generation of 16 pulses 1 : Generation of 16 pulses Fig. 19. Structure of data slicer control registers (1) Clamping Circuit and Low-pass Filter This filter attenuates the noise of the composite video signal input 7 ° from the CVn pin. The CVWv pin to which composite video signal is ‘Syne slice register input requires a capacitor (0.1 uF) coupling outside. Pull down the [ To] [fo] lo] L] lef] (SSL : address 00316) CV pin with a resistor of hundreds of kloohms to 1M . In addition, LT LITT] we recommend to install externally a simple low-pass fiter using a Fix these bits to "00001017" resistor and a capacitor at the GVW pin (refer to Figure 18). it Vertical i (2) Sync Slice Circuit signal (Veen) genereing This circuit takes out a composite sync signal from the output signal method selection bit of the low-pass filter. Figure 20 shows the structure of the syne slice 0: Method 1 register. 1: Method 2 Fig. 20. Structure of syne slice register _ M@ 6249828 0025831 470 : ae ELECTRIC 2-697

M37267M4-XXXSP, M37267M6-XXXSP, M37267M8-XXXSP M37267EE-XXXSP, M37267EESP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER | a (3) Synchronizing Signal Separation Circuit (4) Timing Signal Generating Circuit This circuit separates a horizontal synchronizing signal and a vertical This circuit generates a reference clock which is 832 times as large synichronizing signal from the composite sync signal taken out inthe _as the horizontal synchronizing signal frequency. It also generates syne slice circuit. various timing signals on the basis of the reference clock, horizontal © Horizontal synchronizing signal (Hsep) ‘synchronizing signal and vertical synchronizing signal. The circuit ‘A one-shot horizontal synchronizing signal Hsep is generated at _operates by setting bit 0 of data slicer control register 2 (address the falling edge of the composite syne signal. O0DF 6) to “1.” © Vertical synchronizing signal (Veep) “The reference clock can be used as a display clock for CRT display ‘As a Veep signal generating method, it is possible to select one of function in addition to the data slicer. The Hsvvc signal can be used the following 2 methods by using bit 7 of the sync slice register —_as.a count source instead of the composite sync signal. However, (address 00E316), when the Hsvwc signal is selected, the data slicer cannot be used. A “Method 1 The “L" level width of the composite sync signal is count source of the reference clock can be selected by bit 1 of data measured. Ifthis width exceeds a certain time, a Vsep _slicer control register 2 (address OODF te). signal is generated in synchronization with the rising _-Reading bit 5 of data slicer control register 2 permits determinating of the timing signal immediately after this “L” level. the shape of the V-pulse portion of the composite sync signal. As “Method 2 The “L” level width of the composite sync signal is shown in Figure 22, when the A level matches the B level, this bit is measured. If this width exceeds a certain time, itis “0.” In the case of a mismatch, the bitis “1.” detected whether a falling of the composite sync For the pins RVCO and the HLF, connect a resistor and a capacitor signal exits or not in the “L" level period of the timing _as shown in Figure 18. Make the length of wiring which is connected signal immediately after this “L" level Ifa falling exists, to these pins as short as possible so that a leakage current may not ‘a Veeo signal is generated in synchronization with be generated. 7 the rising of the timing signal (refer to Figure 21). Figure 21 shows a Vsep generating timing. The timing signal shown _Note: It takes a few tens of milliseconds until the reference clock in the figure is generated from the reference clock which the timing becomes stable after the data slicer and the timing signal ‘generating circuit outputs. generating circuit are started. In this period, various timing signals, Hsop signals and Vsep signals become unstable. For this reason, take stabilization time.into consideration when programming. Composite V-pulse syne signal I | CU pulse width is tong, ‘ml to" poiod ie [Hulse wish is shor, BS 0 Timing TANAALAAAnr TTA ° : H ‘sync signal an Vooo signal TULL LT: AoA ‘A Voop signal is generated at a rising of the timing signal AB immediately after the °L” level width of the composite syne signal exceeds a certain time. Fig. 21. Veep generating timing (method 2) Fig. 22. Determination of V-pulse waveform eee 2-698, ELECTRIC

M37267M4-XXXSP, M37267M6-XXXSP, M37267M8-XXXSP M37267EE-XXXSP, M37267EESP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER a (5) Line 21 Decision Circuit ® Selection of field to be sliced data © Decision of fine 21 Field to be sliced data is selected by bit 1 of data slicer control This circuit decides a line (line 21) on which caption data is register 1 (address OODE%6). When bit 2 of the data slicer control superimposed. register 1 is set to “1,” itis possible to decide line 21 for both fields. Set the number of Hsep to be input in the period from a falling of ‘The field determination flag can be read out by bit 5 of the data \\Vsep to a line on which caption data is superimposed in bits 0 to 4 slicer control register 1. This flag changes at the falling of Vsep. of the caption position register (address 00E016). The number of Hsep is counted by hardware. The line which matches the set value (6) Reference Voltage Generating Circuit and in the caption position register is regarded as line 21, Comparator The values of “0016” to “1F16" can be set in the caption position The composite video signal clamped by the clamping circuit is input register. Bit 7 to bit § are used for testing. Set “1002." Figure 23 _to the reference voltage generating circuit and the comparator. ‘shows the signals in the vertical blanking interval. Figure 24 shows the structure of the caption position register. Video signal Vertical blanking interval ann = O00 i Composite i video signal ! Veco Line 21 Heep, Count value to be set in the caption position register ("1 116" in this case) ited drawing i Clock run-in Start bit + 16-bit data i | Composite video i signal min, max. Start bit i : Time to be set in the ! : start bit position register ! Fig. 23. Signals in vertical blanking interval © Reference voltage generaling circuit This circuit generates a reference voltage (slice voltage) by using Zz o capton positon mgiater the amplitude of the clock run-in at line 21 of the field selected by position regi [polo] T TTT] aerate bit 1 of the data slicer control register. Connect a capacitor of about 1000 pF between the VioLD pin and the Vss pin, and make the Ly length of wiring as short as possible so that a leakage current may Number of horizontal synchronizing not be generated. lin = foe ate aevae ® Comparator ; a ‘The comparator compares the voltage of the composite video signal Fix those bits to "1000 with the voltage (reference voltage) generated in the reference voltage generating circuit, and converts the composite video signal Fig. 24. Structure of caption position register into a digital value. WM 6249828 0025833 643 &—_—— oars ELECTRIC 2-699

M37267M4-XXXSP, M37267M6-XXXSP, M37267M8-XXXSP M37267EE-XXXSP, M37267EESP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER (7) Start Bit Detecting Circuit The time is set in bits 0 to 6 of the start bit position register (address ‘This circuit detects a start bit at line 21 decided in the line 21 decision 00E116) (refer to Figure 26). Set a value fit for the following Circuit, For start bit detection, itis possible to select one of the following conditions. ‘two types by using bit 1 of the clock run-in régister 2 (address 00716). Figure 26 shows the structure of the start bit position register. © After the lapse of the time corresponding to the set value of the start bit position register (address 00E118), the first rising of the : composite video signal is detected as a start bit. “Time from the falling of the horizontal 4 X set value of the start bit position Tithe from the falling of the horizontal ‘synchronizing signal to the last rising |< _| register x reference clock period <__| synchronizing signal to occurrence of of the clock run-in the start bit @ After a falling of the clock run-in pulse set in bits 2 to 0 of clock run- in detect register 2 (address 00E916) is detected, a start bit is 7 0 detected by sampling a comparator output. A sampling clock for Start bit position register sampling is obtained by dividing the reference clock generated in (SP : address 00E116) the timing signal generating circuit by 13. Figure 27 shows the structure of clock run-in detect register 2. Start bit generating time The contents of bits 2 to 0 of clock run-in detect register 2 and bit Tozontal syechveviang signal 4 of clock run-in register 2 are written at a falling of the horizontal Hiploselene sill ead synchronizing signal. For this reason, even if an instruction for X set value ("0016" to “7F 16") X setting is executed, the contents of the register cannot be rewritten reference clock period : until a falling of the horizontal synchronizing signal. DSC1 bit 7 control bit 0: Generation of 16 pulses 1 : Generation of 16 pulses and detection of clock run-in Zz 0 Fig. 26. Structure of start bit position register Clock runsin register 2 LLofoT PL] [4] cere ‘cdsress 00271) : Fix this bit to “1° z 0 Clock run-in detect register 2 Start bit detecting method (CRD2 : address 00E916) selection bit 0: Method 1 1: Method 2 ‘Clock run-in pulses for sampling b2 bt bo Fix these bits to “1001112” 0 0 0: Not available 0 0 1: 4stpuise 0 4 0:2nd pulse 0 1 1:3rd pulse 1 0 074th puise Fig. 25. Structure of clock run-in register 2 1 0 1:5th puise 1 1 0:6th pulse 1 1 = 1:7th pulse Data clock generating time Time from detection of a start bit to occurrence of a data clock : = (13 + set value) X reference clock period Fig. 27. Structure of clock run-in detect register 2 WM 6249828 0025834 Sat Mm

MITSUBISHI MICROCOMPUTERS, M37267M4-XXXSP, M37267M6-XXXSP, M37267M8-XXXSP M37267EE-XXXSP, M37267EESP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER sess (8) Clock run-in determination circuit This circuit sets a window in the clock run-in portion in the composite Zz 0 video signal, and then determinates clock run-in by counting the Window register number of pulses in this window. Set the time from a falling of the (fT TTT TTI (WN : address 00E2:6) horizontal synchronizing signal to a start of the window by bits 0 to 5 LITT EI Window start me of the window ragister (address 00E216; refer to Figure 28). The Time from a falling of the window ends according to the contents of the setting of the start bit horizontal synchronizing signal position register (refer to Figure 26). toa start of the window = 4 X set The count value of pulses in the window is stored in clock run-in value Conve t0 “SF 16") X reference register 1 (address OOF616; refer to Figure 28). When this count value oon Is 4 to 6, itis determined as a clock run-in. Accordingly, set the count Fix thesa bits t0 “0” value so that the window may start after the first pulse of the clock run-in (refer to Figure 30). Fig. 28. Structure of window register ‘The contents to be set in the window register are written at a falling of the horizontal synchronizing signal. For this reason, even if an instruction for setting is executed, the contents of the register cannot be rewritten untii a faling of the horizontal synchronizing signal. 0 Reference clock is counted in the period from a falling of the clock [ol fos] [ TT] (Cat noarose Gost) pulse set in bits 0 to 2 of the clock run-in detect register 2 (address . 00E916) to the next falling. The count value is stored in bits 3 to 7 of Ly] - the clock run-in detect register 1 (address 00E81s) (When the count Clock run-in count value value exceeds “IF 1s,” *1F16” is held). Read out these bits after the occurence of a data slicer interrupt (refer to (11) Interrupt Request Fix these bits to“01012" Generating Circuit). Figure 31 shows the structure of clock run-in detect register 1. Fig, 29. Structure of clock run‘in register 7 (9) Data clock generating circuit This circuit generates a data clock phase-synchronized with the start bit detected in the start bit detecting circuit rants a Suribtaata + Set the time from detection of the start bit to occurrence of the data signal Clock run-in) ,_ 16-bit data clock in bits 3 to 7 of the clock run-in detect register 2 (address <> 00E916). The time to be set is represented by the following expression: Composite rm >——_e video signal = Time = (13 + set value) X reference clock period (at Xin = 8 MHz) Window = |__| For a data clock, 16 pulses are generated. When just 16 pulses have Time to be set in the| When the count value been generated, bit 7 of the data slicer control register is set to “1" window register In the window is 4 to 6, {reer to Figure 19). When method 1 is already selected as a start bit Slime wo be satin Us fe determined as a detecting method, this bit becomes a logical product (AND) value the start bit position . with a clock run-in determination result by setting bit7 of the start bit register position register to “1.” Fig 20. Wi " When method 2 is already selected as a start bit detecting method "9-90. Window setting and 16 pulses are generated of a data clock regardless of bit 7 of the t start bit position register, this bit is set to “1.” The contents of this bit are reset at a falling of the vertical synchronizing signal (Vsep). Clock run-in detect register 4 (CRD1 : address 00E816) Test bits : read-only Number of reference clocks to be counted in one clock run-in pulse period Fig. 31. Structure of clock run-in detect register 1 MM 6249828 0025835 41b me ~— a MITSUBISHI ae ELECTRIC 2-701

M37267M4-XXXSP, M37267M6-XXXSP, M37267M8-XXXSP M37267EE-XXXSP, M37267EESP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER (10) 16-bit Shift Register ‘The latch value can be obtained by reading out the sync pulse counter The caption data converted into a digital value by the comparator is _register (address OOEAte). A count source is selected by bit 5 of the stored into the16-bit shift register in synchronization with the data —_syni¢ pulse counter register. The count time (T time) varies depending clock. The contents of the high-order 8 bits of the stored caption data _on the selected count source. and the contents of the low-order 8 bits of the same data can be When the Hsywc signal has been selected as a reference clock source obtained by reading out the data register 2 (address 00ESie) and —_in the status which bit 1 of the data slicer control register 2 (address data register 1 (address 00E416), respectively. These registers are 00D Fie) is setto “1,” the synchronizing signal counter cannot be used. reset to “0” at a falling of Veep. Read out data registers 1 and 2 after _ Figure 32 shows the structure of the sync pulse counter and Figure the occurence of a data slicer interrupt (refer to (11) Interrupt Request 33 shows the synchronizing signal counter block diagram. Generating Circuit). (11) Interrupt Request Generating Circuit A data slicer interrupt request occurs concurrently with an end of the 7 0 line specifiedin the caption position register (address 00E016),a falling ‘Sync pulse counter register of the composite sync signal. Read out the contents of data registers LIITTTT1 (YC: address 0OEAt0) 1 and 2 and the contents of bits 3 to 7 of the clock run-in detect [TTT] register 1 after the occurence of a data slicer interrupt request. ‘Count value (12) Synchronizing Signal Counter [Count source] Counttme——_—+| The synchronizing signal counter counts the composite syne signal taken out rom a video signal nthe data scr ccult ortho verical synchronizing signal Vsep as a count source. Signal _|(At262, 15 ms, 104m) = 8 MHz) The count value in a certain time (T time) generated by f(Xin)/2" or 4: Composite | 4(xX0)/2"3 {(Xiny/2*' is stored into the §-bit latch. Accordingly, the latch value sync signal | (At 1024 ps, f(Xin) = 8 MHz) changes in the cycle of T time. When the count value exceeds “1Fis,” “1Fi6" is stored into the latch. Fig. 32. Sync pulse counter register fxn _O sexmye2e? b Composite 6, syne signal Reset tort Of re [os] ten ener) ob ‘counter register Selection gate : connected to black a Fig. 33. Synchronizing signal counter block diagram M@ 6249428 0025436 352 _ aE

M37267M4-XXXSP, M37267M6-XXXSP, M37267M8-XXXSP- M37267EE-XXXSP, M37267EESP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER MULTI-MASTER I2C-BUS INTERFACE Table 3. Multi-master I2C-BUS interface functions ‘The multi-master |2C-BUS interface is a circuit for serial communica- [tem | ~*Function —CO~‘(dzd tions conformed withthe Philips I2C-BUS data transfer format. This om interface, having an arbitration lost detection function and a synchro- tn conformity with Phips Pc-aus ‘nous function, is useful for serial communications of the multi-mas- 10-bit addressing format ter. 7-bit addressing format Figure 34 shows a block diagram of the muiti-master I2C-BUS inter- Gigh-speed clock mode face and Table 3 shows multimaster I2C-BUS interface functions. ‘This muiti-master I2C-BUS interface consists of the I2C address reg- In conformity with Pips °C-BUS ister, the IPC data shift register, the IC clock control register, the °C Master transmission control register, the I2C status register and other control circuits. Communication mode | Master reception Slave transmission Slave reception 9: System clock = {(Xiny2 Note: We are not responsible for any third party's inftingement of patent rights or other rights atibutable to the use of the con- trol function (bits 6 and 7 of the I2C control register at address (00F 816) for connections between the I2C-BUS interface and ports (SCL1, SCL2, SDA1, SDAZ). : b7__PCaddress register 0 [saod)sapsisan4]sandsand sap fsaod pePebepebeepope] mg] ea TT Lint i it [| fateh] T] sera | [Noise = ied (rr rirrth | | LL TF pe a Te De och [— | | lala a7" a : BB | circuit | ; Seria Noise Clock | | | OES") SS PRESS eesllsblbs ——— — 12C clock control register S1D_ IC clock contro! register . System clock (6) Fig. 34. Block diagram of multi-master I?C-BUS interface MM 6249828 0025837 295 me MITSUBISHI eS 2-703

M37267M4-XXXSP, M37267M6-XXXSP, M37267M8-XXXSP M37267EE-XXXSP, M37267EESP ‘SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER (1) PC Data Shift Register ‘The I°C data shift register (SO : address OOF616) is an 8-bit shift 7 ° register to stora receive data and write transmit data. sd caod ood andenod “Tan] 12 C address register ‘When transmit data is written into this register, itis transferred to the [odor of ned edo] (SOD: address 00F716) ‘outside from bit 7 in synchronization with the SCL clock, and each time one-bit data is output, the data of this register are shifted one bit ‘Read/write bit to the left. When data is received, it is input to this register from bit 0 . in synchronization with the SCL clock, and each time one-bit data is Slave address input, the data of this register are shifted one bit to the left. The 2C data shift register is in a writa enable status only when the : ESO bit of the I2C control register (address 00F 916) is “1.” The bit Fig. 35. Structure of °C address register counter is reset by @ write instruction to the [2C data shift register. ‘When both the ESO bit and the MST bit of the PC status register (address 00F816) are “1,” the SCL is output by a write instruction to @) ve Clock Control Register At) Es used t0 sot ACK the IC data shift register. Reading data from the I2C data shift regis- ‘control, SCL mode and SCL ney. ters always enabled regardiess of the ES0 bit value. Bits 0 to 4: SCL frequency control bits (CCRO-CCR4) Those bit . . Note: To write data into the C data shift register after setting the ene std rove crac Uasely headin ‘ MST bit to “0” (slave mode), keep an interval of 8 machine. Tax it epscties he SCL mode. When this bits set to “0 the stan- cycles or more, dard clock mode is set. When the bit is set to “1,” the high-speed clock mode is set. @ PC Address Register Bit 6: ACK bit (ACK BIT) @ PC address register (address 00F716) consists of a7-bit slave THis bi gots the SDA status whon an AGK clock goneraled. When soaress end a ‘ec ‘ or Inthe eos mo tne ave a this bit is set to “0,” the ACK retum mode is set and make SDA “L” at ress written in piiseaieapehcaanelih ress data to the occurrence of an ACK clock. When the bit is set to “1," the ACK wore Aecawnte POW. START condition are detected. ‘non-return mode is set. The SDA is held in the *H” status at the oc- : Read currence of an ACK clock. Nottsad ine 7B adrossi ng mode Inte Toph adaressing node, However, when the slave address matches the address data in the ctnenrhoniesi: be eo fe compares wt Contents reception of address data at ACK BIT =*0," the SDA is automatically wa sae nile ns in ce reais condition a2" (ACK is retumed), I there is a mismatch betwoen the slave i pai automatically when the stop address and the address data, the SDA Is automatically made . “HE(ACK is not returned). Bits 1 to 7: Slave address (SADO-SADS) These bits store slave addresses. Regardless of the 7-bit address- ACK clock: Clock for acknowledgement ing mode and the 10-bit addressing mode, the address data trans- ° mitted from the master is compared with the contents ofthese bits. Bit 7. acK clock bit (ACK) . This bit specifies a mode of acknowledgment which is an acknowl- edgment response of data transmission. When this bit Is set to “0,” the no ACK clock mode is set. In this case, no ACK clock occurs after data transmission. When the bit is set to “1,” the ACK clock ‘mode is set and the master generates an ACK clock upon comple- tion of each 1-byte data transmission. The device for transmitting address data and control data releases the SDA at the occurrence of an ACK clock (make SDA “H’) and receives the ACK bit generated by the data receiving device. Note: Do not write data into the I2C clock control register during ‘transmitting. if data is written during transmitting, the 2C clock generator is reset, so that data cannot be transmitted nor- mally. . MM £249428 0025838 12cS

number of bits specified with these bits are transmitted. 0: Standard clock the address data is always transmitted and received in 8 bits. 0: ACK is retumed, tha reetface te enabled. nck clock vt When £0 =0,"the folowing is performed. ; . TE AGK cock status register at address OOF 816 ). Fig. 36. Structure of 2C clock control register abled. Table 4. Set values of C clock control register and SCL frequency _ThS bit decides whether or not o recognize slave addresses. When and ports (refer to Figure 37).

MITSUBISHI MICROCOMPUTERS. M37267M4-XXXSP, M37267M6-XXXSP, M37267M8-XXXSP M37267EE-XXXSP, M37267EESP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER . and ON-SCREEN DISPLAY CONTROLLER v 7 o “f” BSELO adjioe FC contol register CS O—O SCLIPI: . (S1D : address OOF 916) v Mult-master °C °F Sclaipte transmit/receive bits) 2c-BUS «1 BSELO b2 bt bo interface O— spatts tole v : - - Oo O——O SDA2/P14 10 0:4 10 1:3 11 0:2 Note : When using multi-master I2C-BUS interface, 14404 set bits 3 and 4 of the serial /O mode register {address OOEB16) to “1.” [2C-BUS interface use enable bit Fig. 37. Connection port control by BSELO and BSEL1 °: Disabled Data format selection bit 0: Addressing format (5) PC Status Register 1: Free data format The °C status register (address 00F 816) controls the I2C-BUS inter- face status, The low-order 4 bits are read-only bits and the high- Addressing format order 4 bits can be read out and written to. SH Ok . Bit 0: Last receive bit (LRB) Vena This bit stores the last bit value of received data and can also be 1: 10-bit addressing used for ACK receive confirmation. If ACK is retuned when an ACK format clock occurs, the LRB bit is set to “0.” If ACK is not retumed, this bit - : is set to “1.” Except in the ACK mode, the last bit value of received period control bits data is input. The state of this bit is changed from “1” to “O" by execut- Parana end ports ing a write instruction to the [?C data shift register (address OOF 616). b7 b6 Connection port Bit 1: General call detecting fiag (ADO) 0 0: None This bitis set to “1” when a general call* whose address data is all“O" 0 1: SCL, SDA1 is received in the slave mode. By a general call of the master device, ise every slave device receives control data after the general call. The * sci2) Spaz : ADO bit is set to “0” by detecting the STOP condition or START con- dition. Fig. 38. Structure of |2C control register General call: The master transmits the general call address “0016” toall slaves. MBit 2: Slave address comparison flag (AAS) This flag indicates a comparison result of address data. @in the slave receive mode, when the 7-bit addressing format is selected, this bit is set to “1” in one of the following conditions. The address data immediately after occurrence of a START . condition agrees with the slave address stored in the high-order 7 bits of the °C address register (address 0OF716). ‘A general call is received. @in the slave reception mode, when the 10-bit addressing format is selected, this bit is set to “1” with the following condition ‘When the address data is compared with the I@C address register (8 bits consisted of slave address and RBW), the first bytes agree. ® The state of this bit is changed from “1” to “0” by executing a write instruction to the (2C data shift register (address OOF 616). M@® 6249824 0025840 643 2-706 eS

M37267M4-XXXSP, M37267M6-XXXSP, M37267M8-XXXSP M37267EE-XXXSP, M37267EESP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER nanan een @ Bit 3; Arbitration lost* detecting flag (AL) mitted by the master is “1.” When the ALS bit is “0” and the RAW bit is In the master transmission mode, when the SDA is made “L" byany “0,” the TRX bit is cleared to 0" (receive). other device, arbitration is judged to have been lost, so that this bitis The TAX bit is cleared to “O" in one of the following conditions. ‘sat to “1.” At the same time, the TRX bits set to“0,” sothatimmedi- When arbitration lost is detected. ately after transmission of the byte whose arbitration was lost is com- When a STOP condition is detected. pleted, the MST bit is set to “0.” In the case arbitration is lost during ‘When occurence of a START condition is disabled by the START slave address transmission, the TRX bit is set to “0” and the recep- condition duplication preventing function (Note). tion mode is set. Consequently, it becomes possible to receive and ——_e With MST = “0” and when a START condition is detected. recognize its own slave address transmitted by another master de- With MST = “0” and when ACK non-retum is detected, vice. *Atreset {© Bit 7: Communication mode specification bit (master/stave speci- ‘Arbitration lost: The status in which communication as a master is fication bit: MST) disabled. This bit is used for master/slave specification for data communica- Bit 4: [2C-BUS interface interrupt request bit (PIN) tion. When this bit is “0,” the slave is specified, so that a START This bit generates an interrupt request signal. Each time 1-byte data condition and a STOP condition generated by the master are re- 's transmitted, the state of the PIN bit changes from “1” to“0." Atthe ceived, and data communication is performed in synchronization with ‘same time, an interrupt request signal occurs to the CPU. The PIN the clock generated by the master. When this bit is “1,” the master is bit is set to “0” in synchronization with a falling of the last clock (in- specified and a START condition and a STOP condition are gener- cluding the ACK clock) of an internal clock and an interrupt request ated, and also the clocks required for data communication are gen- signal occurs in synchronization with a falling of the PIN bit. When grated on the SCL. the PIN bit is “0,” the SCL is kept in the “0” state and clock generation ‘The MST bit is cleared to “0” in one of the following conditions. is disabled. Figure 40 shows an interrupt request signal generating ‘immediately after completion of 1-byte data transmission when ar- timing chart. bitration lost is detected The PIN bitis set to “1” in one of the following conditions, ‘When a STOP condition is detected. ‘* Executing a write instruction to the |?C data shift register (address ‘When occurence of a START condition is disabled by the START OOF 616). condition duplication preventing function (Note). ‘When the ESO bitis “0” *Atreset At reset The conditions in which the PIN bit is set to “O" are shown below: Note: The START condition duplication prevention function disables ‘Immediately after completion of 1-byte data transmission (includ- the occurence of a START condition, reset of bit counter and ing when arbitration lost is detected) SCL output when the following condition is satisfied: ‘Immediately after completion of 1-byte data reception *a START condition is set by another master device. © n the slave reception mode, with ALS =“0" and immediately after ‘completion of slave address or general call address reception in the slave reception mode, with ALS = “1” and immediately after completion of address data reception MBit 5: Bus busy flag (88) This bit indicates the status of use of the bus system. When this bit is set to “0,” this bus system is not busy and a START condition can be generated. When this bit is set to “1,” this bus system is busy and the ‘occurrence of a START condition is disabled by the START condi- tion duplication prevention function (Note). This flag can be written by software only in the master transmission mode. in the other modes, this bit is set to “1” by detecting a START condition and set to “0” by detecting a STOP condition. When the ESO bit of the I2C control register (address OOF 916) is “0” and at reset, the BB flag is kept In the “0” state. ‘1 Bit 6: Communication mode specification bit (transfer direction specification bit: TAX) This bit decides a direction of transfer for data communication. When this bit is “0,” the reception mode is selected and the data of a trans- mitting device is received. When the bit is “1,” the transmission mode Is selected and address data and control data are output onto the SDA in synchronization with the clock generated on the SCL. ‘When the ALS bit of the I2C control register (address 00F916) is “0” in the slave reception mode is selacted, the TAX bit is set to “1” (transmit) if the least significant bit (R/W bit) of the address data trans- M§ 6249828 002584) 727 ———— Petre ELECTRIC 2-707

M37267M4-XXXSP, M37267M6-XXXSP, M37267M8-XXXSP M37267EE-XXXSP, M37267EESP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER 7 (6) START Condition Generating Method o When the ESO bit of the I2C contro! register (address 00F916) is “1,” fusrfrax] es enn] at [ans ane] apperabe rc an ‘execute a write instruction to the I2C status register (address 00F 816) for setting the MST, TRX and BB bits to “1.” Then a START condi- tion occurs. After that, the bit counter becomes “0002” and an SCL usa {for 1 byte is output. The START condition generating timing and BB 1: Last bit = “1” bit set timing are different in the standard clock mode and the high- speed clock mode. Refer to Figure 41, the START condition generat- Sena call detecting flag ing timing diagram, and Table 5, the START condition/STOP condi- (Note) 1 ein 0: No general call detected tion generating timing table. 1: General call detected Slave address comparison flag (Note) PC status register 0 : Address disagreement wie signal 1: Address agreement H ‘Arbitration jost detecting flag SDA poe H (Note) Hi + Settimetor 0: Not detected BB fag = __|__! B8fag- 1: Detected TTSeup—t J . rime 7 H P°C-BUS interface interrupt : request OR pt request Fig. 41. START condition generating timing diagram 1: No interrupt request issued . (7) STOP Condition Generating Method Bus busy flag ‘When the ESO bit of the 7C control register (address 0OF916) is “1,” 0: Bus free ‘execute a write instruction to the IC status register (address OOF 816) 1: Bus busy for setting the MST bit and the TRX bit to “1” and the BB bit to “0 Then a STOP condition occurs. The STOP condition generating tim- Communication mode ing and the BB flag reset timing are different in the standard clock wooo olave receive thode mode and the high-speed clock mode. Refer to Figure 42, the STOP 01 : Slave transmit mode condition generating timing diagram, and Table 5, the START condi- 10: Master receive mode ing tims u d a tion/STOP condition generating timing table. Note: These bit and flags can be read out but cannot be written. F Fig. 39. Structure of |2C status register ns oy TT cr — nn) _ + Setup. . | Hold time- SDA 1 ene 1. eset tine for seu r 1 | BBfag = ___i8efiag # PIN : rs ae Fig. 42. STOP condition generating timing diagram i Table 5. START condition/STOP condition generating timing table mora [Item Standard clock mode | High-speed clock mode | [Setup time | "5.0 us (20 cycles) Fig. 40. Interrupt request signal generating timing 3.0 us (12 cycles) 1.5 us (6 cycles) Note: Absolute time at ¢ = 4 MHz. The value in parentheses de- notes the number of g cycles. M@! 6249428 0025842 bob Ml 2-708 oe

MITSUBISHI MICROCOMPUTERS. M37267M4-XXXSP, M37267M6-XXXSP, M37267M8-XXXSP M37267EE-XXXSP, M37267EESP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER oS eee (8) START/STOP Condition Detecting Condi- (9) Address Data Communication tions ‘There are two address data communication formats, namely, 7-bit The START/STOP condition detecting conditions are shown in Fig- addressing format and 10-bit addressing format. The respective ad- ure 43 and Table 6. Only when the 3 conditions of Table 5 are satis- dress communication formats is described below. fied, a START/STOP condition can be detected. © 7-bit addressing format To meet the 7-bit addressing format, set the 10BIT SAD bit of the Note: When a STOP condition is detected in the slave mode °C control register (address 00F 916) to *0.* The first 7-bit address (MST = 0), an interrupt request signal “IICIRQ” occurs to the data transmitted from the master is compared with the high-order CPU. 7-bit slave address stored in the I2C address register (address 00F716). At the time of this comparison, address comparison of the RBW bit of the I2C address register (address 00F716) is not 17777 SCL release time ~~~» made. For the data transmission format when the 7-bit addressing Sct —_su» format is selected, refer to Figure 44, (1) and (2). po ingen} Hold time : 10-bit addressing format Ce To meet the 10-bit addressing format, set the 10BIT SAD bit of the £---$0tUp Hold time (PC control register (address 00F 916) to “1.” An address compari- 7 firs SDA ——<— f ‘son Is made between the first-byte address data transmitted from (STOP concition) the master and the 7-bit slave address stored in the I?C address register (address 00F716). At the time of this comparison, an ad- Fig. 43. START condition/STOP condition detecting timing diagram dress comparison between the RBW bit of the I2C address regis- ter (address 00F 716) and the R/W bit which is the last bit of the Table 6, START condition/STOP condi ‘ fc address data transmitted from the master is made. In the 10-bit abe cond ConcBon detecting condone addressing mode, the F/W bit which is the last bit of the address data not only specifies the direction of communication for control 6-5 4s (26 cycles) <SCt release 1.0 us (4 cycles) <SCL release data but also is processed as an address data bit. 3.25 us (13 cycles) < Hold time Note: Absolute time at ¢ = 4 MHz. The value in parentheses de- notes the number of 9 cjcles. ee EN Ie 7 bits “0° 1toBbits 1 to8 bits (1) A master-transmitter transmits data to a slave-receiver Tits “1 1toB8bits 1 toB bits (2) A master-receiver receives data from a slave-transmitter 7bits “O° 8 bits 1108 bis 1to8 bits (3) A master-transmitter transmits data to a slave-receiver with a 10-bit address 7bits “0” 8bits 7 bits “TY TtoBbits 1 to Bbits (4) A master-receiver receives data from a slave-transmitter with a 10-bit address S : START condition P : STOP condition [1] From master to slave A: ACK bit RWW : Read/Write bit CO From slave to master ‘Sr: Restart condition Fig. 44. Address data communication format MITSUBISHI ae ELECTRIC 2-709

M37267M4-XXXSP, M37267M6-XXXSP, M37267M8-XXXSP M37267EE-XXXSP, M37267EESP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER When the first-byte address data matches the slave address, the @ «When all transmitted addresses are “0” (general call) AAS bit of the I2C status ragister (address 00F816) is set to “1.” After ‘ADO of the °C status register (address 00F816) is set to 1” and the second-byta address data is stored into the I2C data shift register an interrupt request signal occurs. (address 00F616), make an address comparison between the sec- “When the transmitted addresses match the address set in @ ‘ond-byte data and the slave address by software. When the address ASS of the °C status register (address 00F816) is set to “1” and data of the 2 bytes matches the slave address, set the RBW bit of the an interrupt request signal occurs. °C address register (address 00F716) to “1” by software. This pro- sin the cases other than the above cessing can match the 7-bit slave address and R/W data, which are ‘ADO and AAS of the I?C status register (address OOF 816) are received after a RESTART condition is detected, with the value of set to “0” and no interrupt request signal occurs. the I°C address register (address 00F 716). For the data transmission ® Set dummy data in the PC data shift register (address OOF 616). format when the 10-bit addressing format is selected, refer to Figure @ when receiving control data of more than 1 byte, repeat step @. 44, (3) and (4). ® When a STOP condition is detected, the communication ends. (10) Example of Master Transmission An example of master transmission in the standard clock mode, at the SCL frequency of 100 kHz and in the ACK retum mode is shown below. © Set a slave address in the high-order 7 bits of the IC address register (address 0OF716) and “0” in the RBW bit. @® Set the ACK retum mode and SCL = 100 kHz by setting “8516 in the IC clock control register (address OOFAt6). @ Set “1016" in the [°C status register (address 00F816) and hold the SCL at the “H” level. @ Set a communication enable status by setting “4816 in the I2C control register (address 00F 916). © Set the address data of the destination of transmission in the high- order 7 bits of the PC data shift register (address 00F616) and set “0” in the least significant bit. © Set “F016” in the PC status register (address 00F816) to generate a START condition. At this time, an SCL for 1 byte and an ACK clock automatically occurs. ® Set transmit data in the |2C data shift register (address OOF 616). At this time, an SCL and an ACK clock automatically occurs. @® When transmitting control data of more than 1 byte, repeat step © Set “Do16" in the [°C status register (address OOF 816). After this, . if ACK is not retumed oF transmission ends, a STOP condition occurs. (11) Example of Stave Reception An example of slave reception in the high-speed clock mode, at the SCL frequency of 400 kHz, in the ACK non-return mode and using the addressing format is shown below. @ Set a slave address in the high-order 7 bits of the 2C address register (address OOF 716) and *0” in the RBW bit. @ Set the no ACK clock mode and SCL = 400 kHz by setting “2516” in the °C clock control register (address OOFA16). @ Set “1016" in the I2C status register (address 00F816) and hold the SCL at the “H” level. @ Set a communication enable status by setting “4816” in the [°C control register (address 00F 916). © When a START condition is received, an address comparison is made. Mm 6249828 0025844 429 ° PR 2-710 ELECTRIC :

MITSUBISH! MICROCOMPUTERS M37267M4-XXXSP, M37267M6-XXXSP, M37267M8-XXXSP M37267EE-XXXSP, M37267EESP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER: Main clock Clock for display Data slicer osct osc2 Hsync Vsync clock oO oO O90 (Addresses 00D916, OODAi6) 7 oe pee (Address OOCF 6) | i : | eases CE Field identification Farsaaba 0002 = 16 00DEs are: f | Vertical position ES] resisters [ _paecosraemey | L__ espa psn : FES character size registers | nc contol cuit | — a=, | To ro | oy , circuit - RAM for dis ) | — “beste Fo € bits X 9) of (Address 0ODB16) x 192 Cations OIDOW, De) — | 7 a (Address 021016) se Titi | RG 8 our _oure}e~ mxour Data bus Fig. 46. Block diagram of CRT display control circuit Me 6249828 002e584t 271 =r

M37267M4-XXXSP, M37267M6-XXXSP, M37267M8-XXXSP M37267EE-XXXSP, M37267EESP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER Ss 7 ° 7 0 CRT control register Display mode register (Ce : adress 0G) (OM: address OOCEYe) Block 1 display mode *ocatoicks depeyon ‘specification bit (Note 1) 1: Alltblocks display on 0: CCD mode 1: OSD mode Block 1 display contro! bit 0: Block display off Block 2 display mode 1: Block 1 display on specification bit (Note 1) ‘Block 2 display contro! bit o eee 0: Block 2 play oft 1080 mode ‘

1 Block 2 display on Block 3 display mode

specification bit (Note 1) Block 3 display control bit 0: CCD mode 0 : Blook 3 display off 1: OSD mode 1: Block 3 display on Block 4 display mode Block 4 display contro bit ‘specification bit (Note 1) 0: Block 4 display off ‘0: CCD mode 11: Block 4 display on 1: OSD mode Display oscillation stop flag Display font specification bit 0: Oscillation stopped o:* at incphase, 1: Oscillation enabled “" at out-of-phase 1: *(@” atin-phase, Mask mode 2 control bit (Note 2) “()" at out-of-phase (0: Mask mode off (Refer to Figure 55) 1: Mask mode on Phase difference PIaOUT2 pin sich bt determination flag (Note 2) t0uT2 0: in-phase 1: Qut-of-phase Notes 1: lay Is controlled by logical ict (AND) between the tic a eck Seplny conta ot an oath None hepay con Bt Automatic solid space 2: Refer to (12) Mask Function for mask mode 2. 0: OFF 1:0N ‘Automatic solid space Fig. 47. Structure of CRT control register Tecognition code 0: 0916 1: 3916 Notes 1: Even if the display mode is switched during display, the display screen remains unchanged Until a rising (falling) of the next Vsvnc, 2: This flag is a read-only. The value to be read trom| the register is fixed regardless of bit 4. Fig. 48. Structure of display mode register — M@ 6249628 002584? 138 MM

M37267M4-XXXSP, M37267M6-XXXSP, M37267M8-XXXSP M37267EE-XXXSP, M37267EESP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER (2) Display Position Blocks are displayed in conformance with the following rules: The display positions of characters are specified in units called a _ @ When the display position is overlapped with another block “block.” There are 4 blocks, blocks 1 to 4. Up to $4 characters can be (Figure 49, (b)), a lower block number (1 to 4) is displayed on the displayed in each block (refer to (6) Memory for Display). front. The display position of each block can be set in both horizontal and @ When another block display position appears while one block is vertical directions by software, displayed, the block with a larger set value as the vertical display ‘The display position in the horizontal direction can be selected for all stait position is displayed. blocks in common from 128-step display positions in units of 4Tc --@ In the case of a block (block 1 or 2) for which “priority display” is (Tc = oscillating cycle for display) already set by the priority display control register, this block is ‘The display position in the vertical direction for each block can be displayed with top priority regardless of © and @ above (Figure selected from 512-step display positions in units of single scanning 49, (d)). line. @ inthe case both blocks are of ‘priority display’, they are displayed in conformance with rule of @. For the priority display function, refer to (13) Priority Function. (HR) : Bit of CVS, and Cvt-==--We--f---f od (@) Example when each block is separated (HR) H Brz01 vs, araova [ee (Block 3 is not displayed) (0) Example when block 3 overlaps with block 1 (HAY f Bitz of CVS, and Cv3-----.¥-----. | Blok? (@) Example when block 3 overlaps in process of block 1 (block 1 Is set to “no priomty display’) (HR) } (d) Example when block 3 overlaps in process of block 1 (block 1 is set to “priority display”) Note : CVX (X : 1 to 5) indicates the contents of vertical position registers. Fig. 49. Display position s MITSUBISHI 2-74 ELECTRIC

tails, refer to (12) CRT Output Pin Control. Vsync control 1 2 vertical display start positions. jitter. 2: Refer to (12) Mask Function. each step is one scanning line) as values “0116” to *7F16” in vertical register is shown in Figure 52. Figure 51. 7 0

; . MITSUBISHI MICROCOMPUTERS M37267M4-XXXSP, M37267M6-XXXSP, M37267M8-XXXSP M37267EE-XXXSP, M37267EESP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER (3) Character Size The size of characters to be displayed can be from § sizes for each _size in the horizontal direction can be selected by setting bit 2 of block. Use the character size register (addresses 000716 and 00D816) _—_ each character size register to “1.” When 1 scanning line is selected to seta character size. The character size of block 1 can be specified as the vertical size (minimum size), the phase difference determina- by using bits 2 to 0 of the character size register; the character size _ tion dieplay* is performed. Table 8 shows the relation between the of block 2 can be specified by using bits 6 to 4; the character size of __set values in the character size register and the character sizes. block 3 can be specified by using bits 2 to 0 in the character size ‘register 2; the character size of block 4 can be specified by using bits 6 to 4, Figure 53 shows the structure of the character size register. The character size can be selected from 3 sizes: minimum size, me- dium size and large size. Each character size is determined by the number of scanning lines in the height (vertical) direction and the oscillating cycle for display (Tc) in the width (horizontal) direction. ~ The minimum size consists of [1 scanning line] x {2Tc}; the medium size consists of [2 scanning lines] X [4Tc]; and the large size con- sists of (4 scanning lines] X [8Tc]. The medium and large 1/2 times z ° Character ice register 1 (CSt ; address 000716) ‘Block 1 character size selection bits (Note) mum} peat 0.00: Micimum size 001: Medum size 01 0: tage szo ont: 100; Fone sot "i 1.0.1: Medium size (1/2 in horizontal) um 110: Large size (1/2 in horizontal) 141: Domotet Block 2 charactor size selection bits (Note) (12 in horizontal) ponenr 00.0: Minimum size 001: Medurm size 010: Large size 014 100; } Bonatoet 1.01: Medium size (1/2 in horizontal) Large 11.0: Large size (1/2 in horizontal) 141: Dono et z o Character ie rite 2 (82: adress 900816) [Horizontal display (1/2 in horizontal) ‘Block 3 character size selection bits (Note) start position wepibo Py pciatend Fig. 54. Display start position of each character size (horizontal direction) 010: Lage sz0 O14: 100: fone eat 101 um size (1/2 in horizontal) 110: Large size (1/2 in horizontal) 441: Domotect “Block 4 character size selection bits (Note) tevebe 000: Minimum size 001: Medium size 010: Large size O14 400: }Donetset 10.1: Medium size (1/2 hodzonta 110: Lage ize (12 in horizontal 411:Dorot et Note : Reler to Table 8 for et values, Fig, 53. Structure of character size register M@® 6249828 0025850 722 = MITSUBISHI 2-716 oe MESES

Table 8. Relation between set values in character size register and character sizes Position is common to all blocks even when the character size varies with each block (refer to Figure 54). The phase difference determination function determines whether a ‘of the VsyNc control signal in the microcomputer is detected. ‘case where both the horizontal sync signal and the vertical syne signal Figure 55). sync signal untill a falling edge of the Vsync contro! signal (refer to the value of the display font specification bit. 1 dot in the in-phase field.

MITSUBISHI MICROCOMPUTERS. M37267M4-XXXSP, M37267M6-XXXSP, M37267M8-XXXSP M37267EE-XXXSP, M37267EESP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER: Both Hsync signal and Vsync signal are negative-polarity input Phase difference! Paulos Display font 5 fe LL | a [Sa tha oe (Odd-numbered) 4 Vsyne ral sind’ | (to i eed ee :ven-numbere Hi > rcrecon| ir phase ee iter i PY ents Lg inataso | otter | 2 | Sen _| oarnumbered) ita ee When using the phase difference determination flag, be sure to set bit 0 of the PWM mode register! (address 020A16) to “0.” Main dot b7 bs bS b4 b3 b2 bi bo MELLEL WEEE. 0 aa Ulla i“ i“ ms Di ills Blank area(font = “0016") 1 alice alien wmeteaame setae — | ope ETT font is dis 1d at out-of-phase. Bit 5 of the SsnAnSESnanmnaeny CA Vili Ze UMMM AME omeedeneae VA. MLA MALLE ALLL TIA

8 Wntelirnimasimeniitiies a Zs

B Cl A Po MH i“ (ea ‘om — Wa A Yi Under line area (font = 0016 or FF 16) bs ba bs b2 bi bo <———__ Rounding dots Character ROM font configuration diagram Note: The phase difference determination flag changes at a rising edge of the Vsync control signal (negative-polarity input) in the microcomputer. Fig. 55. Relation between phrase difference determination flag and display font M@@® 62494628 0025852 STS

M37267M4-XXXSP, M37267M6-XXXSP, M37267M8-XXXSP M37267EE-XXXSP, M37267EESP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER (5) Clock for Display As a clock for display to be used for CRT display, itis possible to select one of the following 3 types. 7 0 © Clock output from the data slicer Display clock selection register 1 ‘Main clock supplied from the XIN pin (CKS1 : address 00001) ‘Clock from the LC oscilator supplied from the pins OSC1 and OSC2. B , This clock for display can be selected for each block by the display bas pote) nt ex aetection clock selection register (addresses 000816, OODAt6). A variety of ssnerto character sizes can be obtained by combining character sizes with 100 4 ibn ener punvoln) locks for display. When selecting the clock from the LC oscillator as 00xx: LC oscillator a clock for display, set bits 7 and 6 of the mixing control register (OSC1, 08C2 pins) (address 021316) to “1” and “0,” respectively. Block 2 display clock selection When selecting the main clock, set the oscillation frequency to bits (Note) 8 MHz. br be pss He 10.00 : Data slicer clock 1.001: Main clock (Xin pin) 00x: LC oscilator (OSC1, OSC2 pins) 7 ° Display clock selection register 2 (CKS2 : address 0ODA16) Block 3 display clock selection bits (Note) tabentto 1000 : Data slicer clock 1.0.0 1 : Main clock (XIN pin) 00xx:LC oscillator (O8C1, OSC2 pins) Block 4 display clock selection bits (Note) reese 10.00: Data slicer clock 10.0 1 : Main clock (Xin pin) 00Xx: LC oscillator (OSC1, OSC2 pins) Note: Even if the clock for display is switched during display, the display screen remains unchanged untit a rising (falling) of the next VsvNc. Fig. 56. Structure of display clock selection register “MM 6249828 0025853 43) Mm , eaten ELECTRIC 2-719

M37267M4-XXXSP, M37267M6-XXXSP, M37267M8-XXXSP M37267EE-XXXSP, M37267EESP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER (6) Memory for Display ‘The CRT display ROM has a capacity of 3648 bytes. Since 19 bytes. There are 2 types of memory for display : CRT display ROM (ad- _are required for 1 character data, the ROM can stores up to 192 dresses 1000016 to 122FF16) used to store character dot data _kinds of characters. (masked) and CRT display RAM (addresses 0£0016 to OFE116) used Within the CRT display ROM area, data for main dot font of each to specify the colors and characters to be displayed. The following _character that is [vertical 8 dots] X {horizontal 8 dots} is stored at describes each type of display memory. addresses 1000X16 to 10BFX16 (where X = 0, 2, 4, 6, 8, A, C, E), data for rounding of each character that is [vertical 8 dots] X [hori- @ ROM for display (addresses 1000016 to 122FF1e) zontal 8 dots] is stored at 1000716 to 10BFY 16 (where Y = 1, 3, §, 7, ‘The CRT display ROM contains dot pattem data for characters tobe 9, B, D, F), data for part of each character that is [vertical 2 dots] x displayed. For characters stored in this ROM to be actually displayed, _—_ {horizontal 8 dots] is stored at addresses 1200Mi6 to 122FMie (where {tis necessary to specity them by writing the character code inherent M= 0,2, 4, 6, 8, A, C, E), and data for part of each character that is ‘to each character (code determined based on the addresses in the [vertical 2 dots] X [horizontal 8 dots] is stored at 1200N16 to 122FN16 CRT display ROM) into the CRT display RAM. The character code (where N= 1, 3, §, 7, 9, B, D, F), as shown in Figure §7. list is shown in Table 9, Character code [Fre F iT (whe ES st: ia (where n = "0016" to “BFi6”) ES SECC. SA HSEEES 3a { pllistisialils || (eee | | h ine I : . eT | hl a a al Address in Main dot font Dataindisplay Address in Rounding dot font Data in display display ROM ROM display ROM ROM 1000016+101exn16+018 [ | | BE | | | | to 1000016+101exnt6+t16 AZ TY [J] ccr : 1000016+10rexn:6+2:6 {| fi MT |] 2816 1000016+101exni6+313 GA | A] De 1000016+10rexni6-4:6{ | | || |] 1] oo 1000016+101exnie+518 YA | | (D216 10000:6+101exnie6ie | MN | | MM | | 446 1000016+101exnr8+710 AA | TT | | cone Se a Be 1000016+101exnver1e ZAZA | TT || core 1000016+101exnieAts | | | MM || 4416 1000016+1016xmi6+B16 WA FFie 10000:6+101exmerCrs| [| | | Tt TT | oo 1000016+101exnieDie AA | | | ME Ete roooorer1orexnmerEe | TTT TTT) oo 1000016+10exnie+Fis LAA || Bete 120001e+416xn16+016 0016 12000:6+4:6xnve+16 ZAZA | | | I Ett 1200016+416Xn16+216 0016 12000:6+416Xnie+316 VA, FF 16 :Set"1." Fig. 57. Display character stored data

7 MM 6249628 0025854 378

Table 9. Character code list (partially abbreviated) @ RAM for display (addresses 0£0016 to OFE116) dots dots dots tents of the CRT display RAM.

Table 10. Contents of CRT display RAM

M37267M4-XXXSP, M37267M6-XXXSP, M37267M8-XXXSP M37267EE-XXXSP, M37267EESP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER Blocks 1, 2, 3,4 {Character specification] 7 0 1st character : OE0016 to ‘34th character : OE2116 Character code Specify 192 characters ("0016" to “BFi6") (Block 2 ; addresses 0E4016 to 0E6116, block3 ; addresses 0E8016 to OEA116, block4 ; addresses 0EC016 to OEE1 16) [Attribute code specification] 7 ° 1st character : OF 0016 to ‘S4th character : OF 2116 Attribute code . R pin output Gpin output B pin output OUT? pin output Flash output Underline output Italic output OUT2 pin output (Block 2 ; addresses OF 4016 to OF 6116, block3 ; addresses OF 8016 to OFA116, block4 ; addresses OF C016 to OFE116) Fig. 58. Structure of CRT display RAM — M@ 6249828 0025857 087 MM

. MITSUBISHI MICROCOMPUTERS, M37267M4-XXXSP, M37267M6-XXXSP, M37267M8-XXXSP M37267EE-XXXSP, M37267EESP : SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER (7) Attribute Code Italic is formed by slanting the font stored in the display ROM to.the Regarding display colors, three color outputs, R, Gand B, are tumed _upper right. As shown in Figure 60 (c) and (d), when italic Is specified, on and off by controlling of the low-order 3 bits of the attribute code _the font overlaps in the right-adjacent character area. In the overlapped to display 8 color types for each character. This attribute code canbe _—_ area, the display color of the left-hand character has priority. The 1st set for each character, so 7 colors can be displayed. character and 34th character of each block cannot be displayed in ‘Whether the OUT pin outputs or notis switched by bit of the attribute italic, code. When the OUT! pin outputs, which of the character output or For flash, the flash period can be changed by bit 6 of the OUT control character area OUT! blank output is switched for each block by the > register. However, in the flashing status, the duty is fixed at 75%. OUT control register (address 021016) (refer to Figure 59). However, The on/off of OUT1 and OUT? flash can be selected by bits 4 and 5, ‘when the solid space auto-generating function is turned on, the respectively. character area blank output may be selected regardiess of the above An underline is output at the 12th dot in the vertical direction in the bit. For the solid space auto-generating function, refer to (9) Automatic + CCD mode. Underline specified only in the CCD mode. Solid Space Function. Flash and italic can be specified in both modes. ‘Whether OUT2 pin outputs or not is switched by bit 7 of the attribute. Figure 61 shows the structure of the attribute code and Figure 62 code. When the OUT2 pin outputs, the same waveform as the _shows the structure of the OUT control register. character area OUT{ blank output is output. Bits 4 to 6 of the attribute code control turing on and off flash, _underiine and italic respectively. Figure 60 shows an example of italic and underline display in the case where “A” Is displayed with 7X 9 dots. i Rae Po (a) x No OUT1 output | our} Hl OUTI output A,G,B L Character output | OUT H n Lt H OUT1 output es oo @) Characterarea | GB Lb ‘OUT! blank output} OUT1 a 7 7 on a es om A ry A s x A Wy, s 7) x Z2) MMA a 2) °% Fig. 59 Switch between character output and character area blank output - MM 6249828 0025858 113 MM 2-724 oe ERS

M37267M4-XXXSP, M37267M6-XXXSP, M37267M8-XXXSP M37267EE-XXXSP, M37267EESP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER ON SCREEN DISPLAY CONTROLLER Po occeeen se "me oeea aaeee aoe @| a. © aann8 5 a 25 & amEEn as §| one @ a2 8 a: & PECreee acccnn CoCo} Coco} PEreeee (@) Ordinary (b) Underline Co occenen) hs ae amen. Lech Hagen | eel a nem = s228 aes = ascn8 [ em | [ iam | | om | i ome | Poco | ooo | Peco Po Coe CeCeerery) S2eeeee8 {c) Italic (@) Italic, underline Fig. 60. Example of attribute display (in CCD mode) _W@@ 6249828 0025859 5ST

4 MITSUBISHI 2-705

M37267M4-XXXSP, M37267M6-XXXSP, M37267M8-XXXSP M37267EE-XXXSP, M37267EESP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER eee 7 ° 7 ° OUT control register “Bock CT TEL TTT] eure caarete 2101) ‘fadresses oF 001 to OF2116) COUT: pin contro bit book 1) i 0: Character. {addres OF 4018 to OF611e) 0: Characog capt : (addresses OF 8016 to OFA116) Blocks OUT? pin control bit (block 2) : (addresses OFCO16 to OFE116) 0: Character output 1: Blank output R pin output ai : (0: No character output ‘OUT1 pin contro! bit (block 3) 1: Character output 0: Character output 1: Blank output G pin output 0: No charactor output ‘OUTt pin control bit (block 4) 1: Character output ° 3 Sree curs ouput 8 pin output OUT? output flash 0: No character output specification bit 1: Character output 0: No flash 1: Flash OUT! pin output 0: No output peckiborverieal 1: Output 0: No flash Flash output . 1: Flash 0: No flash Flash period selection bit 1: Flash 0: About 2 times/s(Vsyno/32) 1: About 1 time/s(Vsync/64) Undertine output too" ; 0: No underline output Fix this bit to “0. 1: Underline output . hale output Fig. 62. Structure of OUT control register 0: Ordinary output

1 Italie output

0: No output : 1: Output Fig. 61. Structure of attribute code M@ 6249828 0025860 67) sm ae ERE

format. ‘example of combined display of italic font and ordinary font. Table 11. Italic display correspondence table Color (blue) are not mixed. | inblank area. color (blue) are not mixed. | in blank area.

3 EEX RSS ESS E2804

the character background. | backgrounds not displayed, | the character background. | background is not displayed. background is not displayed. background is not displayed. Notes 1: The portion “B" in which character dots are displayed is not mixed with any TV video signal. 2: The wavy-tined arrows in the Table denote video signals. 3: For background color and color switching, refer to (10) Character background coloring function.

Table 11. Italic display correspondence table (continued) the character background. in blank area. the character background. in blank area. Notes 1: The portion “8” in which character dots are displayed is not mixed with any TV video signal. 2: The wavy-lined arrows in the Table denote video signals.

M37267M4-XXXSP, M37267M6-XXXSP, M37267M8-XXXSP M37267EE-XXXSP, M37267EESP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER ss (8) Multiline Display (9) Automatic Solid Space Function ‘The M37267M6-XXXSP can ordinarily display 4 lines on the CRT This function generates automatically the solid space (OUT! blank screen by displaying 4 blocks at different vertical positions. in addi- output) of the character area in CCD mode, tion, it can display up to 16 lines by using CRT interrupts. This function is tumed on and off by bit 6 of the display mode register A CRT Interrupt request occurs at the point at which display of each (address 00CF1e). Whether or not the OUT! blank is output to the block has been completed. In other words, when a scanning line character area is controlled by the character code. A recognition reaches the point of the display position (specified by the vertical character code (“0916" or “3916”) for auto-generating can be selected Position registers) of a certain block, the character display of that by bit7of the display mode register. block starts, and an interrupt occurs at the point at which the scan- Accordingly, OUT 1 blank is output the following conditions: ning line exceeds the block. + When bit 3 of the attribute code is set to “1” (OUT! output). + When the left and right character codes including the character Note: A CRT interrupt does not occur at the end of display when code to be displayed are not “3916” ("0916") the block is not displayed, In other words, if a block is set to ‘When using this function, select “blank output” by the OUT control off display with the display control bit of the CRT control reg- register. ister (address OOCEt6), a CRT interrupt request does not Note: Blank output is disabled on the left side of the 1st character ‘occur (refer to Figure 64). and on the right side of the 34th character of each block. __|., CRT interrupt request” Block 1 (on display) |_| _. “CRT interrupt request” _{.., oRTntemptronuesr | [—~Bicck aon asnayy |_|, scr terug roqueer Block 1° (on display) |... CRT interrupt request” | ["" “Block f'(off display) {|__| ., No*CRT interupt request” -f.y “OR Tintorupt request | [Block 2 (otf dgplay) |_| ., No*CRT inter request (On display (CRT interrupt request occurs at the end of block Off display (CRT interrupt request does not occur at the end display) of block display) Fig. 64. Timing of CRT interrupt request When setting the character code “2016” as the character A, “2116” as the character B. (Display memory) J Character to be displayed . : 16 16: 16: 16: 16! 16: 16 16; 16! Ee ae a ee) (Display screen) I tst ‘nd t ‘4th character character (No blank oufput character Fig. 65 Display screen example of automatic solid space — iM 6249824 0025863 380 x i ae ene 2-729

M37267M4-XXXSP, M37267M6-XXXSP, M37267M8-XXXSP M37267EE-XXXSP, M37267EESP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER (10) Character Background Coloring Function Character background coloring can be performed for each screen in the display area of each block. 8-color coloring is possible by setting z 0 bits 2 to 0 of the background color control register (address OODB16). Background color contol register ‘When selecting "black" for a character background color, set bits 2 to (BGG: address 000818) O each to “0.” Character back outpul In addition, a color switching function, which can switch between a pbrier fr lana character background color and a character color for each block, is 0: No output available. 1: Output This function permits coloring for a character background color for each character. Whether or not to perform coloring switching can be cantolbi (eran controlled by bits 7 to 4 of the background color control register. 0: No output 1: Output Character background output control bit (Blue) 0: No output . 1: Output Block 1 coloring switch bit 0: No switch 1: Switch Block 2 coloring switch bit 0: No switch 1: Switch Block 3 coloring switch bit 0 : No switch 1: Switeh Block 4 coloring switch bit 0 : No switch 1: Switch Fig. 66. Structure of background color control register RPP KUN mr Re aaa a | ROL Od ll Me weeq tel rand Res Gee, a Ee Secs = iii Rod bso Resecegess 8h Po Ax Petetetets 5h 4 bss Meee | eee <-> x igenesscecereregk , F % Rs BS Noswitch Switch IRR | kx bot Witetetete oh ie & i] fecenececee: | Se) eed So TTT etetetetet Mel | ROOOOCOOCT TTT Tl x. {11 oven BQ Red (The color of character “A” is set to red, "B” to cyan, and character background to blue.) Fig. 67. Display example of coloring switch function MITSUBISHL 2-730 ELECTRIC

M37267M4-XXXSP, M37267M6-XXXSP, M37267M8-XXXSP M37267EE-XXXSP, M37267EESP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER eines (11) Mixing Function Color signats (MXR, MXG, MXB, and MXOUT) input from outside 7 A and color signals (R, G, B, and OUT1) generated internally can be Mixing control register ORed and output as a mixed signal. [TL Te TTT (MIX : address 021316) ‘The mixing control register (address 021316) can be used to turn on L | and off the mixing of the extemal and intemal color signals, and also Mixing output control bits (Note 1) to specify which of the two signals has priority when they overlap. 7D O° No intemal or external ‘The MXB and MXOUT pins can also be used as external input pins. * color signal output for timer 2 and timer 3. © 1: Internal color signal output Examples of displays generated with an intemal color signal for the 1 0: External color signal output letter “I” and an extemal color signal for the letter “O" are shown in m4 ae onal surat extemal Figure 69. -Overlapped part control bits (Note 2) ba b3 0 0: No priority given to internal and extemal color signals of overlapped part 0 1: Extomal color signal of ‘overlapped part has priority 1. 0: Intemal color signal of ‘overlapped part has priority 1. 1 :No intemal or external color signal output for overapped part ix this it to “0.” ‘OSC oscilation circuit selection bits | b7 bé 0 0: 32kHz oscillation 1 0: LC oscillation Ot: 10: } Not available Notes 1 : OUT2 pin output is output regardless of set value. 2:: This bits ineffective for OUT2 pin output. Fig. 68. Structure of mixing control register Display when neither an external Display an internal color signal Display when an external color nor an intemal color signal has hhas priority signal has priority Priority Note : The letter “I” Is displayed with an intemal color signal, the letter “O” is displayed with an extemal color signal. Fig. 69. Example of display provided by mixing function —— MH 6249828 0025865 153 MM tne ELECTRIC 2-731

: M37267M4-XXXSP, M37267M6-XXXSP, M37267M8-XXXSP M37267EE-XXXSP, M37267EESP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER: (12) CRT Output Pin Control ‘The CRT output pins R, G, B, and OUT? can also function as ports 7 ° P52, PSs, P54 and PSs. Set the corresponding bit of the port PS di- CAT output polarity register rection register (address 00CB16) to “0” to specify these pins as CRT {CO : address 021216) output pins, or set it to "1" to specify it as a general-purpose port PS pins. The OUT2 can also function as port P10. Set bit 7 of the CRT FVG/B output polarity switch bit control register (address 0OCE16) to “0” to specify it as port P10, set 0 : Positive polarity output ___ ito “1" to specity it as OUT2 pin. 1: Negative polarity output The input polarity of the HsyNc, VsyNc, MXR, MXG, MXB, and MXOUT signals can be specified with the bits of the CRT input polar- OUT! output polarity switch bit ity register (address 021116). The input polarity of signals HSYNc and 0 : Positive polarity output ‘\\VsyNc and output polarity of signals A, G, B, OUT1 and OUT2 can 1: Negative polarity output be specified with the bits of the CRT output polarity register (address 021216) . Set a bit to “0” to specify positive polarity; set it to “1” to OUT2 output polarity switch bit specify negative polarity. 0: Posttve polanty ouput The structure of the CRT output polarity register is shown in Figure logative polarity output 70 and that of the CRT input polarity register Is shown in Figure 71. output ewitching bt 0: R output (13) Raster Coloring Function 11: Raster coloring output ‘An entire screen (raster) can be colored by setting the bits 7 to 0 of the CRT output polarity register. Since each of the R, G, B, OUT1, G output switching bit and OUT2 pins can be switched to raster coloring output, 7 raster ‘Or Gouput colors can be obtained. 1 : Raster coloring output If the OUT1 pin has been set to raster coloring output, a raster color- ing signal is always output during 1 horizontal scanning period. This B output switching bit + setting is necessary for erasing a background TV image. 0: B output If the R, G, and B pins have been set to output, a raster coloring 1: Raster coloring output signal is output in the part except a no-raster colored character (in OUT! output switch bit Figure 72, a character “O") during 1 horizontal scanning period. This 0: OUT! output ensures that character colors are not mixed with the raster color. 1: Raster coloring output The raster colorling output are not mixed with the character output ‘and with the blank output from the OUT! pin. However, the raster oe coloring output is mixed with the blank output from the OUT2 pin. 1 : Raster coloring output ‘An example in which a magenta character “I” and a red character “O" —— are displayed with blue raster coloring is shown in Figure 72. Fig. 70. Structure of CRT output polarity register z ) TLD. Loo T Lo] TT] carpet pay rp “RED : UV “BLUE Hsync input polarity switch bit A UY, \\ VW » Verne input polarity switch bit Hee MXOUT input polarity switch bit i ri rn 1 ni : Si R ‘ Pitt across Fix these bits to "0." as — Yor e—-farw 0 : Positive active edge input H H 1: Negative active edge input ont [| Frsvne, Vern wavetomm exampie | eee polarity | VSYNC_L polarity Fig. 71. Structure of CRT input polarity register (MM 6249828 O0258bb OFT Ml sre Patan

M37267M4-XXXSP, M37267M6-XXXSP, M37267M8-XXXSP M37267EE-XXXSP, M37267EESP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER SU aan (14) Mask Function ‘Tha M37267M6-XXXSP can set a display disable area by masking the display area. However, this mask function is ineffective for the z ° ‘extemal color signals (refer to (11) Mixing Function) and the blocks Mask mode register 1 with priority display (refer to (15) Priority Display Function) of raster (MM1 : address 00DC16) coloring (refer to (13) Raster Coloring Function). © Mask mode 1 In this mode, when the count value of the horizontal syne signal . (Hsync) matches the value sat in the mask mode register 1, a poation it teak mode t quste) ‘mask is set. At the display end position of the masked block, the mask is reset. It follows that 1 display block is masked. However, when another block is displayed on the next scanning line, the 7 o mask is not reset even if the display of a masked block ends. A br reser 200b10) mask set position can be set for each line by a total of 9 bits including . the mask mode register 1 (address 00DC16) and bit 4 of the vertical Position register 5 (address 000616). When this function is not used, ‘set the mask set position to a larger value than the number of lines Mask reset position in mask of the TV set. mode 2 (Note) @ Mask mode 2 This mode is started by setting bit 6 of the CRT control register Note: Set values except “0016.” {address 00CEte) to “1”. In this mode, a mask is set at the timing of the vertical sync signal (Vsyvc) and the mask is reset when the Count value of the Hsvnc signal matches the value setin the mask F573. Siructure of mask mode registers mode register 2 (address 00DD'6). Unlike mask mode 1, the entire . display up to the mask reset position is masked. This mask reset position is set by the mask mode register 2. Fig. 74 shows a display in the case where the value of the mask mode register 2is satin the procass of block 4 and the value of the mask mode register 1 is set in the process of block 3. ‘A smooth Rollup style and scrolling display in the text mode are Performed by the mask function and by rewriting the value of the vertical position register with a Vsvnc interrupt. _M@ 6249828 0025867 T2b a evens 2-733

M37267M4-XXXSP, M37267M6-XXXSP, M37267M8-XXXSP . M37267EE-XXXSP, M37267EESP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER <— Set mask mode 2 Mask cvs M2 G <— Nodisplay <— Display cove [ob ™ cvs Mt ooo <— Display Ys <— No display i Mask 1 <— Reset mask mode 1 ov [= - ™ Notes 1: CVX (X = 1 to 4): Indicates the contents of vertical position register X. 2: MMY (Y = 1 or 2): Indicates the contents of mask mode register Y. 3: The mask function is ineffective for priority-display blocks. Fig. 74, Mask position Mi 6249828 0025668 Ibe a

MITSUBISHI MICROCOMPUTERS, M37267M4-XXXSP, M37267M6-XXXSP, M37267M8-XXXSP M37267EE-XXXSP, M37267EESP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER (15) Priority Display Function For blocks 1 and 2, there is a priority display function which can display these blocks with higher priority than blocks 3 and 4. This function is 7 ° made effective by setting bits 1 and 0 of the priority display control Priority display control register register (address 00D016) to “1.” When the vertical display start (PC : address 00D016) postion for blocks 8 and 4 comes while blocks 1 and 2 are displayed, ; display of blocks 3 and 4 is not started. The blocks being displayed Block neety oan bit with priority cannot be masked. 1: Priority ‘Oo play y A CRT interrupt request for blocks 1 and 2 is disabled by setting bits 2 and bit 3 ofthe priority display control register to “1”. Blok 2 ry py cord Parform setting as follows by using bits 3 to 0 of the priority display : rity display ater 1: Priority display @Biocks 3 and 4 ara processed with multiline display by using a Block {interrupt request CRT interrupt as CCD caption display. contro! bit @Set blocks 1 and 2 to “priority display” and “no CRT interrupt request” 0: Intorupt roquost ‘as channel selection display. The channel selection display for a 1+ No interrupt request maximum of 2 lines is processed. Block 2 interrupt request With the above settings of © and @, both caption display and control bit channel selection control display can be simultaneously performed. ¢ : Interrupt request A + No interrupt request When blocks 1 and 2 are set to “priority display”, set the interrupt request control bit to ‘no CRT interrupt request.” Figure 76 shows an example of screen display using the priority . Sisplay function. Fig. 75. Structure of priority display control register

12345 Bons

eR BE ---> car interrupt request ble we > car interrupt request disabled peo FY Block E> GT interrupt request

12345 Bra

<---> CRT interrupt request ---+» CRT interrupt request 1234 5 Bexs ----> CRT interrupt request 123.45 sexs ----> CRT interrupt request | No priority display block Priority display block Fig. 76. Simultaneous display example —M@ 6249828 0025869 679 —

MITSUBISHI MICROCOMPUTERS: M37267M4-XXXSP, M37267M6-XXXSP, M37267M8-XXXSP M37267EE-XXXSP, M37267EESP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER ee INTERRUPT INTERVAL DETERMINATION the interval ofa positive polarity (rising transition) ; when the bit is. FUNCTION set to “1,” determination is made of the interval of a negative po- ‘The M37267M6-XXXSP incorporates an interrupt interval determi- laxity (falling transition) Nation clrcult. This interrupt interval determination circuit has an 8-bit _ 4, The reference clock is selected by using bit 1 of the interrupt inter- binary up counter as shown in Figure 77. Using this counter, it deter- val determination controt register. When the bit is cleared to “0,” a mines an interval of a pulse width on the INT or INT2 (refer to Fig- ‘32ys clock is selected ; when the bitis set to “,” a 16s clock is ure 79), selected (based on an oscillation frequency of @MHZzin either case), The following describes how the interrupt interval is determined. 5. Simultaneously when the input pulse of the specified polarity 1. The determination mode is selected by using bit 5 of the interrupt (rising or falling transition) occurs on the INT1 pin (or INT2 pin), interval determination control register (address OOEF 1e). When this the 8-bit binary up counter starts counting up with the selected bit is set to “0,” the interrupt interval determination mode is se- reference clock (32us or 161s). lected; when the bit is set to “1,” the pulse width determination _6. Simultaneously with the next input pulse, the value of the 8-bit mode is selected. binary up counter is loaded into the interrupt interval determina- 2. The interrupt input to be determined (INT1 input or INT2 input) is tion register (address OOEE'6) and the counter is immediately re- selected by using bit 2 in the interrupt interval determination con- set ("0016"). The reference clock is input in succession even after trol register (address OOEF 16). When this bit is cleared to “0,” the the counter is reset, and the counter restarts counting up from INT! input is selected ; when the bit is set to “1,” the INT2 input is “oor”, selected. 7. When count value “FE16” js reached, the 8-bit binary up counter 3. When the INT1 input is to be determined, the polarity is selected stops counting. Then, simultaneously when the next reference by using bit 3 of the interrupt interval determination control clock is input, the counter sets value “FF 16" to the interrupt inter- register ; when the INT2 input is to be determined, the polarity val determination register. The reference clock is generated by selected by using bit 4 of the interrupt interval determination setting bit 0 of the PWM mode register 1 to °0.” control register. When the relevant bit is cleared to “0,” determination is made of M@ 6249628 0025870 S10

MITSUBISHI MICROCOMPUTERS, M37267M4-XXXSP, M37267M6-XXXSP, M37267M8-XXXSP M37267EE-XXXSP, M37267EESP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER 16ps cow Ser RE: REo INT2 (Note) 8 RE2 (Address OOEE16) >t ° bck cobs Se a :«ata bus RE : Interrupt interval determination control register Note: The pulse width of external interrupt INT1 and INT2 needs 5 or more machine cycles. Fig. 77, Block diagram of interrupt interval determination circult 7 oO Interrupt interval determination INT1 oF 2 input control register (RE : address OOEF 1) REs RE: }Count interval H H {Interrupt interval determination 0 0 <> H

1 Operating 104 H <—, :

‘Reference clock selection bit . (at (in) = 8MHz) RE; : Bit (| = 3, 4) of interrupt interval determination tiie control register (address OOEF 6) yrnal interrupt input pin selection bit " rs n ‘0: INT? input Fig. 79. Setting value of interrpt interval determination control register 1: INT2 input and measuring interval 'INT1 pin input polarity switch bit 0 : Positive polarity input 1: Negative polarity input ‘INT2 pin input polarity switch bit 0 : Positive polarity input 1: Negative polarity input ‘Interrupt interval determination mode ‘switch bit 0: Interrupt interval determination mode 1: Pulse width determination mode Fig. 78. Structure of interrupt interval determination control register MM 6249428 0025871 457 ae ELECTRIC 2-737

M37267M4-XXXSP, M37267M6-XXXSP, M37267M8-XXXSP M37267EE-XXXSP, M37267EESP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER RESET CIRCUIT ‘The M37267M6-XXXSP is reset according to the sequence shown Poweron in Figure 81. It starts the program from the address formed by using to the content of address FFFF16 as the high-order address and the i AM45V content of the address FFFEt6 as the low-order address, when the Power source voltage 0 V v3 RESET pin is held at “L" level for 2 ys or more while the power source 14 voltage is 5 V + 10 % and the oscillation of a quartz-crystal oscillator * - ba ‘oF a ceramic resonator is stable and then returned to “H" level. The Reset input votage 0 V TO internal state of microcomputer at reset are shown in Figure 82. ‘An example of the reset circuit is shown in Figure 80. ‘The reset input voltage must be kept 0.9 V or less until the power $ ‘source voltage surpasses 4.5 V. 2 ice = RESET —~ RESET ohn | vss M37267M6-XXXSP Fig. 80. Example of reset circuit -_ | intemal RESET ee Address K_2 X [7 Xor. SXo1.s-Xor, SXFFFEX FFF AR Reset address from the vector table Data x2} K_? X_? XADLX ADH) Notes 1 : (Xin) and {(9) are in the relation : (Xin) = 2+ (6). Gock eyo (Note 3) 2: A question mark (?) indicates an undefined state that ‘depends on the previous state. ‘3: Immediately ator a reset, timer 3 and timer 4 are ‘connected in hardware. At this time, "FF1e”is set in timer 3 and °0716" is set to timer 4. Timer 3 counts down with f(Xin)/16, and reset state is released by the timer 4 . overflow signal. Fig. 81. Reset sequence MM 62498626 0025872 393 Ae 2-738 ELECTRIC

. MITSUBISHI MICROCOMPUTERS M37267M4-XXXSP, M37267M6-XXXSP, M37267M8-XXXSP M37267EE-XXXSP, M37267EESP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER OO Address Contents of register Address Contents of register Port PO direction register (00116) (nteruptinterval determination contol regster (QOEF 16) Por PY direction register {00C316) Timor + (00F O16) Port P2 direction register (00C516) Timer 2 (00F 116) Port P3 direction register (00c716) Timer 3 (00F216) Port P4 direction register (00ca16) (“0016 Timer (00F316) Port PS direction register (Q0CBi6) ‘Timer mode register 1 (00F 416) CRT control register (00CE:6) Timer mode register 2 (00F516) Display mode register (00CF re) RC address register (OOF 716) Priority display control register (00D016) FC status register (00F 816) Horizontal position register (00D116) C control register (00F 916) Vertical position register 5 (00D618) °C clock control register (O0FAe) Character size register 1 (000716) CPU mode register (00FB16) ‘Character size register 2 (00D81e) Interrupt request register 1 (00F C16) Display clock selection register1 (00D916) Interrupt request register 2 (OOFD16) Display clock selection register (Q0DAx6) Interrupt control register 1 (00F E16) Background color control register. (QODB1e) Interrupt control register 2 (OOFF1e) [0016 J Data slicer control register 1 (Q0DE 16) PWM mode register 1 (020A6) Data slicer control register 2 (00DF 16) PWM mode register 2 (020816) ‘Caption positon register (00E016) Timers (020C16) Start bit position register (00E116) Timer 6 (02006) ("_FFis] Window register (00E216) ‘Timer 3 courn select register (020F 16) (0016) ‘Syne slice register (00E316) [0016] Our controt register (021016) Data register 1 (00E416) CRT input polarity register (021116) Data register 2 (Q0ES16) CRT output control register (021216) (Clock run-in register 1 (00E616) ‘Mixing control register (021316) ‘Clock run-in register 2 {00E716) AD control register 2 (021416) Clockd run-in detect register 1 (00E816) Processor status register (PS) Clockd run-in detect register 2 (00E916) Program counter (PCH) ‘Sync pulse counter register (QOEAte) (Per) ‘Serial VO mode register (Q0EB16) ‘AD control register 1 (00ED16) Note : The contents of all other registers and RAM are undefined at reset, so set their initial values. [ : Undetinea Bd) : Unused bit Fig. 82. Internal state of microcomputer at reset WM 6249828 0025873 2cT | ae ELECTRIC 2-739

M37267M4-XXXSP, M37267M6-XXXSP, M37267M8-XXXSP M37267EE-XXXSP, M37267EESP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER Ports POs, P10, P15—P17, P2, P30, P31 r—] > |) al e (CMOS3 output y © Ports P0s, P10, P1s-P1: Data bus: Port latch | P2, P30, P31 <J | > Note: Each port is also used as below: P10: OUT2 P17: SiN <} P24-P2s : AD3-AD1 Ports POo-P02, P04-PO7 De N-channel open-drain output PLL O Renee finpoeee Data bus Note: Each port is also used as below: | rea: rerr [Cd | Ports P11-P14 vad [ _ Nechannel open-drain ouput ene 0 Romer Data bus | > Note: Each port is also used as below: <4 P12: SCL2 P13: SDA1 P14: SDA2 Fig. 83. V0 pin block diagram (1) M@@ 6249428 0025874 bb mm

M37267M4-XXXSP, M37267M6-XXXSP, M37267M8-XXXSP M37267EE-XXXSP, M37267EESP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER e———— Sour, Scux

4 N-channel open-drain output

PL ° so Se Data bus | > 1 Note: Each pin is also used as below: Sout : Pas Scuk : Pas qj Hsync, Vsvnc Schmidt input R,G,B, OUT! CMOS output Internal circuit HsyNec, Vsync — Ports Pa4o-P4s Internal ~ R,G,B, OUT! Note: Each pin is also used as if ~~ below: RR: P52 Data bus Ports P4o-P4s eee ; B: P54 Note: Each portis also used as below: ‘OUT! : PBs P40 : MXP/ADS P41: INT2/MXG Pao : TIMZ/MXB Ps : TIM3/MXOUT 4a: INT Fig. 84. 1/0 pin block diagram (2) M@® 6249828 0025875 OT? . SS eM 2-71

M37267M4-XXXSP, M37267M6-XXXSP, M37267M8-XXXSP M37267EE-XXXSP, M37267EESP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER i CLOCK GENERATING CIRCUIT (3) Low-Speed Mode The M37267M6-XXXSP has 2 built-in oscillation-circults. An oscila-_If the intemal clock is generated from the sub-clock (XCIN), a low tion circuit can be formad by connecting a resonator between XIN _power consumption operation can be realized by stopping only the and XoUT (XeIN and Xcour). Use the circuit constants in accordance main clock Xin. To stop the main clock, set bit 6 (CM) of the CPU with the resonator manufacturer's recommended values. No exter. mode register (00FB16) to “1.” When the main clock Xin is restarted, nal resistor is needed between XIN and Xourt since a feed-back re. _the program must allow enough time to for oscillation to stabilize. sistor exists on-chip. However, an external feed-back resistor Is Note that in low-power-consumption mode the XciN-XCOUT drivabilty neaded between XCIN and Xcour. When using XciN-XCOUT as sub- can be reduced, allowing even lower power consumption (60,8 with clock, clear bits 7 and 6 of the mixing control register to “0.” To sup-_f (CIN) = S2kHz). To reduce the XciN-XcouT drivabilty, clear bit 5 ply a clock signal externally, input it to the Xin (XCIN) pin and make (CMs) of the CPU mode register (00FB16) to °0.” At reset, this bit is. the Xour (XcouT) pin open. set to “1" and strong drivabllity Is selected to help the oscillation to After reset has completed, the intemal clock ¢is half the frequency of ‘start. When an STP instruction is executed, set this bit to “1” by soft- Xin, Immediately after poweron, both the Xin and XcIN clock start _ware before executing. ‘oscillating. To set the internal clock ¢ to low-speed operation mode, set bit7 of the CPU mode register (address OOF B16) to “1.” % tulle dock peneratng circuit is shown in Figure 56. When the Xom__Xoour__Xm_Xour STP instruction is executed, the intemal clock ¢ stops at “H" level. At 4 the same time, timers 3 and 4 are connectad in hardware and “FF 16” RB Spy is set in the timer 3, “0716” is sot in the timer 4. Select {(XIN)/16 or Oo oO {(XcIN)/16 as the timer 3 count source (set both bit 0 of the timer mode register 2 and bit 0 at address 020F 6 to “0” before the execu- ae aed ca are tion of the STP instruction). And besides, set the timer 3 and timer 4 interrupt enable bits to disabled ("0") before execution of the STP instruction. The oscillator restarts when extemal interruptis accepted, Fig. 85. Caramic resonator circuit example however, the intemal clock ¢ keeps its “H” level until timer 4 over- flows. Because this allows time for oscillation stabilizing when a ce- ramic resonator or a quartz-crystal oscillator is used. (2) Wait mode the “H” level but the oscillator continues running. This walt state is Xcw__Xcour_Xww__Xour reloased at reset or when an interrupt is accepted (Note). Since the cscillator does not stop, the next instruction can be executed at once. Open Open Note: In the wait mode, the following interrupts are invalid. External oscillation External oscillation (1) Vswnc interrupt circuit or extemal circuit (2) CRT interrupt pulse (3) Timers 1 and 2 interrupt using P4s/TIM2/MXB pin input as Veo Vee count source ves LA LA ves SUL (4) Timer 3 interrupt using P4a/TIM3/MXOUT pin input as count source Fig. 86. Extemal clock input circuit example (6) Data slicer interrupt (6) Multi-master I?C-BUS interface interrupt (7) X1n/4096 interrupt (8) Allimer interrupts using (X1n)/2 or (XcIn)/2 as count source (9) All timer interrupts using f(Xin)/4096 or f(XCIN)/4096 as count source ME 6249828 002587b 739 oan 2-742 ELECTRIC

M37267M4-XXXSP, M37267M6-XXXSP, M37267M8-XXXSP M37267EE-XXXSP, M37267EESP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER eee Xon Xcour fe) O DB, CP ‘OSC scillation circult J0- Selection bits (Notes 1.4 * Timer 3 count Timer 4 count Xn Xour stop bit (Notes 1, 2) Stop bit (Notes 1, 2) [refer |} p “O° Timer 3 intemal system clock kon bi solaction bi (Notes 1,3) ‘count source selection bit (Notes 1, 2) {| Main clock (Xin-Xour) stop bit (Notes 1, 3) (intemal clock) Internal system clock selection bit (Notes 1, 3) Cf Reset sTPinstruction | WT an STP instruction Ct CP Interrupt disable flag | . Interrupt request Notes 1: The value at reset is “0.” 2: Refer to the structure of timer mode register 2. 3: Refer to the structure of CPU mode register (next page). 4; Refer to the structure of mixing control register. Fig. 87. Clock generating circuit block diagram | MM 6249828 0025877 975 one oor

M37267M4-XXXSP, M37267M6-XXXSP, M37267M8-XXXSP M37267EE-XXXSP, M37267EESP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER WIT instruction STP instruction @MHz oscitiating = \\ gg 8MHz oscillating §—\\\\ > atte cscilaing 82kH2z oscillating bea Sopped Timer operating —§ /————— Ko)=4MH2 = ——\\_ $s stopped (1H) Interupt Interrupt (Note 1) Extemal INT, [Sec | [ extemat vt or SV/O interrupt M7 =0 CM7=1 a WIT instruction ‘STP instruction ae posers ——— 8MH2 oscillating §—\\\\ >} 8MHz stopped $s stopped (H") 82kHz oscillating *— 82kHz stopped (Note 3) Interrupt Interrupt (Note 2) CMs =0 ‘The program must allow time for 8MHz CMe =1 ‘oscillation to stabilize MHz stopped WIT instruction STP instruction ‘32kHz oscillating < 8MHz stopped ~ ‘8MHz stopped @ is stopped ("H") 32kHz oscillating 32kHz stopped Timer operating §—§_§ / > (9) = tekHz |... ¢= stopped ("H") (Note 3) Interrupt Interrupt (Note 2) CPU mode register (Address : OOFBi6) ‘CMs : Main clock (Xin-Xour) stop bit 0: Oscillating 1: Stopped ‘CM : Intemal system clock selection bit 0: Xin-Xour selected (high-speed mode) 1: Xein-Xcour selected (low-speed mode) The example assumes that 8 MH2 is being applied to the Xin pin and 32 kHz to the Xan pin. The ¢ indicates the intemal clock. Notes 1: When the STP state is ended, a delay of approximately 8ms is automatically generated by timer 3 and timer 4, 2: The delay after the STP state ends is approximately 2s. ‘3: When the intemal clock ¢ divided by 8 is used as the timer count source, the frequency of the count source is 2kH2. Fig. 88. State transitions of system clock WB 6249828 0025876 601

M37267M4-XXXSP, M37267M6-XXXSP, M37267M8-XXXSP M37267EE-XXXSP, M37267EESP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER NS DISPLAY OSCILLATION CIRCUIT ADDRESSING MODE The CRT display clock oscillation circuit has a built-in clock oscilta- ‘The memory access is reinforced with 17 kinds of addressing modes. tion circuits, so that a clock for CRT display can be obtained simply Refer to the SERIES 740 <Software> User's Manual for details. by connecting an LC across the pins OSC 1 and OSC 2. Which of the sub-clock or the display oscillation circuit is selected by setting _ MACHINE INSTRUCTIONS bits 6 and 7 of the mixing control register (address 021316). ‘There are 71 machine instructions. Refer to the SERIES 740 <Sott- ware> User's Manual for details. PROGRAMMING NOTES (1) The divide ratio of the timer is 1/(n+1).. | cect css | (2) Even though the BBC and BBS instructions are executed imme- sci _oscz diately after the interrupt request bits are modified (by the pro- is gram), those instructions are only valid for the contents before L the modification. At least one instruction cycle is needed (such as cr ce ‘an NOP) between the modification of the interrupt request bits 4 aa and the execution of the BC and BBS instructions, . (8) After the ADC and SBC instruction is executed (in decimal mode), ‘one instruction cycle (such as an NOP) is needed before the SEC, - Fig. 89. Display oscillation circuit CLC, or CLD instruction is executed. (4) An NOP instruction is needed immediately after the execution of ‘a PLP instruction, (6) In order to avoid noise and latch-up, connect a bypass capacitor AUTO-CLEAR CIRCUIT (= 0.1 4F) directly between the Voc pin-Vss pin, AVcc pin-Vss When power source is supplied, the auto-clear function can be per- pin, and the Vcc pin-CNVss pin using a thick wire. formed by connecting the following circuit to the RESET pin. Circuit example 1 ~ | Circuit example 2 RESET Note : Make the level change from “L” to “H” at the point ‘at which the power source voltage exceeds the specified voltage, Fig. 90. Auto-clear circuit example M@ 6249828 0025879 748 oe ERS 2-745

M37267M4-XXXSP, M37267M6-XXXSP, M37267M8-XXXSP : M37267EE-XXXSP, M37267EESP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER DATA REQUIRED FOR MASK ORDERS PROM Programming Method The following are necessary when ordering a mask ROM produc- ‘The built-in PROM of the One Time PROM version (blank) and buit- tion: in EPROM version can be read or programmed with a general-pur- pose PROM programmer using a special programming adapter. (1) Mask ROM Order Confirmation Form eran ten OE rg rom form @5-pin DIP Type | waree7es [poaraog | 270101, three identical copies) MST267EE POATAOG ‘The PROM of the One Time PROM version (blank) is not tested or . screened in the assembly process and following processes. To en- ‘sure proper operation after programming, the procedure shown in Figure 91 is recommended to verify programming. PROM programmer (160°C for 40 hours) PROM programmer Caution : The screening temperature is far higher than the storage temperature. Never expose to 150°C exceeding 100 hours. Fig. 91. Programming and testing of One Time PROM version M@ 6249628 0025880 4bT eave" 2-746 ELECTRIC

M37267M4-XXXSP, M37267M6-XXXSP, M37267M8-XXXSP M37267EE-XXXSP, M37267EESP ‘SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER ABSOLUTE MAXIMUM RATINGS . [_Symbot_ [Parameter Concitions [Ratings ——=«dr Un | Tl votagos are based jw | Fates [oats TV vi Output transistors are ~0.3t06 v vw Input voltage P0o-P07, P1o-P17, P20-P27, cut off, 0.3 to Veo + 0.3 v Po, P31, P4o-P4s, P64, O8G1, Xin, HSYNC, VsvNc, . RESET, CVn ; Vo Output voltage: P03, Pto-P'17, P20-P27, 0.3 to Voc + 0.3 v P30, Pa, R, G, B, OUTI, Xour, OSC2 Circuit current R, G, B, OUT1, OUT2, POs, 0 to 1 (Note t) P1s-P17, P20-P27, P30, P31 Circuit current R, G, B, OUT, OUT2, 0102 (Note 2) POs, P1s-P17, P20-P27, Sour, Scuk [io [Oreuiteurent pape |S oto) «| oma | [rus | ote curent Poo-Poe, Popo [0 1 te 2) mn [tos [cireutcurent. Paap TT to 10 (Noto) | ma | [Ps [ Powerdissipation Tene | OSC [tox [operating perature ee] [tsp [Storage temperature OT CdYCOSCSC totes Cie RECOMMENDED OPERATING CONDITIONS (12 =-10 °C to 70°C, Voc = 5 V + 10 %, unless otherwise noted) Pe [OO himits a ee! Power source voltage (Note 4), During CPU, CRT, data slicer operation [45 [so {55 [Vv | | Wee, Avec [RAM hold voltage (when clocks stopped) CT SO | SCT is | [vss | Powersourcavolage dT SC Vint “H” input voltage P0o-P07, P10-P'17, P20-P27, P30, P31, 0.8Vec Veco v P40-P46, P64, HsyNc, VsyNc, RESET, Xin, OSC1 “H" input voltag SCL1, SCL2, SDA1, SDA2(WhenusingPC-BUS) | O.7Vec | __—'| veo | v | vis “L" input voltage POo-PO7, P10-P17, P20-P27, Po, P31, ae P4o-P46, P63, P64 “L” input voltage SCL1, SCL2, SDAT, SDAZ(WhenusingPG-BUS)[ 0 | | oavec | v_| vis “L" input voltage (Note 6) P41—-P44, P46, P17, HSYNC, VSYNC, {| °| RESET, Xin, OSC1 [im | “H” average output current (Note 1) R, G, B, OUT1, OUT2, POs, Pts-P17, a a P20-P27, P30, P31, “L’ average output current (Note 2), G, B, OUT1, OUT2, POs, P1s-P17, |; | 2 | {es — — as “L" average output current (Note 2)_P11-P14 | [ mA | | fois [ "1" average output current (Note 2) P00-PO2, POsPO7 S| S| Si ta] [ tore: [*L" average output current (Note 3) POPS C*d St ma] Oscilation frequency (for CPU operation) (Note 5) Xv | 36 [780 [at [Me | | fcux___[ Ossiation frequency (for sub-clock operation) (Note7)__—— | i | ae | a | ae | Oscillation frequency (for CRT display) sci [60 [13.0] mi | | fer | Inputtrequency TIM2,TIMG,INTH,INT2 | | «iY t00 | ee | | free inputtrequeney Souk dS | | rss | inputfrequeney SOLE, SOL Sid | | trea [input frequency “Horizontal syne. signal of video signal | 16.262 | 16.764 | 16206 | KH | [vi inputampltude video signal“ ovn Tt | fs | M@™ 6249828 0025881 3Tb : SE MITSUBISH ae ELECTRIC 2-747

M37267M4-XXXSP, M37267M6-XXXSP, M37267M8-XXXSP : M37267EE-XXXSP, M37267EESP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER: eS ELECTRIC CHARACTERISTICS (vcc = 5 v + 10 %, Vss = 0 V, f(XiN) = 8 MHz, Ta = -10 °C to 70 °C, unless otherwise noted) a [Win [Tye [Max | [Power source current [System operation. |Voc=5.5V, |CRTOFF (im) = 8 MHz| Data slicer OFF CRTON Data slicer: ON Voc = §.5 V, (Xin) = 0, f(XcIN) = S2kH2, CRT OFF, Data slicer OFF, A Low-power dissipation ut mode set (CMs ="0", CMa = “1") [voo=55V,ixn)=emral | 2 | «| ma | Voc = 5.5 V, (Xin) = 0, 1(XcIn) = S2kHz, Low-power dissipation mode set (CMs = "0", CM6="1") HA [Stop mode Voc = 5.5 V, (Xin) = 0, (Xow) = 0 Vou "HF output voltage Ri, G, B, OUT1, OUT2, Pos, [Vcc =4.5V 24 Pis-Pt7, P20-P27, P30, P31_|IOH=~0.5 mA v Vou "L" output voltage, G, B, OUT1, OUT2, Veo=4.5V Sout, Scux, POo-PO7, lo. =0.5 mA Pis-P17, P20-P22 FL output voltage Po, PSt Vvoo=4.5V [rowan rears iitetim || FE ouipatvetage PTF vec=a48v [loc=Sma | |_| 0a _| [iu=6maf |] 08 | View |Hysteresis ESET Woossov Tos To? | Hysteresis (Note 6) HSYNG, Vsvno, Pai-P4s, |Vec=5.0V. v P46, P11-P 14, P17 za "+P input leak current RESET, POs, P1o-P17, Voc =5.5V . P20-P27, P30, P31, P4o-P46, |Vi= 5.5 V BA P63, P64, HSYNC, VSYNC *L* input leak current RESET, POo-PO7, Pto-P17, |Vcc=5.5V P20-P2z7, P30, P31, P4o-P46, | Vi=0V HA P63, P64, HSYNC, VSYNC- “4° output leak current POo-PO2, POs-PO7 Voc =5.5V A Vo=12V # = Eeewarm, fe Te] between SCL1 and SCL2, SDA1 and SDA2) Notes 1: The total current that flows out of the IC must be 20 mA (max.). 2: The total input current to IC (IoL1 + loL2 + 1oLs) must be 20 mA of fess. ‘3: The total average input currant for ports P30, P31 to IC must be 10 mA or less. 4: Connect 0.1 1F or more capacitor extemally across the power source pins Voo-Vss and AVco-Vss so as to reduce power source noise. . ‘Also connect 0.1 iF or more capacitor externally across the pins Voo-CNVss. &: Use a quartz-crystal oscillator or a ceramic resonator for the CPU oscillation circuit. When using the data slicer, use 8 MHz. 6: P41—P44 have the hysteresis when these pins are used as interrupt input pins or timer input pins, P11—P14 have the hysteresis when these pins are used as multi-master !2C-BUS interface ports. P17 and P4s have the hysteresis when these pins are used as serial I/ 7: When using the sub-clock, set fox < fopU/3. M@™ 6249828 0025882 232

M37267M4-XXXSP, M37267M6-XXXSP, M37267M8-XXXSP M37267EE-XXXSP, M37267EESP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER Nee te aiieretS A-D COMPARATOR CHARACTERISTICS (Vcc = 5 V + 10 %, Vss =0 V, f(Xin) = 8 MHz, Ta =-10 °C to 70 °C, unless otherwise noted) ee) | =| Reson ts | | =| Nondnestiener | |__| Differential non-inearity enor TT at 8 | cc Oa to (SUM) = OmA | Vesr___[ Fultscaletransiton enor Vocesazy TTT? tsa | [vw [Anaioginoutcurent veo | MULTI-MASTER I7C-BUS BUS LINE CHARACTERISTICS | sma | Paramete arameter | Min. [Max [Min [Max | a 2 | wosta [Hold time for START condition To as | [wow | t'period of scLciock a ts [ir | Rising ime of both SCL and SDA signals T1000 | 20+0.1G [300 | ns | [won [Datahoisime 8 Ts | [two | *H’period of SCL clock Tes | [tr | Falling ime of both SCLand SDA signals TL 800 | 2040.1 | 300 | ns | [tsuoat | Datasotuptme E00 | [ tsusta | Sotuptimeforrepeated START condiion Ta? [Tos Tas | [1susro[SetuptimeotSTOP condition EO Tos Tas | Note: Co = total capacitance of 1 bus line : 1 tour : j : moss usr ; : Pio tr yt Ha te: isi ~ Isr tot _ tHo:sTA ‘tHO:DAT ‘tHIGH ‘tSU:DAT tsusTA” _ Fig. 92. Definition diagram of timing on multi-master I2C-BUS MB 6249828 0025883 179 | one | ELECTRIC 2-749

M5M44100Bu,L,TP,RT-5,-6,-7,-8,-5S,-6S,-7S,-8S FAST PAGE MODE 4194304-BIT(4194304-WORD BY 1-BIT)DYNAMIC RAM se eeeOoocauXE Note 28. Self refresh sequence Two refreshing ways should be used properly depending on the low pulse width(trass) of RAS signal during self refresh period. 1. In case of taass < 300ms

1.1 Distriduted refresh during Read/Write operation

(A) Timing Diagrams Read/Write Cycle Self Retresh Cycle Read/Write Cycle faust Cycle __j__Self Refresh Cycle), __Read/Write Cycle tNSD trass < 300ms. tsNo ws mva0sUan ee Ven Cala last refresh cycle first refresh cycle Table 2 able 1.1.1 CBR distributed Refresh Read/Wate Cycle | Read/Write | Self Refresh © Switching from read/write operation to self refresh operation. Self Refresh Read/Write The time interval from the falling edge of RAS signal CBR distributed in the last CBR refresh cycle during read/write operation refresh beso + tsno S$ 16.4ms period to the falling edge of RAS signal at the start of RAS only self refresh operation should be set within tnso (shown distributed refresh] ‘NSS 16 us in table 2). ‘© Switching from self refresh operation to read/write operation. The time interval from the rising edge of RAS signal at the end of self refresh operation to the falling edge of (B) Definition of refresh RAS signal in the first CBR refresh cycle during read/ Definition of CBR distributed refresh write operation period should be set within tsyo (shown The CBR distributed refresh performs more then in table 2). 1024 discrete CBR cycles within 16.4 ms. Definition of RAS only distributed refresh 1.1.2 RAS only distributed refresh All combination of ten row address signals(Ao~As) © Switching from read/write operation to self refresh operation, are selected during 1024 discrete RAS only refresh The time interval tsp from the falling edge of RAS signal cycles within 16.4 ms. in the last RAS only refresh cycle during read/write ‘operation period to the falling edge of RAS signal at the start of self refresh operation should be set within 16 us. ‘© Switching from self refresh operation to read/write operation. The time interval tsno from the rising edge of RAS signal at the end of self refresh operation to the falling edge of RAS signal in the first CBR refresh cycle during read/ write operation period should be set within 16 us. sess MITSUBISHI WM 6249425 0025117 362 a ate MiTsuBst 3-1

M5M44100ByJ,L,TP,RT-5,-6,-7,-8,-5S,-6S,-7S,-8S FAST PAGE MODE 4194304-BIT(4194304-WORD BY 1-BIT)DYNAMIC RAM ——_ ere

1.2 Burst refresh during Read/Write operation

(A) Timing diagram Read/Write Self_Retresh_ Read/Write tNsB, trass < 300ms tSNB “ 0a Caan Oe Wan Uate first refresh cycles refresh cycles last refresh cycles 1023 cycles 1023 cycles refresh cycles Table 3 = 1.2.1 CBR distributed Refresh Write | Self = Read/Write Cycle | Read/Write » oor © Switching from read/write operation to self refresh operation. COR bust The time interval tuse from the falling edge of RAS signal period to the falling edge of RAS signal at the start of RAS only burst self refresh operation should be set within 16.4 ms. © Switching from self refresh operation to read/write operation. The time interval tsne from the rising edge of RAS signal at the end of self refresh operation to the falling edge (B) Definition of burst refresh of RAS signal in the last CBR refresh cycle during read Definition of CBR burst refresh /write operation period should be set within 16.4 ms. The CBR burst refresh performs more then 1024 continuous CBR cycles within 16.4ms. 1.2.2 RAS only distributed refresh Definition of RAS only burst refresh ‘© Switching from read/write operation to self refresh operation. All combination of ten row address signals (Ao~ As) The time interval from the falling edge of RAS signal are selected during 1024 continuous RAS only in the first FAS only refresh cycle during read/write refresh oycles within 16.4 ms. operation period to the falling edge of RAS signal at the start of self refresh operation should be set within tss (shown in table 3). © Switching from self refresh operation to read/write operation. The time interval from the rising edge of RAS signal at the end of self refresh operation to the falling edge of RAS signal in the last RAS only refresh cycle during read/ write operation period should be set within tsna (shown in table 3). wm £249825 0025118 219 ml

4 MITSUBISHI

M5M44100BJ,L,TP,RT-5,-6,-7,-8,-5S,-6S,-7S,-8S FAST PAGE MODE 4194304-BIT(4194304-WORD BY 1-BIT)DYNAMIC RAM 2. In case of trass 2 300ms (A) Timing diagram Self Refresh Read/Write tras 2 300ms trer " se ata refresh cycle 1024 cycle Table 4 CBR distributed refresh RAS only burst refresh (B) Definition of refresh The same as 1.1-(B) and 1.2-(B) Regardless of the refresh (CBR distributed refresh, RAS only distributed refresh, CBR burst refresh, RAS only burst refresh) during Read/Write operation the minimum of 1024 cycles refresh should be preformed within 16.4 ms from the rising edge of RAS signal at the end of self refresh operation. eae WM 6249825 0025119 155 ELECTRIC 3-13