M37260E6-XXXFP

M37260M6-XXXSP MITSUBISHI | Alldatasheet

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M37260E6-XXXSP/FP, M37260E6SP/FP 37260E6: SP/FP, M37260E6SP/ SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with ON-SCREEN DISPLAY CONTROLLER

DESCRIPTION

The M37260M6-XXXSP/FP is a single-chip microcomputer de- PIN CONFIGURATION (Top VIEW) signed with CMOS silicon gate technology. It is housed in a §2-pin shrink plastic molded DIP or a 64-pin plastic molded QFP. This ose: [i fg2] - voc single-chip microcomputer is useful for the high-tech on-screen dis- oscar [2] pl Po play system for TVs. re ie 5 oe In addition to their simple instruction sets, the ROM, RAM, and VO hones False addresses are placed on the same memory map to enable easy pro- wxaipss~ [B] Fiz] Po gramming. MXBIPSATIM2—> 3] + Pos The features of the M37260E6-XXXSP/FP and the M37260E6SP/ woapse [| Fs] «Po FP are similar to those of the M37260M6-XXXSPYFP except that Mxoutiese — [5] faa] Por these chips have a built-in PROM which can be.written electrically. Fut [id g Bern ‘Accordingly, the following descriptions will be for the M37260MF- GPa Sern XXXSP/FP unless otherwise noted. Bae fF 8 faerie OuT/P4a + [4 & Baris FEATURES csynpes + [ig RB falaris ‘© Number of basic instructions ..jnsmnnnnnnnennnnssrnee 6D Pare fig ° Pte @ Memory Siz@ ROM wesecsnncnennnnctenintnennne 24 K bytes pumten Ea oer RAM .sssscsestctesietereneentenetneternteeeeees 320 bytes: paasrare fal Espn ROM for display nnmnnnnninnenennser20 K bytes pusnsareenn a oe . RAM for display «nnneinrnieeemneeese 280 bytES Powscusc. fa Epon. The minimum instruction execution time ‘cNvss + Bai] pax sesutuntesstustasenssstassnensee 0.58 (At BMHZ oscillation frequency) RESET» fal 0] > P25 @ Power SOUFCE VOMAQE -.esnsnetataenstnestnestsnatncene SV £ 10% xm Bal a] <> Pas # Power dissipation ..nsnscnneninnnannmntnmesnnnes MOMW xoure BI [23] + Per {at 4MHz frequency, Voc = 5.8V, at CRT display) ves» fg] E6 ‘# Subroutine MeStING ..s.eieesesuseerenetneneennesenee 96 levels (Max.) eUnterUpts .ssesssssssesenseesseaneinersinsiuseanen TY types, 11 vectors Outline 52P4B © Programmable VO ports (Ports PO, P1, P2, P3 ) nrnnnennnnces 30 © Output port (Port PA) .nnensnnnqnnnnnaimnnnnennsnne® Input port (Port PS) ..csescsussmsstreenenanensetieeenseansenesisensnnerens T © Sefial YO .nnnnsnstennnceene MAXIMUM 64-bit x 1 channel * CRT display function Display characters -ccnnrnnnnennnn 40 characters x 3 lines (25 lines max.) Dot StUCtUre .nnmnninnmnnnnninen 12% 20 dots OF 16 x 20 dots Character $120 .nnnsnnnnnnnnennnsninnnnnnnnne 30 KINGS (minimum dot width is 1/2 scanning line) Character color kinds ({t can be specified by the character) max. 16 kinds (R, G, B, |) Character background color (It can be specified by the block) max. 16 kinds (R, G, B, !) Raster color (max. 15 kinds) Display layout Vert c icnnnnnennntcnneenenitnercnee 1024 levels Bordering (horizontal and vertical) APPLICATION wv - MM 6249828 0025676 177

MITSUBISHI MICROCOMPUTERS, M37260M6-XXXSP/FP M37260E6-XXXSP/FP, M37260E6SP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with ON-SCREEN DISPLAY CONTROLLER PIN CONFIGURATION (TOP VIEW) RPSL LsT aT aT aTLess ttt oe ee tt

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MITSUBISHI MICROCOMPUTERS, M37260M6-XXXSP/FP M37260E6-XXXSP/FP, M37260E6SP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with ON-SCREEN DISPLAY CONTROLLER iE EIT CHS MICROCOMPUTER with ON-SCREEN DISPLAY. CONTROLLER . | Es;

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M37260E6-XXXSP/FP, M37260E6SP/FP . SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with ON-SCREEN DISPLAY CONTROLLER $$$ $$$ Emm sma CMOS MICROCOMPUTER with ON-SCREEN DISPLAY CONTROLLER FUNCTIONS Parameter ction [Number ofbasicinstusions «dS ‘ 7 0.5us (The minimum instruction execution time, at 8MHz oscill- [ec requeney «BE mani] [Row eek byes [Raw seo bytes Memory size 0 [ort Ram 280 byes [Po.Pi.Pe [10 [eit (GMOS output [Paper 0‘ 2x + (CMOS output) P32 — P35 4-bit x 1 (can be used as serial /O pins and external interrupt Inpuvout pin) (N-channel open drain output) neu put ports On t 6-bit x 1 (can be used as R, G, B, |, OUT, and CSYN pins) he (CMOS output) 7-bit x 1 (can be used as HSYNC, VsyNc, MXR, MXG, MXB, ‘XI, and MXOUT pins) 63-bit (maximum) x1, Special seal VO EBD I [timers Fsittinere ‘One external interrupt, eight internal interrupts, one software ; ; CRT display function 20 types (Fimimum dot width fs 2 scanning ine) ‘ ‘Two built-in circuits (externally connected a ceramic resonator _—— [Powersourcewotage iv toe |_| Power dissipation | [Operating temperaturerange «dt to 0G [Devicestucte «dO silicon gate process] M@™ 6249828 0025679 986 a ———— MITSUBISHI 2-545 ae ELECTRIC

M37260E6-XXXSP/FP, M37260E6SP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with ON-SCREEN DISPLAY CONTROLLER ee PIN DESCRIPTION Vss- [onvss [Cnvss |_| This is connected to Vss. RESET | Reset input To enter the reset state, the reset input pin must be kept at a°L” for 2ys or more (under normal Vcc conditions), Hf more time is needed for the crystal oscillator to stabilize, this “L” condition should be main- tained for the required time. ~ pm [Seckinpat | not | This chip has an internal clock generating circuit. To control generating frequency, an external ceramic resonator of a quartz-crystal oscillator is connected between Xin and XOUT pins. If an Glock output Output | external clock is used, the clock source should be connected the XIN pin and the XOuT pin should be left open. [5 [ing oupat | Opt [Tis is aming ouputpin Poo PO7 | VO por PO Port PO is an 8-bit I/O port with direction register allowing each /O bit to be individually pro- grammed as input or output. At reset, this port is set to input mode. The output structure is CMOS output. [Pio—Pi7 |VOponPi | WO _| Port Pt is an 8-bit I/O port and has basically the same functions as port PO. [P20-P27 |VOponP2 | VO _| Port P2is an 8-bit I/O port and has basically the same functions as port PO. P30—P36 | VO port PS Port P3 is a 6-bit VO port and has basically the same functions as port PO, but the output struc- ture of P30 and P31 is CMOS output and the output structure of P32 — P35 is N-channel open drain, P32 is in common with external interrupt input pin INT. When serial /O is used, P32, P33, P34, and P3s work as CS, SROY, SIN/SOUT, and SCLK pins, respectively. When special serial VO is used, P3s, and P3s work as SDA and SCL pins, respectively. Joser[Gackinptforcrr | rout | There are VO pins of the clock generating circuit for the CRT display function. display ‘Clock output for CAT display HsYNe input This is a horizontal synchronizing signal input for CRT display. This pin is in common with in- put Port P50. Jere [vewcinest | eeu | This is a vertical synchronizing signal input for CRT display. This pin is in common with input Port P51. MXR, MXG, | Video signal input ‘These are video signal input pins. MXR, MXG, MXB, MXI, and MXOUT are in common with MXB, MXI, | for mixing P52, P63, PSs, PSs, and PSs. Also P54 and P55 are in common with external clock input pins MXOUT TiM2 and TIM3. R,G,B,1, | CAT output This is a 5-bit oulput pin for CRT display. The output structure is CMOS output. R, G, B, I, and our OUT are in common with P4o, P41, P42, Pas, and Pa. ‘Composite sync This is a composite sync signal output pin, and in common with output port PAs. ‘signal output

. MITSUBISHI MICROCOMPUTERS, M37260M6-XXXSP/FP M37260E6-XXXSP/FP, M37260E6SP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with ON-SCREEN DISPLAY CONTROLLER ee FUNCTIONAL DESCRIPTION CPU Mode Register Central Processing Unit (CPU) The CPU mode register is allocated at address OOFB16. The CPU The M37260M6-XXXSPIFP uses the standard 740 family instruction mode register contains the stack page selection bit and the internal set. Refer to the table of 740 family addressing modes and machine system clock output selection bit! instructions or the SERIES 740 (Software) User's Manual for details : on the instruction set. Machine-resident 740 family instructions are as follows: The FST, SLW, MUL and DIV instruction cannot be used. ‘The WIT and STP instruction can be used. z o \\ LET TTT [o[0] cru mode register (address 00F B16) U Processor mode bits bi bo © 0: Single-chip mode 01: 10: | Not available da: ‘Stack page selection bit (Note 1) 0: Zero page 1:1 page ' Internal system clock cutput selection bit 0: Output is stopped (Note 2) i 1: Internal system clock ¢ output Notes 1: Please beware of this bit when programming because it is set to “1” after the reset release. 2: The internal system clock ¢ stoppes at “H.” Fig. 1 Structure of CPU mode register — M@ 6249828 0025681 534

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MITSUBISHI MICROCOMPUTERS ‘ M37260M6-XXXSP/FP M37260E6-XXXSP/FP, M37260E6SP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with ON-SCREEN DISPLAY CONTROLLER MEMORY interrupt Vector Area Special Function Register (SFR) Area ‘The interrupt vector area contains reset and interrupt vectors. ‘The special function register (SFR) area in the zero page contains control registers such as /O ports and timers. Zero Page: ‘The 256 bytes from addresses 000016 to OOFF'16 are called the zero RAM . page area. The internal RAM and the special function registers RAM is used for data storage and for stack area of subroutine calls. (SFR) are allocated to this area. and interrupts. The zero page addressing mode can be used to specify memory and register addresses in the zero page area. Access to this area with ROM only 2 bytes is possible in the zero page addressing mode. ROM is used for storing user programs as well as the interrupt vector area. Special Page ‘The 256 bytes from addresses FFO016 to FFFF 16 are called the spe- RAM for Display cial page area. The special page addressing mode can be used to RAM for display is used for specifing the character codes and colors specify memory addresses in the special page area. Access to this to display. area with only 2 bytes is possible in the special page addressing mode. ROM for Display ROM for display is used for storing character data. oe 192 Oe bMe9) | coe gl 00C016 Zoro page SFR area OOFFi6| (128 bytes) | 017F 6} (280 bytes) 21A716| (20 K bytes) TFFF16| ~ | : rom — | FFOOs6| (24 K bytes) FFDEt6| Special page . Interrupt vector area FFFFi6 Note: Refer to Table 4. Contents of CRT display RAM. Fig.2 Memory map M@ 6249828 0025682 470 - MITSUBISHI 2848 . ae ELECTRIC

M37260E6-XXXSP/FP, M37260E6SP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with ON-SCREEN DISPLAY CONTROLLER ee o0co16 [Por PO 00E 016 00116 | Port Po direction register 00E1 16 | Vertical postion register 1 (block 1) 006216 [Por Pi 00E216 [ Vertical position register 2 (block 2) 006316 [ Port Pi direction register ~ O0E3t6 | Vertical postion registor 3 (block 3) 00C416 | Por P2 00416 | Vertical position register 4 (block 1 to 3) 00C516 [Port P2 drecion register OESt6 | Mixing circuit control register 00C716 | Port PS direction ragistar O0E7i6 | _ . 00C8i6 |PonPa O0E8:6 | CRT input polarity register 00Ce16 | Pon Pa contor rapisk ‘00916 | Sync. generator control register oocBie[ Q0EBi6 | Display block counter 00CD16 | Serial VO mode register 1 QOEDi6 | Wipe mode register = O0CE16 QOEE16 | Wipe star register O0CF is | Serial VO register 0 OOEF is — 000016 | Serial VO register + 00F Ors [Timer 1 000116 00F 116 | Timer2 000216 | Senal VO register 3 — 00F216 | Timer 3. - i 000316 | Serial VO register 4 00F3t6 | Timer 4 | O0D416 | Serial VO register OOF 416 : o0Dsi6 | Serial 10 register 6 OOF S16 | Timer 34 mode register 00D616 | Serial VO register 7 OOF616 | Special serial VO register | o0D716 OOF716 | Special mode register | 000816 | Character size register 2 (block 2) oF ere | Speci = 00D316 | Character size register 3 (block 3) OOF916 OODAI6 Cs | OODBi16 | Blank control register 2 (block 2) - OOF Bie | CPU mods register ' 00DCi6 | Blank control register 3 (block 3) O0F Cie | interrupt request register 1 : ODD 16 | 0c erupt occurence pasion RTT eRe OOF Die | intorupt request register’2———_—] OODE 16 | Block 2 intemupt ocourrence pasition cortrol regis OOFEt6 | interupt control register! ___ - ODF 16 | Biod ntoruptcocurence pesiion convolegster OFF 6 [interrupt contiot regi : Fig. 3 Memory map of special function register (SFR) «MM 6249828 0025683 307 mm

Interrupts are vectored interrupts with priorities shown in Table 1. vertical synchronization signal. an interrupt. . the CRT is completed. in the vector table. The interrupt request bit is cleared automatically. ‘of a pin changes from “L" to “H” or from “H” to “L”, and generates. in interrupt request registers 1 and 2 and the interrupt enable bits are “O" at reset. the interrupt request registers 1 and 2 and interrupt control registers An interrupt is generated by an overflow of timer 1, 2, 3 or 4. cepted when the interrupt enable bit is “1”, interrupt request bit is “1”, function. cleared with a program, but not set. The interrupt enable bit can be ‘serial /O mode register 2 (address 00CE16). the interrupt disable flag (non-maskable). Table 1. Interrupt vector addresses and priority. .

: M37260M6-XXXSP/FP M37260E6-XXXSP/FP, M37260E6SP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with ON-SCREEN DISPLAY CONTROLLER es 7 0 7 0° Interrupt request register1 [OT T [TT [ [_] interrupt request register 2 (IREQ1 : address OOFC:6) {ICON1 : address OOFD16) Timer 1 interrupt request bit INT interrupt request bit Timer 2 interrupt request bit Serial VO interrupt request bit Timer 3 interrupt request bit ‘Ims interrupt request bit Timer 4 interrupt request bit CRT interrupt request bit VSYNC interrupt request bit Fix this bit to “0” 0: No interrupt request issued 1: Interrupt request issued 7 0 z o Interrupt control register 1 Interrupt control register 2 (IREQ2 : address OOF Ere) (ICON2 : address OOFF16) | Timer 1 interrupt enable bit INT interrupt enable bit | Timer 2 interrupt enable bit Serial VO interrupt enable bit Timer 3 interrupt enable bit ‘Ims interrupt enable bit Timer 4 interrupt enable bit CAT interrupt enable bit ‘sync interrupt enable bit : 0: Interrupt disabled 1: Interrupt enabled ; Fig. 4 Structure of interrupt-related registers Interrupt request bit Interrupt enable bit Interrupt disable flag(!) BRK instructio instruction — interrupt request Fig. 5 Interrupt controt , ME 6249828 0025685 aT

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: M37260M6-XXXSP/FP M37260E6-XXXSP/FP, M37260E6SP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with ON-SCREEN DISPLAY CONTROLLER TIMER . the internal clock is connected. ‘The M37260M6-XXXSP has four timers; timer 1, timer 2, timer 3 and Because of this, the program starts with stable clock. timer 4, All of timers are €-bit structure and have 8-bit latches. . A block diagram of timer 1 through 4 is shown in Figure 7. Allof the timers are down count timers and their divide ratio are 1/(n +1), where n is the contents of timer latch. ‘The same value is set to timer by writing the count value to the latch z o {addresses 00F016 to OOF316 : timer 1 to timer 4). Z Timer 12 made regia ‘When a timer reaches “0016" and the next count pulse is input to a |] ] .(112M : address oor ste) timer, a value whichis the contents of the reload latch are loaded into |_| Timer 1 count source selection bt the timer. The timer interrupt request bit is set at the next count pulse 1 | of iN) vided by 16 after the timer reaches “016”. | *1024y8 coc The contents of each timer is shown in following. | yimer 2 count source selection bit 0: Internal clock (1) Timer 1 1 External clock from P&4/MXB Either f (XIN) divided by 16 or a 102418 clock can be selected M2 pin as the count source of timer 1. ne aout top bit (When the Xin clock is 4MHz, set bits 7 and 4 of the syne gen- 1: Count stop erator control register (address 00E916) to “0”. When the XIN clock is 8MHz, set bit 7 of the sync generator con- Timer 2 count stop bit trol register to “0” and bit 4 to “1".) When bit 0 of the timer 12 0: Count start mode register (address 00F416) is “0”, f (Xin) divided by 16 is 1: Count stop selected ; when it is “1”, the 1024ys clock is selected. Timer 1 interrupt request is occurred with timer 1 overfiow. eta ta ox source 0: (KIN) divided by 16 (2) Timer 2 1: Timer 1 overflow 1 (XIN) divided by 16, timer 1 overflow signal, or an external ? 6 clock input from PS4/MXB/TIM2 pin can be selected as the Timer 34 mode register count source of timer 2 by specifying bit 4 and 1 of the timer 12 ea: OOFS18) mode reaister( Cor ase). | Timer 3 count source selection bit Timer 2 interrupt request is occurred with timer 2 overflow. | | oi iGinrguansore (3) Timer 3 | “nMg pn Either f (XIN) divided by 16 or an external clock input from P55/ _— ‘timer 4 intema!-clock source. MXUTIMS pin can be selected as the count source of timer 3 by selection bit ‘specifying bit 0 of the timer 34 mode register (address 00F516). : Timer 3 overflow Timer 3 interrupt request is occurred with timer 3 overflow. | 131 04N) dlvided by 16 | Timer 3 count stop bit (4) Timer 4 3 Gount stop 1 (Xin) divided by 16, f (Xin) divided by 2, or timer 3 overfiow sig- : nal can be selected as the count source of timer 4 by specifying Timer 4 count stop bit bit 4 and 1 of the timer 34 mode register (address 0OFS16).. o: Gount start ‘Timer 4 interrupt request is occurred with timer 4 overflow. And *Count stop the timer 4 overiow signal can be used as the lock source of Tinéx 4 count source selection bi special serial VO. 0: Internal clock At reset, timers 3 and 4 are connected by hardware and “FF 16” 1:1 (XIN) divided by 2 is automatically set in timer 8; "0716" in timer 4. The f(XIN)/16 is selected as the timer 3 count source. The internal reset is re- leased by timer 4 overflow at these state, the internal clock is ~ connected. Fig. 6 Structure of timer 12 mode register and timer 34 mode register At execution of the STP instruction, timers 3 and 4 are con- nected by hardware and "FF16" is automatically set in timer 3; “0716” in timer 4. However, the 1(XIN)/16 is not selected as the timer 3 count source. So set bit 0 of the timer 34 mode register (address 00F516) to "0" before the execution of the STP instruc- tion ({(XIn)/16 is selected as the timer 8 count source). The in- ternal STP state is released by timer 4 overflow at these state, MM 6249828 DOSE Bb Da oe oats

M37260E6-XXXSP/FP, M37260E6SP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with ON-SCREEN DISPLAY CONTROLLER EEN DISPLAY CONTROLLER Data bus 8 ea (eee $ Black colored 1024s clock ‘ side atrese, oO Fa 8 ‘ fos 72 8 i— > Timer 1 (8) of Timers Le] Lie | : | ve SH — | > 5] | 5 8 Hy PS¢MXB/TIM2 : | timer oO > Ton Py; Timer 2 (8) i interrupt request . TH2Ms 8 4 = LCE 28 ates sant i instruction O— +o a B ‘ : {_Timer 36) > fires, [4 _— 8 | bad S 134m Cy ; L_Timer4e)_ J nee T3aMa 13 Timer 4 (8) interrupt request T34Me 8 = T12M: Timer 12 mode register ‘T34M : Timer 34 mode register i Notes 1: “H" pulse width of external clock inputs TIM2 and TIM3 needs 4 machine cycles or more. 2: when the external clock source is selected, timers 2 and 3 are counted at arising edge of input signal. ‘3: In the stop mode or the wait mode, external clock inputs TIM2 and TIM3 cannot be used. Fig. 7 Timer block diagram . SL M@™@ 6249828 0025b87 TS2 MITSUBISHI - oa tee Bosse

M37260E6-XXXSP/FP, M37260E6SP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with ON-SCREEN DISPLAY CONTROLLER ee SERIAL VO Bit 2 of the serial VO mode register 1 (address 00CD16) selects ‘The M37260M6-XXXSP has a built-in serial VO function that can el whether the synchronizaion ‘clock is supplied internally or externally ther transmit of receive up to 64-bits of serial data in clock-synchro- _(from the ScLK pin) ang, ifthe internal clock is selected, bits 1 and O nized form. The serial /O function can transfer up to 64 bits of data _select whether f (Xin) is divided by 8, 16,32, or 64, Bits4 and 3 select in 8-bit units according to the setting of the serial /O shift register. whether port P3 is used for serial VO. Bits 2, 1,and 0 of the serial VO ‘Ablock diagram of the serial /O function is shown in Fig.8. The se- mode register 2 select the count of the transfer clock at which the rial VO receive enabled signal pin (GADY), syn chronization clock YO _serial VO interrupt request is generated. The operation of the serial / pin (ScLK), and data /O pins (SoUT and SIN) also function asthe P3__O function is described below. . port. Data bus moe} ] : P33 latch b12 gt 418 Suis, Bi sM2 6 6 6 i Seavi| ‘Synchronization’ las PSMi0 ss P3a/SAov1 C) & " # Sis Srou 2 P32CS_ OC b; ‘SM24—q ) > 2: reson O Powe fae TeaTon} | SMis SM14 Serial VO counter (1) to (8) =| Serial YO . = interrupt P3slatch SDA ‘Jrequea Pawsm © e-—( C Suir P| o 2 i ‘SMis: LSB--MSB % Selection gate : Connected to black colored a side at reset. Fig. 8 Serial VO block diagram M@ 6249828 0025688 999 MM - MITSUBISHI 2-854 ae ELECTRIC

MITSUBISHI MICROCOMPUTERS. M37260E6-XXXSP/FP, M37260E6SP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with ON-SCREEN DISPLAY CONTROLLER RRO MICROCOMPUTER with ON-SCREEN DISPLAY CONTROLLER If the serial I/O register 0 (address O0CF 16) is written to, the SDV when the interrupt request bit is set. Use a clock of no more that signal is at “H” during the write cycle ; it then goes “L” when the write 1MHz with a duty cycle of 50% as the external clock. cycle ends to indicate reception enabled status. If the serial /O. ‘Serial /O timing is shown in Fig. 9. If an external clock is used for the register’s transfer clock goes “L” even once the SROY signal goes transfer, the external clock must be “H” when the serial I/O counter is “tH”, During the write cycle to the serial I/O register 0, the value set in initialized. If the internal clock is switched to an external clock, make the serial /O mode register 2 is set in the serial VO counter, and the ‘sure that it is switched while no transfer is in Progress, and make serial I/O register’s transfer clock is forced to “H”. After the write cycle ‘sure that the serial I/O counter is initialized after the switch. ends, the data in each register is shifted one bit in sequence from A connection example for transferring data from one M37260M6- serial I/O register 0 to serial I/O register 1, serial /O register 2, serial XXXSP to another is shown in Fig. 10. If P32 is used as the TS pin, VO register 3, serial VO register 4, serial VO register 5, serial VO reg- set the P32 direction register to input ("0") and set bit 4 of the serial ister 6, to serial /O register 7 until it is finally output from the Sout VO mode register 2 to “0”. pin, each time the transfer clock changes from “H” to “L". Bit 6 of the ‘This setting ensures that the transfer clock is fixed at “H" when the serial /O mode register selects whether transfer is from the lowest P32 input signal is “H", and data is not shifted. If the P32 input signal bit of each serial I/O register, or from the highest bit. goes “L", data will be Shifted according to the clock input from the | During reception, data is fetched from the SIN pin each time the P3s/SCLK pin. Note that if bit 4 of the serial I/O mode register 2 is set i transfer clock changes from “L” to “H” and, at the same time, the data to “1”, the data will be shifted according to the clock input from the in each register is shifted one bit in sequence from serial /O register P36/SCLK pin, regardless of the P32 input signal. 7 to serial /O register 6, serial VO register 5, serial /O register 4, Notes : When writing programs, remember that the serial /O cou- ‘serial /O register 3, serial /O register 2, serial I/O register 1, to serial nter will also be set by using bit manipulation instructions ~ i W/O register 0. ‘such as SEB and CLB to write to the serial /O register 0. If the transfer clock is the count value set in the serial /O mode reg- 2: When writing data to serial VO registers 0 to 7, make sure ister 2, when the serial /O counter reaches “0”, the transfer clock that serial 1/O register 0 is the last one written to. stops at "H" and the corresponding interrupt request bit is set. 3: When an external clock is used as the synchronizing clock, ‘ tan external clock is selected as the clock, source, it must be con- write transmit data to the serial /O register at “H” of the ! trolled externally because the transfer clock does not stop, even ‘transfer clock input level. i fos Transfer RAAAANAnAN ce RANAANANAN clock Serial We register Swsour “| Y@aiXoo Nou XaXoaNOuXOoYOaNOX ) — TYoelXDaN Ory OrXaNoaNorNorXONOT ROY | interrupt request bit set Note:The timing at which the intrtpt request i is set canbe solactd by the serial LO mode regs 2 from 8 postions ranging rom the completion of the transter of byte 1 to the completion of the transter of byte 8. Fig. 9 Serial I/O timing WM 6249828 0025689 625 a - —— MITSUBISHI 2- oe HERS 58

M37260E6-XXXSP/FP, M37260E6SP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with ON-SCREEN DISPLAY CONTROLLER Transmission side Reception side Serial YO mode register 1 Sev Serial /O mode register 1 SRov Rov Bit7 Bito Bit7 Bito LoTxfofo[s | +[x]*] ES EEE she sax Synchronous clock sou Set the direction register for SADY pin in input mode. Sour Sorel cota sin . Fig. 10 Example of serial /O connection 7 0 z 0 Serial /O mode register 1 Serial VO mode register 2 (SIOMAI : address 00CD 16) {SIOMR2 : address OOCE 16) Intemal synchronous clock Serial VO interrupt request control bits selection bits 000: Interrupt is requested at 8 00 : Oscillation divided by 8 count of transfer clock 01 : Oscillation divided by 16 001 : Interrupt is requested at 16 10 : Oscillation divided by 32 count of transfer clock 11 : Oscillation divided by 64 010: Interrupt is requested at 24 , count of transfer clock Synchronous clock selection bit 011: Interrupt is requested at 32 1: Intental dole - count of transfer clock : 100: Interrupt is requested at 40 count of transfer clock Serial VO and special seri! WO 101: Interrupt is requested at 48 port selection bits 8 count of transter clock XO: P34, P35 : 01 : SOUTISIN pin, ScLx pin 110: Interrupt is requested at 56 11: SDA, SCL pin count of transfer clock 111: Interrupt is requested at 64 SROY signal output selection bit count of transfer clock 0: Port P33 1: SRDY signal output pin Interrupt source selection bit 0: Serial /O interrupt Transfer direction selection bit ‘1: special serial I/O interrupt 0:LSB first _ 1: MSB first GS pin control bit 0: CS pin input is valid ‘Sour contro! bit 1: CS pin input is invalid 0: SOUT output | (Data are shift by external clock Nolo :"Cmeans 0 ort" 1: SOUT output “H” that is not related CS pin input) Fig. 11 Structure of serial /O mode register 1 Fig. 12 Structure of serial YO mode register 2 mm 4249828 OO25b90 S47 mM a fe Meas ELECTRIC

MITSUBISHI MICROCOMPUTERS, M37260M6-XXXSP/FP M37260E6-XXXSP/FP, M37260E6SP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with ON-SCREEN DISPLAY CONTROLLER SEE TT OM MICROCOMPUTER with ON-SCREEN DISPLAY CONTROLLER 3 , a a a ol Baw A N i) a] ia) ial ll fl fl [el Nz BH A i Bel Hd EI Nz BE RL Blof BEE Bh NE lal fa] [el [al lal (2) Ne aa} ig E ENN A N3 g A A NNN N - HERE NNQR Ns ll ll fl NNANA Nz El El NN WN VN. NE I) fl fl bl NNN NAN Ne s NK NNN N NANANAN Na NNNAN NN NN N NNNN NNN NOONE NNN AN NN NAN Ne BN NAN AN NANA fz] NNN AN NNNN 3 NNN N..NNSWNN la] © wNNNN NNB lel § gN NN N N Bl i i i aINANNA Aa a a =N N N N El fa) EE Els NNNN fel {al lal [al lel NNN N.nw lz! [2 isl & NNN AN él jel ll [al 1g aN Bd be Be El? , S e 8, 23203 ela: a ; a Fig. 13 Serial VO register state during transmission of 2-byte date Mm 6249828 002569) 483 =< —

MITSUBISHI MICROCOMPUTERS, M37260M6-XXXSP/FP ; M37260E6-XXXSP/FP, M37260E6SP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with ON-SCREEN DISPLAY CONTROLLER eS CROCOMPUTER with ON SCREEN DISPLAY CONTROLLER BIN NNN NNN AN y N NN N NNN WN Ne NNN NUON NN NooNe NNVNN NNNN NG eN NN N NNN AN N IN NN A NNANA N< NNN AN NNN AN Ne NNN Ne NNN AN NN NN Ne. NNNN NNNN AN AN ANA NNN AN N NNN AN NNN AN N NNN N NN NA Ne NNNN NNNN_ Asa NNNN NNNN_ WP ON NN AN NNN WAWN [3] NNNN NNNN e N N N Nove Q N N N - ALS NNNN NNN@ la] 5 aANNN NNBE ES gN NN N N la ll? BN N NAN ff] f] } [a] NNN A lal fa} la} [2 a NNN Nu 2) Bue NNN N NN N N ll fal lal (a lalo NNN lal {al [al [el lZl3 aN N fl fa l] [al fl (el [23 Weel El el a El? »BE Fig. 14 Serial VO register state during reception of 2-byte date ‘wm b2uga28 o02sb92 3LT 2-0 hy HE

MITSUBISHI MICROCOMPUTERS, M37260M6-XXXSP/FP M37260E6-XXXSP/FP, M37260E6SP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with ON-SCREEN DISPLAY CONTROLLER SPECIAL MODE (I2C BUS MODE") ter (address 00F618). The start signal has been completed. M37260M6-XXXSP has a special serial /O cirouit that can be recep- The hardware automatically sends out data of 9-clock cycle. The tion or transmission of serial data in conformity with I2C (inter 1C) bus 9th clock is for ACK reception and the output level becomes “H” at format. this clock. if other master outputs the start signal to transmit data FC bus is a two line directional serial bus developed by Philips to simultaneously with this 9th clock, it is not detected as an transfer and control data among internal ICs of a machinery. artitrationlost. M37260M6-XXXSP's special serial I/O is not included the clock When the ACK bit has been transmitted, bit 1 of the interrupt re- synchronisation function and the arbitration detectable function at quest register 2 is set to "1" (issue of interrupt request), notifying multimaster. the end of data transmission. Operations of master transmission and master reception with special To transmit data successively, write data to be sent to the special serial VO explained in the following: serial YO register, and set the interrupt enabled state again. By re- eating this procedure, unlimited number of bytes can be trans- | (1) Master Transmission mitted. | @ To generate an interrupt at the end of transmission, set bit 3 of @ To terminate data transfer, clear bits 0 and 1 of the special mode serial YO mode register 2 (address 00CE'6) to “1” so as to special register 2 to "0". | serial /O interrupt is selected. @ Set bit 1 clock SCL to “1”. ® Then set bit 1 of interrupt control register 2 (address OOFF te) to 4) Then set bit 0 data SDA to “1”. This procedure transmits the stop “1” so as to special serial I/O interrupt is enabled. Clear the inter- signal. rupt disable flag | to, “0” by using the CLI instruction. Figure 16 shows master transmission timing explained above.(the @ The output signals of master transmission SDA and SCL are out- numbers in this figure are correspond to above explained num- put from ports P34 and P35. Set all bts (bits 4 and 5) correspond- bers.) ing to P34 and P35 of the port P3 register (address 00C516) and the port P3 direction ragister(address 00C716)to “1”. (2) Master Reception @ Set the transmission clock. The transmission clock uses the over- Master reception is carried out in the interrupt routine after data is flow signal of timer 4. Set appropriate value in timer 4 and timer _ transferred by master transmission. For master transmission and in- ; 34 mode register. (For instance, if (XIN) /2 is selected as the clock _terrupt thereafter, see the preceding section (1) Master transmission source of timer 4 and 9 is set in timer 4 when { (KIN) is 4MHz, the (the process until (in Figure 16.) master transmission clock frequency is 100kHz.) @ In the interrupt routine, set master reception ACK provided (2216) © Set contents of the special mode register 2 (address OOF 816). in the special mode register 1 (address OOF7:6). (Usually, the vaule is 0316") ® Write “FF16" in the special serial VO register (address OOF616). @ Set the bits 3 and 4 of serial VO mode register 1(address 00CD ie) ‘This sets data line SDA to “H” and to perform 8-clock master re- ‘so as the port P34 and P36 is specified to SDA and SCL. After that ception. Then, a clock of “L” is transmitted to data line SDA for ‘set the special mode register 1 (address 00F716). Figure 18 ACK receiving. In the ACK provided mode, the above ACK is au- shows the stucture of special mode registers 1 and 2. tomatically sent out. Initial setting is completed by the above procedure. @ Repeat the above receiving operation for a necessary number of @ Clear bits 0 and 1 of special mode register 2 (to “0") to make both times. Then return to the master transmission mode and transmit SDA and SCL output to “L”. This is for arbitration. immediately af- the stop signal by the same procedure for the master transmission ter this, write data to be transmitted in the special serial VO regis- {the process from @ to @ in Figure 16.) - Figure 17 shows master reception timing. WM 6249828 0025693 256 MM Pa ee a

: M37260M6-XXXSP/FP . M37260E6-XXXSP/FP, M37260E6SP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with ON-SCREEN DISPLAY CONTROLLER SB PRSSCL Ot hee | Interrupt request ‘SVO counter PowsoAO——f OF | | oy a pen re | ontrol Selection gate : a. “o Connected to black ‘SM13 colored side at reset. SVO shift register Data bus Zee si sieee sd lee pee ee ene Fig. 15 Special serial /O block diagram PauSDA KX bs X bs Kos Kits X'be Xb» Xen Yan} KX eos Ovw® 2 — . ® ® oS oo o0® Fig. 16 Master transmission timing “ Reception pavson ~~ |_urXeXosXbaXtaXeeKoiXooyhod FT TT ET TT hod pws LIU UU Un_ an nA _ or 3 Same as © to @ of Figure 16 POWSDA He ~ P3s/SCL. T —~ - en” @ . o ® @® Fig. 17 Master reception timing M@ 6249828 0025694 19° - MITSUBISHI 2-860 ae MERE

MITSUBISHI MICROCOMPUTERS. M37260E6-XXXSP/FP, M37260E6SP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with ON-SCREEN DISPLAY CONTROLLER oe eee 7 9 z 0 ‘Special mode register 1 Special mode register 2 (SB : address OOF716) (SC : address OOF 8816) Transmission and reception mode Data line control bit selection bit 0: SDA outputs “L” | 0: Reception mode 1: SDA outputs “H” 1: Transmission mode — Synchronous clock selection bit Clock line control bit 0: External clock 0: SCL outputs *L" 1: Timer 4 overflow 1: SCL outputs “H” | ———— ACK recognition bit | 0: ACK was received | 1: ACK is not received | —— Wait function 1 enable bit 0: Wait function 1 is disabled ; 1: Wait function 1 is enabled ——— Wait function 2 enable bit | 0: Wait function 2is disabled | | 1: Wait function 2 is enabled | | ACK operation selection bit Wait function 1 acceptance display bit | 0: ACK is not transmitted or received. 0: Wait function 1 is not accepting | 1: ACK is tramsmitted and received. 11: Wait function 1 is accepting | a ‘Start signal detect bit ————— Wait function 2 acceptance display bit . 0 : Start signal is not detected 0: Wait function 2 is not accepting | 1: Start signal was detected 1: Wait function 2 is accepting ‘Stop signal detect bit 0: Stop signal is not detected 1: Stop signal was detected Fig. 18 Structure of special mode registers 1 and 2 (3) Wait Functions The wait functions can be released by setting the corresponding bit 5 Wait function 1 holds the SCL line at “L” after the 8th clock falls in _or 6 of the special mode register 2 to “1". special mode. Wait function 2 holds the SCL line at“L" after the Sth Notes 4 : Clear the STAAT signal detection bit (bit 6) and the STOP ‘lock falls in the same way. signal detection bit (bit 7) of the special mode register 1 by ‘When one of the wait functions operates, the internal counter that writing “1” to bit 6 or bit 7. counts the clock must be reset after bit 3 or 4 of the special mode 2: If the special serial I/O function is operating, change the ; register 2 is set to “1”, to enable the corresponding wait function 1 or value of bit 4 of the sync generator control register (ad- 2 to operate, Reset the internal counter by writing data to the special dress 00E916) to suit the frequency of the system clock \\ serial VO register (address 00F616), or by setting the START signal (Xn). detection bit to “1". Reset the internal counter for each byte before data transfer. Pater oe

M37260E6-XXXSP/FP, M37260E6SP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with ON-SCREEN DISPLAY CONTROLLER 0SC1 OSC2 sync VsYNC Oo 90 Le) ie) 4 [Display oscillation e circuit [| : Synchronous 4 (Address 00E916) Syne generar Syne i control register generator | : (Address OOEAt6) CSYNC | | a - (Addresses 00E 116 to OOE416) [| | ee Vertical position registers | oot F a (Adaresses O0D716 to 00D916) Display position a Character size registers ry “4 (Address 00E016) rd : [sf circuit RAM for display ie | 22 bits x 40x 1 ROM for display} +16 bits x 40 x2 16bits.x 20 x 510 RAM for B: a ‘border function Shift register LL Shift register | 16 or 12 bits TE 16 or 12 bits b Output circuit (Address 00EC16) aa CLC | n MXR d Mixing circuit k (Address 00E516) we E RG _B_)_ our MxOUT Data bus Fig. 20 CRT display control circuit block diagram WM 6249828 0025697 IT] me

4 MITSUBISHI 2-563

. M37260E6-XXXSP/FP, M37260E6SP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with ON-SCREEN DISPLAY CONTROLLER LN Vertical positions for each block can be set in 1024 steps (where 7 0 each step is one scanning line) as values 0016 to FFI6 in vertical CRT control register Position registers 1 to 3 (addresses 00E116 to OOESi6)and values fT TTTirit) (CO : address OOEAt6) 0016 to 3F'16 in bits 0 to 5 of vertical position register 4. The structures of the vertical position registers are shown in Figure 22. All-blocks display control bit (Note) 0: All-blocks diplay off 1: Alblocks display on 7 0 . Block 1 display control bit Vertical position registers 1, 2,3 0: Block 1 display off (CV1 : address 00116) 1: Block 1 display on (CV2 : address 00E216) (CV3 : address 00E3t6) Block 2 display contro! bit 0: Block 2 display off 1 : Block 2 display splay on Setting of lower 8 bits of i ‘ , Block 3 display control bit ‘vetical daplay start positions 0 : Block 3 display off 1: Block 3 display on Block 1 color specification mode Z 2 selection bit Vertical position register 4 0: Ordinary mode (CV4: address 00E416) 1: 1/2-character unit color specification mode Setting of upper 2 bits of block 1 Display oscillation stop flag vertical display start positions 0: Oscillation stopped 1: Oscilation enabled Setting of upper 2 bits of block 2 Scafning tne double-count made Nay vertical display start positions ‘0: Normal 256 count mode

11 Scanning line double-count mode Setting of upper 2 bits of block 3

vertical display start positions Fix this bit 0 °0." Fig. 22 Structure of vertical position registers Note: Display is controlled by logical product (AND) between the all-blocks display contro! bit and each block display contro! bit. The horizontal position is common to all blocks, and can be set in 256 Fig. 21 Structure of CRT control register steps (where one step is 4To, To being the display oscillation period) {as values 0016 to FF16 in the horizontal position register (address (1) Display Position 00E016). The structure of the horizontal position register is shown in Character display position is specified in units called blocks. There Figure 24. are three blocks ~ block 1 to block 3 and each block can hold up to 40 characters (tor details, refer to the previous section (3) Memory for Display). The display position of each block can be set horizontally and verti- cally by software. Horizontal positions can be selected for all blacks in common from 256-steps in 4Tc units (Where Tc : display oscillation period). Vertical display positions can be selected for each block from 1024~ ‘steps in single scanning line units. Ifa display start position is superimposed on another block ((b) in Figure 23), the block with the smallest number (1 to 3) is displayed. If the display position of a block comes while another block is dis- played ((c) in Figure 23), the second block is displayed. : Mi 62494828 0025698 438 - MITSUBISHI 2-564 ae ELECTRIC

M37260E6-XXXSP/FP, M37260E6SP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with ON-SCREEN DISPLAY CONTROLLER cm | TT Bits O and 1 of -¥ --}---[--- 4 Bits 2 and 3 of i CV4, and CV2 | ~~ Bits 4 andS of CVs, ) | wee ' (a) Example when each block is separated T 1 : Bits Oand 1 of | ' ' CV4, and CV1-" ~~ 4 - ! CV4, and CV2 1 ' Bits 4 and 5 of CVs, | > i (b) Example when the display start position of a block overlaps with some other block Bits 0 and 1 of ‘ C4, and CWI = yoo Bits 2 and 3 of eee ene - Bits 4and 5 of CVs, y__ | (©) Example when one block is displaying some other block is superimposed. Fig. 23 Display position and value of vertical position registers CVx (x : 1 to 4) M@® 6249628 0025699 774 Se

M37260E6-XXXSP/FP, M37260E6SP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with ON-SCREEN DISPLAY CONTROLLER 7 o Horizontal position register 2 (HR : address O0E0t6) . eas —

442077702777 NNRm)

Horizontal display start A VATA AA DL AAAA 0016 to FFt6 “A | For the 12 dots wide SATA ATA AAA TTT] =x 20 dots high font, SAA AA AAA AAA TTT) the shaded part of TEAC I the character ROM LALA AA AAALA Fig. 24 Structure of horizontal position register 20) EAC (2) Character Si Recaaaecaceccumeel aracter Size Ganngoannann: esug00n77577mmmn| ‘The size of characters to be displayed can be selected from 30 types, e aaoacageecagumen ir AL POLAPCOLZE OE by combining 5 vertical types and 6 horizontal types in block units. maz ocaceeceecoeee Set the size with the character size registers (addresses 00D716 to 14] genzgense coc eeEe 000916). Either of two character font configurations, 12 dots wide x RE eee tH 20 dots high or 16 dots wide x 20 dots high, can be selected for each high or * 9 Character ROM font configuration diagram The configuration of the character ROM font is shown in Figure 26. ‘The display start position in the horizontal direction is the same, r®- 925 Character ROM font for 12 dots wide x20 dots high font <gardless of changes in character size, but it does differ ifthe charac- ter font configuration is changed. The display start position in the horizontal direction for 16 dots wide x 20 dots high characters is 4c to the right of that for 12 dots wide x 20 dots high characters. 7 oO CLIC J character size registers 1, 2, 3 (C81 : address 000716) (CS2: address 000816) (C83: address 000916) | 1 Vertical character size switching bits IN | (000 : 1 dot = 1H | O01: 1dot=2H - | 010 : 1 dot = 3H O11 :1 dot = 4H 1XX : 1 dot = 1/2H Horizontal character size , switching bits 000: 1 dot = 1Tc 001 :1 dot = 2Te 010: 1 dot =3Tc 011:1dot=4Tc 1X0: 1 dot = 6Tc 1X1: 1 dot = 8Te - ‘Character font configuration switching bit (0: 12 dots wide x 20 dots high font 1: 16 dots wide x 20 dots high font Notes1 : 1H = 1 scanning line width 2: Te: Display oscillation period 3:X:10r0 Fig, 25 Structure of character size registers M 62498248 0025700 clb — - MITSUBISHI 2-868 oe Nee

MITSUBISHI MICROCOMPUTERS, M37260M6-XXXSP/FP M37260E6-XXXSP/FP, M37260E6SP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with ON-SCREEN DISPLAY CONTROLLER i ET —clreunnmnas: The 1 dot = 1/2 scanning line display function differentiates between odd-numbered and even-numbered fields from differences in the waveform in the synchronization signals used by the interlace method, and displays one character font for both fields. Bit 6 of the syne generator control register (address O0E916) controls the active edge ofthe field identification flag, and the character font divided for each field can be selected. The field identification flag can also be read out from bit 6 of the dis- . play block counter (address OOEB16). | te ie — aT : Size : size : 1dot ~N Horizontal display start position for a P\\ torzontal play star position for 16 x 20 dot characters 12 x 20 dot characters Fig. 27 Display start positions (horizontal) for each character size M@® 6249828 0025701 15° mm

M37260E6-XXXSP/FP, M37260E6SP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with ON-SCREEN DISPLAY CONTROLLER ee eneineseiiesiissnemsiitesntitadiiiesesiaslitiisedssiatbutinsitasiiaiheadiatsathy ‘The description below assumes that field identification is based on , ; the case where the active edges of both the horizontal and vertical = # 63.5 sec» synchronization signals are negative. { Each field is identified as either odd or even by the hardware detect- ke-—12 cycle —i i ing the positions of the falling edges of the horizontal and vertical M i - ‘synchronization signals, and comparing them. Therefore, to ensure tone ogra { { correct field identification, make sure that the two synchronization i signals are input in accordance with the identification criteria given > <> below. Qu seci2usec 2 seci2usec = Since the field identification is based on the system clock (XIN), make i i Hl sure that the value of bit 4 of the syne generator control register (ad- H ‘dress 00E916) is changed in accordance with the frequency of the Vertical ane} { system clock. signal Even-numbered field : The vertical synchronization signal falls within Even-numberd field Odd-numberd field 2us before or after the fall of the horizontal synchronization signal. Fig. 28. Identification criteria for field identification ‘Odd-numbered field : The vertical synchronization signal falls within 2us before or after a point 1/2 a cycle after the fail of the horizontal synchronization sig- nal. Sync signal fol entiation tag active | Field identification fag bt . Field s {bit 6of the sync | (bit 6 of the display block | Display font {Example : negative edge inpul) generator control register) | counter) Horizontal syne signal O part ‘Odd-numbered field Vertical syne { O part ‘signal Horizontal . syne signal O part Even-numbered field Vertical sync 1 D part signal b7bsv6 b4b3b2b1 HOb7 bEDED4DSb2b1bO oo Weyer yy ee arr yyy Pree oT TTT Ty SEE EEE Example ; When the field identification flag active edge bit is 0, odd-num- Sette Tp ELPA ETT] bered fields display the O tont and even-numbered fields dis- 2 | Play the Gi font, Bit 6 of the display block counter can be read se AAR as the field identification flag : it is “1" for an odd-numbered field, ACE EEE EEE reer “0 for an even-numbered field. errr rr yy rrr rrr ery Ty yyy ry (/ See * See eee FCP er sop Pe See wae - a Character ROM font configuration Note : The field identification flag changes at the fall of the vertical syne signal (negative edge input). Fig. 29 Relationships between field identification flag and display font M@ 6249828 0025702 099 - MITSUBISHI

MITSUBISHI! MICROCOMPUTERS M37260E6-XXXSP/FP, M37260E6SP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with ON-SCREEN DISPLAY CONTROLLER —______ SINGLE-CHIP 8 BIT CMOS MICROCOMPUTER with ON-SCREEN DISPLAY CONTROLLER Character code Beas aanateeeeeet HH HHH Pry ioe SSESRSEe Ses Ey HH

28 SSSSSSEEEs Be

F SESEESESEGES & BESSSRSEEEEE FF | ‘Address in display ROM Data in display Address in display ROM Data in display | ROM ROM t ‘b7b605b4D3b201b0 b7b6bSb4Ib2b1b0 i 300016 + 201 On CTT T] oor 1 Tw Beoores aoexmes oe = EC] Be 300016 + Sorex ries gs aaeuuees 88 300016 + 2016 x n16 + 416. perry) O16 300016 + 2016 x n16 + 516. PITT TTT) 8016 300016 + 2016 x ni6 + 616. EHH O16 300016 + 2016 x n16 + 716 TTT) 806 300016 + 2016 x n16 + B16 SEGG88 Be SpNRNE + Bote x M16 + Se 2 SSSeEs) Bs Bosc gaxmsae CCC ie Spegacmesh AT) ge 300016 + 2016 x nis + E16. SSee8 Be 300016 + 2016 x m6 + Fis TTT) 2016 300016 + Zhve xe + 016 S88 Bee 300016 + 2016 x m6 + 1116 TT ery) 1016 16 + 2016 x M16 + 1216 Se88 eee W00016 + 2016 x N16 + 1316 rTTy HH 1016 300016 + 2016 x m16 + 1416 eee8 See 300016 + 2016 x m6 + 1516 eee Seen 300016 + 2016 x ni6 + 1616. 1016 300016 + 2016 N16 + 1716 Seen Bee 300016 + 2016 x n16 + 1816 rtyTy 1F16 S006 + Sorex mies 1816 Pir Féis 300016 + 2016 x ni6 + TAN tty anal 1016 300016 + 2016 x nis + 1Bi6. seen See 900016 + 2016 x n16 + 1C16 SS Sees 300016 + 2016 x ni6 + 1Di6 eanee See 300016 + 2016 x ni6 + 1E16 CEPT) 206 00016 + 2016 x m6 + 1F 16 COTTE) 046 ‘b7b6bSb4b3b2b1b0 b7b6bSb4b32b1b0 700016 + 816 x N16 + O16 2016 700016 + 816 x M16 + 116 0416 700016 + 816 x N16 + 216. 4016 ‘700016 + 816 x n16 + 316 0216 700016 + 816 x N16 + 416 4016 700016 + 816 x N16 + 516 026 700016 + 816 x N16 + 616. 0016 700016 + 816 x N16 + 716 0016 Fig. 30 Storage format of display characters (3) Memory for Display There are two types of memory for display : CRT display ROM (ad- —_ever, a two-character space is required for test purposes, so in prac- dresses 300016 to 7FFF16) which contains previously stored tice 510 characters can be stored for display. (masked) character dot data, and display RAM (addresses 200016 to Within the CRT display ROM area, data for part of each character 27FF16) which specifies characters and colors to be displayed. that is (upper 16 dots high] x {left-hand 8 dots wide] is stored at ad- ‘These memory types are described below. dresses 300X16 to SFFXI6 (where X = 0, 2, 4, 6, 8, A, C, E),data for part of each character that is {upper 16 dots high] x [right-hand 8 dots @ ROM for dispiay(addresses 300016 to 7FFF16) wide] is stored at 30016 to 3FFY16 (where Y = 1,3, 5, 7,9, B, DF), The CRT display ROM contains dot pattern data for display charac- ata for part of each character that is [lower 4 dots high] x [left-hand ters. To display these stored characters in operation, ‘specify charac- 8 dots wide] is stored at addresses 700M16 to 7FFM16 (where M =0, ter codes (code determined based on addresses in CRT display 2, 4,6, 8, A, C, E), and data for part of each character that is flower 4 ROM) that are specific to those characters, by writing them to the dots high] x [right-hand 8 dots wide] is stored at 700N16 to 7FFN16 CRT display RAM. (where N = 1,3, 5, 7, 9, B, D, F), as shown in Figure 30. ‘Since the CRT display ROM has contains 20K bytes and the data for ‘one character takes up 40 bytes, 512 characters can be stored. How- M@@ 6249828 0025703 T25 MM MITSUBISHI 2-669 ae ELECTRIC

M37260E6-XXXSP/FP, M37260E6SP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with ON-SCREEN DISPLAY CONTROLLER Table 3, Character Code Chart (Partially abbreviated) Each character code used when specifying display characters is de- fined as nis (where n = 0 to 1FF), and is determined based on the Character address in CRT display ROM that contains the data for that charac- ‘code ter (see the storage format of display character shown in Fig. 30). dots dots dots ‘dots ‘The character codes are listed in Table 3. 300016 | 7000; | 0016 | 700I16 300216 700216 300316 700316 @® RAM for display (addresses 200016 to 27FF 16) 300416 | 700416 | 300516 | 700516 The CRT display RAM is allocated at addresses 200016 to 27FF16, 300616 | 700616 | 300716 | 700716 and is divided into a display character code specification part and a 300816 300916 display color code specification part for each block. The contents of 300816 300816 this area are shown in Table 4. 300C16 300016 For example, to display one character at the first character position coors | 00816 300F 16 (the left edge) of block 1, write the character code to bit 6 of address 301016 301116 20C016 and to address 200016, and write the color code to the lower- 301216 301316 | | most 6 bits (bits 0 to 5) of address 200016. For details of the color 301416 301516 codes, see section (4) Color codes. The structure of the CRT display 301616 301716 RAM is shown in Fig.31. 201816 301916 ‘When generating a mask for the M37260M6-XXXSP, note that the sie ot Be character patterns of Table 6 and Table 7 must be written to the soles ; core specified addresses as a test character pattem. 302016 | 700eie | so2tie | 700916 302216 | 7O0A1e | 302316 | .700B16 302416 | 700cis | 302516 | 700Di6 302616 | 700E% | 302716 | 700FI6 302816 302916 302A16 302816 302C16 302016 302E16 302F16 303016 308116 303216 303316 303416 308516 303616 308716 303816 303816 303416 303816 303C16 303016 303E16 303F 16 Po fs @FEOs | 7FFBi6 | GFEI1G | 7FFOI6 6FE2I6 | 7FFAIs | FES | 7FFBI6 6FE4is | 7FFCIs | GFESIg | 7FFDIS 6FE616 TFFEI6 6FE7I6 TFFFI6 6FEB16 GFESI6 6FEAIG 6FEBIO FEC 6FEDIS serie | SEEN OFEF IS 6FFOS GFF IG oF F216 GFFa16 : 6FFai6 6FF516 6FFé16 6FF7i6 GFFar6 oFFa6 6FFAtG GFFBIC GFFC6 6FFDI6 6FFEIS 6FFFi6 . MM 6249828 0025704 9b) a - MITSUBISHI 2-870 ae ELECTRIC

Table 4. Contents of CRT display RAM

M37260E6-XXXSP/FP, M37260E6SP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with ON-SCREEN DISPLAY CONTROLLER eee Block + {Character specification] 7 0 tst character : 200016 to 0th character : 202716 Low-order 8 bits of character code [Color and character specification] 7 0 1st character : 200016 to 40th character : 20E716 ~ Color code specification in the normal mode or former 1/2 color code specification in the 1/2- character unit color specification mode High-order 1 bit of character code 7 0 1st character : 218016 to Latter 1/2 color code specification in the 1/2- character unit color specification mode Block 2 and 3 [Character specification] 7 5 tst character : 204016 to 40th character : 206716 (Addresses 208016 to 20716 Low-order 8 bits of character code in the case of block 3) {Color and character specification] ? ° ‘Ast character : 210016 to 40th character : 212716 - (Addresses 214016 to 216716 Color code specification in the case of block 3) High-order 1 bit of character code “Fig. 31 Structure of CRT display RAM me 6249828 O02570b 734 = —————— 2-672 MITSUBISHI 5 oe RS

memory overwritten by these addresses, and the contents of these. _been displayed, by an event such as a CRT interrupt. currently being displayed is accessed. Table 5. Block overwriting of display memory from the CPU for a block overwriting address or for display memory.

Table 6. Test character pattern 1 settings (4) Color Codes Table 7. Test character pattern 2 settings 1: Character output

M37260E6-XXXSP/FP, M37260E6SP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with ON-SCREEN DISPLAY CONTROLLER (5) 1/2-Character Unit Color Specification + Left-hand half : The color of the color code specified by bits 0 to 5 of Mode color code specification addresses 20C016 to 20E716 in the CRT ” Colors can be specified in 1/2-characters units for the characters of display RAM. block 1 alone, by setting bit 4 of the CRT control register (address - Right-hand half : The color of the color code specified by bits Oto 5 | OOEA16). In 1/2-character unit color specification mode, each half of of color code specification addresses 218016 to 21A716 in the CRT 1 a display character in block 1 is displayed as follows : display RAM. | Color of the color code Color of the color code specitied by bits 0 to specified by bits 0 to 5 Block 1 of address 200016 of address 200116 (@) Ordinary display Color of the color code} Color of the color code Color of the color code} Color of the color code specified by bits0to5 } specified by bits Oto 5 specified bybitsOto5 { specified by bits Oto 5 Block 1 of address 200018} ~— of address 218016 of address 20C116 | of address 218116 (©) Display with 1/2-character unit color specification Fig. 34 Correspondence between ordinary color specification and 1/2-character unit color specification mode . ME 6249828 0025709 443 mm

: MITSUBISHI MICROCOMPUTERS, M37260M6-XXXSP/FP M37260E6-XXXSP/FP, M37260E6SP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with ON-SCREEN DISPLAY CONTROLLER (6) Multiline Display @ Read the value of the display block counter. ‘The M37260M6-XXXSP can ordinarily display three lines of charac- _@) The value of @ enables identification of a block whose display ters, in three blocks with different vertical positions. has completed (whether a CRT interrupt generation cause has” In adcition, up to 25 lines can be displayed by using CRT interrupts occurred). and the display block counter. @ Read the interrupt position control register. ART interrupt is a function that generates an interrupt for each @) The value of @ enables identification of the number of dots at block at the point at which the display of any desired number of dots which the CRT interrupt is to occur. has been completed. In other words, when a scanning line reaches © Write the display character code, color code, and vertical display the point of the display position (specified by the vertical and horizon- position of that block into the character code, color code (CRT tal position registers) of a certain block, the character display of that display RAM contents), and Vertical display position (contents of block starts,and an interrupt is issued at the point at which the num- vertical position register) to be displayed next. bet of dots set by the interrupt position control register is exceeded. The structure of the display block counter is shown in Figure 35. Mf the lateral character size has been set to 1 dot = 1/2 scanning line width, the CRT interrupt position can be set to 10 steps in 1 block/2 dot units ; for all other scanning line widths it can be set to 20 steps in 7 A : 1 block/1 dot units. Display block countar The display block counter counts the number of times the display of (CBC : address 00EB16) a block has been completed, and its contents are incremented by 1 each time the display of one block is completed. Seer ent Blocks To provide multiline display, enable CRT interrupts by clearing the ; finerem ated aah Tne a block is interrupt disable flag to “0” and setting the CRT interrupt enable bit displayed.) (bit 4 at address OOFE16) to “1”, Field identiicaion tag ‘The processing within the CRT interrupt processing routine is as fol- lows. Fig. 35 Structure of display block counter mm 6249828 0025710 165 MM

MITSUBISHI MICROCOMPUTERS, M37260M6-XXXSP/FP M37260E6-XXXSP/FP, M37260E6SP/FP ‘SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with ON-SCREEN DISPLAY CONTROLLER EE ee eee es sae z 2 (@) When lateral character size is not 1 dot = 1/2 scanning line width Interrupt occurrence position control register Interrupt occurrence i Bosition control register] Timing of interrupt request generation i Block 1 interrupt occurrence i position control register [>4 bs [be [bt [to]

2 Clit (address 00DD16) 0 0 0 0 0 | Interrupt after completion of 1-dot display

© 0 0 0 1 | Interrupt atter completion of 2-dot display | Block 2 interupt occurrence 0 © 0 1. 0 | Interrupt after completion of 3-dot display position control register Pete (accross OOS To) 0 0 0 1 1 | erupt atercomplton odo ply | : : Block 3 inte ; positon contol regster 1 0 0 1 4 | Intemupt after completion of 20-dot display GI (address OODF 16) : : |e ea (00 interrupt requests) oe Interrupt request generation Position specification (0) When lateral character size is 1 dot = 1/2 scanning line width |Odd-numbered | Ever- numbered] wae ae Interrupt request Block 2 20 dots Ptrea 0 0 0 0 x [i [2] Interrupt request ooo 1 x [3 [4 | 20 dots 0 0 1 0 x Jinemptater [5 [6 baat Interrupt request 0 0 1 4 x Jeampltionot [7 [8 _|dsply|

200 Dx rn ee

Inte : (@) Interrupt request after block display "OUP Teavest x re 10014 x [ 19 | 20 | : x 10 dots : x |e isabled (no interrupt requests) Hoxd To dots Interrupt request [_Beks | Interrupt request Fig. 38 Timing of interrupt request generation with respect to values 10608 erupt request in interrupt position control register (b) Interrupt request during block display (after 10 dots displayed) Fig. 37 Timing of CRT interrupts - M@ 6249828 0025742 OTL MM

M37260E6-XXXSP/FP, M37260E6SP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with ON-SCREEN DISPLAY CONTROLLER Count value Interrupt positions . 4 Fig. 39 Timing of CRT interrupts and values in display block counter (7) Scanning Line Double-Count Mode ‘Scanning line double-count mode can be specified by setting bit 6 of ‘Scanning line double-count mode enables an increase in character the CRT control register (address OOEA16) to “1”. size in the vertical direction to twice the normal size, and it can also ‘Since this mode functions in screen units, a change in mode while a double the display start position of the characters in the vertical di- ‘screen is being displayed is not validated until the next screen is dis- rection by double-counting scanning lines. In other words, the verti- played. cal position register sets either a normal mode in which one step is ‘one scanning line, or a scanning line double-count mode is which . one step is two scanning fines. Vertical position A Vertical position A x2 A [| | ‘Scanning line 20 lines Ax2 | | ‘Scanning line 40 lines (a) Display in the normal mode (b) Display in the scanning line double count mode Fig. 40 Corresponding between normal mode display and scanning line double-count mode display ~ MITSUBISHI 2-876 oe MEEs

MITSUBISHI MICROCOMPUTERS, M37260M6-XXXSP/FP M37260E6-XXXSP/FP, M37260E6SP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with ON-SCREEN DISPLAY CONTROLLER Neate eta eats (8) Border Function ‘The border can be set in block units by the blank control registers. A one clock (one dot) border can be drawn around each character _ (addresses OODAré to O0DC16). The relationship between the set- displayed, in both the horizontal and vertical directions. tings of the blank control registers and the border function are listed This border is output from the OUT pin. In this case, bits 4 and 5 in _in Table 8, and the structure of the blank control registers is shown in 1 the color code (the OUT pin output contents) are ignored, and the Fig. 42. t border output is output from the OUT pin. i | Table 8. Corresponding between the blank control register value and border function R, G, B, | output —n_ ee ee ee X:10r0 CTT LLB z 9 rol ' ZZ 77), | (BL2 : address 0ODB16) YA YUGLLY Uh (BLS : address 00DC16) QA_| | | ZA ZOGEREEEZZ 7 . MEREEEEZZ ZZ HZ | XO: Same asthe RG. Band! ouputs LT EA | || 01 : Border output including character [| XE | | | | 11 : Output of border alone Ys UY iN Ou CZ | OO ee pennround Y GORReeeees 1: Character background Y COLUUULLAG) Coloring output Y Y Gpin output SOLGULY4UEGGZ o Sonne ene LETPPT rT yt ttt 1: Character background coloring output B pin output is border. 0: No character background Mis display by character data. coloring output 1: Character background Fig. 41 Border example tpn cua ail (0: No character background coloring output . 1: Character background coloring output Note : X means 0 or 1. Fig. 42 Structure of blank control registers ~M@ 6249828 0025713 9745 Mm MITSUBISHI -579 oe SRE ,

. M37260M6-XXXSP/FP M37260E6-XXXSP/FP, M37260E6SP/FP SINGLE-CHIP 8-8IT CMOS MICROCOMPUTER with ON-SCREEN DISPLAY CONTROLLER (a) When vertical character size is not 1 dot = 1/2 scanning line width, borders avobe the uppermost dots and borders below the lowermost dots of the character font are not displayed. 16 dots ‘4 (eee, (eeeeeY 4) AAA AA Aa SERRE Eeeee eee ree ERS SSSR eee ree eee - CO) eee Cee . 20 dots. eee oe SERRE SRR SSSRSSee eee pores Cee Coe seer SeeeGapereee 107 7 7, BB: Character dots 7 oe? 7s 7 i: Border dots (©) When vertical character size is 1 dot = 1/2 scanning line width, borders avobe and below the uppermost dots and borders below the lowermost dots of the character font are not displayed. 16 dots : —__VSR_ “4 7? C7 SSS RR Sees eee eee Coe roe Cee eee SSR SESS eee eee Corre ; Coo ee Cee SERS SSS eee eee Cae Cee Core eee ieee CO eee 207 ae 8 7 Ye 17) VEAL TT VARA TT TT Va Fig. 43. Notice of border function MP 6249828 0025714 800 Me - MITSUBISHI 2-880 oe SRE

blank part), excluding the character part of, or character border part _Q and 1 of the blank control register. | can be set for a screen when mutt-line display is used. Table 9. Display types ‘Notes 1 : If there are no character R,G,8,and | outputs,the background R.G,B, and | signals become the same as the OUT: ‘output. ‘the background area (@ in Figure 44).

: M37260M6-XXXSP/FP : M37260E6-XXXSP/FP, M37260E6SP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with ON-SCREEN DISPLAY CONTROLLER ee fo) ® @ 7 0 — ~ Mixing circuit control register YUY ly (address 00€516)

4 Mixing output control bits

rj —— ie SAI, 00 "Ro formal or external VN N Gi N “coor signal output V) N Vy, N N {SSS 11 Mixed internal and extemal N A N N N. ‘color signal output Overlapped part control bits Background coloring Background coloring No background and extemal color signals character with border character with border coloring character of overlapped part 01 : Extemal color signal of 9, eiapped part has pry 10 : Internal color signal of Fig. 44. Notice of character background color function Internal 1 iP ty 11 : No internal or external (10) Mixing Function color signal output for Color signals (MXR, MXG, MXB, MXI, and MXOUT) input from out- overlapped part side and color signals (R, G, B, |, and OUT) generated internally can be ORed and output as a mixed signal. Hi Nasal lamictal signal ‘The mixing control register (address 00E516) can be used to turn on 0: Color signal output ‘and off the mixing of the external and internal color signals, and also 1: Overlap signal output to specify which of the two signals has priority when they are com- ‘The | pin can be switched to output an overlapped signal indicating O86 osciaton crealt enone bits the parts of the external color signals (MXR, MXG, MXB, MXI, and 40X : LC oscillation circuit MXOUT) and internal color signals (R, G, B, |, and OUT) that are Note: means 1 or0 overlapped. ‘The MXB and MX! pins can also be used as external input pins for Fig. 45 Structure of mixing control register timer 2 and timer 3. Examples of displays generated with an internal color signal for the letter “I” and an external color signal for the letter “O" are shown in Figure 46. Display when neither external nor Display internal color signal has Display when external color internal color signal has priority priority signal has priority Fig. 46 Examples of display provided by mixing function M@@ 6249828 0025716 683 MM - MITSUBISHI 2882 ae ELECTRIC

M37260E6-XXXSP/FP, M37260E6SP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with ON-SCREEN DISPLAY CONTROLLER ee : (11) CRT Output Pin Control 7 } i The CRT output pins R, G, B, |, and OUT and the synogenerator out- ar ‘i put pin CSYN can also function as ports P4o, P41, Paz, Pas, Pa, and (avrese EC) 4s, Clear the corresponding bit of the port Pa control register (ad- : dress 000916) to "0" to specify these pins as CRT output pins, or set RIGIB output active edge bit it to “1” to specify it as a general-purpose port P4 pins, 0 : Positive active edge output The input active edges of the HSyNc, Vsync, MXR, MXG, MXB, MXI, 1: Negative active edge output and MXOUT signals can be specified with the bits of the CRT input , polarity register (address 00E816), and the output active edges of the O Bostve acts eige output R, G, B, |, and OUT signals can be specified with the bits of the CRT 1 : Negative active edge output output polarity register (address 00EC16). Clear a bit to “0” to specify positive active edge ; setit to“1" to specify negative active edge.The OUT output active ce bt put structure of the CRT output polarity register is shown in Fig.48 and + Positive active edge o that of the CRT input polarity register is shown in Fig.49. 1 Negative active edge output R output switching bit (12) Raster Coloring Function O:Rouput An entire screen (raster) can be colored by setting the upper 5 bits of 1: Raster coloring output the CRT output polarity register. Since each of the R, G, B, and | pins ; can be switched to raster coloring output, 16 raster colors can be ob- @ Fey era Lad tained. 1 : Raster coloring output If the OUT pin has been set to raster coloring output, a raster color- ing signal is always output during the horizontal scanning period. B output switching bit This setting is necessary for erasing a background TV image. 0: Boutput tf the R, G, B, and I pins have been set to raster coloring output, a 1: Raster coloring output raster coloring signal is output during the horizontal scanning period whenever there is no other color character output. This ensures that ! omen bit character colors do not mix with the raster color. 1 : Raster coloring output ‘An example in which a magenta letter “I” and a red letter“O” are dis- played with blue raster coloring is shown in Fig.47. OUT output switching bit 0: OUT output 1: Raster coloring output . Fig. 48. Structure of CRT output polarity register Zz 0 CofoT T TT JT [ | cat input polarity register (address OOE816) - HSYNC input active edge bit Y UY Yes B/N YW — VsyNc input active edge bit » Lz ZINN LAA ke MXR/MXG/MXB input active edge bit Gi G4 YW | Mat input active edge bit { i if iui a MXOUT input active edge bit Hence Uf i ii Tri Ly a ey Ree By INT input active edi R tT) [777 | signals across input active edge bi B ee es Se ee AA Fix these bits to “0” 1: Negative active edge input Fig. 47 Example of raster coloring Fig. 49 Structure of CRT input polarity register - MM 6249828 0025717 SLT Mm MITSUBISHI 2-583 ae ELECTRIC

@ Wipe mode Down and UP modes, providing a total of six modes. ‘The M37260M6-XXXSP allows the display area to be gradually ex- Table 10 shows the contents of each wipe mode. Table 10. Wipe operation in each mode and the values of wipe mode register

1 GHIiJKL

1 MNOPQR

@ Wipe speed ‘The wipe speed is shown in Table 11. V=16.7ms 262.5 HsvNe signals per screen done in units of 4H alone. Table 12. Wipe mode and wipe resolution

Table 13. Relationship between wipe speed and wipe resolution Note : Values in parenthases reer to resolutions for bi-scan method. To pertorm a wipe with the bi-scan method, set bit 6 of the CRT control ragister to “1”.

7 D SYNC GENERATOR

M37260E6-XXXSP/FP, M37260E6SP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with ON-SCREEN DISPLAY CONTROLLER $$$ | 8 g : al ¢ 3] iS 3 e =| fe g 2| z g| fe F 2 oe 5) 2. 8 8 g £3, 2 5 = BE BIELSE g 8 5 ells z/ 3m g {| 8 FS S iret - ~ | E 5 | € Wo Yo 3 ce Fy S 3 3 3 ! ale 3 3 ale 3 § ale g {ale | deg 3 al 8 = S + + 2 = jooof oo eo . oor oe pe ee Te CS a = es | 3 pe z 8 B33 3 8 So} 5ee 25 EQ ED e 26 ED E a| 85a SEQ £3 ER | SEQ Bea | ER] EB g| £28 £28 3 3 Ete E25 | 25 35 8) a2 352] 38 38 | 362 252] 55] 58 ae - Fig. 52 Relation between the synchronization signals of sync generator and output waveform . M@™ 6249828 0025720 O04 TT

MITSUBISHI MICROCOMPUTERS. M37260M6-XXXSP/FP M37260E6-XXXSP/FP, M37260E6SP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with ON-SCREEN DISPLAY CONTROLLER a ——— i RESET CIRCUIT stable and then returned to “H” level. The internal initializations fol- The M37260M6-XXXSPIFP is reset according to the sequence _lowing reset are shown in Figure 54. shown in Figure 3. It starts the program from the address formed by An example of the reset circuit is shown in Figure 55.The reset input using the content of address FFFF16 as the high order address and voltage must be kept below 0.6V until the supply voltage surpasses the content of the address FFFE16 as the low order address, when 4.5V. the RESET pin is held at “L” level for no less than 2us while the power voltage is SV + 10% and the crystal oscillator oscillation is xin eee . o RESET Internal RESET Address 2 ED OP) Ts GE Gp Gp 6, Reset address from the vector table Data C2 K 2 X 2X 2X 2 Kade X Ady) 32768 count of XIN clock cycle (Note 3) Note 1: (Xin) and f (¢) are in the relationship : { (XIN) = 2+ (¢). 2: A question mark (?) indicates an undefined state that depends on the previous state 3: Immediately after a reset, FF16 is automatically set in timer 3 and 0716 in timer 4 and timer 4, timer 3 and the ‘lock (t(XiN) divided by 16) are connected in series. Reset state is canceled by the overtiow signal of timer 4. Fig. 53 Reset sequence . M@™ 6249828 0025721 THO Za MITSUBISHI 2-587 ae ELECTRIC

: MITSUBISHI MICROCOMPUTERS M37260M6-XXXSP/FP M37260E6-XXXSP/FP, M37260E6SP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with ON-SCREEN DISPLAY CONTROLLER Access Contents of register . Powefon (1) PonPo dracon register oocte~[___ oe | “ (2) Port Pt direction register 000318 . Power source Jae . (8) PonPediectonregeter oocse~| ow | voltage OV——~" | (4) PonPsdrectonrgster 0067 ~|~]>=]o]0]0]0]0]9| tot voltage OV To (6) sonavomoserogstert oocow[ oe] () Seria vo mode egiter2 o0c€ w ~[x]=]x]0[0[0] 09] (©) chaactrsizergisers o0078~[x| |] 11 [1] S _ ©) Chaacterszeresiser2 oovse{x) || 11] 1 | 8255 (10) crarctersze registers oopow~(x] | | [| | 1 | i : (19 Blonk contat register oodaw~(xx] | 11 |] | (12) Birkconreirgster2 ' oo08e~(Pf TT TLL . 23\\RESET (13) olnk contests oovew-fPT TT TLL se a Bag eteruet ezzereree ooo owe -[e[fe| ||] LI (15) Besez owrreptesexereres oooes-(x]x[x] | | | | | 3 lvss oo Bossa esmcurrsscerees coors ~[x]xfx] | | || | (17 Hoteralposton easter oe 0%-( aoe | MS7260M6-XXXSP (16) Vercal posionregiters ope 4 ~ [x] (20 CRT inputpolerty egser O0ESe | oo | 20 Sregeneatercontalegste OOFS%~| cow _| . (20 cA contalregster - OBEAW~{ cow + (29) oupiay vox counter 008 ~[«] 9] 9] 0] 0] 9] 0] 0] (24 CRT ouou polatyregstee OOECH | __ cow __| (25) Wipe moseregiter ow ~ [=o] 9] 0] [9] 0] 0] (26) Tee 1 oor ow 27 Tener? ooriw~| ome | (28) Tinea ooree-[ Fre ‘| (29) Ter oorsw~| one | (20) Ter 12 mode register 00F 416 [x] x]0] 0] 9] 0]9] (01) Tiners4moderegiser 00 “=| =] =[0]0]0] 0] 0] (82) Special mode register 1 OOF 716 ~| (o[o} o]~|x]x]o]o} (22) Special moderegater2 oF 8 ~|x]0]0]0]0]0]0] 0] 24 cpumose reper oo ~{ | | | [af ]0]9] (28) intent requestregster 1 ooFGw ~[=]*]o]0]0]0]0]9] (36) intorupt request register 2 00F Dw [x] x] x]x]x}0] 00] (37 tern conrtrepsters oof Ew ~[x]=]0]0]0]0] 0] ] (68) iornptcontctregiser2 oF Fw [=] =]=]*]=]0]0]] (20) Processor status register Aor ; (40) Progam counter Pon [_omragao | ron |_emnacer | Note: The blank above, the contents of al other registers and RAM are undefined, so set their initial values. At reset, “0" is read from the bits marked X. Fig. 54 Internal state of microcomputer at reset MM 6249828 0025722 9387 ao Pa Mene

MITSUBISHI MICROCOMPUTERS. M37260M6-XXXSP/FP . M37260E6-XXXSP/FP, M37260E6SP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with ON-SCREEN DISPLAY CONTROLLER | VO PORTS ©) 08C1, OSC2 pins | (1) Port Po Clock inputioutput pins for CRT display function. Port PO is an 8-bit VO port with CMOS output. (6) Hsyno, Vsyne pins “As shown in the memory map (Figure 3), port PO can be ac- HsyNc is a horizontal synchronizing signal input pin for CRT dis- : cessed at zero page memory address 000016. play. Port PO has a direction ragister (address 00C116) which can be VsyNc is a vertical synchronizing signal input pin for CRT dis- used to program each individual bit as input (0") or as output play. ("1"). Ifthe pins are programmed as output, the output data is (7), G, B, |, OUT pins. latched to the port register and then output. When data is read This is a §-bit output pin for CRT display and in common with from the output port the output pin level is not read, only the P4o—P4s, latched data in the port register is read. This allows a previously (8). CSYNpin output value to be read correctly even though the output voltage CSYN pin outputs the composite syne signal by the sync gen- H level is shifted up or down. erator. | Pins set as input are in the floating state and the signal levels CSYN pin is in common with Pas, | can thus be read. When data is written into the input port, the (9) MXR, MXG, MXB, MXI, MXOUT pins i data is latched only to the port latch and the pin stil remains in These are video signal input pins for mixing function. i the floating state, MXR, MXG, MXB, MXI, and MXOUT are in common with the in- 2) Pot Pt ut port PS2, P63, P54, PSs, P56. MXB and MXI are also in com- ; Port P1 has the same function as port PO. mon with the external clock input pins TIM2 and TIM3. , (3) Por P2 (10) ¢ pin Port P2 has the same function as port PO. The internal system clock (1/2 the frequency of the oscillator (4) Port P3 connected between the XIN and XOUT pins) is output from this i Port P3 is a 6-bit 10 port with function similar to port PO, but the pin. If an STP or WIT instruction is executed, output stops atter i output structure of P80, P31 is CMOS output, and P32-P36 is N- going “tr. | channel open drain. P32 is in common with the external input pin INT and the serial VO input pin TS. ' When a serial I/O function is selected, P33 to P35 work as SROY, i ‘SINSOUT, and ScLK pins. i When a special serial /O function is selected, P34 and P3s work as SDA and SCL pins. i i mm ob2une28 o025723 813 MM are ERE zt

M37260E6-XXXSP/FP, M37260E6SP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with ON-SCREEN DISPLAY CONTROLLER _____SNGLE-GHIP 8 cMOs MICROCOMPUTER wih ON-SCREEN DISPLAY CONTROLLER Port PO, P1, P2, P30, P31 CMOS 3-state output iran S oa Hoe Ormtra Pra ra | p> Ports P32 to P35 ©. Nechannel open drain output D> ° oe ee Data bus ) > 1 Note : P32 may also be used as ‘external interrupt input, Hsyno, Vsyno, MXR, MXG, @, R, G, B, |, OUT,CSYN MXB, MXI, MXOUT nf CMOS output Internal circuit HsyNc, VSYNC, MXR, MXG, MXB, Internal circuit 9, R, G, B, |, OUT,CSYN MXI, MXOUT Note : HSYNC, VSYNC, MXR, MXG, Note : R, G,B, |, OUT, CSYN pins MXB, MXI, MXOUT piris may may also be used as output also be used as input port port Pdo to Pas. . . P50 to P56. Fig. 56/0 pin block diagram "MM 6249828 OO25 724 7ST MM me sto one

is set to “1” after the reset release. Table 14. The value of CPU mode register at reset Note: High-order 4 bits are undefined.

9 MITSUBISHI 2-591

MITSUBISHI MICROCOMPUTERS. M37260E6-XXXSP/FP, M37260E6SP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with ON-SCREEN DISPLAY CONTROLLER CLOCK GENERATING CIRCUIT Use the circuit constants in accordance with the resonator ‘The built-in clock generating circuit is shown in Figure 61. manufacturer's recommended values. When the STP instruction is executed, the intemal clock ¢ stops os- The example of external clock usage is shown in Figure 60 XIN is the Gillating at “H" level. At the same time, timers 3 and 4 are connected _input, and XOUT is open. in hardware and “FF16” is set in the timer 3, “0716" is set in the timer 4, Select {(XIN)/16 as the timer 3 count source (set both bit 0 of the timer 34 mode register to “0” before the execution of the STP instruc- tion). And besides, set the timer 3 and timer 4 interrupt enable bits to Gisabled ("0") before execution of the STP instruction. M37260M6-XXXSP The oscillator is restarted when an external interrupt is accepted. Xin Xour However, the internal clock » keeps its “H” level until timer 4 over- 24 25 flows. : This is because the oscillator needs a set-up period if a ceramic reso- 0 nator or a quartz-crystal oscillator is used. > CIN 4NiHz Cour When the WIT instruction is executed, the internal clock stops in a a: the “H” level but the oscillator continues running. . This wait state is cleared when an interrupt is accepted (Note). Fig. 69. Ceramic resonator crcult example ‘Since the oscitation does not stop, the next instructions are executed at once. To return from the stop or the wait state, set the interrupt enable bit to “1” before executing the STP or the WIT instruction. M37260M6-XXXSP Note: In the wait mode, the following interrupts are invalid. Xin (1) sync interrupt Pz] (2) CRT interrupt (3) Timer 2 interrupt using P54/MXB/TIM2 pin input as count Vec. source External oscillation . (4) Timer 3 interrupt using PS8/MXI/TIMS pin input as count circuit Vss source (6) tms interrupt Fig. 60 External clock input circuit example (6) Timer 4 interrupt using f(Xiny/2 as count source The circuit example using a ceramic resonator (or a quartz-crystal oszillator) is shown in Figure 59. Interrupt request , nem 5 > C disable flag | Reset STP instruction] STP instruction |) Jo— Internal clock # Dy =H 2 TadMo O° 60 me +b» ssiton ate:co lection gate : Connected to black XIN Xout colored side at reset. T34Mo, T34M2 : bit 0 and bit 2 of timer 34 mode register Fig. 61 Clock generating circuit block diagram MH 6249828 0025726 See - MITSUBISHI 282 oe Re

M37260E6-XXXSP/FP, M37260E6SP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with ON-SCREEN DISPLAY CONTROLLER er Or—vevm| DISPLAY OSCILLATION CIRCUIT PROGRAMMING NOTES. The CRT display clock osciliation circuithas builtin RC and LC oscil: _(1) The divide ratio of the timer is 1/ (n+1). lation circuits, so that a clock can be obtained simply by connecting _(2) Even though the BBC and BBS instructions are executed imme- an RC or LC circuit between the OSC1 and OSC2 pins. Giately after the interrupt request bits are modified {by the pro- Select the RC or LC oscillation circuit by setting bits 6 and 7 of the gram), those instructions are only valid for the contents before the mixing control register (see the structure of the mixing control regis modification. At least one instruction cycle is needed (such as an ter in Figure 46). NOP) between the modification of the interrupt request bits and the execution of the BBC and BBS instructions. (8) After the ADC and SBC instructions are executed (indecimal mode), one instruction cycle (such as an NOP) is needed before the SEC, CLC, or CLO instructions are executed. 5 1 oscil (4) An NOP instruction is needed immediately after the execution of osc _osca | frampieal values) a PLP instruction. ond Ct = 5pF {8) In order to avoid noise and latch-up, connect a bypass capacitor C2 = 5pF (= 0.1/F) directly between the Vc pin and Vss pin using a thick C1 C2 Lf=9yH wire. I A fort % 14MHz Fig. 62 Display oscillation circuit AUTO CLAER CIRCUIT When power is supplied, the auto-clear function can be performed by connecting the following circuit to reset pin. Circuit example 1 ~ DE | Circuit example 2 | ; : RESET DE | Note : Make the level change from “L" to “H” at the point at which the power voltage exceeds the specified voltage. Fig. 63 Auto clear circuit example M@™ 6249828 0025727 4E9 - $$ MITSUBISHI 2-593 ae ELECTRIC

M37260E6-XXXSP/FP, M37260E6SP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with ON-SCREEN DISPLAY CONTROLLER DATA REQUIRED FOR MASK ORDERS PROM Programming Method ‘The following are necessary when ordering a mask ROM production: The built-in PROM of the blank One Time PROM version and built-in EPROM version can be read or programmed with a general-purpose (1) Mask ROM Order Confirmation Form PROM programmer using a special programming adapter. (2) Mark Specification Form (3) Data to be written to ROM, in EPROM form(28-pin DIP type 27512, three identical copies) [Product [Name of Programming Adapter _] | a726ome-xxxsp | Poaa736_ | . The PROM of the blank One Time PROM version is not tested or screened in the assembly process and following processes. To en- sure proper operation after programming, the procedure shown in Figure 64 is recommended to verify programming. Programming with PROM programmer ‘Sereening (Caution) (180 for 40 hours) Verification with PROM programmer Caution : The screening temperature is far higher than the storage temperature. Never expose to ‘ 150°C exceeding 100 hours. Fig. 64 Programming and testing of One Time PROM version - MITSUBISHI 2-604 : ae ELECTRIC

M37260E6-XXXSP/FP, M37260E6SP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with ON-SCREEN DISPLAY CONTROLLER ee ABSOLUTE MAXIMUM RATINGS [ Symbol [Parameter Conditions “Ratings Unit] Input voltage CNVSs Tnput voltage PO0— PO7, P10— Piz, P20- P27, i P30 — Pas, MXR, MXG, MXB, MXI, All voltages are based on Vss. -0.3t0 Voc +0.3 v MXOUT, HsyNe, Vsync, RESET ‘Output transistors are cut off. Output voltage PO0— P07, Pto— P17, P20- P27, vo P30- P35, R, G, B, l, OUT, CSYN, -03t0evec+03 | v XouT, OSC2 Gircuit current R, G, B, |, OUT, CSYN, POO— PO7, Circuit current R, G, B, |, OUT, CSYN, POO P07, [or | PiocPiipacrntaore | | Ota ea) | Ps [Power dissipation a ee PO Storage temperature P00 125 | RECOMMENDED OPERATING CONDITIONS (ta - -10 to 70°C, Voc = 5V + 10% unless otherwise noted) [ome | emt e | | | Min. [ Typ. | Max. | Power source votage (Note 8) During the CPU and CRT operation | 4.6 | 50 | 55 | V_| |vss__[Powersourcevoltage TO TT oT | “Ht input voltage P00 POr, Pi0~ P17, P20— P27, P30 — P33, HSYNC, VSYNC, MXR, vu MXG, MXB, MXI, MXOUT, o.8vec Veo | v RESET, xin, OSC! [vin [*H"inputvottage P34, Pas f7VOoT | voc |v | “L" input voltage POo- P07, Pto— P17, P20— P27, Vis P30, P31, P33, MXR, MXG, oavec| v MXOUT “Linput voltage P32, P34, P35, HSVNC, VSYNG, Vue RESET, XIN, OSC1, MXB, MXI o2vec| Vv “HP average output current (Note 1) R, G, 8, |, OUT, . CSYN, POo— Po, P10— P17, P20 P27, P30, P31 “T average output current (Note 2) R, G, B, 1, OUT, CSYN, POo- Por, Pto- P17, P20~ P27, P30— P35 | foru | Osciliation frequency (for CPU operation) (Note 4) | 36 [40 [a1 | mrz | ‘Oscillation frequency (for CRT display) [12.0 [14.0 | 160 | Muz | Input frequency INT, TIM2, TIM3, SCL a a Input frequency SouK re Notes 1: The total current that flows out of the IC should be 20mA (max.). 2: The otal curent shold be Oma (ax). 3: Connect 0.022uF or more capacitor externally between the Vcc - Vs power source pins 80 as to reduce power source noise. Also connect 0.068yF or more capacitor externally between the Vcc - CNVss pins. 4: Use a quartz-crystal oscillator or a ceramic resonator for the CPU oscillation circuit. WM 6249628 0025729 23) MITSUBISHI 2- oe MEEe 598

M37260E6-XXXSP/FP, M37260E6SP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with ON-SCREEN DISPLAY CONTROLLER ELECTRIC CHARACTERISTICS (vec - Sv + 10%, Vss'= OV, f (KIN) = 4MHz, Ta = -10 to 70°C unless otherwise noted) ym | Min. | Typ. [ Max. | VOC = 5.5V, f (Xin) = 4MHz CRT OFF mA Power source current Voc = 5.5V, f (XIN) = 4MHz CRTON [Atstopmoge TT 800 na Von “HP output voltage POo- P07, Pio Pt7, P20— P27, | Vcc=4.5V Vv he P30, P31, R, GB, |, OUT, CSYN_| lon = ~0.5mA “L” output voltage PO0- P07, Pio- P17, P20-P27, | Voo=45V 04 Vou P30- P33, R, G, B, |, OUT, CSYN | lou = 0.5mA v “L° output voltage P34, P35 Voo=45V lou= ama [HysteresisRESET [cov 0 | 07 | Vt+-VT- | Hysteresis (Note) HSYNC, VSYNC, P32, P34, P35, v MXB, MXt Voc = 6.0V “H” input leak current RESET, P0o— P07, Pio~ P17, P20 - P27, P30~ P35, Hsyno, ” | Voc = 5.5V A \\Vsync, MXR, MXG, MXB, MXI, | Vo = 5.5V u MXOUT “L” input leak current RESET, P0o~ P07, Pto- P17, loa P20 - P27, P30 P35, HsyNc, "| Voc = 5.6V A Vsync, MXR, MXG, MXB, MXI, | Vo = OV Las MXOUT - Note : P32, MXB,MXI have the hysteresis when these pins.are used as interrupt input pins or timer input pins. P34, Ps have the hysteresis when these pins are used as serial 1/0 and special serial I/O ports. - MM 6249828 0025730 753 ae Pee

M5M44100Bu,L,TP,RT-5,-6,-7,-8,-5S,-6S,-7S,-8S FAST PAGE MODE 4194304-BIT(4194304-WORD BY 1-BIT)DYNAMIC RAM se eeeOoocauXE Note 28. Self refresh sequence Two refreshing ways should be used properly depending on the low pulse width(trass) of RAS signal during self refresh period. 1. In case of taass < 300ms

1.1 Distriduted refresh during Read/Write operation

(A) Timing Diagrams Read/Write Cycle Self Retresh Cycle Read/Write Cycle faust Cycle __j__Self Refresh Cycle), __Read/Write Cycle tNSD trass < 300ms. tsNo ws mva0sUan ee Ven Cala last refresh cycle first refresh cycle Table 2 able 1.1.1 CBR distributed Refresh Read/Wate Cycle | Read/Write | Self Refresh © Switching from read/write operation to self refresh operation. Self Refresh Read/Write The time interval from the falling edge of RAS signal CBR distributed in the last CBR refresh cycle during read/write operation refresh beso + tsno S$ 16.4ms period to the falling edge of RAS signal at the start of RAS only self refresh operation should be set within tnso (shown distributed refresh] ‘NSS 16 us in table 2). ‘© Switching from self refresh operation to read/write operation. The time interval from the rising edge of RAS signal at the end of self refresh operation to the falling edge of (B) Definition of refresh RAS signal in the first CBR refresh cycle during read/ Definition of CBR distributed refresh write operation period should be set within tsyo (shown The CBR distributed refresh performs more then in table 2). 1024 discrete CBR cycles within 16.4 ms. Definition of RAS only distributed refresh 1.1.2 RAS only distributed refresh All combination of ten row address signals(Ao~As) © Switching from read/write operation to self refresh operation, are selected during 1024 discrete RAS only refresh The time interval tsp from the falling edge of RAS signal cycles within 16.4 ms. in the last RAS only refresh cycle during read/write ‘operation period to the falling edge of RAS signal at the start of self refresh operation should be set within 16 us. ‘© Switching from self refresh operation to read/write operation. The time interval tsno from the rising edge of RAS signal at the end of self refresh operation to the falling edge of RAS signal in the first CBR refresh cycle during read/ write operation period should be set within 16 us. sess MITSUBISHI WM 6249425 0025117 362 a ate MiTsuBst 3-1

M5M44100ByJ,L,TP,RT-5,-6,-7,-8,-5S,-6S,-7S,-8S FAST PAGE MODE 4194304-BIT(4194304-WORD BY 1-BIT)DYNAMIC RAM ——_ ere

1.2 Burst refresh during Read/Write operation

(A) Timing diagram Read/Write Self_Retresh_ Read/Write tNsB, trass < 300ms tSNB “ 0a Caan Oe Wan Uate first refresh cycles refresh cycles last refresh cycles 1023 cycles 1023 cycles refresh cycles Table 3 = 1.2.1 CBR distributed Refresh Write | Self = Read/Write Cycle | Read/Write » oor © Switching from read/write operation to self refresh operation. COR bust The time interval tuse from the falling edge of RAS signal period to the falling edge of RAS signal at the start of RAS only burst self refresh operation should be set within 16.4 ms. © Switching from self refresh operation to read/write operation. The time interval tsne from the rising edge of RAS signal at the end of self refresh operation to the falling edge (B) Definition of burst refresh of RAS signal in the last CBR refresh cycle during read Definition of CBR burst refresh /write operation period should be set within 16.4 ms. The CBR burst refresh performs more then 1024 continuous CBR cycles within 16.4ms. 1.2.2 RAS only distributed refresh Definition of RAS only burst refresh ‘© Switching from read/write operation to self refresh operation. All combination of ten row address signals (Ao~ As) The time interval from the falling edge of RAS signal are selected during 1024 continuous RAS only in the first FAS only refresh cycle during read/write refresh oycles within 16.4 ms. operation period to the falling edge of RAS signal at the start of self refresh operation should be set within tss (shown in table 3). © Switching from self refresh operation to read/write operation. The time interval from the rising edge of RAS signal at the end of self refresh operation to the falling edge of RAS signal in the last RAS only refresh cycle during read/ write operation period should be set within tsna (shown in table 3). wm £249825 0025118 219 ml

4 MITSUBISHI

M5M44100BJ,L,TP,RT-5,-6,-7,-8,-5S,-6S,-7S,-8S FAST PAGE MODE 4194304-BIT(4194304-WORD BY 1-BIT)DYNAMIC RAM 2. In case of trass 2 300ms (A) Timing diagram Self Refresh Read/Write tras 2 300ms trer " se ata refresh cycle 1024 cycle Table 4 CBR distributed refresh RAS only burst refresh (B) Definition of refresh The same as 1.1-(B) and 1.2-(B) Regardless of the refresh (CBR distributed refresh, RAS only distributed refresh, CBR burst refresh, RAS only burst refresh) during Read/Write operation the minimum of 1024 cycles refresh should be preformed within 16.4 ms from the rising edge of RAS signal at the end of self refresh operation. eae WM 6249825 0025119 155 ELECTRIC 3-13