M37221

Mitsubishi Electric Sem...

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER???

Manufacturer: Mitsubishi Electric Sem...

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M37221EF MITSUBISHI | Alldatasheet

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Technical content

PIN CONFIGURATION (TOP VIEW)

CRT display function (16 lines maximum) Kinds of character colors (It can be specified by the character) maximum 7 kinds (R, G, B) Kinds of character background colors (It can be specified by the character) maximum 7 kinds (R, G, B) Kinds of raster colors (maximum 7 kinds) Display position Bordering (horizontal and vertical) APPLICATION TV Outline 42P4B

DESCRIPTION

The M37221EF-XXXSP and M37221EFSP are single-chip microcom- puters designed with CMOS silicon gate technology. They are housed in a 42-pin shrink plastic molded DIP. In addition to their simple instruction sets, the ROM, RAM and I/O addresses are placed on the same memory map to enable easy pro- gramming. The M37221EF-XXXSP and M37221EFSP have a PWM output func- tion and a OSD display function, so it is useful for a channel selection system for TV.

FEATURES

Memory size
The minimum instruction execution time (at 8 MHz oscillation frequency, VCC =5.5V, at CRT display) SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOL TAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER M37221EF-XXXSP,M37221EFSP MITSUBISHI MICROCOMPUTERS

M37221EF-XXXSP,M37221EFSP MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOL TAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER FUNCTIONAL BLOCK DIAGRAM of M37221EF-XXXSP OUT1 Clock input Clock output X IN XOUT Reset input VCC VSS CNV SS Clock output for display Input ports P33, P34 OSC1 OSC2 Clock input for display INT2 INT1 PWM5 PWM4 PWM3 PWM2 PWM1 PWM0 P5 (4) B G R HSYNC VSYNC A-D comparator 14-bit PWM circuit 8-bit PWM circuit Accumulator A (8) Timer 4 T4 (8) Timer 3 T3 (8) Timer 2 T2 (8) Timer 1 T1 (8) Timer count source selection circuit TIM2 TIM3 Instruction register (8) Instruction decoder Control signal CRT circuit Stack pointer S (8) Index register Y (8) Index register X (8) Processor status register PS (8) 8-bit arithmetic and logical unit ROM

62 K bytes

PC L (8) Program counter PC H (8) RAM 1216 bytes Data Clock generating circuit RESET Output ports P52–P55 Address bus SI/O(8) SIN SCLK SOUT INT3 1 0 9876543 I/O port P0 2829303132333435 P1 (8) I/O port P1 15141312 11363738 P2 (8) I/O port P2 I/O ports P30–P3 2 17262716 P3 (3)P0 (8) 39 4041 42 2 1 2019 25 22 21 18 24 23 ( ) Timing output D-A D-A converter OUT2 Multi-master I C-BUS interface

M37221EF-XXXSP,M37221EFSP MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER 0.5 µs (the minimum instruction execution time, at 8 MHz oscillation fre- quency)

8 MHz (maximum)

8 K bytes

8-bit 5 1 (N-channel open-drain output structure, can be used as PWM output pins, INT input pins, A-D input pin) 4-bit 5 1 (CMOS input/output structure, can be used as CRT output pin, A-D input pins, INT input pin) 4-bit 5 1 (CMOS input/output structure, can be used as multi-master I 2C- BUS interface) 2-bit 5 1 (CMOS input/output or N-channel open-drain output structure, can be used as serial I/O pins) 6-bit 5 1 (CMOS input/output structure, can be used as serial input pin, external clock input pins) 2-bit 5 1 (CMOS input/output or N-channel open-drain output structure, can be used as A-D input pins, D-A conversion output pins) 1-bit 5 1 (N-channel open-drain output structure) 2-bit 5 1 (can be used as CRT display clock I/O pins) 4-bit 5 1 (CMOS output structure, can be used as CRT output pins) 8-bit 5 1 1 (2 systems) 6 channels (6-bit resolution) 2 (6-bit resolution) 14-bit 5 1, 8-bit 5 6 8-bit timer 5 4 32 bytes 5 2 96 levels (maximum) External interrupt 5 3, Internal timer interrupt 5 4, Serial I/O interrupt 5 1, CRT interrupt 5 1, Multi-master I 2C-BUS interface interrupt 5 1, f(XIN)/4096 interrupt 5 1, VSYNC interrupt 5 1, BRK interrupt 5 1 2 built-in circuits (externally connected a ceramic resonator or a quartz- crystal oscillator)

5 V ± 10 %

165 mW typ. (at oscillation frequency f CPU = 8 MHz, fCRT = 8 MHz) 110 mW typ. (at oscillation frequency fCPU = 8 MHz) 1.65 mW (maximum) –10 °C to 70 °C CMOS silicon gate process 42-pin shrink plastic molded DIP 24 characters 5 2 lines (maximum 16 lines by software) 12 5 16 dots 256 kinds 3 kinds Maximum 7 kinds (R, G, B); can be specified by the character 64 levels (horizontal) 5 128 levels (vertical) Parameter Functions FUNCTIONS Number of basic instructions Instruction execution time Clock frequency Memory size Input/Output ports Serial I/O Multi-master I2C-BUS interface A-D comparator D-A converter PWM output circuit Timers ROM correction function Subroutine nesting Interrupt Clock generating circuit Power source voltage Power dissipation Operating temperature range Device structure Package CRT display function ROM RAM CRT ROM CRT RAM 0, P15–P17 P11–P1 4 P20, P21 P22–P2 7 P30, P31 P32 P33, P34 P52–P5 5 I/O I/O I/O I/O I/O I/O I/O Input Output CRT ON CRT OFF In stop mode Number of display characters Dot structure Kinds of characters Kinds of character sizes Kinds of character colors Display position (horizontal, vertical)

M37221EF-XXXSP,M37221EFSP MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOL TAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER Power source CNV SS Reset input Clock input Clock output I/O port P0 PWM output External interrupt input Analog input I/O port P1 CRT output Multi-master I 2C-BUS interface Analog input External interrupt input I/O port P2 External clock input Serial I/O synchro- nizing clock input/ output Serial I/O data input/output I/O port P3 Analog input D-A conversion output Input port P3 Clock input for CRT display Clock output for CRT display V CC , VSS. CNV SS RESET XIN XOUT P00/PWM0– P05/PWM5, P06/INT2/ A-D4, P07/INT1 P10/OUT2, P11/SCL1, P12/SCL2, P13/SDA1, P14/SDA2, P15/A-D1/ INT3, 6/A-D2, P17/A-D3 P20/SCLK , P21/SOUT , P22/SIN, P23/TIM3, P24/TIM2, P25–P2 7 P30/A-D5/ DA1, 1/A-D6/ DA2, P33/OSC1, P34/OSC2 Input Input Output I/O Output Input Input I/O Output I/O Input Input I/O Input I/O I/O I/O Input Output Input Input Output Apply voltage of 5 V ± 10 % (typical) to V CC , and 0 V to VSS . This is connected to VSS . To enter the reset state, the reset input pin must be kept at a “L” for 2 µs or more (under normal VCC conditions). If more time is needed for the quartz-crystal oscillator to stabilize, this “L” condition should be maintained for the required time. This chip has an internal clock generating circuit. To control generating frequency, an external ceramic resonator or a quartz-crystal oscillator is connected between pins X IN and XOUT . If an external clock is used, the clock source should be connected to the XIN pin and the XOUT pin should be left open. Port P0 is an 8-bit I/O port with direction register allowing each I/O bit to be individually programmed as input or output. At reset, this port is set to input mode. The output structure is N-channel open-drain output. The note out of this Table gives a full of port P0 function. Pins P0 0–P0 5 are also used as PWM output pins PWM0–PWM5 respectively. The output structure is N-channel open-drain output. Pins P06 , P07 are also used as external interrupt input pins INT2, INT1 respectively. P06 pin is also used as analog input pin A-D4. Port P1 is an 8-bit I/O port and has basically the same functions as port P0. The output structure is CMOS output. Pins P10 is also used as CRT output pin OUT2. The output structure is CMOS output. Pins P11–P14 are used as SCL1, SCL2, SDA1 and SDA2 respectively, when multi-master I2C-BUS interface is used. The output structure is N-channel open-drain output. Pins P15–P1 7 are also used as analog input pins A-D1 to A-D3 respectively. P15 pin is also used as external interrupt input pin INT3. Port P2 is an 8-bit I/O port and has basically the same functions as port P0. The output structure is CMOS output. Pins P23, P24 are also used as external clock input pins TIM3, TIM2 respectively. P20 pin is also used as serial I/O synchronizing clock input/output pin SCLK . The output structure is N-channel open-drain output. Pins P21, P22 are also used as serial I/O data input/output pins SOUT , SIN respectively. The output structure is N-channel open-drain output. Ports P30–P3 2 are a 3-bit I/O port and has basically the same functions as port P0. Either CMOS output or N-channel open-drain output structure can be selected as the port P30 and P31. The output structure of port P32 is N-channel open-drain output. Pins P30, P31 are also used as analog input pins A-D5, A-D6 respectively. Pins P30, P31 are also used as D-A conversion output pins DA1, DA2 respectively. Ports P33, P34 are a 2-bit input port. P33 pin is also used as CRT display clock input pin OSC1. P34 pin is also used as CRT display clock output pin OSC2. The output structure is CMOS output. PIN DESCRIPTION Pin Name Functions Input/ Output

M37221EF-XXXSP,M37221EFSP MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER Output port P5 CRT output H SYNC input VSYNC input DA output PIN DESCRIPTION (continued) P52/R, P53/G, P54/B, P55/OUT1 H SYNC VSYNC D-A Ports P52–P5 5 are a 4-bit output port. The output structure is CMOS output. Pins P52–P55 are also used as CRT output pins R, G, B, OUT1 respectively. The output structure is CMOS output. This is a horizontal synchronizing signal input for CRT. This is a vertical synchronizing signal input for CRT. This is a 14-bit PWM output pin. Output Output Input Input Output Note : As shown in the memory map (Figure 3), port P0 is accessed as a memory at address 00C016 of zero page. Port P0 has the port P0 direction register (address 00C116 of zero page) which can be used to program each bit as an input (“0”) or an output (“1”). The pins programmed as “1” in the direction register are output pins. When pins are programmed as “0,” they are input pins. When pins are programmed as output pins, the output data are written into the port latch and then output. When data is read from the output pins, the output pin level is not read but the data of the port latch is read. This allows a previously-output value to be read correctly even if the output “L” voltage has risen, for example, because a light emitting diode was directly driven. The input pins are in the floating state, so the values of the pins can be read. When data is written into the input pin, it is written only into the port latch, while the pin remains in the floating state.

M37221EF-XXXSP,M37221EFSP MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOL TAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER CPU Mode Register The CPU mode register contains the stack page selection bit. The CPU mode register is allocated at address 00FB16. FUNCTIONAL DESCRIPTION Central Processing Unit (CPU) The M37221EF-XXXSP uses the standard 740 family instruction set. Refer to the table of 740 family addressing modes and machine in- structions or the SERIES 740 <Software> User’s Manual for details on the instruction set. Machine-resident 740 family instructions are as follows: The FST, SLW instruction cannot be used. The MUL, DIV, WIT and STP instruction can be used. Fig. 1. Structure of CPU mode register 1 111 1 0 0 CPU mode register (CPUM : address 00FB16) Fix these bits to “0.” Stack page selection bit (Note) 0 : Zero page 1 : 1 page Fix these bits to “1.” Note :Please beware of this bit when programming because it is set to “1” after the reset release.

M37221EF-XXXSP,M37221EFSP MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER MEMORY Special Function Register (SFR) Area The special function register (SFR) area in the zero page contains control registers such as I/O ports and timers. RAM RAM is used for data storage and for stack area of subroutine calls and interrupts. ROM ROM is used for storing user programs as well as the interrupt vector area. RAM for Display RAM for display is used for specifying the character codes and col- ors to display. ROM for Display ROM for display is used for storing character data. Interrupt Vector Area The interrupt vector area contains reset and interrupt vectors. Zero Page The 256 bytes from addresses 000016 to 00FF16 are called the zero page area. The internal RAM and the special function registers (SFR) are allocated to this area. The zero page addressing mode can be used to specify memory and register addresses in the zero page area. Access to this area with only 2 bytes is possible in the zero page addressing mode. Special Page The 256 bytes from addresses FF0016 to FFFF16 are called the spe- cial page area. The special page addressing mode can be used to specify memory addresses in the special page area. Access to this area with only 2 bytes is possible in the special page addressing mode. 000016 00C0 16 00FF16 01FF16 06B716 080016 SFR area ROM correction memory (RAM) Not used FFFF 16 FFDE 16 FF0016 060016 Interrupt vector area Not used 1000016 11FFF 16 1FFFF 16 ROM for display (8 K bytes) Special page ROM (62 K bytes) RAM for display (Note) (96 bytes) Zero pageRAM (448 bytes) 05FF16 030016 RAM (768 bytes) 02FF16 02C0 16 021716 Not used 2 page register Not used 021B16 Note: Refer to Table 12. Contents of CRT display RAM. Fig. 2. Memory map

M37221EF-XXXSP,M37221EFSP MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOL TAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER Fig. 3. Memory map of SFR (special function register) (1) P30SP31S PW0PW1PW2PW3PW4PW5PW6PW7 PN2PN3PN4 SM0SM1SM2SM3SM5SM6 b7 b0 0016 b7 b0 0016 0016 0000 000 0 0000 000 0 ???? 0000 000 0 0000 000 0 0000 000 0 ? ? DA1SDA2S DA10DA11DA12DA13DA14DA15 DA20DA21DA22DA23DA24DA25 SAD0SAD1SAD2SAD3SAD4SAD5SAD6 RBW LRBAD0AASALPINBBTRXMST BC0BC1BC2ES0ALS10 BIT SADBSEL0BSEL1 CCR0CCR1CCR2CCR3CCR4FAST MODE ACK BITACK 0016 0016 0016 0000 01? 0 0 : “0” immediately after reset : Fix this bit to “0” (do not write “1”) : Nothing is allocated n SFR area (addresses C016 to DF16) : “1” immediately after reset : undefined immediately after reset D0 16 D1 16 D2 16 D3 16 D4 16 D5 16 D6 16 D7 16 D8 16 D9 16 DA 16 DB 16 DC 16 DD 16 DE 16 DF 16 C0 16 C1 16 C2 16 C3 16 C4 16 C5 16 C6 16 C7 16 C8 16 C9 16 CB 16 CC 16 CD 16 CE 16 CF 16 CA 16 Address Port P5 (P5) Port P5 direction register (D5) Port P3 output mode control register (P3S) DA-H register (DA-H) DA-L register (DA-L) PWM0 register (PWM0) Port P1 (P1) Port P1 direction register (D1) Port P3 (P3) Port P3 direction register (D3) Port P2 (P2) Port P2 direction register (D2) Register Port P0 (P0) Port P0 direction register (D0) PWM1 register (PWM1) PWM2 register (PWM2) PWM3 register (PWM3) PWM4 register (PWM4) PWM output control register 1 (PW) PWM output control register 2 (PN) Serial I/O mode register (SM) Serial I/O regsiter (SIO) DA1 conversion register (DA1) DA2 conversion register (DA2) Bit allocation State immediately after reset I C data shift register (S0)2 I C address register (S0D)2 I C status register (S1)2 I C control register (S1D)2 I C clock control register (S2)2

M37221EF-XXXSP,M37221EFSP MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER Fig. 4. Memory map of SFR (special function register) (2) b7 b0 HR0HR1HR2HR3HR4HR5 CV10CV11CV12CV13CV14CV15CV16 CV20CV21CV22CV23CV24CV25CV26 CS10CS11CS20CS21 MD10MD20 CO01CO02CO03CO05 /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines CO11CO12CO13CO15 CO21CO22CO23CO25 CO31CO32CO33CO35 CC0CC1CC2 VSYCR/G/BOUT1OP5OP6OP7 HSYC CK0CK1 ADM0ADM1ADM2ADM4 /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines ADC0ADC1/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines ADC2ADC4 ADC3ADC5 /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines T34M0 /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines T34M1T34M2T34M3T34M4/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines T12M0 /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines T12M1T12M2T12M3T12M4 CK0RE5 RE4 RE3 CM2 /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines TM1R /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines TM2RTM3RTM4RCRTRVSCRIT3R CK0 /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines MSR 1T1R1T2RS1R /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines TM1E /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines TM2ETM3ETM4ECRTEVSCEIT3E 1T1E1T2ES1EMSE T34M5 /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines b7 b0 /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines CK0 /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines CK0 /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines 00 00 0000 ????00 00 ??00 00 0 0 00 00 0000 0016 /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines00 0000 0/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines 0 ?00 000 00 00 0000 00 FF16 0716 FF16 0716 00 0000 00 00 0000 00 /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines 00 00 /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines 0?/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines 0 1/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines 0 00 00 0 000 00 00 0 0/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines 00 00 0 000 00 00 0 000 0016 /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines 1 /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines 11 /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines 1 /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines 0 00 00 0 0 0 0 00 00 0 0 0 0 00 00 0 0 0 0 00 00 0 0 0 CO04 CO14 CO24 CO34 CO06 CO16 CO26 CO36 CO07 CO17 CO27 CO37 CC7 OUT2 IICR IICE F016 F116 F216 F316 F416 F516 F616 F716 F816 F916 FA 16 FB 16 FC 16 FD 16 FE 16 FF16 E016 E116 E216 E316 E416 E516 E616 E716 E816 E916 EB 16 EC 16 ED 16 EE 16 EF 16 EA 16 Address CRT control register (CC) CRT port control register (CRTP) A-D control register 1 (AD1) A-D control register 2 (AD2) Timer 1 (TM1) Vertical register 2 (CV2) Color register 0 (CO0) Color register 1 (CO1) Character size register (CS) Border selection register (MD) Register Horizontal register (HR) Vertical register 1 (CV1) Timer 2 (TM2) Timer 3 (TM3) Timer 4 (TM4) Timer 12 mode register (T12M) Timer 34 mode register (T34M) PWM5 register (PWM5) Interrupt input polarity register (RE) Test register (TEST) Interrupt request register 1 (IREQ1) Interrupt request register 2 (IREQ2) Interrupt control register 1 (ICON1) Interrupt control register 2 (ICON2) Color register 2 (CO2) Color register 3 (CO3) CRT clock selection register (CK) CPU mode register (CPUM) Bit allocation State immediately after reset /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines 0 : “0” immediately after reset /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines : Fix this bit to “0” (do not write “1”) : Nothing is allocated n SFR area (addresses E016 to FF16) : “1” immediately after reset : undefined immediately after reset : Fix this bit to “1” (do not write “0”)

M37221EF-XXXSP,M37221EFSP MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOL TAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER Fig. 5. Memory map of 2 page register 21016 21116 21216 21316 21416 21516 21616 21716 21816 21916 21A16 21B16 21C 16 21D 16 21E16 21F16 20016 20116 20216 20316 20416 20516 20616 20716 20816 20916 20B16 20C 16 20D 16 20E16 20F16 20A16 b7 b0 RCR1 /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines b7 b0 00 0 00 /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines 0 00RCR0 Address Register ROM correction address 1 (high-order) Bit allocation State immediately after reset 0 : “0” immediately after reset /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines : Fix this bit to “0” (do not write “1”) : Nothing is allocated n SFR area (addresses 20016 to 21F16) ROM correction address 1 (low-order) ROM correction address 2 (high-order) ROM correction address 2 (low-order) ROM correction enable register (RCR)

table because its operation is similar to an interrupt. register are automatically stored into the stack. the interrupt-related registers. be set to “0” and “1” by a program. Reset is treated as a non-maskable interrupt with the highest priority. Figure 6 shows interrupt control. that all bits are cleared to “0” at reset. An interrupt is generated by an overflow of timer 1, 2, 3 or 4. Table 1. Interrupt vector addresses and priority

M37221EF-XXXSP,M37221EFSP MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOL TAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER (5) f(XIN)/4096 interrupt This interrupt occurs regularly with a f(XIN)/4096 period. Set bit 0 of the PWM output control register 1 to “0.” (6) Multi-master I2C-BUS interface interrupt This is an interrupt related to the multi-maseter I2C-BUS inter- face. (7) BRK instruction interrupt This software interrupt has the least significant priority. It does not have a corresponding interrupt enable bit, and it is not af- fected by the interrupt disable flag I (non-maskable). Fig. 6. Interrupt control Interrupt request bit Interrupt enable bit Interrupt disable flag I BRK instruction Reset Interrupt request

M37221EF-XXXSP,M37221EFSP MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER Fix this bit to “0.” INT3 polarity switch bit 0 : Positive polarity 1 : Negative polarity Interrupt input polarity register (RE : address 00F9 16) Fix these bits to “0.” INT1 polarity switch bit 0 : Positive polarity 1 : Negative polarity INT2 polarity switch bit 0 : Positive polarity 1 : Negative polarity 7 0 Interrupt request register 1 (IREQ1 : address 00FC16) 0 : No interrupt request issued 1 : Interrupt request issued Interrupt request register 2 (IREQ2 : address 00FD16) Serial I/O interrupt request bit Fix this bit to “0.” INT1 interrupt request bit INT2 interrupt request bit f(XIN)/4096 interrupt request bit 0 : Interrupt disabled 1 : Interrupt enabled Serial I/O interrupt enable bit Interrupt control register 2 (ICON2 : address 00FF16) INT1 interrupt enable bit INT2 interrupt enable bit Fix this bit to “0.” f(XIN)/4096 interrupt enable bit Fix these bits to “0.” 00 0 Interrupt control register 1 (ICON1 : address 00FE16) Timer 1 interrupt enable bit Timer 2 interrupt enable bit Timer 3 interrupt enable bit Timer 4 interrupt enable bit CRT interrupt enable bit VSYNC interrupt enable bit INT3 interrupt enable bit Timer 1 interrupt request bit Timer 2 interrupt request bit Timer 3 interrupt request bit Timer 4 interrupt request bit CRT interrupt request bit VSYNC interrupt request bit INT3 interrupt request bit Multi-master I C-BUS interface interrupt request bit Multi-master I C-BUS interface interrupt enable bit Fig. 7. Structure of interrupt-related registers

M37221EF-XXXSP,M37221EFSP MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOL TAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER TIMERS The M37221EF-XXXSP has 4 timers: timer 1, timer 2, timer 3, and timer 4. All timers are 8-bit timer with the 8-bit timer latch. The timer block diagram is shown in Figure 9. All of the timers count down and their divide ratio is 1/(n+1), where n is the value of timer latch. The value is set to a timer at the same time by writing a count value to the corresponding timer latch (addresses 00F0 16 to 00F316). The count value is decremented by 1. The timer interrupt request bit is set to “1” by a timer overflow at the next count pulse after the count value reaches “00 16”. (1) Timer 1 Timer 1 can select one of the following count sources:

f(XIN)/16
f(XIN)/4096 The count source of timer 1 is selected by setting bit 0 of the timer 12 mode register (address 00F4 16). Timer 1 interrupt request occurs at timer 1 overflow. (2) Timer 2 Timer 2 can select one of the following count sources:
f(XIN)/16
Timer 1 overflow signal
External clock from the P24/TIM2 pin The count source of timer 2 is selected by setting bits 4 and 1 of the timer 12 mode register (address 00F4 16). When timer 1 overflow signal is a count source for the timer 2, the timer 1 functions as an 8- bit prescaler. Timer 2 interrupt request occurs at timer 2 overflow. (3) Timer 3 Timer 3 can select one of the following count sources:
f(XIN)/16
External clock from the HSYNC pin
External clock from the P23/TIM3 pin The count source of timer 3 is selected by setting bits 5 and 0 of the timer 34 mode register (address 00F5 16) Timer 3 interrupt request occurs at timer 3 overflow. (4) Timer 4 Timer 4 can select one of the following count sources:
f(XIN)/16
f(XIN)/2
Timer 3 overflow signal The count source of timer 3 is selected by setting bits 4 and 1 of the timer 34 mode register (address 00F5 16). When timer 3 overflow signal is a count source for the timer 4, the timer 3 functions as an 8- bit prescaler. Timer 4 interrupt request occurs at timer 4 overflow. At reset, timers 3 and 4 are connected by hardware and “FF 16” is automatically set in timer 3; “0716” in timer 4. The f(XIN)/16 is se- lected as the timer 3 count source. The internal reset is released by timer 4 overflow at these state, the internal clock is connected. At execution of the STP instruction, timers 3 and 4 are connected by hardware and “FF 16” is automatically set in timer 3; “0716” in timer 4. However, the f(XIN)/16 is not selected as the timer 3 count source. So set bit 0 of the timer 34 mode register (address 00F516) to “0” before the execution of the STP instruction (f(XIN)/16 is selected as the timer 3 count source). The internal STP state is released by timer 4 overflow at these state, the internal clock is connected. Because of this, the program starts with the stable clock. The structure of timer-related registers is shown in Figure 8.

M37221EF-XXXSP,M37221EFSP MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER Fig. 8. Structure of timer-related registers Timer 2 count stop bit 0 : Count start 1 : Count stop Timer 12 mode register (T12M : address 00F416) Timer 1 count source selection bit 0 : f(X IN)/16 1 : f(XIN)/4096 Timer 2 count source selection bit 0 : Internal clock 1 : External clock from P24/TIM2 pin Timer 1 count stop bit 0 : Count start 1 : Count stop Timer 2 internal count source selection bit 0 : f(X IN)/16 1 : Timer 1 overflow Timer 34 mode register (T34M : address 00F5 16) Timer 3 count source selection bit 0 : f(XIN)/16 1 : External clock Timer 4 internal count source selection bit 0 : Timer 3 overflow 1 : f(X IN)/16 Timer 3 count stop bit 0 : Count start 1 : Count stop Timer 4 count stop bit 0 : Count start 1 : Count stop Timer 4 count source selection bit 0 : Internal clock 1 : f(XIN)/2 Timer 3 external count source selection bit 0 : External clock from P2 3/TIM3 pin 1 : External clock from HSYNC pin Fix this bit to “0.”

M37221EF-XXXSP,M37221EFSP MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOL TAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER Fig. 9. Timer block diagram Timer 1 (8) 1/2 1/8 Timer 1 latch (8) T12M0 T12M2 T12M4 T12M1 T12M3 Timer 2 (8) Timer 2 latch (8) Timer 3 (8) Timer 3 latch (8) Timer 4 (8) Timer 4 latch (8) Data bus Timer 1 interrupt request Timer 2 interrupt request T34M0 T34M2 T34M5 T34M4 T34M3 T34M1 XIN P24/TIM2 P23/TIM3 Selection gate : Connected to black colored side at reset T12M : Timer 12 mode register T34M : Timer 34 mode register Notes 1 : “H” pulse width of external clock inputs TIM2 and TIM3 needs 4 machine cycles or more. 2 : When the external clock source is selected, timers 2 and 3 are counted at a rising edge of input signal. 3 : In the stop mode or the wait mode, external clock inputs TIM2 and TIM3 cannot be used. FF16 0716 H SYNC Reset STP instruction Timer 3 interrupt request Timer 4 interrupt request

M37221EF-XXXSP,M37221EFSP MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER SERIAL I/O The M37221EF-XXXSP has a built-in serial I/O which can either trans- mit or receive 8-bit data in serial in the clock synchronous mode. The serial I/O block diagram is shown in Figure 10. The synchroniz- ing clock I/O pin (S CLK ), and data I/O pins (SOUT , SIN) also function as port P2. Bit 2 of the serial I/O mode register (address 00DC 16) selects whether the synchronizing clock is supplied internally or externally (from the 0/SCLK pin). When an internal clock is selected, bits 1 and 0 select whether f(XIN) is divided by 4, 16, 32, or 64. Bit 3 selects whether port P2 is used for serial I/O or not. To use the P22/SIN pin as the SIN pin, set the bit 2 of the port P2 direction register (address 00C516) to “0.” The operation of the serial I/O function is described below. The func- tion of the serial I/O differs depending on the clock source; external clock or internal clock. Fig. 10. Serial I/O block diagram Serial I/O shift register (8) Data bus Serial I/O interrupt request Selection gate : Connected to black colored side at reset.Synchronization circuit Frequency divider 1/81/4 1/16 SM1 SM0 Serial I/O counter (8) SM5: LSB MSB S SM2 SM6 XIN P22/SIN P21/SOUT P20/SCLK SM3 P21 latch P20 latch SM3 (Address 00DD16) SM : Serial I/O mode register Note: When the data is set in the serial I/O register (address 00DD16), the register functions as the serial I/O shift register. (Note)

M37221EF-XXXSP,M37221EFSP MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOL TAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER Serial I/O mode register (SM : address 00DC16) Internal synchronizing clock selection bits b1 b0 0 0 : f(X IN)/4 0 1 : f(XIN)/16 1 0 : f(XIN)/32 1 1 : f(XIN)/64 Synchronizing clock selection bit 0 : External clock 1 : Internal clock Serial I/O port selection bit 0 : P20, P21 functions as port 1 : SCLK , SOUT Fix this bit to “0.” Transfer direction selection bit 0 : LSB first 1 : MSB first Serial input pin selection bit 0 : Input signal from SIN pin 1 : Input signal from SOUT pin Internal clock—the serial I/O counter is set to “7” during write cycle into the serial I/O register (address 00DD16), and transfer clock goes “H” forcibly. At each falling edge of the transfer clock after the write cycle, serial data is output from the S OUT pin. Transfer direction can be selected by bit 5 of the serial I/O mode register. At each rising edge of the transfer clock, data is input from the S IN pin and data in the serial I/O register is shifted 1 bit. After the transfer clock has counted 8 times, the serial I/O counter becomes “0” and the transfer clock stops at “H.” At this time the inter- rupt request bit is set to “1.” External clock—when an external clock is selected as the clock source, the interrupt request is set to “1” after the transfer clock has counted 8 times. However, transfer operation does not stop, so con- trol the clock externally. Use the external clock of 1MHz or less with a duty cycle of 50%. The serial I/O timing is shown in Figure 12. When using an external clock for transfer, the external clock must be held at “H” for initializing the serial I/O counter. When switching between an internal clock and an external clock, do not switch during transfer. Also, be sure to ini- tialize the serial I/O counter after switching. Notes 1:On programming, note that the serial I/O counter is set by writing to the serial I/O register with the bit managing in- structions as SEB and CLB instructions. 2: When an external clock is used as the synchronizing clock, write transmit data to the serial I/O register at “H” of the transfer clock input level. Fig. 11. Structure of serial I/O mode register Fig. 12. Serial I/O timing (for LSB first) Synchroninzing clock Transfer clock Serial I/O register write signal Serial I/O output SOUT D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7 (Note) Serial I/O input SIN Note : When an internal clock is selected, the SOUT pin is at high-impedance after transfer is completed. Interrupt request bit is set to “1”

M37221EF-XXXSP,M37221EFSP MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER Fig. 13. Signals on serial I/O common transmission/reception mode Serial I/O Common Transmission/Reception Mode By writing “1” to bit 6 of the serial I/O mode register, signals SIN and SOUT are switched internally to be able to transmit or receive the serial data. Figure 13 shows signals on serial I/O common transmission/recep- tion mode. Note:When receiving the serial data after writing “FF 16” to the serial I/O register. Serial I/O shift register (8) “1” “0” ClockP20/SCLK P21/SOUT P22/SIN SM6 SM: Serial I/O mode register

Table 2. Multi-master I2C-BUS interface functionsMULTI-MASTER I 2C-BUS INTERFACE face and Table 2 shows multi-master I2C-BUS interface functions. control register, the I2C status register and other control circuits. ports (SCL1, SCL2, SDA1, SDA2).

M37221EF-XXXSP,M37221EFSP MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER (1) I2C Data Shift Register The I2C data shift register (S0 : address 00D716) is an 8-bit shift register to store receive data and write transmit data. When transmit data is written into this register, it is transferred to the outside from bit 7 in synchronization with the SCL clock, and each time one-bit data is output, the data of this register are shifted one bit to the left. When data is received, it is input to this register from bit 0 in synchronization with the SCL clock, and each time one-bit data is input, the data of this register are shifted one bit to the left. The I 2C data shift register is in a write enable status only when the ES0 bit of the I2C control register (address 00DA16) is “1.” The bit counter is reset by a write instruction to the I2C data shift register. When both the ES0 bit and the MST bit of the I2C status register (address 00D916) are “1,” the SCL is output by a write instruction to the I2C data shift register. Reading data from the I2C data shift regis- ter is always enabled regardless of the ES0 bit value. Note: To write data into the I2C data shift register after setting the MST bit to “0” (slave mode), keep an interval of 8 machine cycles or more. (2) I2C Address Register The I2C address register (address 00D816) consists of a 7-bit slave address and a read/write bit. In the addressing mode, the slave ad- dress written in this register is compared with the address data to be received immediately after the START condition are detected. n Bit 0: Read/write bit (RBW) Not used in the 7-bit addressing mode. In the 10-bit addressing mode, the first address data to be received is compared with the contents (SAD6 to SAD0 + RBW) of the I 2C address register. The RBW bit is cleared to “0” automatically when the stop condition is detected. n Bits 1 to 7: Slave address (SAD0–SAD6) These bits store slave addresses. Regardless of the 7-bit address- ing mode and the 10-bit addressing mode, the address data trans- mitted from the master is compared with the contents of these bits. (3) I2C Clock Control Register The I2C clock control register (address 00DB16) is used to set ACK control, SCL mode and SCL frequency. n Bits 0 to 4: SCL frequency control bits (CCR0–CCR4) These bits control the SCL frequency. Refer to Table 3. n Bit 5: SCL mode specification bit (FAST MODE) This bit specifies the SCL mode. When this bit is set to “0,” the stan- dard clock mode is set. When the bit is set to “1,” the high-speed clock mode is set. n Bit 6: ACK bit (ACK BIT) This bit sets the SDA status when an ACK clock ] is generated. When this bit is set to “0,” the ACK return mode is set and make SDA “L” at the occurrence of an ACK clock. When the bit is set to “1,” the ACK non-return mode is set. The SDA is held in the “H” status at the oc- currence of an ACK clock. However, when the slave address matches the address data in the reception of address data at ACK BIT = “0,” the SDA is automatically made “L” (ACK is returned). If there is a mismatch between the slave address and the address data, the SDA is automatically made “H”(ACK is not returned). ]ACK clock: Clock for acknowledgement n Bit 7: ACK clock bit (ACK) This bit specifies a mode of acknowledgment which is an acknowl- edgment response of data transmission. When this bit is set to “0,” the no ACK clock mode is set. In this case, no ACK clock occurs after data transmission. When the bit is set to “1,” the ACK clock mode is set and the master generates an ACK clock upon comple- tion of each 1-byte data transmission.The device for transmitting address data and control data releases the SDA at the occurrence of an ACK clock (make SDA “H”) and receives the ACK bit generated by the data receiving device. Note: Do not write data into the I 2C clock control register during transmitting. If data is written during transmitting, the I2C clock generator is reset, so that data cannot be transmitted nor- mally. Fig. 15. Structure of I 2C address register SAD6 SAD5 SAD4 SAD3 SAD2 SAD1 SAD0 RBW Slave address I2 C address register (S0D: address 00D816) Read/write bit

Table 3. Set values of I2C clock control register and SCL frequency number of bits specified with these bits are transmitted. the address data is always transmitted and received in 8 bits. When ES0 = “0,” the following is performed.

PIN = “1,” BB = “0” and AL = “0” are set (they are bits of the I2C status register at address 00D916 ).
Writing data to the I2C data shift register (address 00D716) is dis- abled. n Bit 4: Data format selection bit (ALS) This bit decides whether or not to recognize slave addresses. When this bit is set to “0,” the addressing format is selected, so that ad- dress data is recognized. When a match is found between a slave address and address data as a result of comparison or when a gen- eral call (refer to “(5) I 2C Status Register,” bit 1) is received, trans- mission processing can be performed. When this bit is set to “1,” the free data format is selected, so that slave addresses are not recog- nized. n Bit 5: Addressing format selection bit (10BIT SAD) This bit selects a slave address specification format. When this bit is set to “0,” the 7-bit addressing format is selected. In this case, only the high-order 7 bits (slave address) of the I 2C address register (ad- dress 00D816) are compared with address data. When this bit is set to “1,” the 10-bit addressing format is selected, all the bits of the I2C address register are compared with address data. n Bits 6 and 7: Connection control bits between I 2C-BUS interface and ports (BSEL0, BSEL1) These bits controls the connection between SCL and ports or SDA and ports (refer to Figure 17). SCL frequency (at φ = 4MHz, unit : kHz) Setting value of CCR4–CCR0 Standard clock mode Setting disabled Setting disabled Setting disabled Setting disabled Setting disabled 100 83.3 500/CCR value 17.2 16.6 16.1 High-speed clock mode Setting disabled Setting disabled Setting disabled 333 250 400(Note) 166 1000/CCR value 34.5 33.3 32.3 CCR4 CCR3 CCR2 CCR1 CCR0 Note: At 400 kHz in the high-speed clock mode, the duty is 40%. In the other cases, the duty is 50%. Fig. 16. Structure of I2C clock control register

M37221EF-XXXSP,M37221EFSP MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER (5) I2C Status Register The I2C status register (address 00D916) controls the I2C-BUS inter- face status. The low-order 4 bits are read-only bits and the high- order 4 bits can be read out and written to. n Bit 0: Last receive bit (LRB) This bit stores the last bit value of received data and can also be used for ACK receive confirmation. If ACK is returned when an ACK clock occurs, the LRB bit is set to “0.” If ACK is not returned, this bit is set to “1.” Except in the ACK mode, the last bit value of received data is input. The state of this bit is changed from “1” to “0” by execut- ing a write instruction to the I 2C data shift register (address 00D716). n Bit 1: General call detecting flag (AD0) This bit is set to “1” when a general call] whose address data is all “0” is received in the slave mode. By a general call of the master device, every slave device receives control data after the general call. The AD0 bit is set to “0” by detecting the STOP condition or START con- dition. ]General call: The master transmits the general call address “00 16” to all slaves. n Bit 2: Slave address comparison flag (AAS) This flag indicates a comparison result of address data. À In the slave receive mode, when the 7-bit addressing format is selected, this bit is set to “1” in one of the following conditions.

The address data immediately after occurrence of a START condition agrees with the slave address stored in the high-order 7 bits of the I 2C address register (address 00D816).
A general call is received. \` In the slave reception mode, when the 10-bit addressing format is selected, this bit is set to “1” with the following condition.
When the address data is compared with the I2C address register (8 bits consisted of slave address and RBW), the first bytes agree. ´ The state of this bit is changed from “1” to “0” by executing a write instruction to the I2C data shift register (address 00D716). Fig. 17. Connection port control by BSEL0 and BSEL1 Fig. 18. Structure of I2C control register “0” “1” BSEL0 SCL1/P11 SCL2/P12 “0” “1” BSEL1 “0” “1” BSEL0 SDA1/P1 SDA2/P1 4 “0” “1” BSEL1 Multi-master I2C-BUS interface SCL SDA BSEL1 BSEL0 10 BIT SAD ALS ES0 BC2 BC1 BC0 Connection control bits between I2C-BUS interface and ports b7 b6 Connection port 0 0 : None 0 1 : SCL1, SDA1 1 0 : SCL2, SDA2 1 1 : SCL1, SDA1, SCL2, SDA2 I 2C control register (S1D : address 00DA16) Bit counter (Number of transmit/receive bits) b2 b1 b0 0 0 0 : 8 0 0 1 : 7 0 1 0 : 6 0 1 1 : 5 1 0 0 : 4 1 0 1 : 3 1 1 0 : 2 1 1 1 : 1 I 2C-BUS interface use enable bit 0 : Disabled 1 : Enabled Data format selection bit 0 : Addressing format 1 : Free data format Addressing format selection bit 0 : 7-bit addressing format 1 : 10-bit addressing format

M37221EF-XXXSP,M37221EFSP MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOL TAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER n Bit 3: Arbitration lost] detecting flag (AL) In the master transmission mode, when the SDA is made “L” by any other device, arbitration is judged to have been lost, so that this bit is set to “1.” At the same time, the TRX bit is set to “0,” so that immedi- ately after transmission of the byte whose arbitration was lost is com- pleted, the MST bit is set to “0.” In the case arbitration is lost during slave address transmission, the TRX bit is set to “0” and the recep- tion mode is set. Consequently, it becomes possible to receive and recognize its own slave address transmitted by another master de- vice. ]Arbitration lost: The status in which communication as a master is disabled. n Bit 4: I 2C-BUS interface interrupt request bit (PIN) This bit generates an interrupt request signal. Each time 1-byte data is transmitted, the state of the PIN bit changes from “1” to “0.” At the same time, an interrupt request signal occurs to the CPU. The PIN bit is set to “0” in synchronization with a falling of the last clock (in- cluding the ACK clock) of an internal clock and an interrupt request signal occurs in synchronization with a falling of the PIN bit. When the PIN bit is “0,” the SCL is kept in the “0” state and clock generation is disabled. Figure 20 shows an interrupt request signal generating timing chart. The PIN bit is set to “1” in one of the following conditions.

Executing a write instruction to the I2C data shift register (address 00D7 16).
When the ES0 bit is “0”
At reset The conditions in which the PIN bit is set to “0” are shown below:
Immediately after completion of 1-byte data transmission (includ- ing when arbitration lost is detected)
Immediately after completion of 1-byte data reception
In the slave reception mode, with ALS = “0” and immediately after completion of slave address or general call address reception
In the slave reception mode, with ALS = “1” and immediately after completion of address data reception n Bit 5: Bus busy flag (BB) This bit indicates the status of use of the bus system. When this bit is set to “0,” this bus system is not busy and a START condition can be generated. When this bit is set to “1,” this bus system is busy and the occurrence of a START condition is disabled by the START condi- tion duplication prevention function (Note). This flag can be written by software only in the master transmission mode. In the other modes, this bit is set to “1” by detecting a START condition and set to “0” by detecting a STOP condition. When the ES0 bit of the I 2C control register (address 00DA16) is “0” and at reset, the BB flag is kept in the “0” state. n Bit 6:Communication mode specification bit (transfer direction specification bit: TRX) This bit decides a direction of transfer for data communication. When this bit is “0,” the reception mode is selected and the data of a trans- mitting device is received. When the bit is “1,” the transmission mode is selected and address data and control data are output onto the SDA in synchronization with the clock generated on the SCL. When the ALS bit of the I 2C control register (address 00DA16) is “0” in the slave reception mode is selected, the TRX bit is set to “1” (transmit) if the least significant bit (R/W bit) of the address data trans- mitted by the master is “1.” When the ALS bit is “0” and the R/W bit is “0,” the TRX bit is cleared to “0” (receive). The TRX bit is cleared to “0” in one of the following conditions.
When arbitration lost is detected.
When a STOP condition is detected.
When occurence of a START condition is disabled by the START condition duplication preventing function (Note).
With MST = “0” and when a START condition is detected.
With MST = “0” and when ACK non-return is detected.
At reset n Bit 7: Communication mode specification bit (master/slave speci- fication bit: MST) This bit is used for master/slave specification for data communica- tion. When this bit is “0,” the slave is specified, so that a START condition and a STOP condition generated by the master are re- ceived, and data communication is performed in synchronization with the clock generated by the master. When this bit is “1,” the master is specified and a START condition and a STOP condition are gener- ated, and also the clocks required for data communication are gen- erated on the SCL. The MST bit is cleared to “0” in one of the following conditions.
Immediately after completion of 1-byte data transmission when ar- bitration lost is detected
When a STOP condition is detected.
When occurence of a START condition is disabled by the START condition duplication preventing function (Note).
At reset Note: The START condition duplication prevention function disables the occurence of a START condition, reset of bit counter and SCL output when the following condition is satisfied:
a START condition is set by another master device.

for setting the MST bit and the TRX bit to “1” and the BB bit to “0”. tion/STOP condition generating timing table. Table 4. START condition/STOP condition generating timing table notes the number of φ cycles.

Table 5. START condition/STOP condition detecting conditions fied, a START/STOP condition can be detected. notes the number of φ cycles. dress communication formats is described below. format is selected, refer to Figure 24, (1) and (2). data but also is processed as an address data bit.

M37221EF-XXXSP,M37221EFSP MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER ¯ •When all transmitted addresses are “0” (general call) AD0 of the I2C status register (address 00D916) is set to “1” and an interrupt request signal occurs.

When the transmitted addresses match the address set in À AAS of the I2C status register (address 00D916) is set to “1” and an interrupt request signal occurs.
In the cases other than the above AD0 and AAS of the I2C status register (address 00D916) are set to “0” and no interrupt request signal occurs. ˘ Set dummy data in the I2C data shift register (address 00D716). ˙ When receiving control data of more than 1 byte, repeat step ˘ . ¨ When a STOP condition is detected, the communication ends. When the first-byte address data matches the slave address, the AAS bit of the I2C status register (address 00D916) is set to “1.” After the second-byte address data is stored into the I2C data shift register (address 00D716), make an address comparison between the sec- ond-byte data and the slave address by software. When the address data of the 2nd byte matches the slave address, set the RBW bit of the I 2C address register (address 00D816) to “1” by software. This__ processing can match the 7-bit slave address and R/W data, which are received after a RESTART condition is detected, with the value of the I 2C address register (address 00D816). For the data transmis- sion format when the 10-bit addressing format is selected, refer to Figure 24, (3) and (4). (10) Example of Master Transmission An example of master transmission in the standard clock mode, at the SCL frequency of 100 kHz and in the ACK return mode is shown below. À Set a slave address in the high-order 7 bits of the I2C address register (address 00D816) and “0” in the RBW bit. \ Set the ACK return mode and SCL = 100 kHz by setting “8516” in the I2C clock control register (address 00DB16). ´ Set “1016” in the I2C status register (address 00D916) and hold the SCL at the “H” level. ˆ Set a communication enable status by setting “4816” in the I2C control register (address 00DA16). ˜ Set the address data of the destination of transmission in the high- order 7 bits of the I 2C data shift register (address 00D716) and set “0” in the least significant bit. ¯ Set “F016” in the I2C status register (address 00D916) to generate a START condition. At this time, an SCL for 1 byte and an ACK clock automatically occurs. ˘ Set transmit data in the I2C data shift register (address 00D716). At this time, an SCL and an ACK clock automatically occurs. ˙ When transmitting control data of more than 1 byte, repeat step ˘ . ¨ Set “D016” in the I2C status register (address 00D916). After this, if ACK is not returned or transmission ends, a STOP condition occurs. (11) Example of Slave Reception An example of slave reception in the high-speed clock mode, at the SCL frequency of 400 kHz, in the ACK non-return mode and using the addressing format is shown below. À Set a slave address in the high-order 7 bits of the I2C address register (address 00D816) and “0” in the RBW bit. \ Set the no ACK clock mode and SCL = 400 kHz by setting “2516” in the I2C clock control register (address 00DB16). ´ Set “1016” in the I2C status register (address 00D916) and hold the SCL at the “H” level. ˆ Set a communication enable status by setting “4816” in the I2C control register (address 00DA16). ˜ When a START condition is received, an address comparison is made.

M37221EF-XXXSP,M37221EFSP MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER LSB Table 6.Relation between the low-order 6-bit data and high-level area increase interval Area longer by τ than that of other tm (m = 0 to 63) Nothing m = 32 m = 16, 48 m = 8, 24, 40, 56 m = 4, 12, 20, 28, 36, 44, 52, 60 m = 2, 6, 10, 14, 18, 22, 26, 30, 34, 38, 42, 46, 50, 54, 58, 62 Low-order 6 bits of data 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 Fig. 25. PWM block diagram PWM1 register (Address : 00D116) 1/2XIN PWM timing generating circuit PWM register (Address : 00D016) b7 b0 8-bit PWM circuit PN3 P00 PW2 D0 0 PWM0 P01 PW3 D0 1 PWM1 P02 PW4 D0 2 PWM2 P03 PW5 D0 3 PWM3 P04 PW6 D0 4 PWM4 P05 PW7 D0 5 PWM5 14-bit PWM circuit PN2 PN4 PW1 DA MSB DA-H register (Address : 00CE16) DA latch (14 bits) DA-L register (Note) (Address : 00CF16) LSB 6 14 D-A PWM2 register (Address : 00D216) PWM3 register (Address : 00D316) PWM4 register (Address : 00D416) PWM5 register (Address : 00F616) Data bus P0 : Port P0 register D0 : Port P0 direction register PW0 b7 b0 Inside of with the others. is as same contents PW : PWM output control register 1 PN : PWM output control register 2 Selection gate : Connected to black colored side when reset. Pass gate : Note : The DA-L register also functions as the low-order 6 bits of the DA latch.

M37221EF-XXXSP,M37221EFSP MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOL TAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER Fig. 26. 8-bit PWM timing (a) Pulses showing the weight of each bit 1 3 5 7 9 20 30 40 50 60 70 80 90 100 110 120 130 140 150 160 170 180 190 200 210 220 230 240 250 255 4 12 20 28 36 44 52 60 68 76 84 92 100 108 116 124 132 140 148 156 164 172 180 188 196 204 212 220 228 236 244 252 16 48 80 112 144 176 208 240 24 40 56 72 88 104 120 136 152 168 184 200 216 232 248 32 96 160 224 64 192 Bit 7 2 6 10 14 18 22 26 30 34 38 42 46 50 54 58 62 66 70 74 78 82 86 90 94 98 102 106 110 114 118 122 126 130 134 138 142 146 150 154 158 162 166 170 174 178 182 186 190 194 198 202 206 210 214 218 222 226 230 234 238 242 246 250 254 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 128 Bit 0 PWM output t = 4 ms T = 1024 ms f(XIN) = 8 MHz (b) Example of 8-bit PWM t 0016 (0) 0116 (1) 1816 (24) FF16 (255) T = 256 t

M37221EF-XXXSP,M37221EFSP MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER Fig. 27. 14-bit PWM output example (f(XIN) = 8 MHz) 0.25ms b7 b0b6 b5 b4 b3 b2 b1 0 0010110 b13 b6 0010110 b0b5 101000 Set “2C16” to DA-H register. [DA-H register] D H At writing of DA-L b0b6 b5 b4 b3 b2 b1 010100 Set “2816” to DA-L register. [DA-L register] D L At writing of DA-L Undefined These bits decide “H” level area of fundamental waveform. These bits decide smaller interval “tm” in which “H” leval area is [“H” level area of fundamental waveform + t ]. = High-order 8-bit value of DA latch5“H” level area of fundamental waveform FF 00 D3FE FD … D6 D4 02 01D5 14-bit PWM output 8-bit counter 0.25ms5 44 FF 00 D3FE FD D6 D4 02 01D5 14-bit PWM output 8-bit counter 0.25ms5 45 Fundamental waveform Waveform of smaller interval “tm” specified by low-order 6 bits Fundamental waveform of smaller interval “tm” which is not specified by low-order 6 bits is not changed. 14-bit PWM output Low-order 6-bit output of DA latch 0.25ms5 44 t = 0.25ms T = 4096ms Repeat period t0 t1 t2 t3 t4 t5 t59 t60 t61 t62 t63 [DA latch] 2C 2B 2A 03 02 01 00 2C 2B 2A 03 02 01 00…… Minimum resolution bit width 0.25ms … …

M37221EF-XXXSP,M37221EFSP MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOL TAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER Fig. 28. Structure of PWM-related registers DA, PWM count source selection bit 0 : Count source supply 1 : Count source stop DA/PN 4 output selection bit 0 : DA output 1 : PN 4 output P00/PWM0 output selection bit 0 : P00 output 1 : PWM0 output P01/PWM1 output selection bit 0 : P01 output 1 : PWM1 output PWM output control register 1 (PW: address 00D516) P02/PWM2 output selection bit 0 : P02 output 1 : PWM2 output P03/PWM3 output selection bit 0 : P03 output 1 : PWM3 output P04/PWM4 output selection bit 0 : P04 output 1 : PWM4 output P05/PWM5 output selection bit 0 : P05 output 1 : PWM5 output PWM output control register 2 (PN: address 00D616) DA output polarity selection bit 0 : Positive polarity 1 : Negative polarity PWM output polarity selection bit 0 : Positive polarity 1 : Negative polarity DA general-purpose output bit 0 : Output “L” 1 : Output “H”

M37221EF-XXXSP,M37221EFSP MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER Storage bit of comparison result 0 : Input voltage < reference voltage 1 : Input voltage > reference voltage A-D control register 1 (AD1: address 00EE 16) Analog input pin selection bits b2 b1 b0 0 0 0 : A-D1 0 0 1 : A-D2 0 1 0 : A-D3 0 1 1 : A-D4 1 0 0 : A-D5 1 0 1 : A-D6 1 1 0 : 1 1 1 : Do not set. A-D control register 1 Bits 0 to 2 Comparator control Data bus Bit 4 Switch tree A-D control register 2 Resistor ladder Compa- rator Analog signal switch Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 A-D control register 1P15/A-D1/INT3 P16/A-D2 P17/A-D3 P06/INT2/A-D4 P30/A-D5/DA1 P31/A-D6/DA2 A-D control register 2 (AD2: address 00EF16) /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines D-A converter set bits Refer to Table 7. A-D control register 2 Bit 1 Bit 0 A-D COMPARATOR A-D comparator consists of 6-bit D-A converter and comparator. A-D comparator block diagram is shown in Figure 31. The reference voltage “V ref” for D-A conversion is set by bits 0 to 5 of the A-D control register 2 (address 00EF16). The comparison result of the analog input voltage and the reference voltage “V ref” is stored in bit 4 of the A-D control register 1 (address 00EE 16). For A-D comparison, set “0” to corresponding bits of the direction register to use ports as analog input pins. Write the data for select of analog input pins to bits 0 to 2 of the A-D control register 1 and write the digital value corresponding to V ref to be compared to the bits 0 to 5 of the A-D control register 2. The voltage comparison starts by writing to the A-D control register 2, and it is completed after 16 ma- chine cycles (NOP instruction 5 8). Table 7.Relation between contents of A-D control register 2 and reference voltage “V ref” Bit 4 Bit 3 Bit 2 Bit 5 1/128 V CC 3/128 VCC 5/128 VCC 123/128 VCC 125/128 VCC 127/128 VCC Reference voltage “Vref” Fig. 29. Structure of A-D control register 1 Fig.30. Structure of A-D control register 2 Fig. 31. A-D comparator block diagram

The M37221EF-XXXSP has 2 D-A converters with 6-bit resolution. D-A converter block diagram is shown in Figure 34. mal number) in the DA conversion register. buffer when driving a low-impedance load. Table 8. Relation between contents of D-A conversion register and

M37221EF-XXXSP,M37221EFSP MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOL TAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER Fig. 37. Block diagram of CRT display control circuit CRT control register (Address 00EA16) Vertical position registers (Addresses 00E116, 00E216) Character size register (Address 00E416) Horizontal position register (Address 00E016) Border selection register (Address 00E516) Display oscillation circuit OSC1 OSC2 Display position control circuit H SYNC VSYNC Display control circuit RAM for display 10 bits 5 24 5 2 Color registers (Addresses 00E616 to 00E916) CRT port control register (Address 00EC16) Data bus ROM for display 12 bits 5 16 5 256 Shift register 12 bits Shift register 12 bits Output circuit R G B OUT1 OUT2

M37221EF-XXXSP,M37221EFSP MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER (2) Display Position The display positions of characters are specified in units called a “block.” There are 2 blocks, block 1 and block 2. Up to 20 characters can be displayed in each block (refer to (4) Memory for Display). The display position of each block can be set in both horizontal and vertical directions by software. The display position in the horizontal direction can be selected for all blocks in common from 64-step display positions in units of 4T C (TC = oscillating cycle for display). The display position in the vertical direction for each block can be selected from 128-step display positions in units of 4 scanning lines. Block 2 is displayed after the display of block 1 is completed (refer to Figure 38 (a)). Accordingly, if the display of block 2 starts during the display of block 1, only block 1 is displayed. Similarly, when multiline display, block 1 is displayed after the display of block 2 is completed (refer to Figure 38 (b)). The vertical position can be specified from 128-step positions (4 scan- ning lines per a step) for each block by setting values “00 16” to “7F16” to bits 0 to 6 in the vertical position register (addresses 00E116 and 00E216). Figure 40 shows the structure of the vertical position regis- ter. Fig. 38. Display position (HR) CV1 CV2 Block 1 Block 2 (a) Example when each block is separated CV1 CV2 Block 1 Block 2 Block 1 (second) CV1 No display No display (b) Example when block 2 overlaps with block 1

M37221EF-XXXSP,M37221EFSP MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOL TAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER The horizontal position is common to all blocks, and can be set in 64 steps (where 1 step is 4TC , TC being the display oscillation period) as values “0016” to “3F16” in bits 0 to 5 of the horizontal position register (address 00E016). The structure of the horizontal position register is shown in Figure 41. The display position in the vertical direction is determined by count- ing the horizontal sync signal (HSYNC ). At this time, it starts to count the rising edge (falling edge) of HSYNC signal from after about 1 ma- chine cycle of rising edge (falling edge) of VSYNC signal. So interval from rising edge (falling edge) of VSYNC signal to rising edge (falling edge) of HSYNC signal needs enough time (2 machine cycles or more) for avoiding jitter. The polarity of HSYNC and VSYNC signals can se- lect with the CRT port control register (address 00EC16). For details. refer to (8) CRT Output Pin Control. Note: When bits 0 and 1 of the CRT port control register (address 00EC 16) are set to “1” (negative polarity), the vertical position is determined by counting falling edge of HSYNC signal after rising edge of VSYNC control signal in the microcomputer (re- fer to Figure 39). Fig. 39. Supplement explanation for display position Fig. 40. Structure of vertical position register Fig. 41. Structure of horizontal position register When bits 0 and 1 of the CRT port control register (address 00EC 16) are set to “1” (negative polarity) VSYNC signal input VSYNC control signal in microcomputer 0.125 to 0.25 [µs] ( at f(X IN) = 8MHz) Period of counting H SYNC signal /LiteDiagLines/LiteDiagLines/LiteDiagLines (Note) H SYNC signal input Not count 12345 Note: Do not generate falling edge of HSYNC signal near rising edge of VSYNC control signal in microcomputer to avoid jitter. Vertical position registers 1, 2 (CV1 : address 00E116) (CV2 : address 00E216) Vertical display start positions 128 steps from “0016” to “7F16” Horizontal position register (HR : address 00E0 16) Horizontal display start positions 64 steps from “0016” to “3F16” (1 step is 4TC)

ture of the character size register. C ) in the width (horizontal) direction. position is common to all blocks even when the character size varies with each block (refer to Figure 43). Table 10. Relation between set values in character size register and character sizes

M37221EF-XXXSP,M37221EFSP MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOL TAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER (4) Memory for Display There are 2 types of display memory : CRT display ROM (addresses 1000016 to 11FFF16) used to store character dot data (masked) and CRT display RAM (addresses 060016 to 06B716) used to specify the colors of characters to be displayed. The following describes each type of display memory. À ROM for display (addresses 1000016 to 11FFF16) The CRT display ROM contains dot pattern data for characters to be displayed. For characters stored in this ROM to be actually displayed, it is necessary to specify them by writing the character code inherent to each character (code determined based on the addresses in the CRT display ROM) into the CRT display RAM. The character code list is shown in Table 11. The CRT display ROM has a capacity of 8 K bytes. Since 32 bytes are required for 1 character data, the ROM can stores up to 256 kinds of characters. The CRT display ROM space is broadly divided into 2 areas. The [vertical 16 dots] 5 [horizontal (left side) 8 dots] data of display char- acters are stored in addresses 10000 16 to 107FF16 and 1100016 to 117FF 16; the [vertical 16 dots] 5 [horizontal (right side) 4 dots] data of display characters are stored in addresses 1080016 to 10FFF16 and 1180016 to 11FFF16 (refer to Figure 44). Note however that the high-order 4 bits in the data to be written to addresses 1080016 to 10FFF 16 and 1180016 to 11FFF16 must be set to “1” (by writing data “FX16”). Fig. 44. Display character stored data 10XX0 16 80016 or 11XX0 16 80016 0000000 0000000 0000010 0000101 0001000 0001000 0001000 0010000 111100 1 0100000 0100000 0100000 0000000 0000101 0000010 01111 000 0000 0000 0000 0000 0000 0000 0100 010 0 0100 0010 0010 0010 0000 0000 0000 10XXF 16 80016 or 11XXF 16 80016 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 b7 b0 b7 b0 b3 10XX0 16 or 11XX0 16 10XXF 16 or 11XXF 16 00000

contents of the CRT display RAM. register No. to the low-order 2 bits (bits 0 and 1) in address 068016. CRT display RAM is shown in Figure 45. Table 12. Contents of CRT display RAM Table 11. Character code list (partially abbreviated)

M37221EF-XXXSP,M37221EFSP MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOL TAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER Fig. 45. Structure of CRT display RAM [Color specification] 0 0 : Specifying color register 0 0 1 : Specifying color register 1 1 0 : Specifying color register 2 1 1 : Specifying color register 3 Color register specification Block 1 [Character specification] Specify 256 characters (“0016” to “FF16”) Character code Block 2 [Character specification] 1st character : 062016 063716 1st character : 068016 24th character : 069716 1st character : 060016 24th character : 061716 [Color specification] 1st character : 06A016 24th character : 06B716 to to to to Specify 256 characters (“0016” to “FF16”) Character code 0 0 : Specifying color register 0 0 1 : Specifying color register 1 1 0 : Specifying color register 2 1 1 : Specifying color register 3 Color register specification 24th character :

M37221EF-XXXSP,M37221EFSP MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER Color register 0, 1, 2, 3 (CO0 : address 00E616) (CO1 : address 00E716) (CO2 : address 00E816) (CO3 : address 00E916) B signal output selection bit 0 : No character is output 1 : Character is output G signal output selection bit 0 : No character is output 1 : Character is output R signal output selection bit 0 : No character is output 1 : Character is output B signal output (background) selection bit (Note 1) 0 : No background color is output 1 : Background color is output G signal output (background) selection bit 0 : No background color is output 1 : Background color is output OUT1 signal output control bit (Notes 1,2) 0 : Character is output 1 : Blank is output R signal output (background) selection bit (Note 2) 0 : No background color is output 1 : Background color is output Notes 1 : When bit 5 = “0” and bit 4 = “1,” there is output same as a character or border output from the OUT1 pin. Do not set bit 5 = “0” and bit 4 = “0.” When only bit 7 = “1” and bit 5 = “0,” there is output from the OUT2 pin. 2 : (5) Color Registers The color of a displayed character can be specified by setting the color to one of the 4 registers (CO0 to CO3: addresses 00E616 to 00E9 16) and then specifying that color register with the CRT display RAM. There are 3 color outputs; R, G and B. By using a combination of these outputs, it is possible to set 2 3–1 (when no output) = 7 col- ors. However, since only 4 color registers are available, up to 4 col- ors can be disabled at one time. R, G and B outputs are set by using bits 1 to 3 in the color register. Bit 5 is used to specify whether a character output or blank output. Figure 46 shows the structure of the color register. Fig. 46. Structure of color registers

Table 13. Display example of character background coloring (when green is set for a character and blue is set for background color) color (green) are not mixed. color (green) are not mixed. background is not displayed.

00 No output

background is not displayed. Notes1 :When COn 5 = “0” and COn4 = “1,” there is output same as a character or border output from the OUT1 pin. 2 : When only COn7 = “1” and COn5 = “0,” there is output from the OUT2 pin. 3 :The portion “A” in which character dots are displayed is not mixed with any TV video signal. 4 :The wavy-lined arrows in the Table denote video signals.

1 Border including character

Table 14. Relationship between set value in border selection register and character border function

M37221EF-XXXSP,M37221EFSP MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOL TAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER (7) Multiline Display The M37221EF-XXXSP can ordinarily display 2 lines on the CRT screen by displaying 2 blocks at different vertical positions. In addi- tion, it can display up to 16 lines by using CRT interrupts. A CRT interrupt request occurs at the point at which display of each block has been completed. In other words, when a scanning line reaches the point of the display position (specified by the vertical position registers) of a certain block, the character display of that block starts, and an interrupt occurs at the point at which the scan- ning line exceeds the block. Note: A CRT interrupt does not occur at the end of display when the block is not displayed. In other words, if a block is set to off display with the display control bit of the CRT control reg- ister (address 00EA 16), a CRT interrupt request does not occur (refer to Figure 49). Fig. 49. Timing of CRT interrupt request Block 1 (on display) “CRT interrupt request” On display (CRT interrupt request occurs at the end of block display) Block 2 (on display) Block 1' (on display) Block 2' (on display) “CRT interrupt request” “CRT interrupt request” “CRT interrupt request” Block 1 (on display) “CRT interrupt request” Off display (CRT interrupt request does not occur at the end of block display) Block 2 (on display) Block 1' (off display) Block 2' (off display) “CRT interrupt request” No “CRT interrupt request” No “CRT interrupt request”

M37221EF-XXXSP,M37221EFSP MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines A'A /LiteDiagLines /LiteDiagLines “RED” “BLUE” H SYNC R B OUT1 Signals across A – A' (8) CRT Output Pin Control The CRT output pins R, G, B, and OUT1 can also function as ports P52, P53, P54 and P55. Set the corresponding bit of the port P5 di- rection register (address 00CB16) to “0” to specify these pins as CRT output pins, or set it to “1” to specify it as an general-purpose port P5 pins. The OUT2 pin can also function as port P1 0. Set bit 7 of the CRT control register (address 00EA16) to “0” to specify it as port P10, set it to “1” to specify it as OUT2 pin. The input polarity of signals H SYNC and VSYNC and output polarity of signals R, G, B, and OUT1 can be specified with the bits of the CRT port control register (address 00EC 16) . Set a bit to “0” to specify positive polarity; set it to “1” to specify negative polarity. The struc- ture of the CRT port control register is shown in Figure 50. (9) Raster Coloring Function An entire screen (raster) can be colored by setting the bits 5 to 7 of the CRT port control register. Since each of the R, G, and B pins can be switched to raster coloring output, 7 raster colors can be obtained. If the R, G, and B pins have been set to MUTE signal output, a raster coloring signal is output in the part except a no-raster colored char- acter (in Figure 51, a character “O”) during 1 horizontal scanning period. This ensures that character colors do not mix with the raster color. In this case, MUTE signal is output from the OUT1 pin. An example in which a magenta character “I” and a red character “O” are displayed with blue raster coloring is shown in Figure 51. Fig. 51. Example of raster coloring Fig. 50. Structure of CRT port control register CRT port control register (CRTP : address 00EC16) H SYNC input polarity switch bit 0 : Positive polarity 1 : Negative polarity R signal output switch bit 0 : R signal output 1 : MUTE signal output V SYNC input polarity switch bit 0 : Positive polarity 1 : Negative polarity R, G, B output polarity switch bit 0 : Positive polarity 1 : Negative polarity OUT1 output polarity switch bit 0 : Positive polarity 1 : Negative polarity G signal output switch bit 0 : G signal output 1 : MUTE signal output B signal output switch bit 0 : B signal output 1 : MUTE signal output OUT2 output polarity switch bit 0 : Positive polarity 1 : Negative polarity

select one of the following 4 types.

Main clock supplied from the XIN pin
Main clock supplied from the XIN pin divided by 1.5
Clock from the LC or RC supplied from the pins OSC1 and OSC2.
Clock from the ceramic resonator or quartz-crystal oscillator sup- plied from the pins OSC1 and OSC2. This clock for display can be selected for each block by the CRT clock selection register (address 00ED 16). When selecting the main clock, set the oscillation frequency to 8 MHz.

Table 15. Set value of CRT clock selection register and clock for display The clock for display is supplied by connecting RC or LC across the pins OSC1 and OSC2. The clock for display is supplied by connecting the following across the pins OSC1 and OSC2.

a ceramic resonator only for CRT display and a feedback resistor
a quartz-crystal oscillator only for CRT display and a feedback resistor (Note) Note: It is necessary to connect other ceramic resonator or quartz-crystal oscillator across the pins X IN and XOUT . Fig. 52. Structure of CRT clock selection register CRT oscillation frequency = f(XIN) CRT oscillation frequency = f(XIN)/1.5

M37221EF-XXXSP,M37221EFSP MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER Fix these bits to “ 0.” ROM correction enable register (RCR : address 021B16) 0 : Disabled 1 : Enabled 0 : Disabled 1 : Enabled Block 1 enable bit Block 2 enable bit ROM CORRECTION FUNCTION This can correct ROM data in ROM (64K bytes). Up to 2 addresses (2 blocks) can be corrected, a program for correction is stored in the ROM memory for correction. The ROM memory for correction is 32 bytes 5 2 blocks. Block 1 : addresses 02C0 16 to 02DF16 Block 2 : addresses 02E016 to 02FF16 Set an address of ROM data to be corrected into the ROM correction address. When the value of the counter matches the ROM data ad- dress in the ROM correction address, the main program branches to the program for correction stored in the ROM memory for correction. To return from the program for correction to the main program, the op code and operand of the JMP instruction (total of 3 bytes) is needed at the end of the program for correction. In the case that the blocks 1 and 2 are used in series, the above instruction is not needed at the end of the block 1. The ROM correction function is controlled by the ROM correction enable register. Notes 1 : Specify the first address (op code address) of each instruction as ROM correction address. 2 :Use the JMP instruction (total of 3 bytes) to return from the main program to the program for correction. 3 :Do not set the same ROM correction address to the blocks 1 and 2. Fig. 54. Structure of ROM correction enable register Fig. 53. ROM correction addresses 021716ROM correction address 1 (high-order) 021816ROM correction address 1 (low-order) 021916ROM correction address 2 (high-order) 021A16ROM correction address 2 (low-order)

internal state of microcomputer at reset are shown in Figure 57. An example of the reset circuit is shown in Figure 55. source voltage surpasses 4.5 V. Figure 56. It starts the program from the address formed by using the Notes 1 : f(XIN) and f( φ ) are in the relation : f(XIN) = 2·f ( φ ). depends on the previous state.

M37221EF-XXXSP,M37221EFSP MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER Fig. 57. Internal state of microcomputer at reset 0016Port P0 direction register 0016 0016 DA-L register PWM output control register 1 0016 I2C status register I2C control register 0016 I2C clock control register 0016 Serial I/O mode register I2C address register Port P1 direction register Port P2 direction register Port P5 Port P5 direction register Port P3 output mode control register PWM output control register 2 000 00 0 00 0 000 Port P3 direction register 0016 0100000 000000 0 (00C116) (00C316) (00C516) (00C716) (00CA16) (00CB16) (00CD16) (00CF16) (00D516) (00D616) (00D816) (00D916) (00DA16) (00DB16) (00DC16) Address Contents of register Address Contents of register Note : The contents of all other registers and RAM are undefined at reset, so set their initial values. ] : Undefined : Unused bit (00E616)Color register 0 Color register 1 Color register 2 Color register 3 (00E716) (00E816) (00E916) 00 00 000 00 00 000 00 00 000 00 00 000 Horizontal register Border selection register Vertical position register 1 Character size register Vertical position register 2 00000 0(00E016) (00E116) (00E216) (00E416) (00E516) DA1 conversion register (00DE16) DA2 conversion register (00DF16) CRT control register CRT port control register CRT clock selection register A-D control register 1 CPU mode register 0716 Timer 12 mode register Interrupt input polarity register Interrupt request register 1 Timer 1 FF16 0716 A-D control register 2 Timer 2 Timer 3 Timer 4 Timer 34 mode register Interrupt request register 2 Interrupt control register 1 Interrupt control register 2 (00EA16) (00EC16) (00ED16) (00EE16) (00EF16) (00F016) (00F116) (00F216) (00F316) (00F416) (00F516) (00F916) (00FB16) (00FC16) (00FD16) (00FE16) (00FF16) 00 00 00 00 000 000 000000 FF16 00000 000000 000 0000 00 00 0000 00000 000 0000 Processor status register Program counter (PS) (PCH ) (PCL) Contents of addressFFFF16 Contents of addressFFFE16 0016 ROM correction address 1 (high-order) 0016 0016ROM correction address 1 (low-order) ROM correction address 2 (high-order) ROM correction address 2 (low-order) (021716) (021816) (021916) (021A16) 0016 ROM correction enable register(021B16) 00 ]]] ]]]]]] ]]]]] ] ]]]]]] ]]]] ]]] ] ]]]]]]] ]]] ] ]]]]] ]]

M37221EF-XXXSP,M37221EFSP MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOL TAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER Fig. 58. I/O pin block diagram (1) Ports P1, P2, P30, P31 Data bus Direction register Port latch Ports P00–P05, P32 Data bus Direction register Port latch Ports P06, P07 Data bus Direction register Port latch N-channel open-drain output Ports P06, P07 Note: Each port is also used as below: P06 : INT2/A-D4 P07 : INT1 N-channel open drain output Ports P00–P0 5, P32 Note: Each port is also used as below: P00–P0 5 : PWM0–PWM5 CMOS output Ports P1, P2, P30, P31 Note: Each port is also used as below: P10 : OUT2 P11 : SCL1 P12 : SCL2 P13 : SDA1 P14 : SDA2 P15 : A-D1/INT3 P16 : A-D2 P17 : A-D3 P20 : SCLK P21 : SOUT P22 : SIN P23 : TIM3 P24 : TIM2 P30 : A-D5/DA1 P31 : A-D6/DA2

M37221EF-XXXSP,M37221EFSP MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER CMOS output D-A, R, G, B, OUT1, OUT2 Note: Each pin is also used as below: R : P5 G : P53 B : P54 OUT1 : P55 OUT2 : P10 Fig. 59. I/O pin block diagram (2) Internal circuit D-A, R, G, B, OUT1, OUT2H SYNC , VSYNC Internal circuit Schmidt input HSYNC , VSYNC

M37221EF-XXXSP,M37221EFSP MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER Interrupt request Interrupt disable flag I Reset SQ RSTP instruction SQ RWIT instruction SQ R STP instruction Reset Internal clock 1/2 1/8 Timer 3 Timer 4 XOUTXIN T34M0 T34M2 Selection gate : Connected to black colored side at reset. T34M : Timer 34 mode register CLOCK GENERATING CIRCUIT The built-in clock generating circuit is shown in Figure 62. When the STP instruction is executed, the internal clock stops at “H” level. At the same time, timers 3 and 4 are connected in hardware and “FF 16” is set in the timer 3, “0716” is set in the timer 4. Select f(XIN)/16 as the timer 3 count source (set bit 0 of the timer 34 mode register to “0” before the execution of the STP instruction). And besides, set the timer 3 and timer 4 interrupt enable bits to disabled (“0”) before ex- ecution of the STP instruction). The oscillator restarts when external interrupt is accepted, however, the internal clock keeps its “H” level until timer 4 overflows. Because this allows time for oscillation stabi- lizing when a ceramic resonator or a quartz-crystal oscillator is used. When the WIT instruction is executed, the internal clock stops in the “H” level but the oscillator continues running. This wait state is released when an interrupt is accepted (Note). Since the oscillator does not stop, the next instruction can be executed at once. When returning from the stop or the wait state, to accept an interrupt, set the corresponding interrupt enable bit to “1” before executing the STP or the WIT instructions. Note: In the wait mode, the following interrupts are invalid. (1) V SYNC interrupt (2) CRT interrupt (3) f(X IN)/4096 interrupt (4) Timer 1 interrupt using f(XIN)/4096 as count source (5) Timer 2 interrupt using P24/TIM2 pin input as count source (6) Timer 3 interrupt using P23/TIM3 pin input as count source (7) Timer 4 interrupt using f(XIN)/2 as count source (8) Multi-master I2C-BUS interface interrupt The circuit example using a ceramic resonator (or a quartz-crystal oscillator) is shown in Figure 60. Use the circuit constants in accor- dance with the resonator manufacture’s recommended values. The circuit example with external clock input is shown in Figure 61. Input the clock to the X IN pin, and open the XOUT pin. Fig. 62. Clock generating circuit block diagram Fig. 61. External clock input circuit example Fig. 60. Ceramic resonator circuit example XIN XOUT CIN M37221EF-XXXSP COUT 2019 XIN M37221EF-XXXSP Vcc Vss External oscillation circuit

M37221EF-XXXSP,M37221EFSP MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER DISPLAY OSCILLATION CIRCUIT The CRT display clock oscillation circuit has a built-in clock oscilla- tion circuits, so that a clock for CRT display can be obtained simply by connecting an LC, an RC, a ceramic resonator or a quartz-crystal oscillator circuit across the pins OSC 1 and OSC 2. Select the clock for display with bits 0 and 1 of the CRT clock selection register (ad- dress 00ED 16). ADDRESSING MODE The memory access is reinforced with 17 kinds of addressing modes. Refer to the SERIES 740 <Software> User’s Manual for details. MACHINE INSTRUCTIONS There are 71 machine instructions. Refer to the SERIES 740 <Soft- ware> User’s Manual for details. PROGRAMMING NOTES (1) The divide ratio of the timer is 1/(n+1). (2) Even though the BBC and BBS instructions are executed imme- diately after the interrupt request bits are modified (by the pro- gram), those instructions are only valid for the contents before the modification. At least one instruction cycle is needed (such as an NOP) between the modification of the interrupt request bits and the execution of the BBC and BBS instructions. (3) After the ADC and SBC instructions are executed (in decimal mode), one instruction cycle (such as an NOP) is needed before the SEC, CLC, or CLD instruction is executed. (4) An NOP instruction is needed immediately after the execution of a PLP instruction. (5) In order to avoid noise and latch-up, connect a bypass capacitor (≈ 0.1 µF) directly between the V CC pin–VSS pin and the VCC pin– CNV SS pin using a thick wire. AUTO-CLEAR CIRCUIT When power source is supplied, the auto-clear function can be per- formed by connecting the following circuit to the RESET pin. Fig. 64. Auto-clear circuit example Fig. 63. Display oscillation circuit OSC2OSC1 L C1 C2 RESET Vss Vcc Circuit example 1 RESET Vss Vcc Circuit example 2 Note : Make the level change from “L” to “H” at the point at which the power source voltage exceeds the specified voltage.

M37221EF-XXXSP,M37221EFSP MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOL TAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER PROM Programming Method The built-in PROM of the One Time PROM version (blank) and built- in EPROM version can be read or programmed with a general-pur- pose PROM programmer using a special programming adapter. Product M37221EFSP Name of Programming Adapter PCA7408 The PROM of the One Time PROM version (blank) is not tested or screened in the assembly process and following processes. To en- sure proper operation after programming, the procedure shown in Figure 65 is recommended to verify programming. Fig. 65. Programming and testing of One Time PROM version Programming with PROM programmer Screening (Caution) (150°C for 40 hours) Verification with PROM programmer Functional check in target device Caution : The screening temperature is far higher than the storage temperature. Never expose to 150°C exceeding 100 hours.

M37221EF-XXXSP,M37221EFSP MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER Power source voltage (Note 4), During CPU, CRT operation Power source voltage “H” input voltage P0 0–P07,P10–P1 7, P20–P27, P30–P34, SIN, SCLK , HSYNC , VSYNC , RESET, XIN, OSC1, TIM2, TIM3, INT1, INT2, INT3 “H” input voltage SCL1, SCL2, SDA1, SDA2 (When using I2C-BUS) “L” input voltage P0 0–P07,P10–P1 7, P20–P27, P30–P34 “L” input voltage SCL1, SCL2, SDA1, SDA2 (When using I2C-BUS) “L” input voltage H SYNC , VSYNC , RESET,TIM2, TIM3, INT1, INT2, INT3, XIN, OSC1, SIN, SCLK “H” average output current (Note 1) R, G, B, OUT1, D-A, P10–P1 7, P20–P2 7, P30, P31 “L” average output current (Note 2) R, G, B, OUT1, D-A, P06, P07, P10, P15–P17, P20–P27, P30–P3 2 “L” average output current (Note 2) P11–P14 “L” average output current (Note 2) P00–P05 “L” average output current (Note 3) P24–P27 Oscillation frequency (for CPU operation) (Note 5) XIN Oscillation frequency (for CRT display) (Note 5) OSC1 Input frequency TIM2, TIM3 Input frequency S CLK Input frequency SCL1, SCL2 V V V V V V V mA mA mA mA mA MHz MHz kHz MHz kHz ABSOLUTE MAXIMUM RATINGS Power source voltage VCC Input voltage CNV SS Input voltage P0 0–P0 7,P10–P17, P20–P27, P30–P3 4, OSC1, XIN, HSYNC , VSYNC , RESET Output voltage P0 6, P07, P10–P1 7, P20–P27, P30–P3 2, R, G, B, OUT1, D-A, XOUT , OSC2 Output voltage P0 0–P0 5 Circuit current R, G, B, OUT1, P1 0–P17, P20–P2 7, P30, P31, D-A Circuit current R, G, B, OUT1, P0 6, P07, P10, P15–P1 7, P20–P2 3, P30–P32, D-A Circuit current P1 1–P1 4 Circuit current P0 0–P0 5 Circuit current P2 4–P2 7 Power dissipation Operating temperature Storage temperature Symbol V CC VI VI VO VO IOH IOL1 IOL2 IOL3 IOL4 Pd Topr Tstg Conditions All voltages are based on VSS . Output transistors are cut off. T a = 25 °C Ratings –0.3 to 6 –0.3 to 6 –0.3 to V CC + 0.3 –0.3 to VCC + 0.3 –0.3 to 13 0 to 1 (Note 1) 0 to 2 (Note 2) 0 to 6 (Note 2) 0 to 1 (Note 2) 0 to 10 (Note 3) 550 –10 to 70 –40 to 125 Unit V V V V V mA mA mA mA mA mW Parameter Max. 5.5 VCC VCC

0.4 VCC

0.3 VCC

0.2 VCC

8.1 8.0 100 400 RECOMMENDED OPERATING CONDITIONS (Ta = –10 °C to 70 °C, VCC = 5 V ± 10 %, unless otherwise noted) VCC VSS VIH1 VIH2 VIL1 VIL2 VIL3 IOH IOL1 IOL2 IOL3 IOL4 fCPU fCRT fhs1 fhs2 fhs3 Min. 4.5 0.8VCC 0.7VCC 7.9 5.0 Typ. 5.0 8.0 LimitsSymbol Parameter Unit Notes 1:The total current that flows out of the IC must be 20 mA (max.). 2:The total input current to IC (IOL1 + IOL2 + IOL3 ) must be 30 mA or less. 3:The total average input current for ports P24–P27 to IC must be 20 mA or less. 4:Connect 0.1 F or more capacitor externally across the power source pins VCC –VSS so as to reduce power source noise. Also connect 0.1 F or more capacitor externally across the pins VCC –CNV SS . 5:Use a quartz-crystal oscillator or a ceramic resonator for the CPU oscillation circuit.

M37221EF-XXXSP,M37221EFSP MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOL TAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER Power source current “H” output voltage R, G, B, OUT1, D-A, P10–P1 7, P20–P27, P30, P31 “L” output voltage R, G, B, OUT1, D-A, P00–P0 7, P10, P15–P1 7, P20–P23, P30–P32 “L” output voltage P11–P14 “L” output voltage P24–P27 Hysteresis RESET Hysteresis (Note) HSYNC , VSYNC , TIM2, TIM3, INT1, INT2, INT3, SCL1, SCL2, SDA1, SDA2, S IN, SCLK “H” input leak current RESET, P00–P0 7, P10–P1 7, P20–P27, P30–P34, HSYNC , VSYNC “L” input leak current RESET, P00–P0 7, P10–P1 7, P20–P27, P30–P34, HSYNC , VSYNC “H” output leak current P00–P05 I2C-BUS·BUS switch connection resistor (between SCL1 and SCL2, SDA1 and SDA2) ELECTRIC CHARACTERISTICS (VCC = 5 V ± 10 %, VSS = 0 V, f(XIN) = 8 MHz, Ta = –10 °C to 70 °C, unless otherwise noted) VCC = 5.5 V, f(XIN) = 8 MHz VCC = 5.5 V, f(XIN) = 0 VCC = 4.5 V IOH = –0.5 mA VCC = 4.5 V IOL = 0.5 mA VCC = 4.5 V IOL = 3 mA IOL = 6 mA VCC = 4.5 V IOL = 10.0 mA VCC = 5.0 V VCC = 5.0 V VCC = 5.5 V VI = 5.5 V VCC = 5.5 V VI = 0 V VCC = 5.5 V VO = 12 V VCC = 4.5 V ICC VOH VOL VT+–VT– IIZH IIZL IOZH RBS Limits Typ. 0.5 0.5 Min. 2.4 Max. 300 0.4 0.4 0.6 3.0 0.7 1.3 130 Symbol Parameter Test conditions Unit Note:P0 6, P07, P15, P23, P24 have the hysteresis when these pins are used as interrupt input pins or timer input pins. P20–P2 2 have the hysteresis when these pins are used as serial I/O pins. P11–P14 have the hysteresis when these pins are used as multi-master I2C-BUS interface pins. mA µA V V V µA µA µA Ω CRT ON CRT OFFSystem operation Stop mode

M37221EF-XXXSP,M37221EFSP MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER A-D COMPARATOR CHARACTERISTICS (VCC = 5 V ± 10 %, VSS = 0 V, f(XIN) = 8 MHz, Ta = –10 °C to 70 °C, unless otherwise noted) Resolution Absolute accuracy Max. bits LSB Min. Limits Typ. UnitTest conditionsParameterSymbol Note: When VCC = 5 V, 1 LSB = 5/64 V. Fig. 66. Definition diagram of timing on multi-master I2C-BUS SDA SCL p tBUF S tHD :STA tLOW tR tHD :DAT tHIGH tF tSU :DAT tSU :STA Sr p tSU :STOtHD :STA MULTI-MASTER I 2C-BUS BUS LINE CHARACTERISTICS Bus free time Hold time for START condition “L” period of SCL clock Rising time of both SCL and SDA signals Data hold time “H” period of SCL clock Falling time of both SCL and SDA signals Data set-up time Set-up time repeated for START condition Set-up time for STOP condition tBUF tHD:STA tLOW tR tHD:DAT tHIGH tF tSU:DAT tSU:STA tSU:STO Min. 4.7 4.0 4.7 4.0 250 4.7 4.0 Max. 1000 300 Min. 1.3 0.6 1.3 20+0.1C b 0.6 20+0.1Cb 100 0.6 0.6 Max. 300 0.9 300 µs µs µs ns µs µs ns ns µs µs Unit Standard clock mode High-speed clock mode ParameterSymbol Note: C b = total capacitance of 1 bus line D-A CONVERTER CHARACTERISTICS (VCC = 5 V ± 10 %, VSS = 0 V, f(XIN) = 8 MHz, Ta = –10 °C to 70 °C, unless otherwise noted) Resolution Absolute accuracy Setting time Output resistor Max. bits µ s kΩ Min. Limits Typ. 2.5 UnitTest conditionsParameterSymbol tsu R O

M37221EF-XXXSP,M37221EFSP MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOL TAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER PACKAGE OUTLINE

M37221EF-XXXSP,M37221EFSP MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER

M37221EF-XXXSP,M37221EFSP MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOL TAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER Sep. First Edition 1996 H-DF319-B Editioned by Committee of editing of Mitsubishi Semiconductor Data Book Published by Mitsubishi Electric Corp., Semiconductor Division This book, or parts thereof, may not be reproduced in any form without permission of Mitsubishi Electric Corporation. ©1996 MITSUBISHI ELECTRIC CORPORATION Printed in Japan MITSUBISHI DATA BOOK SINGLE-CHIP 8-BIT MICROCOMPUTERS Vol.3

Rev. Rev. No. date

1.0 First Edition 9708

2.0 Information about copywright note, revision number, release data added (last page). 971130

2.1 Correct note (P54) 980731

M37221EF-XXXSP, M37221EFSP DATA SHEET (1/1) Revision Description REVISION DESCRIPTION LIST

Product Information

M37221 specifications and overview.

Summary

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER???

Description

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER???

Source title M37221 Datasheet(PDF) - Mitsubishi Electric Semiconductor

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