M37220M3

M37220M3 MITSUBISHI | Alldatasheet

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Technical content

PIN CONFIGURATION (TOP VIEW)

DESCRIPTION

The M37220M3-XXXSP is a single-chip microcomputer designed with CMOS silicon gate technology. It is housed in a 42-pin shrink plastic molded DIP. In addition to their simple instruction sets, the ROM, RAM and I/O addresses are placed on the same memory map to enable easy pro- gramming. The M37220M3-XXXSP has a PWM output function and a OSD dis- play function, so it is useful for a channel selection system for TV.

FEATURES

• Memory size
• The minimum instruction execution time (at 8 MHz oscillation frequency, VCC =5.5V, at CRT display)
• CRT display function (16 lines maximum) Kinds of character colors (It can be specified by the character) maximum 7 kinds (R, G, B) Kinds of raster colors (maximum 7 kinds) Display position Bordering (horizontal and vertical) APPLICATION TV Outline 42P4B MITSUBISHI MICROCOMPUTERS M37220M3-XXXSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER FUNCTIONAL BLOCK DIAGRAM of M37220M3-XXXSP OUT Clock input Clock output XIN XOUT Reset input VCC VSS CNV SS Clock output for display Input ports P33, P34 OSC1 OSC2 Clock input for display INT2 INT1 PWM5 PWM4 PWM3 PWM2 PWM1 PWM0 P5 (4) B G R HSYNC VSYNC A-D comparator 14-bit PWM circuit 8-bit PWM circuit Accumulator A (8) Timer 4 T4 (8) Timer 3 T3 (8) Timer 2 T2 (8) Timer 1 T1 (8) Timer count source selection circuit TIM2 TIM3 Instruction register (8) Instruction decoder Control signal CRT circuit Stack pointer S (8) Index register Y (8) Index register X (8) Processor status register PS (8) 8-bit arithmetic and logical unit ROM

12 K bytes

PC L (8) Program counter PC H (8) RAM 256 bytes Data bus Clock generating circuit RESET Output ports P52–P55 Address bus SI/O(8) SIN SCLK SOUT INT3 10 9 8 7 6 5 4 3 I/O port P0 28 29 30 31 32 3334 35 P1 (8) I/O port P1 15 14 13 1211 3637 38 P2 (8) I/O port P2 I/O ports P30–P32 17 262716 P3 (3)P0 (8) 39 40 41 42 2 1 2019 25 22 21 18 24 23 ( φ ) Timing output D-A D-A converter

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER Number of basic instructions Instruction execution time Clock frequency Memory size Input/Output ports Serial I/O A-D comparatpr D-A converter PWM output circuit Timers Subroutine nesting Interrupt Clock generating circuit Power source voltage Power dissipation Operating temperature range Device structure Package CRT display function 0.5 µs (the minimum instruction execution time, at 8 MHz oscillation fre- quency)

8 MHz (maximum)

8-bit 5 1 (N-channel open-drain output structure, can be used as PWM output pins, INT input pins, A-D input pin) 8-bit 5 1 (CMOS input/output structure, can be used as A-D input pins, INT input pin) 2-bit 5 1 (CMOS input/output or N-channel open-drain output structure, can be used as serial output pins) 6-bit 5 1 (CMOS input/output structure, can be used as serial input pin, external clock input pins) 2-bit 5 1 (CMOS input/output or N-channel open-drain output structure, can be used as A-D input pins, D-A conversion output pins) 1-bit 5 1 (N-channel open-drain output structure) 2-bit 5 1 (can be used as CRT display clock I/O pins) 4-bit 5 1 (CMOS output structure, can be used as CRT output pins) 8-bit 5 1 6 channels (6-bit resolution) 2 (6-bit resolution) 14-bit 5 1, 8-bit 5 6 8-bit timer 5 4 96 levels (maximum) External interrupt 5 3, Internal timer interrupt 5 4, Serial I/O interrupt 5 1, CRT interrupt 5 1, X IN/4096 interrupt 5 1, VSYNC interrupt 5 1, BRK interrupt 5 1 2 built-in circuits (externally connected a ceramic resonator or a quartz- crystal oscillator)

5 V ± 10 %

165 mW typ. (at oscillation frequency fCPU = 8 MHz, fCRT = 8 MHz) 110 mW typ. (at oscillation frequency fCPU = 8 MHz) 1.65 mW (maximum) –10 °C to 70 °C CMOS silicon gate process 42-pin shrink plastic molded DIP 20 characters 5 2 lines (maximum 16 lines by software) 12 5 16 dots 128 kinds 3 kinds Maximum 7 kinds (R, G, B); can be specified by the character 64 levels (horizontal) 5 128 levels (vertical) Parameter Functions FUNCTIONS ROM RAM CRT ROM CRT RAM 0–P1 7 P20, P21 P22–P2 7 P30, P31 P32 P33, P34 P52–P5 5 I/O I/O I/O I/O I/O I/O Input Output CRT ON CRT OFF In stop mode Number of display characters Dot structure Kinds of characters Kinds of character sizes Kinds of character colors Display position (horizontal, vertical)

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER PIN DESCRIPTION Pin Input/ OutputName VCC, VSS CNV SS RESET XIN XOUT P00/PWM0– P05/PWM5, P06/INT2/ A-D4, 7/INT1 P10–P14, P15/A-D1 INT3, 6/A-D2, P17/A-D3 P20/SCLK , P21/SOUT , P22/SIN, P23/TIM3, P24/TIM2, P25–P2 7 P30/A-D5/ DA1, 1/A-D6/ DA2, P33/OSC1, P34/OSC2 Apply voltage of 5 V ± 10 % (typical) to VCC , and 0 V to VSS . This is connected to VSS . To enter the reset state, the reset input pin must be kept at a “L” for 2 µs or more (under normal VCC conditions). If more time is needed for the quartz-crystal oscillator to stabilize, this “L” condition should be maintained for the required time. This chip has an internal clock generating circuit. To control generating frequency, an external ceramic resonator or a quartz-crystal oscillator is connected between pins XIN and XOUT . If an external clock is used, the clock source should be connected to the XIN pin and the XOUT pin should be left open. Port P0 is an 8-bit I/O port with direction register allowing each I/O bit to be individually programmed as input or output. At reset, this port is set to input mode. The output structure is N-channel open-drain output. The note out of this Table gives a full of port P0 function. Pins P0 0–P0 5 are also used as PWM output pins PWM0–PWM5 respectively.The output structure is N-channel open-drain output. Pins P06, P07 are also used as external interrupt input pins INT2, INT1 respectively. Pins P06 is also used as an analog interrupt input pin A-D4. Port P1 is an 8-bit I/O port and has basically the same functions as port P0. The output structure is CMOS output. Pins P15–P1 7 are also used as an analog input pins A-D1 to A-D3. Pin P15 is also used as an external interrupt input pins INT3. Port P2 is an 8-bit I/O port and has basically the same functions as port P0. The output structure is CMOS output. Pins P23, P24 is also used an external clock input pins TIM3, TIM2 respectively. Pins P21, P22 are also used serial I/O data input/output pins SOUT , SIN respectively. The output structure is N-channel open-drain output. Pin P20 is also used serial I/O syncronizing clock input/output pin SCLK . The output struc- ture is N-channel open-drain output. Ports P30–P32 are a 3-bit I/O port and have basically the same functions as port P0. Either CMOS output or N-channel open-drain output structure can be selected as the ports P30 and P31. The output structure of port P32 is N-channel open-drain output. Pins P30, P31 are also used as analog input pins A-D5, A-D6 respectively. Pins P30, P31 are also used as D-A conversion output pins DA1, DA2 respectively. Ports P33, P34 are a 2-bit input port. Pin P33 is also used as CRT display clock input pin OSC1. Pin P34 is also used as CRT display clock output pin OSC2.The output structure is CMOS output. Input Input Output I/O Output Input Input I/O Input Input I/O Input I/O I/O I/O Input Output Input Input Output Power source CNV SS Reset input Clock input Clock output I/O port P0 PWM output External interrupt input Analog input I/O port P1 Analog input External interrupt input I/O port P2 External clock input Serial I/O data input/output Serial I/O synchro- nizing clock input/ output I/O port P3 Analog input D-A conversion output Input port P3 Clock input for CRT display Clock output for CRT display Functions

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER Output port CRT output HSYNC input VSYNC input DA output PIN DESCRIPTION (continued) P52/R, P53/G, P54/B, P55/OUT H SYNC VSYNC D-A Output Output Input Input Output Ports P52–P55 are a 4-bit output port. The output structure is CMOS output. Pins P52–P55 are also used as CRT output pins R, G, B, OUT respectively. The output structure is CMOS output. This is a horizontal synchronizing signal input for CRT display. This is a vertical synchronizing signal input for CRT display. This is an output pin for 14-bit PWM. Note : As shown in the memory map (Figure 3), port P0 is accessed as a memory at address 00C016 of zero page. Port P0 has the port P0 direction register (address 00C116 of zero page) which can be used to program each bit as an input (“0”) or an output (“1”). The pins programmed as “1” in the direction register are output pins. When pins are programmed as “0,” they are input pins. When pins are programmed as output pins, the output data are written into the port latch and then output. When data is read from the output pins, the output pin level is not read but the data of the port latch is read. This allows a previously-output value to be read correctly even if the output “L” voltage has risen, for example, because a light emitting diode was directly driven. The input pins are in the floating state, so the values of the pins can be read. When data is written into the input pin, it is written only into the port latch, while the pin remains in the floating state.

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER 1 111 1 0 0 CPU mode register (CPUM : address 00FB16) Fix these bits to “0.” Stack page selection bit (Note) 0 : Zero page 1 : 1 page Fix these bits to “1.” Note :Please beware of this bit when programming because it is set to “1” after the reset release. CPU Mode Register The CPU mode register contains the stack page selection bit. The CPU mode register is allocated at address 00FB16. FUNCTIONAL DESCRIPTION Central Processing Unit (CPU) The M37220M3-XXXSP uses the standard 740 family instruction set. Refer to the table of 740 family addressing modes and machine in- structions or the SERIES 740 <Software> User’s Manual for details on the instruction set. Machine-resident 740 family instructions are as follows: The FST, SLW instruction cannot be used. The MUL, DIV, WIT and STP instruction can be used. Fig. 1. Structure of CPU mode register

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER 000016 00C0 16 00FF16 013F16 06B316 D000 16 SFR area Not used Not used FFFF 16 FFDE 16 FF0016 060016 Interrupt vector area Not used 1000016 10FFF 16 1FFFF 16 Zero page ROM for display (4 K bytes) Special page ROM (12 K bytes) RAM for display (Note) (80 bytes) RAM (256 bytes) Note : Refer to Table 8. Contents of CRT display RAM. MEMORY Special Function Register (SFR) Area The special function register (SFR) area in the zero page contains control registers such as I/O ports and timers. RAM RAM is used for data storage and for stack area of subroutine calls and interrupts. ROM ROM is used for storing user programs as well as the interrupt vector area. RAM for Display RAM for display is used for specifying the character codes and col- ors to display. ROM for Display ROM for display is used for storing character data. Interrupt Vector Area The interrupt vector area contains reset and interrupt vectors. Zero Page The 256 bytes from addresses 000016 to 00FF16 are called the zero page area. The internal RAM and the special function registers (SFR) are allocated to this area. The zero page addressing mode can be used to specify memory and register addresses in the zero page area. Access to this area with only 2 bytes is possible in the zero page addressing mode. Special Page The 256 bytes from addresses FF0016 to FFFF16 are called the spe- cial page area. The special page addressing mode can be used to specify memory addresses in the special page area. Access to this area with only 2 bytes is possible in the special page addressing mode. Fig. 2. Memory map

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER 0 : “0” immediately after reset : Fix this bit to “0” (do not write “1”) : Nothing is allocated n SFR area (addresses C016 to DF16) D0 16 D1 16 D2 16 D3 16 D4 16 D5 16 D6 16 D7 16 D8 16 D9 16 DA 16 DB 16 DC 16 DD 16 DE 16 DF 16 C0 16 C1 16 C2 16 C3 16 C4 16 C5 16 C6 16 C7 16 C8 16 C9 16 CB 16 CC 16 CD 16 CE 16 CF 16 CA 16 Address Port P5 (P5) Port P5 direction register (D5) Port P3 output mode control register (P3S) DA-H register (DA-H) DA-L register (DA-L) PWM0 register (PWM0) Port P1 (P1) Port P1 direction register (D1) Port P3 (P3) Port P3 direction register (D3) Port P2 (P2) Port P2 direction register (D2) Register Port P0 (P0) Port P0 direction register (D0) PWM1 register (PWM1) PWM2 register (PWM2) PWM3 register (PWM3) PWM4 register (PWM4) PWM output control register 1 (PW) PWM output control register 2 (PN) Serial I/O mode register (SM) Serial I/O regsiter (SIO) DA1 conversion register (DA1) DA2 conversion register (DA2) : “1” immediately after reset : undefined immediately after reset P30SP31S PW0PW1PW2PW3PW4PW5PW6PW7 PN2PN3PN4 SM0SM1SM2SM3SM5SM6 b7 b0 Bit allocation State immediately after reset 0016 b7 b0 0016 0016 0000 000 0 0000 000 0 ???? 0000 000 0 0000 000 0 0000 000 0 ? ? DA1SDA2S DA10DA11DA12DA13DA14DA15 DA20DA21DA22DA23DA24DA25 Fig. 3. Memory map of SFR (special function register) (1)

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER Fig. 4. Memory map of SFR (special function register) (2) F016 F116 F216 F316 F416 F516 F616 F716 F816 F916 FA 16 FB 16 FC 16 FD 16 FE 16 FF16 E016 E116 E216 E316 E416 E516 E616 E716 E816 E916 EB 16 EC 16 ED 16 EE 16 EF 16 EA 16 Address CRT control register (CC) CRT port control register (CRTP) A-D control register 1 (AD1) A-D control register 2 (AD2) Timer 1 (TM1) Vertical register 2 (CV2) Color register 0 (CO0) Color register 1 (CO1) Character size register (CS) Border selection register (MD) Register Horizontal position register (HR) Vertical register 1 (CV1) Timer 2 (TM2) Timer 3 (TM3) Timer 4 (TM4) Timer 12 mode register (T12M) Timer 34 mode register (T34M) PWM5 register (PWM5) Interrupt input polarity register (RE) Test register (TEST) Interrupt request register 1 (IREQ1) Interrupt request register 2 (IREQ2) Interrupt control register 1 (ICON1) Interrupt control register 2 (ICON2) Color register 2 (CO2) Color register 3 (CO3) CRT clock selection register (CK) CPU mode register (CPUM) b7 b0 Bit allocation HR0HR1HR2HR3HR4HR5 CV10CV11CV12CV13CV14CV15CV16 CV20CV21CV22CV23CV24CV25CV26 CS10CS11CS20CS21 MD10MD20 CO01CO02CO03CO05 /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines CO11CO12CO13CO15 CO21CO22CO23CO25 CO31CO32CO33CO35 CC0CC1CC2 VSYCR/G/BOUTOP5OP6OP7 HSYC CK0CK1 ADM0ADM1ADM2ADM4 /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines ADC0ADC1/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines ADC2ADC4 ADC3ADC5 /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines T34M0 /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines T34M1T34M2T34M3T34M4/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines T12M0 /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines T12M1T12M2T12M3T12M4 CK0RE5 RE4 RE3 CM2 /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines TM1R /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines TM2RTM3RTM4RCRTRVSCRIT3R CK0 /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines MSR 1T1R1T2RS1R /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines TM1E /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines TM2ETM3ETM4ECRTEVSCEIT3E 1T1E1T2ES1EMSE T34M5 State immediately after reset /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines b7 b0 /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines CK0 /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines CK0 /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines 00 00 0000 ????00 00 ??00 00 0 0 00 00 0000 0016 /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines00 0000 0/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines 0 ?00 000 00 00 0000 00 FF16 0716 FF16 0716 00 0000 00 00 0000 00 /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines 00 00 /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines 0?/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines 0 1/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines 0 00 00 0 000 00 00 0 0/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines 00 00 0 000 00 00 0 000 0016 /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines 1 /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines 11 /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines 1 /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines 0 00 00 0 0 0 0 00 00 0 0 0 0 00 00 0 0 0 0 00 00 0 0 0 /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines 0 : “0” immediately after reset /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines : Fix this bit to “0” (do not write “1”) : Nothing is allocated n SFR area (addresses E016 to FF16) : “1” immediately after reset : undefined immediately after reset : Fix this bit to “1” (do not write “0”)

the table because its operation is similar to an interrupt. register are automatically stored into the stack. the interrupt-related registers. be set to “0” and “1” by a program. Reset is treated as a non-maskable interrupt with the highest priority. Figure 6 shows interrupt control. that all bits are cleared to “0” at reset. An interrupt is generated by an overflow of timer 1, 2, 3 or 4. fected by the interrupt disable flag I (non-maskable). Table 1. Interrupt vector addresses and priority

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER Fix this bit to “0.” INT3 polarity switch bit 0 : Positive polarity 1 : Negative polarity Interrupt input polarity register (RE : address 00F9 16) Fix these bits to “0.” INT1 polarity switch bit 0 : Positive polarity 1 : Negative polarity INT2 polarity switch bit 0 : Positive polarity 1 : Negative polarity 7 0 Interrupt request register 1 (IREQ1 : address 00FC16) 0 : No interrupt request issued 1 : Interrupt request issued Interrupt request register 2 (IREQ2 : address 00FD16) Serial I/O interrupt request bit Fix this bit to “0.” INT1 interrupt request bit INT2 interrupt request bit XIN/4096 interrupt request bit 0 : Interrupt disabled 1 : Interrupt enabled Serial I/O interrupt enable bit Interrupt control register 2 (ICON2 : address 00FF16) INT1 interrupt enable bit INT2 interrupt enable bit Fix this bit to “0.” XIN/4096 interrupt enable bit Fix these bits to “0.” 00 0 Interrupt control register 1 (ICON1 : address 00FE16) Timer 1 interrupt enable bit Timer 2 interrupt enable bit Timer 3 interrupt enable bit Timer 4 interrupt enable bit CRT interrupt enable bit VSYNC interrupt enable bit INT3 interrupt enable bit Timer 1 interrupt request bit Timer 2 interrupt request bit Timer 3 interrupt request bit Timer 4 interrupt request bit CRT interrupt request bit VSYNC interrupt request bit INT3 interrupt request bit Fig. 5. Structure of interrupt-related registers

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER Fig. 6. Interrupt control Interrupt request bit Interrupt enable bit Interrupt disable flag I BRK instruction Reset Interrupt request

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER TIMERS The M37220M3-XXXSP has 4 timers: timer 1, timer 2, timer 3, and timer 4. All timers are 8-bit timers with the 8-bit timer latch. The timer block diagram is shown in Figure 8. All of the timers count down and their divide ratio is 1/(n+1), where n is the value of timer latch. The value is set to a timer at the same time by writing a count value to the corresponding timer latch (addresses 00F0 16 to 00F316). The count value is decremented by 1. The timer interrupt request bit is set to “1” by a timer overflow at the next count pulse after the count value reaches “00 16”. (1) Timer 1 Timer 1 can select one of the following count sources:

• f(XIN)/16
• f(XIN)/4096 The count source of timer 1 is selected by setting bit 0 of the timer 12 mode register (address 00F4 16). Timer 1 interrupt request occurs at timer 1 overflow. (2) Timer 2 Timer 2 can select one of the following count sources:
• f(XIN)/16
• Timer 1 overflow signal
• External clock from the P24/TIM2 pin The count source of timer 2 is selected by setting bits 4 and 1 of the timer 12 mode register (address 00F4 16). When timer 1 overflow signal is a count source for the timer 2, the timer 1 functions as an 8- bit prescaler. Timer 2 interrupt request occurs at timer 2 overflow. (3) Timer 3 Timer 3 can select one of the following count sources:
• f(XIN)/16
• External clock from the HSYNC pin
• External clock from the P23/TIM3 pin The count source of timer 3 is selected by setting bits 5 and 0 of the timer 34 mode register (address 00F5 16) Timer 3 interrupt request occurs at timer 3 overflow. (4) Timer 4 Timer 4 can select one of the following count sources:
• f(XIN)/16
• f(XIN)/2
• Timer 3 overflow signal The count source of timer 3 is selected by setting bits 4 and 1 of the timer 34 mode register (address 00F5 16). When timer 3 overflow signal is a count source for the timer 4, the timer 3 functions as an 8- bit prescaler. Timer 4 interrupt request occurs at timer 4 overflow. At reset, timers 3 and 4 are connected by hardware and “FF 16” is automatically set in timer 3; “0716” in timer 4. The f(XIN)/16 is se- lected as the timer 3 count source. The internal reset is released by timer 4 overflow at these state, the internal clock is connected. At execution of the STP instruction, timers 3 and 4 are connected by hardware and “FF 16” is automatically set in timer 3; “0716” in timer 4. However, the f(XIN)/16 is not selected as the timer 3 count source. So set bit 0 of the timer 34 mode register (address 00F516) to “0” before the execution of the STP instruction (f(XIN)/16 is selected as the timer 3 count source). The internal STP state is released by timer 4 overflow at these state, the internal clock is connected. Because of this, the program starts with the stable clock. The structure of timer-related registers is shown in Figure 7.

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER Fig. 7. Structure of timer-related registers Timer 2 count stop bit 0 : Count start 1 : Count stop Timer 12 mode register (T12M : address 00F416) Timer 1 count source selection bit 0 : f(X IN)/16 1 : f(XIN)/4096 Timer 2 count source selection bit 0 : Internal clock 1 : External clock from P24/TIM2 pin Timer 1 count stop bit 0 : Count start 1 : Count stop Timer 2 internal count source selection bit 0 : f(X IN)/16 1 : Timer 1 overflow Timer 34 mode register (T34M : address 00F5 16) Timer 3 count source selection bit 0 : f(XIN)/16 1 : External clock Timer 4 internal count source selection bit 0 : Timer 3 overflow 1 : f(X IN)/16 Timer 3 count stop bit 0 : Count start 1 : Count stop Timer 4 count stop bit 0 : Count start 1 : Count stop Timer 4 count source selection bit 0 : Internal clock 1 : f(XIN)/2 Timer 3 external count source selection bit 0 : External clock from P2 3/TIM3 pin 1 : External clock from HSYNC pin Fix this bit to “0.”

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER Timer 1 (8) 1/2 1/8 Timer 1 latch (8) T12M0 T12M2 T12M4 T12M1 T12M3 Timer 2 (8) Timer 2 latch (8) Timer 3 (8) Timer 3 latch (8) Timer 4 (8) Timer 4 latch (8) Data bus Timer 1 interrupt request Timer 2 interrupt request T34M0 T34M2 T34M5 T34M4 T34M3 T34M1 XIN P24/TIM2 P23/TIM3 Selection gate : Connected to black colored side at reset T12M : Timer 12 mode register T34M : Timer 34 mode register Notes 1 : “H” pulse width of external clock inputs TIM2 and TIM3 needs 4 machine cycles or more. 2 : When the external clock source is selected, timers 2 and 3 are counted at a rising edge of input signal. 3 : In the stop mode or the wait mode, external clock inputs TIM2 and TIM3 cannot be used FF16 0716 H SYNC Reset STP instruction Timer 3 interrupt request Timer 4 interrupt request Fig. 8. Timer block diagram

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER Serial I/O shift register (8) Data bus Serial I/O interrupt request Selection gate : Connected to black colored side at reset.Synchronization circuit Frequency divider 1/81/4 1/16 SM1 SM0 Serial I/O counter (8) SM5: LSB MSB S SM2 SM6 XIN P22/SIN P21/SOUT P20/SCLK SM3 P21 latch P20 latch SM3 (Address 00DD16) SM : Serial I/O mode register Note: When the data is set in the serial I/O register (address 00DD16), the register functions as the serial I/O shift register. (Note) SERIAL I/O The M37220M3-XXXSP has a built-in serial I/O which can either trans- mit or receive 8-bit data in serial in the clock synchronous mode. The serial I/O block diagram is shown in Figure 9. The synchronizing clock I/O pin (S CLK ), and data I/O pins (SOUT , SIN) also function as port P2. Bit 2 of the serial I/O mode register (address 00DC 16) selects whether the synchronizing clock is supplied internally or externally (from the 0/SCLK pin). When an internal clock is selected, bits 1 and 0 select whether f(XIN) is divided by 4, 16, 32, or 64. Bit 3 selects whether port P2 is used for serial I/O or not. To use the P22/SIN pin as the SIN pin, set the bit 2 of the port P2 direction register (address 00C516) to “0.” The operation of the serial I/O function is described below. The func- tion of the serial I/O differs depending on the clock source; external clock or internal clock. Fig. 9. Serial I/O block diagram

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER Serial I/O mode register (SM : address 00DC16) Internal synchronizing clock selection bits b1 b0 0 0 : f(X IN)/4 0 1 : f(XIN)/16 1 0 : f(XIN)/32 1 1 : f(XIN)/64 Synchronizing clock selection bit 0 : External clock 1 : Internal clock Serial I/O port selection bit 0 : P20, P21 functions as port 1 : SCLK , SOUT Fix this bit to “0.” Transfer direction selection bit 0 : LSB first 1 : MSB first Serial input pin selection bit 0 : Input signal from SIN pin 1 : Input signal from SOUT pin Internal clock—the serial I/O counter is set to “7” during write cycle into the serial I/O register (address 00DD16), and transfer clock goes “H” forcibly. At each falling edge of the transfer clock after the write cycle, serial data is output from the S OUT pin. Transfer direction can be selected by bit 5 of the serial I/O mode register. At each rising edge of the transfer clock, data is input from the S IN pin and data in the serial I/O register is shifted 1 bit. After the transfer clock has counted 8 times, the serial I/O counter becomes “0” and the transfer clock stops at “H.” At this time the inter- rupt request bit is set to “1.” External clock—when an external clock is selected as the clock source, the interrupt request is set to “1” after the transfer clock has counted 8 times. However, transfer operation does not stop, so con- trol the clock externally. Use the external clock of 1MHz or less with a duty cycle of 50%. The serial I/O timing is shown in Figure 11. When using an external clock for transfer, the external clock must be held at “H” for initializing the serial I/O counter. When switching between an internal clock and an external clock, do not switch during transfer. Also, be sure to ini- tialize the serial I/O counter after switching. Notes 1:On programming, note that the serial I/O counter is set by writing to the serial I/O register with the bit managing in- structions as SEB and CLB instructions. 2: When an external clock is used as the synchronizing clock, write transmit data to the serial I/O register at “H” of the transfer clock input level. Fig. 10. Structure of serial I/O mode register Fig. 11. Serial I/O timing (for LSB first) Synchroninzing clock Transfer clock Serial I/O register write signal Serial I/O output SOUT D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7 (Note) Serial I/O input SIN Note : When an internal clock is selected, the SOUT pin is at high-impedance after transfer is completed. Interrupt request bit is set to “1”

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER Serial I/O shift register (8) “1” “0” ClockP20/SCLK P21/SOUT P22/SIN SM6 SM: Serial I/O mode register Fig. 12. Signals on serial I/O common transmission/reception mode Serial I/O Common Transmission/Reception Mode By writing “1” to bit 6 of the serial I/O mode register, signals SIN and SOUT are switched internally to be able to transmit or receive the serial data. Figure 12 shows signals on serial I/O common transmission/recep- tion mode. Note:When receiving the serial data after writing “FF 16” to the serial I/O register.

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER Inside of with the others. PWM1 register (Address : 00D116) 1/2XIN PWM timing generating circuit PWM register (Address : 00D016) b7 b0 8-bit PWM circuit PN3 P00 PW2 D0 0 PWM0 P0 1 PW3 D0 1 PWM1 P02 PW4 D0 2 PWM2 P03 PW5 D0 3 PWM3 P04 PW6 D0 4 PWM4 P05 PW7 D0 5 PWM5 14-bit PWM circuit PN2 PN4 PW1 DA MSB DA-H register (Address : 00CE16) DA latch (14 bits) DA-L register (Note) (Address : 00CF16) LSB 6 14 D-A PWM2 register (Address : 00D216) PWM3 register (Address : 00D316) PWM4 register (Address : 00D416) PWM5 register (Address : 00F616) Data bus Selection gate : PW PWM output control register 1 PN PWM output control register 2 PW0 b7 b0 Connected to black colored side when reset. is as same contents Pass gate P0 : Port P0 register Note: The DA-L register also functions as the low-order 6 bits of the DA latch. D0 Port P0 direction register LSB Table 2.Relation between the low-order 6-bit data and high-level area increase interval Area longer by τ than that of other tm (m = 0 to 63) Nothing m = 32 m = 16, 48 m = 8, 24, 40, 56 m = 4, 12, 20, 28, 36, 44, 52, 60 m = 2, 6, 10, 14, 18, 22, 26, 30, 34, 38, 42, 46, 50, 54, 58, 62 Low-order 6 bits of data 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 Fig. 13. PWM block diagram

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER Fig. 14. 8-bit PWM timing (a) Pulses showing the weight of each bit 1 3579 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 0 1 0 0 1 1 0 1 2 0 1 3 0 1 4 0 1 5 0 1 6 0 1 7 0 1 8 0 1 9 0 2 0 0 2 1 0 2 2 0 2 3 0 2 4 0 2 5 0 2 5 5 4 12 20 28 36 44 52 60 68 76 84 92 100 108 116 124 132 140 148 156 164 172 180 188 196 204 212 220 228 236 244 252 16 48 80 112 144 176 208 240 24 40 56 72 88 104 120 136 152 168 184 200 216 232 248 32 96 160 224 64 192 Bit 7 2 6 10 14 18 22 26 30 34 38 42 46 50 54 58 62 66 70 74 78 82 86 90 94 98 102 106 110 114 118 122 126 130 134 138 142 146 150 154 158 162 166 170 174 178 182 186 190 194 198 202 206 210 214 218 222 226 230 234 238 242 246 250 254 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 128 Bit 0 PWM output t = 4 s T = 1024 s f(XIN) = 8 MHz (b) Example of 8-bit PWM t 0016 (0) 0116 (1) 1816 (24) FF16 (255) T = 256 t

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER 0.25 µs b7 b0b6 b5 b4 b3 b2 b1 0 0010110 b13 b6 0010110 b0b5 101000 Set “2C16” to DA-H register. [DA-H register] D H At writing of DA-L b0b6 b5 b4 b3 b2 b1 010100 Set “2816” to DA-L register. [DA-L register] D L At writing of DA-L Undefined These bits decide “H” level area of fundamental waveform. These bits decide smaller interval “tm” in which “H” leval area is [“H” level area of fundamental waveform + τ ]. Minimum resolution bit width 0.25µs High-order 8-bit value of DA latch 5“H” level area of fundamental waveform FF 00 D3FE FD D6 D4 02 01D5 14-bit PWM output 8-bit counter 0.25µs5 44 FF 00 D3FE FD D6 D4 02 01D5 14-bit PWM output 8-bit counter 0.25µs5 45 Fundamental waveform Waveform of smaller interval “tm” specified by low-order 6 bits Fundamental waveform of smaller interval “tm” which is not specified by low-order 6 bits is not changed.14-bit PWM output DA latch of Low-order 6-bit output 0.25µs5 44 τ = 0.25µs T = 4096 µs Repeat period t0 t1 t2 t3 t4 t5 t59 t60 t61 t62 t63 [DA latch] 2C 2B 2A … 03 02 01 00 2C 2B 2A 03 02 01 00 Fig. 15. 14-bit PWM output example (f(XIN)= 8 MHz) … …

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER Fig. 16. Structure of PWM-related registers DA, PWM count source selection bit 0 : Count source supply 1 : Count source stop DA/PN 4 output selection bit 0 : DA output 1 : PN 4 output P00/PWM0 output selection bit 0 : P00 output 1 : PWM0 output P01/PWM1 output selection bit 0 : P01 output 1 : PWM1 output PWM output control register 1 (PW: address 00D516) P02/PWM2 output selection bit 0 : P02 output 1 : PWM2 output P03/PWM3 output selection bit 0 : P03 output 1 : PWM3 output P04/PWM4 output selection bit 0 : P04 output 1 : PWM4 output P05/PWM5 output selection bit 0 : P05 output 1 : PWM5 output PWM output control register 2 (PN: address 00D616) DA output polarity selection bit 0 : Positive polarity 1 : Negative polarity PWM output polarity selection bit 0 : Positive polarity 1 : Negative polarity DA general-purpose output bit 0 : Output “L” 1 : Output “H”

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER A-D control register 2 (AD2: address 00EF16) /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines D-A converter set bits Refer to Table 3. A-D control register 1 Bits 0 to 2 Comparator control Data bus Bit 4 Switch tree A-D control register 2 Resistor ladder Compa- rator Analog signal switch Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 A-D control register 1P15/A-D1/INT3 P16/A-D2 P17/A-D3 P06/INT2/A-D4 P30/A-D5/DA1 P31/A-D6/DA2 Storage bit of comparison result 0 : Input voltage < reference voltage 1 : Input voltage > reference voltage A-D control register 1 (AD1: address 00EE 16) Analog input pin selection bits b2 b1 b0 0 0 0 : A-D1 0 0 1 : A-D2 0 1 0 : A-D3 0 1 1 : A-D4 1 0 0 : A-D5 1 0 1 : A-D6 1 1 0 : 1 1 1 : Do not set. A-D control register 2 Bit 1 Bit 0 A-D COMPARATOR A-D comparator consists of 6-bit D-A converter and comparator. A-D comparator block diagram is shown in Figure 19. The reference voltage “V ref” for D-A conversion is set by bits 0 to 5 of the A-D control register 2 (address 00EF16). The comparison result of the analog input voltage and the reference voltage “V ref” is stored in bit 4 of the A-D control register 1 (address 00EE 16). For A-D comparison, set “0” to corresponding bits of the direction register to use ports as analog input pins. Write the data for select of analog input pins to bits 0 to 2 of the A-D control register 1 and write the digital value corresponding to V ref to be compared to the bits 0 to 5 of the A-D control register 2. The voltage comparison starts by writing to the A-D control register 2, and it is completed after 16 ma- chine cycles (NOP instruction 5 8). Table 3.Relation between contents of A-D control register 2 and reference voltage “V ref” Bit 4 Bit 3 Bit 2 Bit 5 1/128 V CC 3/128 VCC 5/128 VCC 123/128 VCC 125/128 VCC 127/128 VCC Reference voltage “Vref” Fig. 17. Structure of A-D control register 1 Fig.18. Structure of A-D control register 2 Fig. 19. A-D comparator block diagram

The M37220M3-XXXSP has 2 D-A converters with 6-bit resolution. D-A converter block diagram is shown in Figure 22. mal number) in the DA conversion register. buffer when driving a low-impedance load. Table 4. Relation between contents of D-A conversion register and

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER Fig. 25. Block diagram of CRT display control circuit CRT control register (Address 00EA16) Vertical position registers (Addresses 00E116, 00E216) Character size register (Address 00E416) Horizontal position register (Address 00E016) Border selection register (Address 00E516) Display oscillation circuit OSC1 OSC2 Display position control circuit H SYNC VSYNC Display control circuit RAM for display 9 bits 5 20 5 2 Color registers (Addresses 00E616 to 00E916) CRT port control register (Address 00EC16) Data bus ROM for display 12 bits 5 16 5 128 Shift register 12 bits Shift register 12 bits Output circuit R G B OUT

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER (2) Display Position The display positions of characters are specified in units called a “block.” There are 2 blocks, block 1 and block 2. Up to 20 characters can be displayed in each block (refer to (4) Memory for display). The display position of each block can be set in both horizontal and vertical directions by software. The display position in the horizontal direction can be selected for all blocks in common from 64-step display positions in units of 4T C (TC = oscillating cycle for display). The display position in the vertical direction for each block can be selected from 128-step display positions in units of 4 scanning lines. Block 2 is displayed after the display of block 1 is completed (refer to Figure 26 (a)). Accordingly, if the display of block 2 starts during the display of block 1, only block 1 is displayed. Similarly, when multiline display, block 1 is displayed after the display of block 2 is completed (refer to Figure 26 (b)). The vertical position can be specified from 128-step positions (4 scan- ning lines per a step) for each block by setting values “00 16” to “7F16” to bits 0 to 6 in the vertical position register (addresses 00E116 and 00E2 16). Figure 28 shows the structure of the vertical position regis- ter. Fig. 26. Display position (HR) CV1 CV2 Block 1 Block 2 (a) Example when each block is separated CV1 CV2 Block 1 Block 2 Block 1 (second) CV1 No display No display (b) Example when block 2 overlaps with block 1

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER Horizontal position register (HR : address 00E016) Horizontal display start positions 64 steps from “0016” to “3F16” (1 step is 4TC) The horizontal position is common to all blocks, and can be set in 64 steps (where 1 step is 4TC , TC being the display oscillation period) as values “0016” to “3F16” in bits 0 to 5 of the horizontal position register (address 00E016). The structure of the horizontal position register is shown in Figure 29. The display position in the vertical direction is determined by count- ing the horizontal sync signal (HSYNC ). At this time, it starts to count the rising edge (falling edge) of HSYNC signal from after about 1 ma- chine cycle of rising edge (falling edge) of VSYNC signal. So interval from rising edge (falling edge) of VSYNC signal to rising edge (falling edge) of HSYNC signal needs enough time (2 machine cycles or more) for avoiding jitter. The polarity of HSYNC and VSYNC signals can se- lect with the CRT port control register (address 00EC16). For details. refer to (8) CRT Output Pin Control. Note: When bits 0 and 1 of the CRT port control register (address 00EC 16) are set to “1” (negative polarity), the vertical position is determined by counting falling edge of HSYNC signal after rising edge of VSYNC control signal in the microcomputer (re- fer to Figure 27). Fig. 27. Supplement explanation for display position Fig. 28. Structure of vertical position register Fig. 29. Structure of horizontal position register When bits 0 and 1 of the CRT port control register (address 00EC 16) are set to “1” (negative polarity) VSYNC signal input VSYNC control signal in microcomputer 0.125 to 0.25 [µs] ( at f(X IN) = 8MHz) Period of counting H SYNC signal (Note) H SYNC signal input Not count 12345 Note: Do not generate falling edge of HSYNC signal near rising edge of VSYNC control signal in microcomputer to avoid jitter. Vertical position registers 1, 2 (CV1 : address 00E116) (CV2 : address 00E216) Vertical display start positions 128 steps from “0016” to “7F16”

ture of the character size register. C ) in the width (horizontal) direction. position is common to all blocks even when the character size varies with each block (refer to Figure 31). Table 6. Relation between set values in character size register and character sizes

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER (4) Memory for Display There are 2 types of memory for display : CRT display ROM (ad- dresses 1000016 to 10FFF16) used to store character dot data (masked) and CRT display RAM (addresses 060016 to 06B316) used to specify the colors of characters to be displayed. The following de- scribes each type of display memory. À ROM for display (addresses 1000016 to 10FFF16) The CRT display ROM contains dot pattern data for characters to be displayed. For characters stored in this ROM to be actually displayed, it is necessary to specify them by writing the character code inherent to each character (code determined based on the addresses in the CRT display ROM) into the CRT display RAM. The character code list is shown in Table 7. The CRT display ROM has a capacity of 4K bytes. Since 32 bytes are required for 1 character data, the ROM can stores up to 128 kinds of characters. The CRT display ROM space is broadly divided into 2 areas. The [vertical 16 dots] 5 [horizontal (left side) 8 dots] data of display char- acters are stored in addresses 10000 16 to 107FF16; the [vertical 16 dots] 5 [horizontal (right side) 4 dots] data of display characters are stored in addresses 1080016 to 10FFF16 (refer to Figure 32). Note however that the high-order 4 bits in the data to be written to ad- dresses 1080016 to 10FFF16 must be set to “1” (by writing data “FX16”). Fig. 32. Display character stored data 0000000 0000000 0000010 0000101 0001000 0001000 0001000 0010000 1111001 0100000 0100000 0100000 0000000 0000101 0000010 01111 000 0000 0000 0000 0000 0000 0000 0100 0100 0100 0010 0010 0010 0000 0000 0000 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 b7 b0 b7 b0 b3 10XX0 16 10XXF 16 10XX0 16 +80016 10XXF 16 +80016 00000

contents of the CRT display RAM. register No. to the low-order 2 bits (bits 0 and 1) in address 068016. CRT display RAM is shown in Figure 33. Table 8. Contents of CRT display RAM Table 7. Character code list (partially abbreviated)

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER Fig. 33. Structure of CRT display RAM [Color specification] 0 0 : Specifying color register 0 0 1 : Specifying color register 1 1 0 : Specifying color register 2 1 1 : Specifying color register 3 Color register specification Block 1 [Character specification] Specify 128 characters (“0016” to “7F16”) Character code Block 2 [Character specification] 1st character : 062016 20th character : 063316 1st character : 068016 20th character : 069316 1st character : 060016 20th character : 061316 [Color specification] 1st character : 06A016 20th character : 06B316 to to to to Specify 128 characters (“0016” to “7F16”) Character code 0 0 : Specifying color register 0 0 1 : Specifying color register 1 1 0 : Specifying color register 2 1 1 : Specifying color register 3 Color register specification

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER (5) Color Registers The color of a displayed character can be specified by setting the color to one of the 4 registers (CO0 to CO3: addresses 00E616 to 00E916) and then specifying that color register with the CRT display RAM. There are 3 color outputs; R, G and B. By using a combination of these outputs, it is possible to set 2 3–1 (when no output) = 7 col- ors. However, since only 4 color registers are available, up to 4 col- ors can be disabled at one time. R, G and B outputs are set by using bits 1 to 3 in the color register. Bit 5 is used to specify whether a character output or blank output. Figure 34 shows the structure of the color register. Color register 0, 1, 2, 3 (CO0 : address 00E616) (CO1 : address 00E716) (CO2 : address 00E816) (CO3 : address 00E916) B signal output selection bit 0 : No character is output 1 : Character is output G signal output selection bit 0 : No character is output 1 : Character is output R signal output selection bit 0 : No character is output 1 : Character is output OUT signal output control bit 0 : Character is output 1 : Blank is output Fig. 34. Structure of color registers

register to “0” (character is output).

1 Border including character

Table 9. Relationship between set value in border selection register and character border function

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER Block 1 (on display) “CRT interrupt request” On display (CRT interrupt request occurs at the end of block display) Block 2 (on display) Block 1' (on display) Block 2' (on display) “CRT interrupt request” “CRT interrupt request” “CRT interrupt request” Block 1 (on display) “CRT interrupt request” Off display (CRT interrupt request does not occur at the end of block display) Block 2 (on display) Block 1' (off display) Block 2' (off display) “CRT interrupt request” No “CRT interrupt request” No “CRT interrupt request” (7) Multiline Display The M37220M3-XXXSP can ordinarily display 2 lines on the CRT screen by displaying 2 blocks at different vertical positions. In addi- tion, it can display up to 16 lines by using CRT interrupts. A CRT interrupt request occurs at the point at which display of each block has been completed. In other words, when a scanning line reaches the point of the display position (specified by the vertical position registers) of a certain block, the character display of that block starts, and an interrupt occurs at the point at which the scan- ning line exceeds the block. Note: A CRT interrupt does not occur at the end of display when the block is not displayed. In other words, if a block is set to off display with the display control bit of the CRT control reg- ister (address 00EA 16), a CRT interrupt request does not occur (refer to Figure 37). Fig. 37. Timing of CRT interrupt request

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines A'A /LiteDiagLines /LiteDiagLines “RED” “BLUE” H SYNC R B OUT Signals across A – A' (8) CRT Output Pin Control The CRT output pins R, G, B, and OUT can also function as ports P52, P53, P54 and P55. Set the corresponding bit of the port P5 di- rection register (address 00CB16) to “0” to specify these pins as CRT output pins, or set it to “1” to specify it as a general-purpose port P5 pins. The input polarity of signals H SYNC and VSYNC and output polarity of signals R, G, B, and OUT can be specified with the bits of the CRT port control register (address 00EC 16) . Set a bit to “0” to specify positive polarity; set it to “1” to specify negative polarity. The struc- ture of the CRT port control register is shown in Figure 38. (9) Raster Coloring Function An entire screen (raster) can be colored by setting the bits 5 to 7 of the CRT port control register. Since each of the R, G, and B pins can be switched to raster coloring output, 7 raster colors can be obtained. If the R, G, and B pins have been set to MUTE signal output, a raster coloring signal is output in the part except a no-raster colored char- acter (in Figure 39, a character “O”) during 1 horizontal scanning period. This ensures that character colors do not mix with the raster color. In this case, MUTE signal is output from the OUT pin. An example in which a magenta character “I” and a red character “O” are displayed with blue raster coloring is shown in Figure 39. Fig. 39. Example of raster coloring Fig. 38. Structure of CRT port control register CRT port control register (CRTP : address 00EC16) H SYNC input polarity switch bit 0 : Positive polarity 1 : Negative polarity R signal output switch bit 0 : R signal output 1 : MUTE signal output V SYNC input polarity switch bit 0 : Positive polarity 1 : Negative polarity R, G, B output polarity switch bit 0 : Positive polarity 1 : Negative polarity OUT output polarity switch bit 0 : Positive polarity 1 : Negative polarity G signal output switch bit 0 : G signal output 1 : MUTE signal output B signal output switch bit 0 : B signal output 1 : MUTE signal output

select one of the following 4 types.

• Main clock supplied from the XIN pin
• Main clock supplied from the XIN pin divided by 1.5
• Clock from the LC or RC supplied from the pins OSC1 and OSC2.
• Clock from the ceramic resonator or quartz-crystal oscillator sup- plied from the pins OSC1 and OSC2. This clock for display can be selected for each block by the CRT clock selection register (address 00ED 16). When selecting the main clock, set the oscillation frequency to 8 MHz.

Table 10. Set value of CRT clock selection register and clock for display The clock for display is supplied by connecting RC or LC across the pins OSC1 and OSC2. The clock for display is supplied by connecting the following across the pins OSC1 and OSC2.

• a ceramic resonator only for CRT display and a feedback resistor
• a quartz-crystal oscillator only for CRT display and a feedback resistor (Note) Note: It is necessary to connect other ceramic resonator or quartz-crystal oscillator across the pins X IN and XOUT . Fig. 40. Structure of CRT clock selection register CRT oscillation frequency = f(XIN) CRT oscillation frequency = f(XIN)/1.5

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER Power source voltage 0 V Reset input voltage 0 V 4.5 V 0.6 V Poweron Vcc RESET Vss M37220M3-XXXSP 3 0.1 µF M51953AL RESET CIRCUIT The M37220M3-XXXSP is reset according to the sequence shown in Figure 41. It starts the program from the address formed by using the content of address FFFF 16 as the high-order address and the content of the address FFFE16 as the low-order address, when the RESET pin is held at “L” level for 2 µs or more while the power source voltage is 5 V ± 10 % and the oscillation of a quartz-crystal oscillator or a ceramic resonator is stable and then returned to “H” level. The internal state of microcomputer at reset are shown in Figure 43. An example of the reset circuit is shown in Figure 42. The reset input voltage must be kept 0.6 V or less until the power source voltage surpasses 4.5 V. Fig. 41. Reset sequence Fig. 42. Example of reset circuit XIN φ RESET Internal RESET SYNC Address Data 32768 count of XIN clock cycle (Note 3) Reset address from the vector table ? ? 01, S 01, S-1 01, S-2 FFFE FFFF AD H , AD L Notes 1 : f(XIN) and f( φ ) are in the relation : f(XIN) = 2·f ( φ ). 2 : A question mark (?) indicates an undefined state that depends on the previous state. Immediately after a reset, timer 3 and timer 4 are connected in hardware. At this time, “FF16” is set in timer 3 and “0716” is set to timer 4. Timer 3 counts down with f(XIN)/16, and reset state is released by the timer 4 overflow signal.

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER 0016Port P0 direction register 0016 0016 DA-L register PWM output control register 1 0016 Serial I/O mode register Port P1 direction register Port P2 direction register Port P5 Port P5 direction register Port P3 output mode control register PWM output control register 2 000 000 00 0 000 Port P3 direction register 00000 0 (00C116) (00C316) (00C516) (00C716) (00CA16) (00CB16) (00CD16) (00CF16) (00D516) (00D616) (00DC16) Address Contents of register Address Contents of register Note : The contents of all other registers and RAM are undefined at reset, so their initial values. ] : Undefined : Unused bit CRT control register CRT port control register CRT clock selection register A-D control register 1 CPU mode register Processor status register 0716 Timer 12 mode register Interrupt input polarity register Interrupt request register 1 Contents of addressFFFE16 Program counter Timer 1 FF16 0716 A-D control register 2 Timer 2 Timer 3 Timer 4 Timer 34 mode register Interrupt request register 2 Interrupt control register 1 Interrupt control register 2 (00EA16) (00EC16) (00ED16) (00EE16) (00EF16) (00F016) (00F116) (00F216) (00F316) (00F416) (00F516) (00F916) (00FB16) (00FC16) (00FD16) (00FE16) (PS) (PCH ) (PCL) (00FF16) 000 00 0 000 000 000000 FF16 00000 000000 000 000 00 00 Contents of addressFFFF16 0000 0000 000 0000 DA1 conversion register (00DE16) Horizontal register Border selection register Vertical position register 1 Character size register (00E616) Vertical position register 2 00000 0(00E016) (00E116) (00E216) (00E416) (00E516) Color register 0 Color register 1 Color register 2 Color register 3 (00E716) (00E816) (00E916) 0000 0000 0000 0000 DA2 conversion register (00DF16) ]]] ]]]]]] ]]]] ]] ]] ]] ]] ]]]]]] ] ]]]]]] ] ]] ] ] ]] ]] ]]] ]] Fig. 43. Internal state of microcomputer at reset

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER Fig. 44. I/O pin block diagram (1) Ports P1, P2, P30, P31 Data bus Direction register Port latch Ports P00–P05, P32 Data bus Direction register Port latch Ports P06, P07 Data bus Direction register Port latch N-channel open drain output Port P00–P05, P32 Note: Each port is also used as below: P00–P05 : PWM0–PWM5 CMOS output Port P1, P2, P30, P31 Note: Each port is also used as below: P15 : A-D1/INT3 P16 : A-D2 P17 : A-D3 P20 : SCLK P21 : SOUT P22 : SIN N-channel open-drain output Port P06, P07 Note: Each port is also used as below: P06 : INT2/A-D4 P07 : INT1 P23 : TIM3 P24 : TIM2 P30 : A-D5/DA1 P31 : A-D6/DA2

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER Data bus D-A, R, G, B, OUT H SYNC , VSYNC Data bus Schmidt input H SYNC , VSYNC CMOS output D-A, R, G, B, OUT Note: Each pin is also used as below: R : P5 G : P53 B : P54 OUT : P55 Fig. 45. I/O pin block diagram (2)

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER CLOCK GENERATING CIRCUIT The built-in clock generating circuit is shown in Figure 48. When the STP instruction is executed, the internal clock stops at “H” level. At the same time, timers 3 and 4 are connected in hardware and “FF 16” is set in the timer 3, “0716” is set in the timer 4. Select f(XIN)/16 as the timer 3 count source (set bit 0 of the timer 34 mode register to “0” before the execution of the STP instruction). And besides, set the timer 3 and timer 4 interrupt enable bits to disabled (“0”) before ex- ecution of the STP instruction). The oscillator restarts when external interrupt is accepted, however, the internal clock keeps its “H” level until timer 4 overflows. Because this allows time for oscillation stabi- lizing when a ceramic resonator or a quartz-crystal oscillator is used. When the WIT instruction is executed, the internal clock stops in the “H” level but the oscillator continues running. This wait state is released when an interrupt is accepted (Note). Since the oscillator does not stop, the next instruction can be executed at once. When returning from the stop or the wait state, to accept an interrupt, set the corresponding interrupt enable bit to “1” before executing the STP or the WIT instructions. Note: In the wait mode, the following interrupts are invalid. (1) V SYNC interrupt (2) CRT interrupt (3) f(X IN)/4096 interrupt (4) Timer 1 interrupt using f(XIN)/4096 as count source (5) Timer 2 interrupt using P24/TIM2 pin input as count source (6) Timer 3 interrupt using P23/TIM3 pin input as count source (7) Timer 4 interrupt using f(XIN)/2 as count source (8) Multi-master I2C-BUS interface interrupt The circuit example using a ceramic resonator (or a quartz-crystal oscillator) is shown in Figure 46. Use the circuit constants in accor- dance with the resonator manufacture’s recommended values. The circuit example with external clock input is shown in Figure 47. Input the clock to the X IN pin, and open the XOUT pin. Interrupt request Interrupt disable flag I Reset SQ RSTP instruction SQ RWIT instruction SQ R STP instruction Reset Internal clock 1/2 1/8 Timer 3 Timer 4 XOUTXIN T34M0 T34M2 Selection gate : Connected to black colored side at reset. T34M : Timer 34 mode register Fig. 48. Clock generating circuit block diagram Fig. 47. External clock input circuit example Fig. 46. Ceramic resonator circuit example XIN XOUT CIN M37220M3-XXXSP COUT 2019 XIN M37220M3-XXXSP Vcc Vss External oscillation circuit

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER RESET Vss Vcc Circuit example 1 RESET Vss Vcc Circuit example 2 Note : Make the level change from “L” to “H” at the point at which the power source voltage exceeds the specified voltage. DISPLAY OSCILLATION CIRCUIT The CRT display clock oscillation circuit has a built-in clock oscilla- tion circuits, so that a clock for display can be obtained simply by connecting an LC, an RC, a ceramic resonator or a quartz-crystal oscillator circuit across the pins OSC 1 and OSC 2. Select the clock for display with bits 0 and 1 of the CRT clock selection register (ad- dress 00ED 16). ADDRESSING MODE The memory access is reinforced with 17 kinds of addressing modes. Refer to the SERIES 740 <Software> User’s Manual for details. MACHINE INSTRUCTIONS There are 71 machine instructions. Refer to the SERIES 740 <Soft- ware> User’s Manual for details. PROGRAMMING NOTES (1) The divide ratio of the timer is 1/(n+1). (2) Even though the BBC and BBS instructions are executed imme- diately after the interrupt request bits are modified (by the pro- gram), those instructions are only valid for the contents before the modification. At least one instruction cycle is needed (such as an NOP) between the modification of the interrupt request bits and the execution of the BBC and BBS instructions. (3) After the ADC and SBC instructions are executed (in decimal mode), one instruction cycle (such as an NOP) is needed before the SEC, CLC, or CLD instruction is executed. (4) An NOP instruction is needed immediately after the execution of a PLP instruction. (5) In order to avoid noise and latch-up, connect a bypass capacitor (≈ 0.1 µF) directly between the V CC pin–VSS pin and the VCC pin– CNV SS pin using a thick wire. DATA REQUIRED FOR MASK ORDERS The following are necessary when ordering a mask ROM produc- tion: (1) Mask ROM Order Confirmation Form (2) Mark Specification Form (3) Data to be written to ROM, in EPROM form (32-pin DIP type 27C101, three identical copies) AUTO-CLEAR CIRCUIT When power source is supplied, the auto-clear function can be per-______ formed by connecting the following circuit to the RESET pin. Fig. 50. Auto-clear circuit example Fig. 49. Display oscillation circuit OSC2OSC1 L C1 C2

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER Power source voltage (Note 4), During CPU, CRT operation Power source voltage “H” input voltage P0 0–P07,P10–P1 7, P20–P27, P30–P34, SIN, SCLK , HSYNC , VSYNC , RESET, XIN, OSC1, TIM2, TIM3, INT1, INT2, INT3 “L” input voltage P0 0–P07,P10–P1 7, P20–P27, P30–P34 “L” input voltage H SYNC , VSYNC , RESET,TIM2, TIM3, INT1, INT2, INT3, XIN, OSC1, SIN, SCLK “H” average output current (Note 1) R, G, B, OUT, D-A, P10–P1 7, P20–P2 7, P30, P31 “L” average output current (Note 2) R, G, B, OUT, D-A, P06, P07, P10–P17, P20–P27, P30–P3 2 “L” average output current (Note 2) P00–P05 “L” average output current (Note 3) P24–P27 Oscillation frequency (for CPU operation) (Note 5) XIN Oscillation frequency (for CRT display) (Note 5) OSC1 Input frequency TIM2, TIM3 Input frequency S CLK VCC VSS VIH1 VIL1 VIL2 IOH IOL1 IOL2 IOL3 fCPU fCRT fhs1 fhs2 V V V V V mA mA mA mA MHz MHz kHz MHz ABSOLUTE MAXIMUM RATINGS Power source voltage VCC Input voltage CNV SS Input voltage P0 0–P0 7,P10–P17, P20–P27, P30–P3 4, OSC1, XIN, HSYNC , VSYNC , RESET Output voltage P0 6, P07, P10–P1 7, P20–P27, P30–P3 2, R, G, B, OUT, D-A, XOUT , OSC2 Output voltage P0 0–P0 5 Circuit current R, G, B, OUT, P1 0–P1 7, P20–P2 7, P30, P31, D-A Circuit current R, G, B, OUT, P0 6, P07, P10–P1 7, P20–P2 3, P30–P32, D-A Circuit current P0 0–P0 5 Circuit current P2 4–P2 7 Power dissipation Operating temperature Storage temperature Symbol V CC VI VI VO VO IOH IOL1 IOL2 IOL3 Pd Topr Tstg Ratings –0.3 to 6 –0.3 to 6 –0.3 to V CC + 0.3 –0.3 to VCC + 0.3 –0.3 to 13 0 to 1 (Note 1) 0 to 2 (Note 2) 0 to 1 (Note 2) 0 to 10 (Note 3) 550 –10 to 70 –40 to 125 Unit V V V V V mA mA mA mA mW Parameter RECOMMENDED OPERATING CONDITIONS (Ta = –10 °C to 70 °C, VCC = 5 V ± 10 %, unless otherwise noted) Min. 4.5 0.8VCC 7.9 5.0 Typ. 5.0 8.0 LimitsSymbol Parameter Unit Notes 1:The total current that flows out of the IC must be 20 mA (max.). 2:The total input current to IC (IOL1 + IOL2 ) must be 30 mA or less. 3:The total average input current for ports P24–P27 to IC must be 20 mA or less. 4:Connect 0.1µ F or more capacitor externally across the power source pins VCC –VSS so as to reduce power source noise. Also connect 0.1µF or more capacitor externally across the pins VCC –CNV SS . 5:Use a quartz-crystal oscillator or a ceramic resonator for the CPU oscillation circuit. Max. 5.5 VCC

0.4 VCC

0.2 VCC

8.1 8.0 100 Conditions All voltages are based on VSS . Output transistors are cut off. T a = 25 °C

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER Power source current “H” output voltage R, G, B, OUT, D-A, P10–P1 7, P20–P27, P30, P31 “L” output voltage R, G, B, OUT, D-A, P00–P0 7, P10–P17, P20–P23, P30–P32 “L” output voltage P24–P27 Hysteresis RESET Hysteresis (Note) HSYNC , VSYNC , TIM2, TIM3, INT1, INT2, INT3, SIN, SCLK “H” input leak current RESET, P00–P0 7, P10–P1 7, P20–P27, P30–P34, HSYNC , VSYNC “L” input leak current RESET, P00–P0 7, P10–P1 7, P20–P27, P30–P34, HSYNC , VSYNC “H” output leak current P00–P05 ELECTRIC CHARACTERISTICS (VCC = 5 V ± 10 %, VSS = 0 V, f(XIN) = 8 MHz, Ta = –10 °C to 70 °C, unless otherwise noted) VCC = 5.5 V, f(XIN) = 8 MHz VCC = 5.5 V, f(XIN) = 0 VCC = 4.5 V IOH = –0.5 mA VCC = 4.5 V IOL = 0.5 mA VCC = 4.5 V IOL = 10.0 mA VCC = 5.0 V VCC = 5.0 V VCC = 5.5 V VI = 5.5 V VCC = 5.5 V VO = 0 V VCC = 5.5 V VI = 12 V ICC VOH VOL VT+–VT– IIZH IIZL IOZH Limits Typ. 0.5 0.5 Min. 2.4 Max. 300 0.4 3.0 0.7 1.3 Symbol Parameter Test conditions Unit mA µA V V V µA µA µA System operation Stop mode CRT OFF CRT ON Note:P06, P07, P15, P23, P24 have the hysteresis when these pins are used as interrupt input pins or timer input pins. P20–P2 2 have the hysteresis when these pins are used as serial I/O pins. A-D COMPARATOR CHARACTERISTICS (VCC = 5 V ± 10 %, VSS = 0 V, f(XIN) = 8 MHz, Ta = –10 °C to 70 °C, unless otherwise noted) Resolution Absolute accuracy Max. bits LSB Min. Limits Typ. UnitTest conditionsParameterSymbol Note: When VCC = 5 V, 1 LSB = 5/64 V. D-A CONVERTER CHARACTERISTICS (VCC = 5 V ± 10 %, VSS = 0 V, f(XIN) = 8 MHz, Ta = –10 °C to 70 °C, unless otherwise noted) Resolution Absolute accuracy Setting time Output resistor Max. bits µs kΩ Min. Limits Typ. 2.5 UnitTest conditionsParameterSymbol tsu R O

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER PACKAGE OUTLINE

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER /LiteDiagLines/LiteDiagLines/LiteDiagLines GZZ–SH09–72B < 56A0 >

740 FAMILY MASK ROM CONFIRMATION FORM

SINGLE-CHIP MICROCOMPUTER M37220M3-XXXSP MITSUBISHI ELECTRIC Mask ROM number Date : Supervisor signature Receipt Section headsignature h Customer Company name Date issued Date : TEL ( ) Note : Please fill in all items marked h . Submitted by Supervisor Issuancesignature h 1. Confirmation Specify the name of the product being ordered and the type of EPROMs submitted. Three EPROMs are required for each pattern. If at least two of the three sets of EPROMs submitted contain identical data, we will produce masks based on this data. We shall assume the responsibility for errors only if the mask ROM data on the products we produce differs from this data. Thus, extreme care must be taken to verify the data in the submitted EPROMs. Checksum code for entire EPROM (hexadecimal notation) 27C101 EPROM address 000016 /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines Product name ASCII code : ‘M37220M3 –’000F16 FFFF 16 Set “FF16” in the shaded area. Write the ASCII codes that indicates the product name of “M37220M3–” to addresses 000016 to 000F16. (1) (2) EPROM type (indicate the type used) D000 16 Character ROM 1 107FF16 h 2. Mark specification Mark specification must be submitted using the correct form for the type package being ordered fill out the appropriate mark specification form (42P4B for M37220M3-XXXSP) and attach to the mask ROM confirmation form. (1/3) Do you set “FF16” in the shaded area ? Do you write the ASCII codes that indicates the product name of “M37220M3–” to addresses 0000 16 to 000F16 ? EPROM data check item (Refer the EPROM data and check “3 ” in the appropriate box) → Yes n → Yes n l l 1000016 10FFF 16 data ROM 12K bytes 1080016 Character ROM 2 1100016 1FFFF 16 h 3. Comments

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER GZZ–SH09–72B <56A0 > SINGLE-CHIP MICROCOMPUTER M37220M3-XXXSP MITSUBISHI ELECTRIC ‘M’= 164D 16‘3’= 33 16‘7’= 37 16‘2’= 32 16‘2’= 32 16‘0’= 30 16‘M’= 4D 16‘3’= 33 000016 000116 000216 000316 000416 000516 000616 000716 Address ‘–’= 162 D 16FF 16FF 16FF 16FF 16FF 16FF 16FF 000816 000916 000A16 000B16 000C 16 000D 16 000E16 000F16 Address Addresses 000016 to 000F16 store the product name, and addresses 1000016 to 10FFF16 store the character pattern. If the name of the product contained in the EPROMs does not match the name on the mask ROM confirmation form, the ROM processing is disabled. Write the data correctly. Inputting the name of the product with the ASCII code ASCII codes ‘M37220M3-’ are listed on the right. The addresses and data are in hexadecimal notation. Inputting the character ROM Input the character ROM data by dividing it into character ROM1 and character ROM2. For the character ROM data, see the next page and on. Writing the product name and character ROM data onto EPROMs (2/3)

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER GZZ–SH09–72B< 56A0 > SINGLE-CHIP MICROCOMPUTER M37220M3-XXXSP MITSUBISHI ELECTRIC The structure of character ROM (divided of 125 16 dots font) Example Character code “1A16” Example 101A016 to 101AF 16 b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0 A B C D E F A B C D E F F016 F016 F016 F016 F016 F016 F016 F016 F816 F816 F816 F416 F416 F416 F016 F016 Example 109A016 to 109AF 16 Character ROM1 Character ROM2 F16 (3/3) 016 416 A16 116 0416 A16 116 116 016 016 F16 016 016 016 016 016

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER

Sep. First Edition 1996 H-DF319-B Editioned by Committee of editing of Mitsubishi Semiconductor Data Book Published by Mitsubishi Electric Corp., Semiconductor Division This book, or parts thereof, may not be reproduced in any form without permission of Mitsubishi Electric Corporation. ©1996 MITSUBISHI ELECTRIC CORPORATION Printed in Japan MITSUBISHI DATA BOOK SINGLE-CHIP 8-BIT MICROCOMPUTERS Vol.3

Rev. Rev. No. date

1.0 First Edition 9708

2.0 Information about copywright note, revision number, release data added (last page). 971130

2.1 Correct note (P43) 980731

(1/1) Revision Description REVISION DESCRIPTION LIST