M37210M3-708SP

M37210M3 MITSUBISHI | Alldatasheet

Document overview

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Technical content

PIN CONFIGURATION (TOP VIEW) P52/R P53/G P54/B P55/OUT P20 P21 P22 P23 P04 P05 P06 P07 P10 P11 P12 P13 P14 P15/A-D1 P16/A-D2 P17/A-D3 P30 P31 RESET OSC1 OSC2 V CC Outline 52P4B

DESCRIPTION

The M37210M3-XXXSP/FP is a single-chip microcomputer designed with CMOS silicon gate technology. It is housed in a 52-pin shrink plastic molded DIP or a 64-pin plastic molded QFP . This single-chip microcomputer is useful for the channel selection system for TVs because it provides PWM function, OSD display function and so on. In addition to their simple instruction sets, the ROM, RAM, and I/O addresses are placed on the same memory map to enable easy pro- gramming. The features of the M37210E4-XXXSP/FP and the M37210E4SP/FP are similar to those of the M37210M4-XXXSP except that these chips have a built-in PROM which can be written electrically. The differences between the M37210M3-XXXSP/FP , the M37210 M4-XXXSP , and the M37211M2-XXXSP are the ROM size, the RAM size, and the PWM outputs as shown below. Accordingly, the follow- ing descriptions will be for the M37210M3-XXXSP/FP unless other- wise noted. Note :After the reset, set the stack page selection bit which is set “1” to “0” because the internal RAM of the M37211M2-XXXSP is in only the zero page.

FEATURES

16 K bytes (M37210M4-XXXSP)

8 K bytes (M37211M2-XXXSP)

320 bytes (M37210M4-XXXSP) 192 bytes (M37211M2-XXXSP)

• The minimum instruction execution time (at 4MHz oscillation frequency, VCC = 5.5V, at CRT display)
• Programmable I/O ports M37210M4 (14-bit 5 1, 6-bit 5 6) .... M37211M2 Type name M37210M3-XXXSP/FP M37210M4-XXXSP M37211M2-XXXSP ROM size

12 K bytes

16 K bytes

8 K bytes

Note : The M37211M2-XXXSP does not have the PWM6 and the PWM7.

• CRT display function (16 lines max.) Character color kinds (It can be specified by the character) max. 7 kinds (R, G, B) Raster color (max. 7 kinds) Display layout Bordering (horizontal and vertical) APPLICATION TV MITSUBISHI MICROCOMPUTERS M37210M3-XXXSP/FP , M37210M4-XXXSP, M37211M2-XXXSP M37210E4-XXXSP/FP , M37210E4SP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLT AGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER HSYNC VSYNC P60/PWM0 P61/PWM1 P62/PWM2 P63/PWM3 P00/PWM4 P01/PWM5 P02/PWM6 P03/PWM7 P42/SIN/A-D5 P41/SCLK P40/SOUT (/IN) D-A P35/INT2/A-D4 P34/INT1 P33/TIM3 P32/TIM2 P24 P25 P26 P27 CNV SS XIN XOUT VSS

M37210M3-XXXSP/FP, M37210M4-XXXSP, M37211M2-XXXSP M37210E4-XXXSP/FP, M37210E4SP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLT AGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER Outline 64P6N-A NC : No connection PIN CONFIGURATION (TOP VIEW) M37210M3-XXXFP P30 NC P31 RESET OSC1 OSC2 Vcc NC NC V SS XOUT XIN CNV SS P27 NC NC P21 NC P20 P55 /OUT P54 /B P53 /G P52 /R NC NC H SYNC VSYNC P60 /PWM0 P61 /PWM1 P62 /PWM2 NC P63 /PWM3 P22 P23 P04 P05 P06 P07 P10 NC P11 P12 P13 P14 NC P15/A-D1 P16/A-D2 P17/A-D3 P00/PWM4 P01/PWM5 P02/PWM6 P03/PWM7 NC P42/SIN/A-D5 P41/SCLK P40/SOUT /(/IN) D-A P35/INT2/A-D4 P34/INT1 P33/TIM3 P32/TIM2 P24 P25 P26

MITSUBISHI MICR OCOMPUTERS M37210M3-XXXSP/FP , M37210M4-XXXSP , M37211M2-XXXSP M37210E4-XXXSP/FP , M37210E4SP/FP SINGLE-CHIP 8-BIT CMOS MICR OCOMPUTER f or VOL TAGE SYNTHESIZER with ON-SCREEN DISPLA Y CONTR OLLER FUNCTIONAL BLOCK DIA GRAM of M37210M3-XXXSP Notes 1 : The M37211M2-XXXSP does not have PWM outputs of pins 9 and 10. 2 : 320 bytes for M37210M4-XXXSP and 192 bytes for M37211M2-XXXSP 3 : 16 K bytes for M37210M4-XXXSP and 8 K bytes for M37211M2-XXXSP Clock input Clock output Reset input RESET 24 25 30 27 26 23 (5V) (0V)(0V) VCC VSS CNV SS D-A H SYNC YSYNC OSC1 OSC2 29 28 14-bit PWM circuit 6-bit PWM circuit Instruction decoder Control signal Instruction register CRT circuit PWM7 PWM6 PWM5 PWM4 PWM3 PWM2 PWM1 PWM0 Timer count source selection circuit Timer 1 T1 (8) Timer 2 T2 (8) Timer 3 T3 (8) Timer 4 T4 (8) TIM2 TIM3 Interrupt interval determination circuit SI/O(8) P4(3) SIN SCLK SOUT P6(4)P3(6) P5(4) OUT B G R A-D5 INT1, INT2 INT1 INT2 A-D4 P2(8)P1(8)P0(8) A-D1 A-D2 A-D3 41 42 43 44 10 9 8 7 33 34 35 36 373 8 39 40 222 1 20 19 45 46 47 48 151 6 17 183 1 32 111 2 13 6 5 4 3 49 505 15 2 I/O port P0 I/O port P1 I/O port P2 I/O port P3 I/O port P4 Output port P6 Video signal output A-D compa- rator Stack pointer (8) Index register Y (8) Accumulator A(8) 8-bit arithmetic and logical unit RAM 256bytes (Note 2) Program counter PCH (8) Program counter PCL(8) ROM (Note 3) Clock generating circuit Address bus Data bus XIN XOUT Index register X (8) Processor status register PS(8)

M37210M3-XXXSP/FP, M37210M4-XXXSP, M37211M2-XXXSP M37210E4-XXXSP/FP, M37210E4SP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLT AGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER M37210M3-XXXSP , M37210M4-XXXSP , M37211M2-XXXSP M37210M3-XXXFP Number of character Character dot construction Kinds of characters Character size Kinds of color Display position (horizontal, vertical) FUNCTIONS Parameter M37210M3-XXXSP/FP M37210M4-XXXSP M37211M2-XXXSP P10 – P14 P15 – P17 0, P31 P32, P35 P40, P41 P42 at CRT display ON at CRT display OFF at stop mode ROM RAM ROM RAM ROM RAM I/O I/O Input I/O I/O Input I/O Input Output Output Functions 0.5µs (the minimum instruction execution time, at 8MHz oscillation frequency) 8MHz 8-bit 5 1 (can be used as N-channel open-drain output and PWM4-PWM7)(Note) 5-bit 5 1 (CMOS 3-state output) 3-bit 5 1 (can be used as A-D input) 8-bit 5 1 (CMOS 3-state output) 2-bit 5 1 (CMOS 3-state input/output) 4-bit 5 1 (can be used as timer input pins, INT input pins and A-D input pins) 2-bit 5 1 (can be used as N-channel open-drain output and serial I/O function pins) 1-bit 5 1 (can be used as serial I/O and A-D input) 4-bit 5 1 (can be used as R, G, B, OUT pins) 4-bit 5 1 (can be used as N-channel open-drain output and PWM0-PWM3 output pins) 8-bit 5 1 8-bit timer 5 4 96 levels (max.) Two external interrupts, four internal timer interrupts, one serial I/O interrupt, one CRT interrupt, one f(XIN)/4096 interrupt, one VSYNC interrupt, BRK instruction Built-in circuit (externally connected a ceramic resonator or a quartz-crystal oscillator) 5V ± 10% 110mW (at 4MHz oscillation frequency, VCC = 5.5V, T yp.) 55mW (at 4MHz oscillation frequency, VCC = 5.5V, Typ.) 1.65mW (Max.) −10 to 70°C CMOS silicon gate process 52-pin shrink plastic molded DIP 64-pin plastic molded QFP 18 characters 5 2 lines : maximum 16 lines (by software) 12 5 16 dots 96 kinds 3 kinds 7 kinds max, (R, G, B) : can be specified by character unit 64 levels (horizontal) 5 128 levels (vertical) Number of basic instructions Instruction execution time Clock frequency Memory size Input/Output ports Serial I/O Timers Subroutine nesting Interrupt Clock generating circuit Power source voltage Power dissipation Operating temperature range Device structure Package CRT display function Note : The M37211M2-XXXSP can be also used as PWM4 and PWM5.

M37210M3-XXXSP/FP, M37210M4-XXXSP, M37211M2-XXXSP M37210E4-XXXSP/FP, M37210E4SP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLT AGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER PIN DESCRIPTION Pin VCC , VSS CNV SS RESET XIN XOUT φ P00 – P07 P11 – P14 P15 – P17 P20 – P27 P30, P31 P32 – P35 P40, P41 P42 P60 – P63 OSC1, OSC2 H SYNC VSYNC R, G, B, OUT D-A Name Power source voltage CNV SS Reset input Clock input Clock output Timing output I/O port P0 I/O port P1 Input port P1 I/O port P2 I/O port P3 Input port P3 I/O port P4 Input port P4 Output port P6 Clock input for CRT display Clock output for CRT display H SYNC input VSYNC input CRT output DA Output Input / Output Input Input Output Output I/O I/O Input I/O I/O Input I/O Input Output Input Output Input Input Output Output Functions Apply voltage of 5V ± 10% to V CC , and 0V to VSS . This is connected to VSS . To enter the reset state, the reset input pin must be kept at a “L ” for 2µs or more (under nor- mal VCC conditions). If more time is needed for the crystal oscillator to stabilize, this “L” condition should be main- tained for the required time. This chip has an internal clock generating circuit. To control generating frequency, an exter- nal ceramic resonator or a quartz-crystal oscillator is connected between the X IN and XOUT pins. If an external clock is used, the clock source should be connected the XIN pin and the XOUT pin should be left open. This is the timing output pin. Port P0 is an 8-bit I/O port with directional registers allowing each I/O bit to be individually programmed as input or output. At reset, this port is set to input mode. The output structure is CMOS output. The output structure is N-channel open-drain output. When PWM4, PWM5, PWM6 and PWM7 are used, P0 0, P01, P02 and P03 are in common with PWM output pins of PWM4, PWM5, PWM6 and PWM7. Ports P10, P11, P12, P13 and P14 are 5-bit I/O ports and have basically the same functions as port P0. The output structure is CMOS output. Ports P15, P16 and P17 are 3-bit input ports and they are in common with input pins of A-D comparator (A-D1, A-D2 and A-D3). Port P2 is an 8-bit I/O port and has basically the same functions as port P0. The output structure is CMOS output. Ports P30 and P31 are 2-bit I/O ports and have basically the same functions as port P0. The output structure is CMOS output. Ports P32, P33, P34 and P35 are 4-bit input ports and ports P32 and P33 are in common with external clock input pins of timers 2 and 3. Ports P34 and P35 are in common with external interrupt input pins INT1 and INT2. Port P35 is in common with an input pin of A-D comparator (A-D4). Ports P40 and P41 are 2-bit I/O ports and have basically the same functions as port P0. When serial I/O is used, ports P40 and P41 are in common with SOUT pin and SCLK pin, re- spectively. Port P42 is an 1-bit Input port, and it is common with an input pin of A-D comparator (A-D5) and serial input pin (SIN). Port P6 is an 4-bit output port. The output structure is N-channel open-drain. This port is in common with 6-bit PWM output pins PWM0-PWM3. This is the I/O pins of the clock generating circuit for the CRT display function. This is the horizontal synchronizing signal input for CRT display. This is the vertical synchronizing signal input for CRT display. This is a 4-bit output pin for CRT display. The output structure is CMOS output. This is in common with port P5 2 – P55. This is an output pin for 14-bit PWM.

M37210M3-XXXSP/FP, M37210M4-XXXSP, M37211M2-XXXSP M37210E4-XXXSP/FP, M37210E4SP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLT AGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER FUNCTIONAL DESCRIPTION Central Processing Unit (CPU) The M37210M3-XXXSP/FP uses the standard 740 family instruction set. Refer to the table of 740 family addressing modes and machine instructions or the SERIES 740 〈Software〉 User’s Manual for details on the instruction set. Machine-resident 740 family instructions are as follows : The FST and SLW instruction cannot be used. The MUL, DIV, WIT , and STP instruction can be used. CPU Mode Register The CPU mode register is allocated at address 00FB16. The CPU mode register contains the stack page selection bit. Note : Please beware of this bit when programming because it is set to “1” after the reset release. Especially the internal RAM of the M37211M2-XXXSP is in the zero page, so be sure to set this bit to “0”. Fig. 1 Structure of CPU mode register Fix these bits to “002” CPU mode register (CPUM : address 00FB16) Stack page selection bit (Note) 0 : Zero page 1 : 1 page Fix these bits to “11112” 0011111

M37210M3-XXXSP/FP, M37210M4-XXXSP, M37211M2-XXXSP M37210E4-XXXSP/FP, M37210E4SP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLT AGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER Fig. 2 Memory map MEMORY Special Function Register (SFR) Area The special function register (SFR) area in the zero page contains control registers such as I/O ports and timers. RAM RAM is used for data storage and for stack area of subroutine calls and interrupts. ROM ROM is used for sroring user programs as well as the interrupt vec- tor area. RAM for Display RAM for display is used for specifing the character codes and colors to display. ROM for Display ROM for display is used for storing character data. Interrupt Vector Area The interrupt vector area contains reset and interrupt vectors. Zero Page The 256 bytes from addresses 000016 to 00FF16 are called the zero page area. The internal RAM and the special function registers (SFR) are allocated to this area. The zero page addressing mode can be used to specify memory and register addresses in the zero page area. Access to this area with only 2 bytes is possible in the zero page addressing mode. Special Page The 256 bytes from addresses FF0016 to FFFF16 are called the spe- cial page area. The special page addressing mode can be used to specify memory addresses in the special page area. Access to this area with only 2 bytes is possible in the special page addressing mode. 000016 00BF 16 00FF16 013F16 017F16 200016 20B116 300016 35FF16 380016 3DFF 16 FFDE 16 FF0016 RAM (192 bytes) for M37211M2RAM (256 bytes) for M37210M3 ROM for display (3 K bytes) ROM (8 K bytes) for M37211M2 Zero page Special page SFR area Not used Not used Not used Not used Interrupt vector area C000 16 D000 16 E00016 FFFF 16 RAM for display (Note) (72 bytes) RAM (320 bytes) for M37210M4 ROM (12 K bytes) for M37210M3 ROM (16 K bytes) for M37210M4 Note : Refer to Table 6. Contents of CRT display RAM

M37210M3-XXXSP/FP, M37210M4-XXXSP, M37211M2-XXXSP M37210E4-XXXSP/FP, M37210E4SP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLT AGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER Fig. 3 Memory map of special function register (SFR ) Note : The M37211M2-XXXSP dose not have this register 00C1 16 00C0 16 00C2 16 00C3 16 00C4 16 00C5 16 00C6 16 00C7 16 00C8 16 00C9 16 00CA 16 00CB 16 00CC 16 00CD 16 00CE 16 00CF 16 00D0 16 00D1 16 00D2 16 00D3 16 00D4 16 00D5 16 00D6 16 00D7 16 00D8 16 00D9 16 00DA 16 00DB 16 00DC 16 00DD 16 00DE 16 00DF 16 Port P1 Port P2 Port P3 Port P4 Port P5 Port P5 control register Port P6 Port P6 directional register 14DA-H register 14DA-L register PWM1 register PWM0 register PWM3 register PWM4 register PWM output control register 1 PWM output control register 2 Interrupt Interval determination register Interrupt Interval determination control register Serial I/O mode register Serial I/O register Port P0 Port P0 directional register Port P1 directional register Port P2 directional register Port P3 directional register Port P4 directional register PWM2 register Vertical position register 2 (block 2) Character size register Color register 0 Color register 2 CRT control register CRT port control register A-D mode register A-D control register Timer 2 Timer 1 Timer 4 Timer 34 mode register PWM5 register PWM6 register (Note) PWM7 register (Note) CPU mode register Interrupt request register 1 Interrupt request register 2 Interrupt control register1 Interrupt control register2 Horizontal position register Vertical position register 1 (block 1) Border selection register Color register 1 Color register 3 Timer 3 Timer 12 mode register 00E016 00E116 00E216 00E316 00E416 00E516 00E616 00E716 00E816 00E916 00EA 16 00EB 16 00EC 16 00ED 16 00EE 16 00EF 16 00F016 00F116 00F216 00F316 00F416 00F516 00F616 00F716 00F816 00F916 00FA 16 00FB 16 00FC 16 00FD 16 00FE 16 00FF16

Table 1. Interrupt vector addresses and priority ternal, 7 internal, 1 software, and reset. in the vector table. The interrupt request bit is cleared automatically. the interrupt disable flag is set. Reset is treated as a non-maskable interrupt with the highest priority. Figure 5 shows interrupts control.

M37210M3-XXXSP/FP, M37210M4-XXXSP, M37211M2-XXXSP M37210E4-XXXSP/FP, M37210E4SP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLT AGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER Fig. 5 Interrupt control Fig. 4 Structure of interrupt-related registers Interrupt request bit Interrupt enable bit Interrupt disable flag (I) BRK instruction reset interrupt request INT1 interrupt enable bit INT2 interrupt enable bit Serial I/O1 interrupt enable bit Fix this bit to “0” f(X IN)/4096 interrupt enable bit Fix these bits to “0” Timer 1 interrupt request bit Timer 2 interrupt request bit Timer 3 interrupt request bit Timer 4 interrupt request bit CRT interrupt request bit V SYNC interrupt request bit Interrupt request register 1 (IREQ1 : address 00FC16) INT1 interrupt request bit INT2 interrupt request bit Serial I/O1 interrupt request bit f(XIN)/4096 interrupt request bit Fix this bit to “0” Interrupt request register 2 (IREQ2 : address 00FD16) Timer 1 interrupt enable bit Timer 2 interrupt enable bit Timer 3 interrupt enable bit Timer 4 interrupt enable bit CRT interrupt enable bit V SYNC interrupt enable bit Fix these bits to “0” Interrupt control register 1 (ICON1 : address 00FE16) Interrupt control register 2 (ICON2 : address 00FF 16) 0 : No interrupt request issued 1 : Interrupt request issued 0 : Interrupt disabled 1 : Interrupt enabled 00000

MITSUBISHI MICR OCOMPUTERS M37210M3-XXXSP/FP , M37210M4-XXXSP , M37211M2-XXXSP M37210E4-XXXSP/FP , M37210E4SP/FP SINGLE-CHIP 8-BIT CMOS MICR OCOMPUTER f or VOL TAGE SYNTHESIZER with ON-SCREEN DISPLA Y CONTR OLLER Fig. 6 Structure of timer-related registers TIMERS The M37210M3-XXXSP has 4 timers: timer 1, timer 2, timer 3 and timer 4. All timers are 8-bit timers with the 8-bit timer latch. The timer block diagram is shown in Figure 7. All of the timers count down and their divide ratio is 1/(n+1), where n is the value of timer latch. The value is set to a timer at the same time by writing a count value to the corresponding timer latch (addresses 00F0 to 00F3 : timers 1 to 4). The count value is decremented by 1. The timer interrupt request bit is set to “1” by an timer overflow at the next count pulse after the count value reaches “00 16. (1) Timer 1 Timer 1 can select one of the following count sources: f(X IN )/16 f(X IN )/4096 The count source of timer 1 is selected by setting bit 0 of the timer 12 mode register (address 00F4 Timer 1 interrupt request occurs at timer 1 overflow. (2) Timer 2 Timer 2 can select one of the following count sources: f(X IN )/16 Timer 1 overflow signal External clock from the P3 /TIM2 pin The count source of timer 2 is selected by setting bits 4 and 1 of the timer 12 mode register (address 00F4 ). When timer 1 overflow signal is a count source for the timer 2, the timer 1 functions as an 8- bit prescaler. Timer 2 interrupt request occurs at timer 2 overflow. (3) Timer 3 Timer 3 can select one of the following count sources: f(X IN )/16 External clock from the P3 /TIM3 pin and the H SYNC pin The count source of timer 3 is selected by setting bits 5 and 0 of the timer 34 mode register (address 00F5 Timer 3 interrupt request occurs at timer 3 overflow. (4) Timer 4 Timer 4 can select one of the following count sources: f(X IN )/16 f(X IN )/2 Timer 3 overflow signal The count source of timer 3 is selected by setting bits 4 and 1 of the timer 34 mode register 2 (address 00F5 ). When timer 3 overflow signal is a count source for the timer 4, the timer 3 functions as an 8- bit prescaler. Timer 4 interrupt request occurs at timer 4 overflow. At reset, timers 3 and 4 are connected by hardware and “FF ” is automatically set in timer 3; “07 ” in timer 4. The f(X IN )/16 is se- lected as the timer 3 count source. The internal reset is released by timer 4 overflow at these state, the internal clock is connected . At execution of the STP instruction, timers 3 and 4 are connected by hardware and “FF ” is automatically set in timer 3; “07 ” in timer 4. However, the f(X IN )16 is not selected as the timer 3 count source. So set bit 0 of the timer 34 mode register (address 00F5 ) to “0” before the execution of the STP instruction (f(X IN )16 is selected as the timer 3 count source). The internal STP state is released by timer 4 over- flow at these state, the internal clock is connected . Because of this, the program starts with stable clock. The structure of timer-related registers is shown in Figure 6. Timer 2 internal count source selection bit 0 : f (X IN ) /16 1 : Timer 1 overflow signal Timer 2 count stop bit 0 : Operation 1 : stop Timer 1 count stop bit 0 : Operation 1 : Stop Timer 2 count source selection bit 0 : Internal clock source 1 : External clock source from /TIM2 pin Timer 1 count source selection bit 0 : f (X IN ) /16 1 : 1024 µ s clock Timer 12 mode register (TM12MR : address 00F4 Timer 3 count source selection bit 0 : f (X IN ) /16 1 : External clock source (bits) Timer 34 mode register (TM34MR : address 00F5 Timer 4 internal count source selection bit 0 : Timer 3 overflow signal 1 : f (X IN ) /16 Timer 3 count stop bit 0 : Operation 1 : Stop Timer 4 count stop bit 0 : Operation 1 : Stop Timer 4 count source selection bit 0 : Internal clock source 1 : f (X IN ) /2 Timer 3 external count source selection bit 0 : P3 /TIM3 pin input 1 : H SYNC pin input Fix this bit to “0”

M37210M3-XXXSP/FP, M37210M4-XXXSP, M37211M2-XXXSP M37210E4-XXXSP/FP, M37210E4SP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLT AGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER Fig. 7 Timer block diagram Notes 1 :“H” pulse width of external clock inputs TIM2 and TIM3 needs 4 machine cycles or more. 2 :When the external clock source is selected, timers 2 and 3 are counted at a rising edge of input signal. 3 :In the stop mode or the wait mode, external clock inputs TIM2 and TIM3 cannot be used. Data bus XIN 1/2 1/8 Timer 1 latch (8) Timer 1 (8) Timer 2 latch (8) Timer 2 (8) D.F. D.F. Timer 3 latch (8) Timer 3 (8) T12M 0 T12M 2 T12M 4 T12M 1 T12M 3 T34M 0 T34M 2 T34M 1 Timer 4 latch (8) Timer 4 (8) P32/TIM2 P33/TIM3 Timer 1 interrupt request T34M 4 T34M 3 0716 Timer 2 interrupt request Timer 3 interrupt request Reset STP instruction Timer 4 interrupt request FF16 H SYNC T34M 5 Selection gate : Connected to black colored side at reset. T12M : Timer 12 mode register T34M : Timer 34 mode register

M37210M3-XXXSP/FP, M37210M4-XXXSP, M37211M2-XXXSP M37210E4-XXXSP/FP, M37210E4SP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLT AGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER Fig. 8 Serial I/O block diagram SERIAL I/O M37210M3-XXXSP has a serial I/O. A block diagram of the serial I/O is shown in Figure 8. Synchronous input/output clock (S CLK ), and the serial I/O pins (SOUT , SIN) are used as port P4. The serial I/O mode registers (address 00DC 16) are 8-bit registers. Bits 0, 1 and 2 of these registers are used to select a synchronous clock source. Bit 3 decides whether parts of P4 will be used as a serial I/O or not. To use P42 as a serial input, set the directional register bit which cor- responds to P42 to “0”. For more information on the directional regis- ter, refer to the I/O pin section. The serial I/O function is discussed below. The function of the serial I/O differs depending on the clock source ; external clock or internal clock. Data bus XIN 1/2 1/2 P41 latch P41/SCLK SM 3 P40 latch SM 3 P40/SOUT P42/SIN SM 2 SM 1 SM 0 1/4 1/8 1/16 Frequency divider Serial I/O counter (8) SM 5 : LSB↔ MSB Serial I/O shift register (8) (address 00DD16) Serial I/O interrupt request Synchronization circuit SM 6 Selection gate : Connected to black colored side at reset.

M37210M3-XXXSP/FP, M37210M4-XXXSP, M37211M2-XXXSP M37210E4-XXXSP/FP, M37210E4SP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLT AGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER Fig. 9 Serial I/O timing (for LSB first) The serial I/O counter is set to 7 when data is stored in the serial I/O register. At each falling edge of the transfer clock, serial data is out- put to S OUT . During the rising edge of this clock, data can be input from SIN and the data in the serial I/O register will be shifted 1 bit. Transfer direction can be selected by bit 5 of serial I/O mode register. After the transfer clock has counted 8 times, the serial I/O register will be empty and the transfer clock will remain at a high level. At this time the interrupt request bit will be set. External clock- If an external clock is used, the interrupt request will be sent after the transfer clock has counted 8 times but transfer clock will not stop. Due to this reason, the external clock must be controlled from the outside. The external clock should not exceed 1MHz at a duty cycle of 50%. The timing diagram is shown in Figure 9. When using an ex- ternal clock for transfer, the external clock must be held at “H” level when the serial I/O counter is initialized. When switching between the internal clock and external clock, the switching must not be per- formed during transfer. Also, the serial I/O counter must be initialized after switching. Notes 1:On programming, note that the serial I/O counter is set by writing to the serial I/O register with the bit managing in- structions as SEB and CLB instructions. 2:When an external clock is used as the synchronizing clock, write transmit data to the serial I/O register at “H” of the transfer clock input level. D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7 (Note 1) Interrupt request bit set Sync. clock Transfer clock Serial I/O register write signal Serial I/O output SOUT Serial I/O input SIN Notes 1 : If internal clock is selected, the Sout pin is at high impedance after transfer is completed. 2 : When an external clock is used as the synchronous clock, write the transmit data to the serial I/O shift register at “H” of the transfer clock input level.

M37210M3-XXXSP/FP, M37210M4-XXXSP, M37211M2-XXXSP M37210E4-XXXSP/FP, M37210E4SP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLT AGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER Fig. 10 Structure of serial I/O mode register Serial I/O common transmission/reception mode. Write 1 to bit 6 of serial I/O mode register, and signals SIN and SOUT switch internal to be able to serial data transmission/reception. Figure 11 shows signals on serial I/O common transmission/recep- tion mode. Note : Receive the serial data after writing “FF 16” to the serial I/O register. Fig. 11 Signals on serial I/O common transmission/reception mode Internal synchronous clock selection bits 00 : f (X IN) /4 01 : f (XIN) /16 10 : f (XIN) /32 11 : f (XIN) /64 Serial l/O mode register (SM : address 00DC 16) Synchronous clock selection bit 0 : External clock 1 : Internal clock Fix this bit to “0” Serial l/O port selection bit 0 : P4 0, P41 1 : SOUT1 ,SCLK signal output pins Transfer direction selection bit 0 : LSB first 1 : MSB first Serial input pin selection bit 0 : Input from S IN pin 1 : Input from SOUT pin Serial I/O shift register P41/SCLK P40/SOUT (/IN) P42/SIN clock1 Input or output The transmission mode SM 6 Port P42 data “1” The reception mode“0”

Six different pulses can be output from the PWM. content of the 6-bit PWM latch, pulses from 5 to 0 are selected. length of entirely high-level output cannot be output, i.e. 64/64. The output example of the 14-bit PWM is shown in Figure 14. lower 6 bits and higher 8 bits. Table 2. Relation between the low-order 6 bits of data and high-level Block diagram of the PWM is shown in Figure 16. lower 6-bit of the DA-L register (address 00CF16).

M37210M3-XXXSP/FP, M37210M4-XXXSP, M37211M2-XXXSP M37210E4-XXXSP/FP, M37210E4SP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLT AGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER Fig. 12 PWM block diagram Note : The M37211M2-XXXSP can not output the PWM. PW : PWM output control register 1 PN : PWM output control register 2 D0 : Port P0 direction register P0 : Port P0 D6 : Port P6 directional register P6 : Port P6 Inside of is as same contents with the others. Data bus PWM0 register (address 00D016) PN 3 P60 D6 0 PW 2 PWM0 Selection gate : connected to black colored side at reset. P61 D6 1 PW 3 PWM1 P62 D6 2 PW 4 PWM2 P63 D6 3 PW 5 PWM3 P00 D0 0 PW 6 PWM4 P01 D0 1 PW 7 PWM5 P02 D0 2 PN 0 PWM6(Note) P03 D0 3 PN 1 PWM7(Note) Timing generator for PWM PW 0 6-bit PWM circuit PN 2 14-bit PWM circuit PN 4 DA D-A PW 1 XIN bit 5 MSB LSB bit 7 bit 0 bit 0 DA-H register (address 00CE16) (14-bit) DA-L register (address 00CF16) 614 Pass gate ü ï ï ï ï ï ï þ ü ï ï ï ï ï ï þ

MITSUBISHI MICR OCOMPUTERS M37210M3-XXXSP/FP , M37210M4-XXXSP , M37211M2-XXXSP M37210E4-XXXSP/FP , M37210E4SP/FP SINGLE-CHIP 8-BIT CMOS MICR OCOMPUTER f or VOL TAGE SYNTHESIZER with ON-SCREEN DISPLA Y CONTR OLLER Fig. 13 6-bit PWM timing 2 6 10 14 18 22 26 30 34 38 42 46 50 54 58 62 13579 19 39 59 4 122 02 83 64 45 26 0 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (0) (1) (24) (63) 16 48 (a) Pulses showing the weight of each bit T = 64t PWM output t = 10 µ s T = 1024 µ s f (X IN ) = 4MHz (b) Example of 6-bit PWM output 24 40 56

MITSUBISHI MICR OCOMPUTERS M37210M3-XXXSP/FP , M37210M4-XXXSP , M37211M2-XXXSP M37210E4-XXXSP/FP , M37210E4SP/FP SINGLE-CHIP 8-BIT CMOS MICR OCOMPUTER f or VOL TAGE SYNTHESIZER with ON-SCREEN DISPLA Y CONTR OLLER Fig. 14 14-bit PWM output example (f (XIN) = 4MHz) Set “2C16” to DA-H register Set “2816” to DA-L register [DA-H register] [DA latch] bit 7 These bits decide smaller intervals tm in which “H” level area is [“H” level area of fundamental waveform plus r] These bits decide “H” level area of fundamental waveform Fundamental waveform 14-bit 8-bit counter PWM output 00 1011 00 bit 0 After writing of DA-L After writing bit 13 bit 0 00 1011 00101 00 0 10 010 0 bit 0 Waveform of smaller intervals tm specified by the lower 6 bits 14-bit PWM output 8-bit counter FF FE FD D6 D5 D4 D3 02 01 00 The fundamental waveform of smaller intervals tm which is not specified by the lower 6 bits is not changed 14-bit PWM output Low-order 6-bit output of DA latch t0 t1 t2 t3 t4 t5 t59 t60 t61 t62 t63 “H” level area of fundamental waveform Minimum bit durations 0.5µs High-order 8 bit value of DA latch= 5() ( 0.5µs 5 44 0.5µs 5 45 0.5µs 2C 2B 2A 03 02 01 FF FE FD D6 D5 D4 D3 02 01 00 2C 2B 2A 03 02 01 00 0.5µs 5 45 T = 8192µs [DA-L register] τ = 0.5µs … … … …

M37210M3-XXXSP/FP, M37210M4-XXXSP, M37211M2-XXXSP M37210E4-XXXSP/FP, M37210E4SP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLT AGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER Fig.15 Structure of PWM output control registers 1 and 2 Note : Fix this bit to “0” (M37211M2-XXXSP). PWM output control register 2 (PN : address 00D616) P00/PWM4 output selection bit 0 : P00 (general-purpose) output 1 : PWM4 (6-bit PWM) output P63/PWM3 output selection bit 0 : P63 (general-purpose) output 1 : PWM3 (6-bit PWM) output P62/PWM2 output selection bit 0 : P62 (general-purpose) output 1 : PWM2 (6-bit PWM) output P61/PWM1 output selection bit 0 : P61 (general-purpose) output 1 : PWM1 (6-bit PWM) output P60/PWM0 output selection bit 0 : P60 (general-purpose) output 1 : PWM0 (6-bit PWM) output D-A pin general-purpose output register 0 : Output “L” 1 : Output “H” DA, PWM count source STOP bit 0 : Supply 1 : Stop PWM output control register 1 (PW : address 00D5 16) DA/PN 4 output selection bit 0 : DA (14-bit PWM) output 1 : PN 4 (general-purpose) output P01/PWM5 output selection bit 0 : P01 (general-purpose) output 1 : PWM5 (6-bit PWM) output P02/PWM6 output selection bit (Note) 0 : P02 (general-purpose) output 1 : PWM6 (6-bit PWM) output P03/PWM7 output selection bit (Note) 0 : P03(general-purpose) output 1 : PWM7 (6-bit PWM) output DA output polarity selection bit 0 : Positive polarity 1 : Negative polarity 6-bit PWM output polarity selection bit 0 : Positive polarity 1 : Negative polarity

Table 3. Relationship between the contents of A-D control register based on the settings of bits 0 to 4. voltage is stored in the A-D control register, bit 5. the voltage comparison is completed.

M37210M3-XXXSP/FP, M37210M4-XXXSP, M37211M2-XXXSP M37210E4-XXXSP/FP, M37210E4SP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLT AGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER Fig. 21 Block diagram of CRT display control circuit (Address 00EA16) CRT control register (Addresses 00E116 to 00E216) Vertical position registers (Address 00E416) Character size register (Address 00E016) Horizontal position register (Address 00E516) Border selection register (Addresses 00E616 to 00E916) Color registers (Address 00EC16) CRT port control register Data bus R G B OUT Output circuit Shift register 12 bits Shift register 12 bits ROM for display 12 bits × 16 × 96 Display control circuit Display position control circuit Display oscillation circuit OSC1 OSC2 H SYNC VSYNC RAM for display 9 bits × 18 × 2

M37210M3-XXXSP/FP, M37210M4-XXXSP, M37211M2-XXXSP M37210E4-XXXSP/FP, M37210E4SP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLT AGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER Fig. 23 Structure of horizontal position register (2) Display Position The display positions of characters are specified in units called a “block”. There are two blocks, block 1 and block 2. Up to 18 characters can be displayed in one block (refer to (4) Memory for Display). The display position of each block in both horizontal and vertical di- rections can be set by software. The horizontal direction is common to all blocks, and is selected from 64-step display positions in units of 4Tc (Tc = oscillating cycle for dis- play). The display position in the vertical direction is selected from 128-step display positions for each block in units of four scanning lines. Block 2 is displayed after the display of block 1 perfectly (fig. 24(a)). Then if the display of block 2 starts during the display of block 1, only block 1 is displayed. As same, when multiline display, block 1 is dis- played after the display of block 2 perfectly (fig. 24(b)). The vertical position can be specified from 128-step positions (four scanning lines per step) for each block by setting values 00 16 to 7F16 to bits 0 to 6 in the vertical position register (addresses 00E116 and 00E215). Figure 22 shows the structure of the vertical position regis- ter. The horizontal direction is common to all blocks, and can be speci- fied from 64-step display positions (4Tc per step (Tc = oscillating cycle for display) by setting values 00 16 to 3F16 to bits 0 to 5 in the horizontal position register (address 00E016). Figure 23 shows the structure of the horizontal position register. Fig. 22 Structure of vertical position registers Vertical position registers 1, 2 (CV1 : address 00E116) (CV2 : address 00E216) The vertical display start positions 128-step positions (00 16 to 7F16) Horizontal position register (HR : address 00E0 16) The horizontal display start positions 64-step positions (00 16 to 3F16)

M37210M3-XXXSP/FP, M37210M4-XXXSP, M37211M2-XXXSP M37210E4-XXXSP/FP, M37210E4SP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLT AGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER Fig. 24 Display position Block 2 (a) Example when each block is separated (b) Example when block 2 overlaps with block 1 (RH) CV 1 CV 2 Block 1 Block 2 CV 1 CV 2 Block 1 Block 1 (second) CV 1 No display No display

ure 25 shows the structure of the character size register. cycle of display oscillation ( = Tc) in the width (horizontal) direction. sists of [three scanning lines] 5 [3 Tc]. ter size register and the character sizes. Table 5. The relationship between the set values of the character size register and the character sizes all blocks even when the character size varies with each block (refer to Figure 26).

Table 6. Character code list 16 to 3DFF16 must be set to “1” (by writing data F016 to FF16). following describes each type of display memory. dresses in the CRT display ROM) into the CRT display RAM.

M37210M3-XXXSP/FP, M37210M4-XXXSP, M37211M2-XXXSP M37210E4-XXXSP/FP, M37210E4SP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLT AGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER The character code used to specify a character to be displayed is determined based on the address in the CRT display ROM in which that character is stored. Assume that data for one character is stored at addresses 3XX0 16 to 3XXF 16 (XX denotes 0016 to 5F16) and addresses 3YY016 to 3YYF16 (YY denotes 8016 to DF16), then the character code for it is “XX16”. In other words, character code for any given character is configured with two middle digits of the four-digit (hexnotated) addresses 300016 to 35FF16 where data for that character is stored. Table 6 lists the character codes. Fig. 27 Display character stored area bit 7 bit 0 bit 7 bit 3 bit 0 3XX0 16+80016 3XXF 16+80016 3XX0 16 00000000 00100000 0 000 010 0 01010 000 0 000 1010 100010 00 0 00 10001 10000 00 1 0 0 10 0 000 10 0 10 0 00000001 000001 00 00000 00 1 0 00000 0 0 000000003XXF 16 11110000 00001111 1 110 100 0 00001 111 1 111 0000 000011 11 1 11 00001 00001 11 1 1 1 11 0 010 0001111 1 11 1 11000 10100111 101111 00 10110 01 1 1 10110 0 0 10000111 00000 11111

play color specifying part for each block. Table 7 shows the contents of the CRT display RAM.

1. The color register No. to be written here is one of the

vance. For details on color registers, refer to (5) Color Registers. The structure of the CRT display RAM is shown in Figure 27. Table 7. The contents of the CRT display RAM

M37210M3-XXXSP/FP, M37210M4-XXXSP, M37211M2-XXXSP M37210E4-XXXSP/FP, M37210E4SP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLT AGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER Fig. 28 Structure of the CRT display RAM Character code (0016 to 5F16) Specify 96 characters Specify color select mode 00 : Color register 0 specification 01 : Color register 1 specification 10 : Color register 2 specification 11 : Color register 3 specification Character code (0016 to 5F16) Specify 96 characters Color register specification 00 : Color register 0 specification 01 : Color register 1 specification 10 : Color register 2 specification 11 : Color register 3 specification Block 1 [Color specification] 1st character : 2080 to 18th character : 209116 Block 2 [Character specification] 1st character : 202016 to 18th character : 203116 [Color specification] 1st character : 20A016 to 18th character : 20B116 [Character specification] 1st character : 200016 to 18th character : 201116

M37210M3-XXXSP/FP, M37210M4-XXXSP, M37211M2-XXXSP M37210E4-XXXSP/FP, M37210E4SP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLT AGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER Fig. 30 Timing of CRT interrupt (Note) : That is to say, “CRT interrupt” occurs even when it is off display by setting the display control flag of the CRT control register (address 00EA16). Block 2’ (on display) Block 1’ (on display) Block 2 (on display) Block 1 (on display) “CRT interrupt” “CRT interrupt” “CRT interrupt” “CRT interrupt” On display (“CRT interrupt” works after block) Block 2’ (off display) Block 1’ (off display) Block 2 (off display) Block 1 (off display) “CRT interrupt” “CRT interrupt” “CRT interrupt” “CRT interrupt” Off display (“CRT interrupt” occurs after block)

character to be displayed in both horizontal and vertical directions. der is output from the OUT pin instead. function. Figure 32 shows the structure of the border select register. is display by character data. Table 8. The relationship between the value set in the border selection register and the character border function

M37210M3-XXXSP/FP, M37210M4-XXXSP, M37211M2-XXXSP M37210E4-XXXSP/FP, M37210E4SP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLT AGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER (8) CRT Output Pin Control CRT output pins R, G, B and OUT are respectively shared with port P52, P53, P54 and P55. When the corresponding bits in the port P5 control register (address 00CB16) are cleared to “0”, the pins are set for CRT output ; when the bits are set to “1”, the pins function as port P5 (general- purpose output pins). The polarities of CRT outputs (R, G, B and OUT, as well as H SYNC and VSYNC ) can be specified by using the CRT port control register (address 00EC16). Use bits 0 to 4 in the CRT port control register to set the output po- larities of H SYNC , VSYNC , R/G/B and OUT . When these bits are cleared to “0”, a positive polarity is selected ; when the bits are set to “1”, a negative polarity is selected. Bits 5 to 7 in the CRT port control register are used to specify pin by pin whether normal video signals or R-MUTE, G-MUTE, and B- MUTE signals are output from each pin (R, G, B). When set for R- MUTE, G-MUTE, and B-MUTE outputs, the whole background colors of the screen become red, green, and blue. Figure 33 shows the structure of the CRT port control register. Fig. 33 Structure of CRT port control register H SYNC input polarity selection bit 0 : Positive polarity 1 : Negative polarity Polarity register (CRTP : address 00EC 16) VSYNC input polarity selection bit 0 : Positive polarity 1 : Negative polarity OUT output polarity selection bit 0 : Positive polarity 1 : Negative polarity R pin output switch bit 0 : R signal output 1 : R-MUTE signal output G pin output switch bit 0 : G signal output 1 : G-MUTE signal output R/G/B output polarity selection bit 0 : Positive polarity 1 : Negative polarity B pin output switch bit 0 : B signal output 1 : B-MUTE signal output

M37210M3-XXXSP/FP, M37210M4-XXXSP, M37211M2-XXXSP M37210E4-XXXSP/FP, M37210E4SP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLT AGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER INTERRUPT INTERVAL DETERMINATION FUNCTION The M37210M3-XXXSP incorporates an interrupt interval determina- tion circuit. This interrupt interval determination circuit has an 8-bit binary up counter as shown in Figure 34. Using this counter, it determines an interval or a pulse width on the INT1 or INT2 (refer to Figure 36). The following describes how the interrupt interval is determined. 1. The interrupt input to be determined (INT1 input or INT2 input) is selected by using bit 2 in the interrupt interval determination con- trol register (address 00D8 16). When this bit is cleared to “0”, the INT1 input is selected ; when the bit is set to “1”, the INT2 input is selected. 2. When the INT1 input is to be determined, the polarity is selected by using bit 3 of the interrupt interval determination control regis- ter ; when the INT2 input is to be determined, the polarity is se- lected by using bit 4 of the interrupt interval determination control register. When the relevant bit is cleared to “0”, determination is made of the interval of a positive polarity (rising transition) ; when the bit is set to “1”, determination is made of the interval of a negative po- Fig. 34 Block diagram of interrupt interval determination circuit Note : The pulse width of external interrupt INT1 and INT2 needs 5 or more machine cycles. Data bus RE 1 INT1 (Note) RE 0 RE 2 INT2 32µs 8-bit binary up counter Interrupt interval determination register 64µs Address 00D716 Control circuit Selection gate : Connected to black colored side at reset. RE : Interrupt interval determination control register larity (falling transition). 3. The reference clock is selected by using bit 1 of the interrupt inter- val determination control register. When the bit is cleared to “0”, a 64ms clock is selected ; when the bit is set to “1”, a 32µ s clock is selected (based on an oscillation frequency of 4MHz in either case). 4. Simultaneously when the input pulse of the specified polarity (ris- ing or falling transition) occurs on the INT1 pin (or INT2 pin), the 8- bit binary up counter starts counting up with the selected reference clock (64µs or 32µ s). 5. Simultaneously with the next input pulse, the value of the 8-bit bi- nary up counter is loaded into the determination register (address 00D7 16) and the counter is immediately reset (0016). The refer- ence clock is input in succession even after the counter is reset, and the counter restarts counting up from “00 16”. 6. When count value “FE16” is reached, the 8-bit binary up counter stops counting. Then, simultaneously when the next reference clock is input, the counter sets value “FF 16” to the determination register.

M37210M3-XXXSP/FP, M37210M4-XXXSP, M37211M2-XXXSP M37210E4-XXXSP/FP, M37210E4SP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLT AGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER RE i : Bitsi (i = 3, 4, 5) of interrupt space distinguish control register (address 00D816) Fig. 36 Interrupt space distinguish control register setting value and the measuring interval Fig. 35 Structure of interrupt space distinguish control register count interval INT1 or 2 input RE 5 RE 4 (RE3) INT2 pin input polarity switch bit 0 : Positive polarity input 1 : Negative polarity input Interrupt interval determination mode switch bit 0 : Interrupt interval determination mode 1 : Pulse width determination mode INT1 pin input polarity switch bit 0 : Positive polarity input 1 : Negative polarity input External interrupt input pin selection bit 0 : INT1 input 1 : INT2 input Reference clock selection bit (At f (X IN) = 4MHZ) 0 : 64ms 1 : 32ms Interrupt interval determination circuit operation control bit 0 : Stop 1 : Operation Interrupt interval determination control register (RE : address 00D8 16)

Figure 39. It starts the program from the address formed by using the “0” is read from all bits which is not used. 3 : The M37211M2-XXXSP dose not have this register.

M37210M3-XXXSP/FP, M37210M4-XXXSP, M37211M2-XXXSP M37210E4-XXXSP/FP, M37210E4SP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLT AGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER Fig. 39 Reset sequence ?P C H PC L PS AD L AD H? ? 00,S 00,S-1 00,S-2 FFFE FFFF? XIN RESET Internal RESET SYNC Address Data 32768 count of XIN clock cycle (Note 3) Reset address from the vector table φ AD H, AD L Note 1 : f (XIN) and f (φ ) are in the relationship : f (XIN) = 2 · f (φ). 2 : A question mark (?) indicates an undefined state that depends on the previous state. 3 : Immediately after a reset, FF16 is automatically set in timer 3 and 0716 in timer 4 and timer 4, timer 3 and the clock (f (XIN) divided by 16) are connected in series. Reset state is canceled by the overflow signal of timer 4.

M37210M3-XXXSP/FP, M37210M4-XXXSP, M37211M2-XXXSP M37210E4-XXXSP/FP, M37210E4SP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLT AGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER I/O PORTS (1) Port P0 Port P0 is an 8-bit I/O port with N-channel open-drain output. As shown in the memory map (Figure 3), port P0 can be ac- cessed at zero page memory address 00C0 16. Port P0 has a directional register (address 00C116) which can be used to program each individual bit as input (“0”) or as output (“1”). If the pins are programmed as output, the output data is latched to the port register and then output. When data is read from the output port the output pin level is not read, only the latched data in the port register is read. This allows a previously output value to be read correctly even though the output voltage level is shifted up or down. Pins set as input are in the floating state and the signal levels can thus be read. When data is written into the input port, the data is latched only to the port latch and the pin still remains in the float- ing state. Ports P0 0-P03 are in common with 6-bit PWM outputs PWM4- PWM7. For the M37211M2, ports P00 and P01 are in common with 6-bit PWM outputs PWM4 and PWM5. (2) Port P1 Port P1 has basically the same function as port P0 except the output structure is CMOS output. But, pins P1 5-P17 are input ports and in common with analog input pins A-D1-A-D3. (3) Port P2 Port P2 has basically the same function as port P1. (4) Port P3 Port P3 are a 2-bit I/O port and a 4-bit input port with function similar to port P2, but the output structure of P3 0, P31 is CMOS output. 2, P33 are in common with the external clock input pins of timer 2 and 3. 4, P35 are in common with the external interrupt input pins INT1, INT2 and P35 with the analog input pin of A-D comparator A-D4. (5) Port P4 Port P4 are a 2-bit I/O port and a 1-bit input port with function similar to port P2, but the output structure is N-channel open- drain output. When a serial I/O function is selected, P4 0-P42 are in common with pins SOUT , SCLK and SIN. (6) OSC1, OSC2 pins Clock input/output pins for CRT display function. (7) HSYNC , VSYNC pins H SYNC is a horizontal synchronizing signal input pin for CRT dis- play . V SYNC is a vertical synchronizing signal input pin for CRT display. (8) R, G, B, OUT pins This is an 4-bit output pin for CRT display and in common with 2-P55. (9) Port P6 Port P6 is an 4-bit output port with function similar to port P0, but the output structure is N-channel opendrain output. This port is in common with 6-bit PWM output pin PWM0-PWM3. (10) D-A pin This is a 14-bit PWM output pin.

M37210M3-XXXSP/FP, M37210M4-XXXSP, M37211M2-XXXSP M37210E4-XXXSP/FP, M37210E4SP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLT AGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER Fig. 40 I/O pin block diagram (1) Note : P40, P41 can also be used as serial I/O pins. Directional register Port latchData bus CMOS 3-state output Port P10 – P14, P2, P30, P31 Port P10 – P14, P2, P30, P31 Directional register Port latchData bus N-channel open-drain outputPort P40,P41 Directional register Port latchData bus N-channel open-drain output Port P0 Port P0 Port P40,P41 SIN/SCLK

M37210M3-XXXSP/FP, M37210M4-XXXSP, M37211M2-XXXSP M37210E4-XXXSP/FP, M37210E4SP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLT AGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER Fig. 41 I/O pin block diagram (2) Note : P15 – P17 are in common with input Pins for A-D comparator. P32, P33 are in common with timer inputs. P34, P35 are in common with external interrupt inputs. P42 is in common with input pins of serial I/O pins. Note : Pins R, G, B, and OUT can also be used as output ports P52 – P55. N-channel open-drain output Port P6 H SYNC , VSYNC Schmitt input H SYNC , VSYNC CMOS output D-A, R, G, B, OUT Data bus Port P15 – P17 Port P15 – P17 Internal circuit D-A, R, G, B, OUT Data bus Ports P32 – P35, P42 TIM2, TIM3, INT1, INT2, or S IN Internal circuit Port P6 Data bus Port latch Note : P6 can also be used as 6-bit PWM output pins.

M37210M3-XXXSP/FP, M37210M4-XXXSP, M37211M2-XXXSP M37210E4-XXXSP/FP, M37210E4SP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLT AGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER CLOCK GENERATING CIRCUIT The built-in clock generating circuit is shown in Figure 44. When the STP instruction is executed, the internal clock φ stops os- cillating at “H” level. At the same time, timers 3 and 4 are connected in hardware and “FF 16” is set in the timer 3, “0716” is set in the timer 4. Select f(XIN)/16 as the timer 3 count source (set bit 0 of the timer 34 mode register to “0” before the execution of the STP instruction). And besides, set the timer 3 and timer 4 interrupt enable bits to dis- abled (“0”) before execution of the STP instruction. The oscillator is restarted when an external interrupt is accepted. However, the internal clock φ keeps its “H” level until timer 4 over- flows. This is because the oscillator needs a set-up period if a ceramic reso- nator or a quartz-crystal oscillator is used. When the WIT instruction is executed, the internal clock φ stops in the “H” level but the oscillator continues running. This wait state is cleared when an interrupt is accepted (Note). Since the oscillation does not stop, the next instructions are executed at once. To return from the stop or the wait state, set the interrupt enable bit to “1” before executing the STP or the WIT instruction. Note :In the wait mode, the following interrupts are invalid. (1) V SYNC interrupt (2) CRT interrupt (3) Timer 2 interrupt using P3 2/TIM2 pin input as count source (4) Timer 3 interrupt using P33/TIM3 pin input as count source (5) Timer 4 interrupt using f(XIN)/2 as count source The circuit example using a ceramic resonator (or a quartz crystal oscillator) is shown in Figure 42. Use the circuit constants in accordance with the resonator manufacture’s recommended values. Fig. 44 Clock generating circuit block diagram Interrupt request Interrupt disable flag I Reset SQ R SQ R SQ R Reset STP instruction Timer 4Timer 31/2 1/8 Internal clock φ TIM3 T34M 2 T34M 0 XIN XOUT WIT instruction STP instruction Selection gate: Connected to black colored side at reset. Fig. 42 Ceramic resonator circuit example Fig. 43 External clock input circuit example M37210M3-XXXSP XIN XOUT 24 25 C IN C OUT M37210M3-XXXSP XIN External oscillation circuit Vcc Vss The example of external clock usage is shown in Figure 43 XIN is the input, and XOUT is open.

MITSUBISHI MICR OCOMPUTERS M37210M3-XXXSP/FP , M37210M4-XXXSP , M37211M2-XXXSP M37210E4-XXXSP/FP , M37210E4SP/FP SINGLE-CHIP 8-BIT CMOS MICR OCOMPUTER f or VOL TAGE SYNTHESIZER with ON-SCREEN DISPLA Y CONTR OLLER DATA REQ UIRED FOR MASK ORDERS The following are necessary when ordering a mask ROM production. (1) Mask ROM Order Confirmation Form (2) Mark Specification Form (3) Data to be written to ROM, in EPROM form (28-pin DIP type 27256, three identical copies) PR OM Pr ogramming Method The built-in PROM of the blank One Time PROM version and built-in EPROM version can be read or programmed with a general-purpose PR OM programmer using a special programming adapter. Product M37210E4SP M37210E4FP Name of Programming Adapter PCA4754 PCA4756 The PR OM of the blank One Time PR OM v ersion is not tested or screened in the assembly process and following processes. To ensure proper operation after programming, the procedure shown in Figure 45 is recommended to verify programming. Fig. 45 Programming and testing of One Time PROM v ersion Programming with PROM programmer Screening (Caution) (150 for 40 hours) Verification with PROM programmer Functional check in target device Caution : The screening temperature is far higher than the storage temperature. Never expose to 150°C ex- ceeding 100 hours. PR OGRAMMING NO TES (1) The divide ratio of the timer is 1/ (n + 1). (2) Even though the BBC and BBS instructions are executed imme- diately after the interrupt request bits are modified (by the pro- gram), those instructions are only valid for the contents before the modification. At least one instruction cycle is needed (such as an NOP) between the modification of the interrupt request bits and the execution of the BBC and BBS instructions. (3) After the ADC and SBC instructions are executed (indecimal op- eration mode), one instruction cycle (such as an NOP) is needed before the SEC, CLC, or CLD instructions are executed. (4) An NOP instruction is needed immediately after the execution of a PLP instruction. (5) In order to avoid noise and latch-up, connect a bypass capacitor ( ≈ 0.1µ F) directly between the VCC pin and VSS pin using a thick wire.

M37210M3-XXXSP/FP, M37210M4-XXXSP, M37211M2-XXXSP M37210E4-XXXSP/FP, M37210E4SP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLT AGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER Parameter Power source voltage (Note 4) During the CPU and the CRT operation Power source voltage “H” input voltage P00 – P07, P10 – P17, P20 – P27, P30 – P35, P40 – P42, HSYNC , VSYNC , RESET, XIN, OSC1, TIM2, TIM3, INT1, INT2, SIN, SCLK “L” input voltage P00 – P07, P10 – P17, P20 – P27, P30 – P35, P40 – P42 “L” input voltage TIM2, TIM3, INT1, INT2, SIN, SCLK , H SYNC , VSYNC , RESET , XIN, OSC1 “H” average output current (Note 1) R, G, B, OUT, P10 – P14, P20 – P27, P30, P31, D-A “L ” average output current (Note 2) R, G, B, OUT, P10 – P14, P20 – P23, P30, P31, P40, P41, D-A “L” average output current (Note 2) P60 – P63, P00 – P07 “L” average output current (Note 3) P24 – P27 Oscillation frequency (for CPU operation)(Note 5) Oscillation frequency (for CRT display) Input frequency TIM2, TIM3, INT1, INT2 Input frequency S CLK Parameter Power source voltage Input voltage CNV SS Input voltage P00 – P07, P10 – P17, P20 – P27, P30 – P35, P40 – P42, HSYNC , VSYNC , RESET, OSC1, XIN Output voltage P10 – P14, P20 – P27, P30, P31, P40, P41, R, G, B, OUT , D-A, XOUT , OSC2 Output voltage P60 – P63, P00 – P07 “H” average output current R, G, B, OUT, P10 – P14, P20 – P23, P30, P31, D-A “L ” average output current R, G, B, OUT, P10 – P14, P20 – P23, P30, P31, P40, P41 D-A “L” average output current P60 – P63, P00 – P07 “L” average output current P24 – P27 Power dissipation Operating temperature Storage temperature ABSOLUTE MAXIMUM RATINGS Symbol VCC VSS VIH VIL VIL IOH IOL1 IOL2 IOL3 fCPU fCRT fhs fhs Min. 4.5 0.8VCC 3.6 4.0 Max. 5.5 VCC 0.4VCC 0.2VCC 8.1 6.0 100 Limits Unit V V V V V mA mA mA mA MHz MHz kHz MHz CC = 5V ± 10%, Ta = –10 to 70°C unless otherwise noted)RECOMMENDED OPERATING CONDITIONS Symbol VCC VI VI VO VO IOH IOL1 IOL2 IOL3 Pd Topr Tstg Conditions All voltages are based on VSS . Output transistors are cut off. Ta = 25°C Ratings – 0.3 to 6 – 0.3 to 6 – 0.3 to V CC + 0.3 – 0.3 to VCC + 0.3 – 0.3 to 13 0 to 1 (Note 1) 0 to 2 (Note 2) 0 to 1 (Note 2) 0 to 10 (Note 3) 550 – 10 to 70 – 40 to 125 Unit V V V V V mA mA mA mA mW Ty p . 5.0 4.0 5.0 Notes 1 :The total current that flows out of the IC should be 20mA (max.). 2: The total of IOL1 and IOL2 should be 30mA (max.). 3 :The total of IOL of port P24-P27 should be 20mA (max.). 4: Connect 0.022µF or more capacitor externally between the VCC – VSS power source pins so as to reduce power source noise. Also connect 0.068µF or more capacitor externally between the V CC – CNV SS pins. 5 :Use a quartz-crystal oscillator or a ceramic resonator for CPU oscillation circuit.

M37210M3-XXXSP/FP, M37210M4-XXXSP, M37211M2-XXXSP M37210E4-XXXSP/FP, M37210E4SP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLT AGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER Parameter Power source current “H” output voltage P10 – P14, P20 – P27, P30, P31, R, G, B, OUT , D-A “L” output voltage P10 – P14, P20 – P23, P30, P31, P40, P41, R, G, B, OUT , D-A “L” output voltage P60 – P63, P00 – P07 “L” output voltage P24 – P27 Hysteresis RESET Hysteresis (Note) H SYNC , VSYNC , TIM2, TIM3, INT1, INT2, SIN, SCLK “H” input leak current RESET , P00 – P07, P10 – P17, P20 – P27, P30 – P35, P40 – P42, HSYNC , VSYNC “L ” input leak current RESET, P00 – P07, P10 – P17, P20 – P27, P30 – P35, P40 – P42, P60 – P63, HSYNC , VSYNC “H” input leak current P60 – P63, P00 – P07 ELECTRIC CHARACTERISTICS (VCC = 5V ± 10%, VSS = 0V , Ta = – 10 to 70°C, f (XIN) = 4MHz unless otherwise noted) C R T C R T OFF ON OFF ON Min. 2.4 Limits Ty p . 0.5 0.5 Test conditions VCC = 5.5V f (XIN) = 4MHz VCC = 5.5V f (XIN) = 8MHz At stop mode VCC = 4.5V IOH = – 0.5mA VCC = 4.5V IOL = 0.5mA VCC = 4.5V IOL = 0.5mA VCC = 4.5V IOL = 10.0mA VCC = 5.0V VCC = 5.0V VCC = 5.5V VI = 5.5V VCC = 5.5V VI = 0V VCC = 5.5V VO = 12V Symbol ICC VOH VOL VT +–VT– IIZH IIZL IOZH Note :P3 2 – P35, have the hysteresis when these pins are used as interrupt input pins or timer input pins. P40 – P42 have the hysteresis when these pins are used as serial I/O ports. Max. 300 0.4 0.4 3.0 0.7 1.3 Unit mA mA µA V V V µA µA µA

MITSUBISHI MICR OCOMPUTERS M37210M3-XXXSP/FP , M37210M4-XXXSP , M37211M2-XXXSP M37210E4-XXXSP/FP , M37210E4SP/FP SINGLE-CHIP 8-BIT CMOS MICR OCOMPUTER f or VOL TAGE SYNTHESIZER with ON-SCREEN DISPLA Y CONTR OLLER PACKA GE OUTLINE

M37210M3-XXXSP/FP, M37210M4-XXXSP, M37211M2-XXXSP M37210E4-XXXSP/FP, M37210E4SP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLT AGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER GZZ–SH06–09B < 25C0 >

740 FAMILY MASK ROM CONFIRMATION FORM

SINGLE-CHIP MICROCOMPUTER M37210M3-XXXSP/FP MITSUBISHI ELECTRIC Mask ROM number Date : Supervisorsignature Receipt Section headsignature h Customer Company name Date issued Date : TEL ( ) Note : Please fill in all items marked h . Submitted by Supervisor Issuancesignature h 1. Confirmation Specify the name of the product being ordered and the type of EPROMs submitted. Three EPROMs are required for each pattern. If at least two of the three sets of EPROMs submitted contain identical data, we will produce masks based on this data. We shall assume the responsibility for errors only if the mask ROM data on the products we produce differs from this data. Thus, extreme care must be taken to verify the data in the submitted EPROMs. /LiteDiagLines/LiteDiagLines/LiteDiagLines Checksum code for entire EPROM (hexadecimal notation) 27256 EPROM address 000016 /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines Product name ASCII code : ‘M37210M3 –’ ROM (12K bytes) 000F16 15FF16 180016 1DFF 16 Set “FF16” in the shaded area. Write the ASCII codes that indicates the product name of “M37210M3–” to addresses 000016 to 000F16. (1) (2) EPROM type (indicate the type used) 100016 Character ROM1 500016 7FFF 16 Character ROM2 h 2. Mark specification Mark specification must be submitted using the correct form for the type package being ordered fill out the appropriate mark specification form (52P4B for M37210M3-XXXSP; 64P6N for M37210M3-XXXFP) and attach to the mask ROM confirmation form. h 3. Comments (1/3) Microcomputer name : M37210M3-XXXSP M37210M3-XXXFP

MITSUBISHI MICR OCOMPUTERS M37210M3-XXXSP/FP , M37210M4-XXXSP , M37211M2-XXXSP M37210E4-XXXSP/FP , M37210E4SP/FP SINGLE-CHIP 8-BIT CMOS MICR OCOMPUTER f or VOL TAGE SYNTHESIZER with ON-SCREEN DISPLA Y CONTR OLLER GZZ–SH06–09B < 25C0 > SINGLE-CHIP MICROCOMPUTER M37210M3-XXXSP/FP MITSUBISHI ELECTRIC ‘M’= 164D 16‘3’= 33 16‘7’= 3 7 16‘2’= 3 2 16‘1’= 3 1 16‘0’= 3 0 16‘M’= 4D 16‘3’= 3 3 000016 000116 000216 000316 000416 000516 000616 000716 Address ‘–’= 162 D 16FF 16FF 16FF 16FF 16FF 16FF 16FF 000816 000916 000A16 000B16 000C 16 000D 16 000E16 000F16 Address Addresses 000016 to 000F16 store the product name, and addresses 100016 to 15FF16 and addresses 180016 to 1DFF16 store the character pattern. If the name of the product contained in the EPROMs does not match the name on the mask ROM confirmation form, the ROM processing is disabled. Write the data correctly. Inputting the name of the product with the ASCII code ASCII codes ‘M37210M3-’ are listed on the right. The addresses and data are in hexadecimal notation. Inputting the character ROM Input the character ROM data by dividing it into character ROM1 and character ROM2. For the character ROM data, see the next page and on. Writing the product name and character ROM data onto EPROMs (2/3)

M37210M3-XXXSP/FP, M37210M4-XXXSP, M37211M2-XXXSP M37210E4-XXXSP/FP, M37210E4SP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLT AGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER GZZ–SH06–09B < 25C0> SINGLE-CHIP MICROCOMPUTER M37210M3-XXXSP/FP MITSUBISHI ELECTRIC The structure of character ROM (divided of 125 16 dots font) Example Character code “1A16” Example 11A016 to 11AF 16 b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0 A B C D E F A B C D E F 0016 0416 0416 0A16 0A16 1116 1116 1116 2016 2016 3F16 4016 4016 4016 0016 0016 F016 F016 F016 F016 F016 F016 F016 F016 F816 F816 F816 F416 F416 F416 F016 F016 Example 19A016 to 19AF 16 Character ROM1 Character ROM2 F16 (3/3)

M37210M3-XXXSP/FP, M37210M4-XXXSP, M37211M2-XXXSP M37210E4-XXXSP/FP, M37210E4SP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLT AGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER GZZ–SH06–10B < 25B0 > SINGLE-CHIP MICROCOMPUTER M37210M4-XXXSP MITSUBISHI ELECTRIC Mask ROM number Date : Supervisorsignature Receipt Section headsignature h Customer Company name Date issued Date : TEL ( ) Note : Please fill in all items marked h . Submitted by Supervisor Issuancesignature h 1. Confirmation Specify the name of the product being ordered and the type of EPROMs submitted. Three EPROMs are required for each pattern. If at least two of the three sets of EPROMs submitted contain identical data, we will produce masks based on this data. We shall assume the responsibility for errors only if the mask ROM data on the products we produce differs from this data. Thus, extreme care must be taken to verify the data in the submitted EPROMs. /LiteDiagLines/LiteDiagLines/LiteDiagLines Checksum code for entire EPROM (hexadecimal notation) 27256 EPROM address 000016 /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines Product name ASCII code : ‘M37210M4 –’ ROM (16K bytes) 000F16 15FF16 180016 1DFF 16 Set “FF16” in the shaded area. Write the ASCII codes that indicates the product name of “M37210M4–” to addresses 000016 to 000F16. (1) (2) EPROM type (indicate the type used) 100016 Character ROM1 400016 7FFF 16 Character ROM2 h 2. Mark specification Mark specification must be submitted using the correct form for the type package being ordered fill out the appropriate mark specification form (52P4B for M37210M4-XXXSP) and attach to the mask ROM confirmation form. h 3. Comments (1/3)

MITSUBISHI MICR OCOMPUTERS M37210M3-XXXSP/FP , M37210M4-XXXSP , M37211M2-XXXSP M37210E4-XXXSP/FP , M37210E4SP/FP SINGLE-CHIP 8-BIT CMOS MICR OCOMPUTER f or VOL TAGE SYNTHESIZER with ON-SCREEN DISPLA Y CONTR OLLER GZZ–SH06–10B < 25B0 > SINGLE-CHIP MICROCOMPUTER M37210M4-XXXSP MITSUBISHI ELECTRIC ‘M’= 164D 16‘3’= 3 3 16‘7’= 3 7 16‘2’= 3 2 16‘1’= 3 1 16‘0’= 3 0 16‘M’= 4D 16‘4’= 3 4 000016 000116 000216 000316 000416 000516 000616 000716 Address ‘–’= 162 D 16FF 16FF 16FF 16FF 16FF 16FF 16FF 000816 000916 000A16 000B16 000C 16 000D 16 000E16 000F16 Address Addresses 000016 to 000F16 store the product name, and addresses 100016 to 15FF16 and addresses 180016 to 1DFF16 store the character pattern. If the name of the product contained in the EPROMs does not match the name on the mask ROM confirmation form, the ROM processing is disabled. Write the data correctly. Inputting the name of the product with the ASCII code ASCII codes ‘M37210M4-’ are listed on the right. The addresses and data are in hexadecimal notation. Inputting the character ROM Input the character ROM data by dividing it into character ROM1 and character ROM2. For the character ROM data, see the next page and on. Writing the product name and character ROM data onto EPROMs (2/3)

M37210M3-XXXSP/FP, M37210M4-XXXSP, M37211M2-XXXSP M37210E4-XXXSP/FP, M37210E4SP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLT AGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER GZZ–SH06–10B < 25B0 > SINGLE-CHIP MICROCOMPUTER M37210M4-XXXSP MITSUBISHI ELECTRIC The structure of character ROM (divided of 125 16 dots font) Example Character code “1A16” Example 11A016 to 11AF 16 b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0 A B C D E F A B C D E F 0016 0416 0416 0A16 0A16 1116 1116 1116 2016 2016 3F16 4016 4016 4016 0016 0016 F016 F016 F016 F016 F016 F016 F016 F016 F816 F816 F816 F416 F416 F416 F016 F016 Example 19A016 to 19AF 16 Character ROM1 Character ROM2 F16 (3/3)

M37210M3-XXXSP/FP, M37210M4-XXXSP, M37211M2-XXXSP M37210E4-XXXSP/FP, M37210E4SP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLT AGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER /LiteDiagLines/LiteDiagLines/LiteDiagLines GZZ–SH06–11B < 25B1 > SINGLE-CHIP MICROCOMPUTER M37211M2-XXXSP MITSUBISHI ELECTRIC Mask ROM number Date : Supervisorsignature Receipt Section headsignature h Customer Company name Date issued Date : TEL ( ) Note : Please fill in all items marked h . Submitted by Supervisor Issuancesignature h 1. Confirmation Specify the name of the product being ordered and the type of EPROMs submitted. Three EPROMs are required for each pattern. If at least two of the three sets of EPROMs submitted contain identical data, we will produce masks based on this data. We shall assume the responsibility for errors only if the mask ROM data on the products we produce differs from this data. Thus, extreme care must be taken to verify the data in the submitted EPROMs. Checksum code for entire EPROM (hexadecimal notation) 27256 EPROM address 000016 /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines Product name ASCII code : ‘M37211M2 –’ ROM (8K bytes) 000F16 15FF16 180016 1DFF 16 Set “FF16” in the shaded area. Write the ASCII codes that indicates the product name of “M37211M2–” to addresses 000016 to 000F16. (1) (2) EPROM type (indicate the type used) 100016 Character ROM1 600016 7FFF 16 Character ROM2 h 2. Mark specification Mark specification must be submitted using the correct form for the type package being ordered fill out the appropriate mark specification form (52P4B for M37211M2-XXXSP) and attach to the mask ROM confirmation form. h 3. Note Set the stack page selection bit to “0”, because this bit is set to “1” after reset but the internal RAM is located at 0 page only. Both P0 2 pin (9th pin) and P03 pin (10th pin) are not used as PWM output pins. (1) (2) h 4. Comments (1/3)

MITSUBISHI MICR OCOMPUTERS M37210M3-XXXSP/FP , M37210M4-XXXSP , M37211M2-XXXSP M37210E4-XXXSP/FP , M37210E4SP/FP SINGLE-CHIP 8-BIT CMOS MICR OCOMPUTER f or VOL TAGE SYNTHESIZER with ON-SCREEN DISPLA Y CONTR OLLER GZZ–SH06–11B< 25B1 > SINGLE-CHIP MICROCOMPUTER M37211M2-XXXSP MITSUBISHI ELECTRIC ‘M’= 164D 16‘3’= 3 3 16‘7’= 3 7 16‘2’= 3 2 16‘1’= 3 1 16‘1’= 3 1 16‘M’= 4D 16‘2’= 32 000016 000116 000216 000316 000416 000516 000616 000716 Address ‘–’= 162 D 16FF 16FF 16FF 16FF 16FF 16FF 16FF 000816 000916 000A16 000B16 000C 16 000D 16 000E16 000F16 Address Addresses 000016 to 000F16 store the product name, and addresses 100016 to 15FF16 and addresses 180016 to 1DFF16 store the character pattern. If the name of the product contained in the EPROMs does not match the name on the mask ROM confirmation form, the ROM processing is disabled. Write the data correctly. Inputting the name of the product with the ASCII code ASCII codes ‘M37211M2-’ are listed on the right. The addresses and data are in hexadecimal notation. Inputting the character ROM Input the character ROM data by dividing it into character ROM1 and character ROM2. For the character ROM data, see the next page and on. Writing the product name and character ROM data onto EPROMs (2/3)

M37210M3-XXXSP/FP, M37210M4-XXXSP, M37211M2-XXXSP M37210E4-XXXSP/FP, M37210E4SP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLT AGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER GZZ–SH06–11B < 25B1 > SINGLE-CHIP MICROCOMPUTER M37211M2-XXXSP MITSUBISHI ELECTRIC The structure of character ROM (divided of 125 16 dots font) Example Character code “1A16” ÜÜ Example 11A0 16 to 11AF 16 b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0 A B C D E F A B C D E F 0016 0416 0416 0A16 0A16 1116 1116 1116 2016 2016 3F16 4016 4016 4016 0016 0016 F016 F016 F016 F016 F016 F016 F016 F016 F816 F816 F816 F416 F416 F416 F016 F016 Example 19A0 16 to 19AF 16 Character ROM1 Character ROM2 F16 (3/3)

M37210M3-XXXSP/FP, M37210M4-XXXSP, M37211M2-XXXSP M37210E4-XXXSP/FP, M37210E4SP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLT AGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER

M37210M3-XXXSP/FP, M37210M4-XXXSP, M37211M2-XXXSP M37210E4-XXXSP/FP, M37210E4SP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLT AGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER

Sep. First Edition 1996 H-DF319-B Editioned by Committee of editing of Mitsubishi Semiconductor Data Book Published by Mitsubishi Electric Corp., Semiconductor Division This book, or parts thereof, may not be reproduced in any form without permission of Mitsubishi Electric Corporation. MITSUBISHI DATA BOOK SINGLE-CHIP 8-BIT MICROCOMPUTERS Vol.3

Rev. Rev. No. date

1.0 First Edition 9708

2.0 Information about copyright note, revision number, release date added (last page). 971130 M37210M3-XXXSP/FP, M37210M4-XXXSP, M37211M2-XXXSP, M37210E4-XXXSP/FP, M37210E4SP/FP DATA SHEET Revision Description REVISION DESCRIPTION LIST (1/1)