M37207MF

M37207MF MITSUBISHI | Alldatasheet

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Technical content

DESCRIPTION

The M37207MF-XXXSP/FP and M37207M8-XXXSP are single-chip microcomputers designed with CMOS silicon gate technology. It is housed in a 64-pin shrink plastic molded DIP or a 80-pin plastic molded QFP. In addition to their simple instruction sets, the ROM, RAM and I/O addresses are placed on the same memory map to enable easy pro- gramming. The M37207MF-XXXSP/FP has a PWM function and an OSD func- tion, so it is useful for a channel selection system for TV. The fea- tures of the M37207EFSP/FP are similar to those of the M37207MF- XXXSP/FP except that these chips have a built-in PROM which can be written electrically. The difference between M37207MF-XXXSP/ FP and M37207M8-XXXSP are the ROM size, RAM size, ROM size for display and kinds of character. Accordingly, the following descrip- tions will be for the M37207MF-XXXSP/FP unless otherwise noted.

• Power dissipation (at VCC = 5.5 V, 8 MHz oscillation frequency, CRT on) (at VCC = 5.5 V, 32 kHz oscillation frequency)
• CRT display function (16 lines maximum) 384 kinds (M37207MF-XXXSP/FP, M37207EFSP/FP) Kinds of character colors (It can be specified by the character) maximum 15 kinds (R, G, B, I) Kinds of character background colors (It can be specified by the character) maximum 7 kinds (R, G, B) 1/2-character unit color specification is possible. Kinds of raster colors (maximum 15 kinds) Display position Bordering (horizontal and vertical) Wipe function Scanning line double count mode display is possible. APPLICATION TV

FEATURES

62K bytes (M37207MF-XXXSP/FP, M37207EFSP/FP) 960 bytes (M37207MF-XXXSP/FP, M37207EFSP/FP) 12K bytes (M37207MF-XXXSP/FP, M37207EFSP/FP)

• Minimum instruction execution time
• Programmable I/O ports MITSUBISHI MICROCOMPUTERS M37207MF-XXXSP/FP, M37207M8-XXXSP M37207EFSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER and ON-SCREEN DISPLAY CONTROLLER

M37207MF-XXXSP/FP, M37207M8-XXXSP M37207EFSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER and ON-SCREEN DISPLAY CONTROLLER PIN CONFIGURATION (TOP VIEW) Outline 64P4B P65/PWM5 P41/SCLK2 /SCL3/XCOUT OSC1/P7 0/AD4 OSC2/P7 1/AD5 P36/INT2/AD2 P35/AD1 P34/INT1 D-A/AD3 P60/PWM0 P61/PWM1 P66/PWM6 P67/PWM7 P33/TIM3 P32/TIM2/AD6 P31 P30 P47/SRDY1 /PWM8 P46/SIN1/PWM9 P43/SRDY2 /SCL2/AD7 P42/SIN2/SDA2/AD8 P40/SOUT2 /SDA3/XCIN VCC H SYNC VSYNC R/P52 G/P53 B/P54 I/P55/TIM1 OVERFLOW P07 P11 P13 P15 P16 P17 P20 P22 P23 P24 P25 P26 P27 P21 P62/PWM2 P63/PWM3 P64/PWM4 P45/SCLK1 /SCL1 P44/SOUT1 /SDA1 OUT/P5 6 P00 P04 P05 P06 M37207MF-XXXSP, M37207M8-XXXSP M37207EFSP f CNV SS RESET XOUT XIN VSS P01 P02 P03 P10 P12 P14

M37207MF-XXXSP/FP, M37207M8-XXXSP M37207EFSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER and ON-SCREEN DISPLAY CONTROLLER PIN CONFIGURATION (TOP VIEW) Outline 80P6N-A NC: Unconnected P07 RESET CNV SS XIN P04 P05 P06 NC NC NC NC NC NC NC NC NC NC NC NC NC 19 20 NC P65/PWM5 P60/PWM0 P61/PWM1 P66/PWM6 P67/PWM7 P33/TIM3 P32/TIM2/AD6 P31 P30 P46/SIN1/PWM9 P62/PWM2 P63/PWM3 P64/PWM4 P45/SCLK1 /SCL1 f XOUT VSS OSC1/P7 0/AD4 OSC2/P7 1/AD5 P36/INT2/AD2 P35/AD1 P34/INT1 D-A/AD3 VCC H SYNC VSYNC R/P52 G/P53 B/P54 I/P55/TIM1 OVERFLOW P11 P13 P15 P16 P17 P20 P22 P23 P24 P25 P26 P27 P21 OUT/P5 6 P00 P01 P02 P03 P10 P12 P14 M37207MF-XXXFP, M37207EFFP NC NC P47/SRDY1 /PWM8 P44/SOUT1 /SDA1 P43/SRDY2 /SCL2/AD7 P42/SIN2/SDA2/AD8 P41/SCLK2 /SCL3/XCOUT P4f/SOUT2 /SDA3/XCIN

M37207MF-XXXSP/FP, M37207M8-XXXSP M37207EFSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER and ON-SCREEN DISPLAY CONTROLLER FUNCTIONAL BLOCK DIAGRAM of M37207M8-XXXSP Clock input Clock output XIN XOUT Reset input VCC VSS CNV SS Clock output for CRT/ Sub-clock output Input ports P70, P71 OSC1 OSC2 Clock input for CRT/ Sub-clock input P1 (8)P0(8) P2 (8) SOUT1 SCLK1 SIN1 SI/O (8) P6 (8) INT1 INT2 P5 (5)I B G R HSYNC VSYNC A-D comparator 8-bit arithmetic and logical unit Accumulator A (8) Timer 6 T6 (8) Timer 5 T5 (8) Timer 4 T4 (8) Timer 3 T3 (8) Timer 2 T2 (8) Timer 1 T1 (8) Timer count source selection circuit TIM2 TIM3 instruction register (8) Instruction decoder Control signal processor status register PS (8) Stack pointer S (8) Index register Y (8) Index register X (8) ROM

64 K bytes

PC L (8) Program counter PC H (8) RAM 960 bytes Data bus Clock generating circuit 30 31 29 RESET 64 32 27 1 2 Address bus 41 42 43 44 45 46 47 48 33 34 35 3637 38 39 40 34 5 15 16 17 18 62 63 I/O ports P00–P07 I/O ports P10–P17 I/O ports P20–P27 I/O ports P30–P36 I/O ports P60–P67 Sync input 12 11 10 9 8714 13 58 59 60 6157 Output ports P52–P56 PWM6 PWM5 PWM4 PWM3 PWM2 PWM1 PWM0 PWM7 Timing output f OUT SRDY1 49 50 51 52 53 54 55 56 Multi-master I2C-BUS Interface SCL2 SDA1 SCL1 SDA2 SCL3 SDA3 8-bit PWM circuit SOUT2 SCLK2 SIN2 SRDY2 P4 (8) 25 24 2322 21 20 19 I/O ports P40–P47 266 D-A 14-bit PWM circuit A-D comparator CRT circuit P3 (7) XCIN XCOUT (Note 1) (Note 2) Note 1: M37207M8-XXXSP has a 512 bytes RAM. Note 2: M37207M8-XXXSP has a 32 K bytes ROM.

M37207MF-XXXSP/FP, M37207M8-XXXSP M37207EFSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER and ON-SCREEN DISPLAY CONTROLLER Number of basic instructions Instruction execution time Clock frequency Memory size Input/Output ports Serial I/O Multi-master I2C-BUS interface A-D comparator PWM output circuit Timers ROM correction function Subroutine nesting Interrupt interval determination circuit Interrupt Clock generating circuit 0–P07 P10–P17 P20–P27 P30, P31 P32–P36 P40–P47 P52–P56 P60–P67 P70, P70 ROM RAM CRT ROM CRT RAM Parameter 0.5 ms (the minimum instruction execution time, at 8 MHz oscillation fre- quency)

8 MHz (maximum)

32 K bytes

8-bit 5 1 (CMOS input/output structure) 8-bit 5 1 (CMOS input/output structure) 8-bit 5 1 (CMOS input/output structure) 2-bit 5 1 (CMOS input/output structure) 5-bit 5 1 (N-channel open-drain output structure, can be used as external clock input pins, A-D input pins, INT input pins) 8-bit 5 1 (N-channel open-drain output structure, can be used as serial I/O pins, A-D input pins, PWM output pins, multi-master I2C-BUS interface, sub-clock I/O pins) 5-bit 5 1 (CMOS output structure, can be used as CRT output pins, an external clock output pin) 8-bit 5 1 (N-channel open-drain output structure, can be used as PWM output) 2-bit 5 1 (can be used as CRT display clock I/O pins, analog input pins) 8-bit 5 1 (2 systems) 1 (3 systems) 8 channels (6-bit resolution) 14-bit 5 1, 8-bit 5 10 8-bit timer 5 6 32 bytes 5 2 128 levels (maximum) External interrupt 5 2, Internal timer interrupt 5 6, Serial I/O interrupt 5 1, CRT interrupt 5 1, Multi-master I 2C-BUS interface interrupt 5 1, f(XIN)/4096 interrupt 5 1, VSYNC interrupt 5 1, BRK interrupt 5 1 2 built-in circuits (externally connected to a ceramic resonator or a quartz- crystal oscillator) I/O I/O I/O I/O I/O I/O Output I/O Input Functions FUNCTIONS ROM correction memory M37207M8-XXXSP M37207MF-XXXSP/FP , M37207EFSP/FP M37207M8-XXXSP M37207MF-XXXSP/FP , M37207EFSP/FP M37207M8-XXXSP M37207MF-XXXSP/FP , M37207EFSP/FP

M37207MF-XXXSP/FP, M37207M8-XXXSP M37207EFSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER and ON-SCREEN DISPLAY CONTROLLER Power source voltage Power dissipation Operating temperature range Device structure Package CRT display function Number of display characters Character display area Kinds of character sizes Kinds of character colors Display position (horizontal, vertical) M37207M8-XXXSPKinds of characters CRT ON CRT OFF CRT OFF Functions

5 V ± 10 %

165 mW typ. (at oscillation frequency f(X IN) = 8 MHz, fOSC = 8 MHz) 82.5 mW typ. (at oscillation frequency f(XIN) = 8 MHz) 0.33 mW typ. (at oscillation frequency fCLK = 32 kHz, f(XIN) = stopped) 1.1 mW (maximum) –10 °C to 70 °C CMOS silicon gate process 64-pin shrink plastic molded DIP 80-pin plastic molded QFP 24 characters 5 3 lines (maximum 16 lines by software) 12 5 16 dots

256 Kinds

384 Kinds

Maximum 15 kinds (R, G, B, I); can be specified by the character 64 levels (horizontal) 5 128 levels (vertical) Parameter FUNCTIONS (continued) In high-speed mode In low-speed mode In stop mode M37207MF-XXXSP, M37207M8-XXXSP M37207EFSP M37207MF-XXXFP, M37207EFFP M37207MF-XXXSP/FP, M37207EFSP/FP

M37207MF-XXXSP/FP, M37207M8-XXXSP M37207EFSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER and ON-SCREEN DISPLAY CONTROLLER Power source CNV SS Reset input Clock input Clock output I/O port P0 I/O port P1 I/O port P2 I/O port P3 I/O port P3 Analog input External clock input External interrupt input I/O port P4 Serial I/O data input/output Serial I/O synchro- nous clock input/ output Serial I/O receive enable signal output Multi-master I2C- BUS interface Sub-clock input Sub-clock output Analog input PWM output Input Input Output I/O I/O I/O I/O I/O Input Input Input I/O I/O I/O Output I/O Input Output Input Output PIN DESCRIPTION Pin Functions Apply voltage of 5 V ± 10 % (typical) to VCC and AVCC , and 0 V to VSS . Connected to VSS . To enter the reset state, the reset input pin must be kept at a “L” for 2 ms or more (under normal VCC conditions). If more time is needed for the quartz-crystal oscillator to stabilize, this “L” condition should be maintained for the required time. This chip has an internal clock generating circuit. To control generating frequency, an external ceramic resonator or a quartz-crystal oscillator is connected between pins X IN and XOUT . If an external clock is used, the clock source should be connected to the XIN pin and the XOUT pin should be left open. Port P0 is an 8-bit I/O port with direction register allowing each I/O bit to be individually programmed as input or output. At reset, this port is set to input mode. The output structure is CMOS output. See notes at end of table for full details of port P0 functions. Port P1 is an 8-bit I/O port and has basically the same functions as port P0. The output structure is CMOS output. Port P2 is an 8-bit I/O port and has basically the same functions as port P0. The output structure is CMOS output. Ports P3 0, P31 are 2-bit I/O ports and have basically the same functions as port P0. The output structure is CMOS output. Ports P32–P36 are 5-bit I/O ports and have basically the same functions as port P0. The output structure is N-channel open-drain output. Pins P32, P35, P36 are also used as analog input pins AD6, AD1 and AD2 respectively. Pins P32, P33 are also used as external clock input pins TIM2, TIM3 respectively. Pins P34, P36 are also used as external interrupt input pins INT1, INT2. Port P4 is an 8-bit I/O port and has basically the same functions as port P0. The output structure is N-channel open-drain output. Pins P40, P42, P44, P46 are also used as serial I/O data input/output pins SOUT2 , SIN2, SOUT1 , SIN1 respectively. The output structure is N-channel open-drain output. Pins P41, P45 are also used as serial I/O synchronous clock input/output pins SCLK2 , SCLK1 respectively. Pins P43, P47 are also used as serial I/O receive enable signal output pins SRDY2 , SRDY1 respectively. The output structure is N-channel open-drain output. Pins P40–P4 5 are also used as SDA3, SCL3, SDA2, SCL2, SDA1, SCL1 respectively when multi-master I2C-BUS interface is used. The output structure is N-channel open- drain output. Pin P40 is also used as sub-clock input pin XCIN. Pin P41 is also used as sub-clock output pin XCOUT . The output structure is N-channel open-drain output. Pins P42, P43 are also used as analog input pins AD8, AD7 respectively. Pins P46, P47 are also used as PWM output pins PWM9, PWM8 respectively. The output structure is N-channel open-drain output. Input/ OutputName VCC, VSS CNV SS RESET XIN XOUT P00–P07 P10–P17 P20–P27 P30, P31 P32/TIM2/ AD6, P33/TIM3, P34/INT1, P35/AD1, P36/INT2/ AD2 P40/SOUT2 / SDA3/X CIN, P41/SCLK2 / SCL3/ X COUT , P42/ SIN2/SDA2/ AD8, P43/SRDY2 / SCL2/AD7, P44/SOUT1 / SDA1, P45/SCLK1 / SCL1, P46/SIN1/ PWM9, P47/SRDY1 / PWM8

M37207MF-XXXSP/FP, M37207M8-XXXSP M37207EFSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER and ON-SCREEN DISPLAY CONTROLLER Output port CRT output Timer 1 overflow signal output I/O port P6 PWM output Input port P7 Clock input for CRT display Clock output for CRT display Analog input H SYNC input VSYNC input Timing output DA output Analog input PIN DESCRIPTION (continued) R/P52, G/P53, B/P54, I/P55/TIM1 OVERFLOW, OUT/P5 6 P60/PWM– P67/PWM7 OSC1/P7 0/ AD4, OSC2/P7 1/ AD5 H SYNC VSYNC f D-A/AD3 Output Output Output I/O Output Input Input Output Input Input Input Output Output Input Ports P5 2–P56 are 5-bit output ports. The output structure is CMOS output. Pins P52–P56 are also used as CRT output pins R, G, B, I, OUT respectively. The output structure is CMOS output. Pin P55 is also used as timer 1 overflow signal output pin TIM1 OVERFLOW. The output structure is CMOS output. Port P6 is an 8-bit I/O port and has basically the same functions as port P0. The output structure is N-channel open-drain output. Pins P60–P6 7 are also used as PWM output pins PWM0–PWM7. The output structure is CMOS output. Ports P70, P71 are 2-bit input port. Pin P70 is also used as CRT display clock input pin OSC1. Pin P71 is also used as CRT display clock output pin OSC2. The output structure is CMOS output. Pins P70, P71 are also used as analog input pins AD4, AD5 respectively. This is a horizontal synchronous signal input for CRT display. This is a vertical synchronous signal input for CRT display. This is a timing output pin. This pin has reset-out output function. The output structure is CMOS output. This is an output pin for 14-bit PWM. The D-A pin is also used as analog input pin AD3. Note : As shown in the memory map (Figure 5), port P0 is accessed as a memory at address 00C016 of zero page. Port P0 has the port P0 direction register (address 00C116 of zero page) which can be used to program each bit as an input (“0”) or an output (“1”). The pins programmed as “1” in the direction register are output pins. When pins are programmed as “0,” they are input pins. When pins are programmed as output pins, the output data are written into the port latch and then output. When data is read from the output pins, the output pin level is not read but the data of the port latch is read. This allows a previously-output value to be read correctly even if the output “L” voltage has risen, for example, because a light emitting diode was directly driven. The input pins float, so the values of the pins can be read. When data is written into the input pin, it is written only into the port latch, while the pin remains in the floating state. Pin Name Input/ Output Functions

M37207MF-XXXSP/FP, M37207M8-XXXSP M37207EFSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER and ON-SCREEN DISPLAY CONTROLLER N-channel open-drain output Ports P46, P47, P60–P67 Note : Each port is also used as follows: P47 : SRDY1 /PWM8 P60–P67 : PWM0–PWM7 Fig. 1. I/O Pin Block Diagram (1) Ports P00–P07, P10–P17, P20–P27, P30, P31, D-A Data bus Direction register Port latch Ports P46, P47, P60–P67 Data bus Direction register Port latch Ports P32–P36, P42–P45 Data bus Direction register Port latch N-channel open-drain output Ports P32–P36, P42–P45 Note : Each port is also used as follows: P32 : TIM2/AD6 P33 : TIM3 P34 : INT1 P35 : AD1 P36 : INT2/AD2 P43 : SRDY2 /SCL2/AD7 P44 : SOUT1 /SDA1 P45 : SCLK1 /SCL1 CMOS output Ports P00–P07, P10–P17, P20–P27, P30, P31, D-A Note : D-A pin is also used as AD3.

M37207MF-XXXSP/FP, M37207M8-XXXSP M37207EFSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER and ON-SCREEN DISPLAY CONTROLLER R, G, B, I, OUT, H SYNC , VSYNC Internal circuit Internal circuit Fig. 2. I/O Pin Block Diagram (2) Schmidt input H SYNC , VSYNC CMOS output P52–P55, φ Note : Each port is also used as follows: P52 : R P53 : G P54 : B P55 : I/TIM1 P56 : OUT P52–P55, φ

M37207MF-XXXSP/FP, M37207M8-XXXSP M37207EFSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER and ON-SCREEN DISPLAY CONTROLLER FUNCTIONAL DESCRIPTION Central Processing Unit (CPU) This microcomputer uses the standard 740 Family instruction set. Refer to the table of 740 Family addressing modes and machine instructions or the SERIES 740 <Software> User’s Manual for de- tails on the instruction set. Machine-resident 740 Family instructions are as follows: The FST, SLW instruction cannot be used. The MUL, DIV, WIT and STP instructions can be used. CPU Mode Register The CPU mode register contains the stack page selection bit and internal system clock selection bit. The CPU mode register is allo- cated at address 00FB 16. Fig. 3. CPU Mode Register b7b6 b5b4b3 b2b1b0 B After resetRW CPU Mode Register 0, 1 Name Functions Processor mode bits (CM0, CM1) 0 0: Single-chip mode 0 1: 1 0: Not available 1 1: Fix these bits to “1.” 1Stack page selection bit (CM2) (See note 1) b1 b0 0: 0 page 1: 1 page

00 CPU mode register (CPUM) (CM) [Address 00FB16]

60 Main Clock (XIN–XOUT )

(CM6) RW RW XCOUT drivability selection bit (CM5) 0: LOW drive 1: HIGH drive 0: Oscillating 1: Stopped

70 Internal system clock

(CM7) RW0: X IN–XOUT selected (high-speed mode) 1: XCIN–XCOUT selected (high-speed mode) Notes 1: This bit is set to “1” after the reset release. 2: The internal system clock f stops at HIGH.

41 Internal system clock

(CM4) (See note 2) 0: Output is stopped 1: Internal system clock f output RW

M37207MF-XXXSP/FP, M37207M8-XXXSP M37207EFSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER and ON-SCREEN DISPLAY CONTROLLER MEMORY Special Function Register (SFR) Area The special function register (SFR) area in the zero page contains control registers such as I/O ports and timers. RAM RAM is used for data storage and for stack area of subroutine calls and interrupts. ROM ROM is used for storing user programs as well as the interrupt vector area. RAM for Display RAM for display is used for specifying the character codes and col- ors to display. ROM for Display ROM for display is used for storing character data. Interrupt Vector Area The interrupt vector area contains reset and interrupt vectors. Zero Page The 256 bytes from addresses 000016 to 00FF16 are called the zero page area. The internal RAM and the special function registers (SFR) are allocated to this area. The zero page addressing mode can be used to specify memory and register addresses in the zero page area. Access to this area with only 2 bytes is possible in the zero page addressing mode. Special Page The 256 bytes from addresses FF0016 to FFFF16 are called the spe- cial page area. The special page addressing mode can be used to specify memory addresses in the special page area. Access to this area with only 2 bytes is possible in the special page addressing mode. Fig. 4. Memory Map ROM Correction Memory (RAM) This is used as the program area for ROM correction. 000016 00C0 16 00FF16 01FF16 033F16 080016 SFR area Not used Not used FFFF 16 FFDE 16 FF00 16 030016 Interrupt vector area Not used 1000016 11FFF 16 1FFFF 16 ROM for display (8 K bytes) for M37207M8 Special page ROM (32 K bytes) for M37207M8 RAM for display (144 bytes) (See note) Zero page Note: Refer to Table 9. Contents of CRT display RAM. 020416 021B16 02C0 16 02FF16 2 page register Not used 06D7 16 060016 Not used ROM correction memory (64 bytes) Block 1: addresses 02C016 to 02DF16 Block 2: addresses 02E016 to 02FF16 800016 04FF16 12FFF 16 ROM for display (12 K bytes) for M37207MF ROM (62 K bytes) for M37207MF RAM (512 bytes) for M37207M8 RAM (960 bytes) for M37207MF

M37207MF-XXXSP/FP, M37207M8-XXXSP M37207EFSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER and ON-SCREEN DISPLAY CONTROLLER Fig. 5. Memory Map of Special Function Register (SFR) n SFR Area (addresses C016 to DF16) D0 16 D1 16 D2 16 D3 16 D4 16 D5 16 D6 16 D7 16 D8 16 D9 16 DA 16 DB 16 DC 16 DD 16 DE 16 DF 16 C0 16 C1 16 C2 16 C3 16 C4 16 C5 16 C6 16 C7 16 C8 16 C9 16 CB 16 CC 16 CD 16 CE 16 CF 16 CA 16 Address Port P5 (P5) Port P5 control register (D5) DA-H register (DA-H) DA-L register (DA-L) PWM0 register (PWM0) Port P1 (P1) Port P1 direction register (D1) Port P3 (P3) Port P3 direction register (D3) Port P2 (P2) Port P2 direction register (D2) Register Port P0 (P0) Port P0 direction register (D0) PWM1 register (PWM1) PWM2 register (PWM2) PWM3 register (PWM3) PWM4 register (PWM4) PWM output control register 1 (PW) PWM output control register 2 (PN) Serial I/O mode register (SM) Serial I/O regsiter (SIO) Bit allocation State immediately after reset : “0” immediately after reset : Undefined immediately after reset <State immediately after reset> : “1” immediately after reset : Fix this bit to “0” (do not write “1”) < Bit allocation> Function bit : No function bit : Fix this bit to “1” (do not write “0”) Name : I2C data shift register (S0) I2C control register (S1D) I2C clock control register (S2) I2C status register (S1) I2C address register (S0D) PW0PW1PW2PW3PW4PW5PW6PW7 PN2PN3PN4 b7 b0 0016 b7 b0 0016 0016 0 ???? ? ? SM0SM1SM2SM3SM5SM6 0 0016 0016 0016 0016 SAD0SAD1SAD2SAD3SAD4SAD5SAD6 RBW LRBAD0AASALPINBBTRXMST BC0BC1BC2ESOALSBSEL0BSEL1 CCR0CCR1CCR2CCR3CCR4ACK 10BIT SAD D1D2D3D4D5D6D7 D0 FAST MODE ACK BIT PN1 PN0 0016 0016 0016 0016 00 0 01 0 0? 0016 RE1RE2RE3RE4RE5 RE0 Port P4 (P4) Port P4 direction register (D4) Port P6 (P6) Port P6 direction register (D6) Interrupt interval determination register (??) Interrupt interval determination control register (RE)

M37207MF-XXXSP/FP, M37207M8-XXXSP M37207EFSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER and ON-SCREEN DISPLAY CONTROLLER Fig. 6. Memory Map of Special Function Register (SFR) b7 b0 Bit allocation State immediately after reset b7 b0 : “0” immediately after reset : Undefined immediately after reset < State immediately after reset > : “1” immediately after reset : Fix this bit to “0” (do not write “1”) < Bit allocation> Function bit : No function bit : Fix this bit to “1” (do not write “0”) Name : F016 F116 F216 F316 F416 F516 F616 F716 F816 F916 FA 16 FB 16 FC 16 FD 16 FE 16 FF16 E016 E116 E216 E316 E416 E516 E616 E716 E816 E916 EB 16 EC 16 ED 16 EE 16 EF 16 EA 16 Address CRT control register 1 (CC) CRT port control register (CRTP) Wipe start register (??) A-D control register 1 (ADM) Timer 1 (TM1) Vertical register 2 (CV2) Color register 0 (CO0) Color register 1 (CO1) Character size register (CS) Border selection register (MD) Register Horizontal register (HR) Vertical register 1 (CV1) Timer 2 (TM2) Timer 3 (TM3) Timer 4 (TM4) Timer mode register 1 (TMR1) Timer mode register 2 (TMR2) PWM5 register (PWM5) PWM8 register (PWM8) PWM9 register (PWM9) Interrupt request register 1 (IREQ1) Interrupt request register 2 (IREQ2) Interrupt control register 1 (ICON1) Interrupt control register 2 (ICON2) Color register 2 (CO2) Color register 3 (CO3) Wipe mode register (SL) CPU mode register (CPUM) n SFR Area (addresses E016 to FF16) HR0HR1HR2HR3HR4HR5 CV10CV11CV12CV13CV14CV15CV16 CV20CV21CV22CV23CV24CV25CV26 CS10CS11CS20CS21 MD10MD20 CO01CO02CO03CO05 CO11CO12CO13CO15 CO21CO22CO23CO25 CO31CO32CO33CO35 CC0CC1CC2 VSYCR/G/BIRGB HSYC SL0SL1 ADM0ADM1ADM2ADM4 TMR10TMR11TMR12TMR13TMR14 CM2 TM1RTM2RTM3RTM4RCRTRVSCRIICR CK0MSR IT1RIT2RS1R TM1ETM2ETM3ETM4ECRTEVSCEIICE IT1EIT2ESIEMSE 0016 ?00 000 00 FF16 0716 FF16 0716 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 SL2SL3SL4SL5SL6 TMR15TMR16TMR17 CM7 CM6 CM5 TM56R TM56ETM56C CK001 11 001 0 CV30CV31CV32CV33CV34CV35CV36 ?0 ?????? CS30CS31CS7 MD11MD21MD31 MD30 CO00 CO11 CO22 CO33 CO04 CO14 CO24 CO34 CO06 CO16 CO26 CO36 CO07 CO17 CO27 CO37 0016

0 CC3CC4CC5CC6

0016TMR20TMR21TMR22TMR23TMR24TMR25TMR26TMR27 Vertical register 3 (CV3) Display block counter (CBC) PWM6 register (PWM6) PWM7 register (PWM7)

M37207MF-XXXSP/FP, M37207M8-XXXSP M37207EFSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER and ON-SCREEN DISPLAY CONTROLLER Fig. 7. Memory Map of 2 Page Register Address Register n SFR Area (addresses 20416 to 21B16) 21016 21116 21216 21316 21416 21516 21616 21716 21816 21916 21A16 21B16 ROM correction address 1 (high-order) ROM correction address 1 (low-order) ROM correction address 2 (high-order) ROM correction address 2 (low-order) ROM correction enable register (RCR) b7 b0 Bit allocation State immediately after reset b7 b0 : “0” immediately after reset : Undefined immediately after reset <State immediately after reset> : “1” immediately after reset : Fix this bit to “0” (do not write “1”) < Bit allocation> Function bit : No function bit : Fix this bit to “1” (do not write “0”) Name : ??P7D0 0016 0016 000 0 00 OP1OP0 0016 0016 0 0016 0016 P7D1P7D2P7D4 CBR0CBR1 ADC0ADC1ADC2ADC3ADC4ADC5 SIC0SIC1SIC2SIC3SIC4SIC5SIC8SIC7 TMR30 00RC1RC0 0016 0016 0016 0016 ??? ?000 0 20416 20516 20616 20716 20816 20916 20A16 20B16 20C 16 20D 16 20E16 20F16 Timer 5 (T5) Timer 6 (T6) Port control register (P7D) Serial I/O control register (SIC) CRT control register 2 (CBR) CRT clock selection register (OP) A-D control register (ADC) Timer mode register (TMR3)

M37207MF-XXXSP/FP, M37207M8-XXXSP M37207EFSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER and ON-SCREEN DISPLAY CONTROLLER Fig. 8. Internal State of Processor Status Register and Program Counter at Reset b7 b0 b7 b0 Register Processor status register (PS) Bit allocation State immediately after reset Program counter (PCH ) Program counter (PCL) Contents of address FFFF16 Contents of address FFFE16 : “0” immediately after reset : Undefined immediately after reset <State immediately after reset> : “1” immediately after reset : Fix this bit to “0” (do not write “1”) <Bit allocation> Function bit : No function bit : Fix this bit to “1” (do not write “0”) Name :

the table because its operation is similar to an interrupt. register are automatically stored into the stack. be set to “0” and “1” by a program. Reset is treated as a non-maskable interrupt with the highest priority. Figure 9 shows interrupt control. detected; when it is “1,” a change from “H” to “L” is detected. Note that all bits are cleared to “0” at reset. An interrupt is generated by an overflow of timer 1, 2, 3 or 4. Table 1. Interrupt Vector Addresses and Priority Note : Switching a source during a program causes an unnecessary interrupt. Therefore, set a source at initializing of program.

M37207MF-XXXSP/FP, M37207M8-XXXSP M37207EFSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER and ON-SCREEN DISPLAY CONTROLLER (5) f(XIN)/4096 interrupt This interrupt occurs regularly with a f(XIN)/4096 period. Set bit 0 of the PWM output control register 1 to “0.” (6) Multi-master I2C-BUS interface interrupt This is an interrupt request related to the multi-master I2C-BUS interface. (7) Timer 5 · 6 interrupt An interrupt is generated by an overflow of timer 5 or 6. Their priorities are same, and can be switched by software. (8) BRK instruction interrupt This software interrupt has the least significant priority. It does not have a corresponding interrupt enable bit, and it is not af- fected by the interrupt disable flag I (non-maskable). Fig. 9. Interrupt Control Interrupt request bit Interrupt enable bit Interrupt disable flag I BRK instruction Reset Interrupt request

M37207MF-XXXSP/FP, M37207M8-XXXSP M37207EFSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER and ON-SCREEN DISPLAY CONTROLLER Fig. 10. Interrupt Request Register 1 b7b6 b5b4b3 b2b1b0 Interrupt request register 1 (IREQ1) [Address 00FC B Name Functions After resetRW Interrupt Request Register 1 0 0 : No interrupt request issued 1 : Interrupt request issued Timer 1 interrupt request bit (TM1R)

1 Timer 2 interrupt

request bit (TM2R)

2 Timer 3 interrupt

request bit (TM3R)

3 Timer 4 interrupt

request bit (TM4R)

4 CRT interrupt

request bit (CRTR) 5V SYNC interrupt request bit (VSCR) 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 ] 0 ] 0 ] 0 ] 0 ] 0 ] Multi-master I2C-BUS interface interrupt request bit (IICR) 0 : No interrupt request issued 1 : Interrupt request issued 16] R R R R R R R 7 Nothing is assigned. This bit is a write disable bit. When this bit is read out, the value is “0.” —R0 Fig. 11. Interrupt Request Register 2 b7b6 b5b4b3 b2b1b0 Interrupt request register 2 (IREQ2) [Address 00FD B Name Functions After resetRW Interrupt Request Register 2

0 INT1 interrupt

request bit (ITIR) 0 : No interrupt request issued 1 : Interrupt request issued

1 INT2 interrupt

request bit (IT2R)

2 Serial I/O interrupt

request bit (SIR) 4 f(XIN)/4096 interrupt request bit (MSR) 3,6 Nothing is assigned. These bits are write disable bits. When these bits are read out, the values are “0.” 7 Fix this bit to “0.” 0 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued ] : “0” can be set by software, but “1” cannot be set. 0 ] 0 ] 0 ] 0 ] 0 : No interrupt request issued 1 : Interrupt request issued 16] R R R R RW

5 Timer 5 • 6 interrupt

request bit (TM56R) 0 : No interrupt request issued 1 : Interrupt request issued 0 ]R

M37207MF-XXXSP/FP, M37207M8-XXXSP M37207EFSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER and ON-SCREEN DISPLAY CONTROLLER Fig. 12. Interrupt Control Register 1 b7b6 b5b4b3 b2b1b0 Interrupt control register 1 (ICON1) [Address 00FE16] B Name Functions After resetRW Interrupt Control Register 1

0 Timer 1 interrupt

enable bit (TM1E) 0 : Interrupt disabled 1 : Interrupt enabled enable bit (TM2E) enable bit (TM3E)

4 CRT interrupt enable

bit (CRTE) 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 RW RW RW RW RW R 0 R Timer 4 interrupt enable bit (TM4E) 0 : Interrupt disabled 1 : Interrupt enabled

5 VSYNC interrupt enable

bit (VSCE) 0 : Interrupt disabled 1 : Interrupt enabled 0R W Multi-master I2C-BUS interface interrupt enable bit (IICE) 0 : Interrupt disabled 1 : Interrupt enabled W —Nothing is assigned. This bit is a write disable bit. When this bit is read out, the value is “0.” Fig. 13. Interrupt Control Register 2 b7b6 b5b4b3 b2b1b0 Interrupt control register 2 (ICON2) [Address 00FF16] B Name Functions After resetRW Interrupt Control Register 2 enable bit (IT1E) 0 : Interrupt disabled 1 : Interrupt enabled

1 INT2 interrupt enable

bit (IT2E) enable bit (SIE) 3, 6Fix these bits to “0.” 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 0 RW RW RW RW 4 f(XIN)/4096 interrupt enable bit (MSE) 0 : Interrupt disabled 1 : Interrupt enabled 0R W enable bit (TM56E) 0 : Interrupt disabled 1 : Interrupt enabled 0R W

7 Timer 5 • 6 interrupt

switch bit (TM56C) 0 : Timer 5 1 : Timer 6 0R W

M37207MF-XXXSP/FP, M37207M8-XXXSP M37207EFSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER and ON-SCREEN DISPLAY CONTROLLER TIMERS The M37267M6-XXXSP has 6 timers: timer 1, timer 2, timer 3, timer 4, timer 5 and timer 6. All timers are 8-bit timers with the 8-bit timer latch. The timer block diagram is shown in Figure 17 . 0 . All of the timers count down and their divide ratio is 1/(n+1), where n is the value of timer latch. By writing a count value to the correspond- ing timer latch (addresses 00F0 16 to 00F316 : timers 1 to 4, addresses 020C 16 and 020D16 : timers 5 and 6), the value is also set to a timer, simultaneously. The count value is decremented by 1. The timer interrupt request bit is set to “1” by a timer overflow at the next count pulse after the count value reaches “00 16.” (1) Timer 1 Timer 1 can select one of the following count sources:

• f(XIN)/16 or f(XCIN)/16
• f(XIN)/4096 or f(XCIN)/4096
• f(XCIN)
• External clock from the TIM2 pin The count source of timer 1 is selected by setting bits 5 and 0 of timer mode register 1 (address 00F4 16). Either f(XIN) or f(XCIN) is selected by bit 7 of the CPU mode register. Timer 1 interrupt request occurs at timer 1 overflow. (2) Timer 2 Timer 2 can select one of the following count sources:
• f(XIN)/16 or f(XCIN)/16
• Timer 1 overflow signal
• External clock from the TIM2 pin The count source of timer 2 is selected by setting bits 4 and 1 of timer mode register 1 (address 00F4 16). Either f(XIN) or f(XCIN) is selected by bit 7 of the CPU mode register. When timer 1 overflow signal is a count source for timer 2, timer 1 functions as an 8-bit prescaler. Timer 2 interrupt request occurs at timer 2 overflow. (3) Timer 3 Timer 3 can select one of the following count sources:
• f(XIN)/16 or f(XCIN)/16
• External clock from the TIM3 pin The count source of timer 3 is selected by setting bit 0 of timer mode register 2 (address 00F516). Either f(XIN) or f(XCIN) is selected by bit 7 of the CPU mode register. Timer 3 interrupt request occurs at timer 3 overflow. (4) Timer 4 Timer 4 can select one of the following count sources:
• f(XIN)/16 or f(XCIN)/16
• f(XIN)/2 or f(XCIN)/2
• Timer 3 overflow signal The count source of timer 3 is selected by setting bits 1 and 4 of timer mode register 2 (address 00F5 16). Either f(XIN) or f(XCIN) is selected by bit 7 of the CPU mode register. When timer 3 overflow signal is a count source for timer 4, the timer 3 functions as an 8-bit prescaler. Timer 4 interrupt request occurs at timer 4 overflow. (5) Timer 5 Timer 5 can select one of the following count sources:
• f(XIN)/16 or f(XCIN)/16
• f(XCIN)
• Timer 4 overflow signal The count source of timer 3 is selected by setting bit 6 of timer mode register 1 (address 00F416) and bit 7 of timer mode register 2 (ad- dress 00F516). Either f(XIN) or f(XCIN) is selected by bit 7 of the CPU mode register. Timer 5 interrupt request occurs at timer 5 overflow. (6) Timer 6 Timer 6 can select one of the following count sources:
• f(XIN)/16 or f(XCIN)/16
• Timer 5 overflow signal The count source of timer 6 is selected by setting bit 7 of timer mode register 1 (address 00F416). Either f(XIN) or f(XCIN) is selected by bit 7 of the CPU mode register. When timer 5 overflow signal is a count source for timer 6, timer 5 functions as an 8-bit prescaler. Timer 6 interrupt request occurs at timer 6 overflow. At reset, timers 3 and 4 are connected by hardware and “FF 16” is automatically set in timer 3; “0716” in timer 4. The f(XIN) ] /16 is se- lected as the timer 3 count source. The internal reset is released by timer 4 overflow in this state and the internal clock is connected. At execution of the STP instruction, timers 3 and 4 are connected by hardware and “FF 16” is automatically set in timer 3; “0716” in timer 4. However, the f(XIN) ] /16 is not selected as the timer 3 count source. So set bit 0 of timer mode register 2 (address 00F516) to “0” before execution of the STP instruction (f(XIN) ] /16 is selected as timer 3 count source). The internal STP state is released by timer 4 overflow in this state and the internal clock is connected. As a result of the above procedure, the program can start under a stable clock. ] : When bit 7 of the CPU mode register (CM 7) is “1,” f(XIN) be- comes f(XCIN). The timer-related registers is shown in Figures 14 to 16.

M37207MF-XXXSP/FP, M37207M8-XXXSP M37207EFSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER and ON-SCREEN DISPLAY CONTROLLER Fig. 14. Timer Mode Register 1 Fig. 15. Timer Mode Register 2 b7b6 b5b4b3 b2b1b0 Timer mode register 1 (TMR1) [Address 00F416] B After reset W Timer Mode Register 1 Name Functions Timer 1 count source selection bit 1 (TMR10, TMR15) b5 b0 0 0: f(XIN)/16 or f(XCIN)/16 (See note) 0 1: f(XIN)/4096 or f(XCIN)/4096 (See note) 1 0: f(XcIN) 1 1: External clock from TIM2 pin Timer 2 count source selection bit 1 (TMR11) 0: Count source selected by bit 4 of TM1 1: External clock from TIM2 pin Timer 1 count stop bit (TMR12) 0: Count start 1: Count stop Timer 2 count stop bit (TMR13) 0: Count start 1: Count stop Timer 2 count source selection bit 2 (TMR14) R WR WR WR WR WR0: f(XIN)/16 or f(XCIN)/16 (See note) 1: Timer 1 overflow

6 Timer 5 count source

selection bit 2 (TMR16) 0: Timer 2 overflow 1: Timer 4 overflow 0W R

7 Timer 6 internal count

(TMR17) 0W R0: f(XIN)/16 or f(XCIN)/16 (See note) 1: Timer 5 overflow Note: Either f(XIN) or f(XCIN) is selected by bit 7 of the CPU mode register. b7b6 b5b4b3 b2b1b0 Timer mode register 2 (TMR2) [Address 00F516] B After resetRW Timer Mode Register 2 Name Functions Timer 3 count source selection bit (TMR20) 0 RW

1 Timer 4 count source

(TMR21) 0R W Timer 3 count stop bit (TMR22) 0: Count start 1: Count stop Timer 4 count stop bit (TMR23) 0: Count start 1: Count stop

5 Timer 5 count stop bit

(TMR25) 0: Count start 1: Count stop

6 Timer 6 count stop bit

(TMR26) 0: Count start 1: Count stop RW RW RW RW RW7 Timer 5 count source selection bit 1 (TMR27) 0: Count source selected by bit 0 of TMR3 1: Count source selected by bit 6 of TMR1 0 : f(XIN)/16 or f(XCIN)/16 (See note) 1 : External clock from TIM3 pin 0 : Timer 3 overflow signal 1 : f(XIN)/16 or f(XCIN)/16 (See note) Note: Either f(XIN) or f(XCIN) is selected by bit 7 of the CPU mode register.

4 Timer 4 count source

(TMR24) 0R W0: Count source selected by bit 1 of TMR2 1 : f(XIN)/2 or f(XCIN)/2 (See note)

M37207MF-XXXSP/FP, M37207M8-XXXSP M37207EFSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER and ON-SCREEN DISPLAY CONTROLLER Fig. 16. Timer Mode Register 3 b7b6 b5b4b3 b2b1b0 Timer mode register 3 (TMR3) [Address 020B16] B After resetRW Timer Mode Register 3 Name Functions Timer 5 count source selection bit 3 (TMR30) 0R W 0R — 0 : f(XIN)/16 or f(XCIN)/16 (See note) 1 : f(XCIN) Note: Either f(XIN) or f(XCIN) is selected by bit 7 of the CPU mode register. to Nothing is assigned. These bits are write disable bits. When these bits are read out, the values are “0.”

M37207MF-XXXSP/FP, M37207M8-XXXSP M37207EFSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER and ON-SCREEN DISPLAY CONTROLLER Fig. 17. Timer Block Diagram CM 7 TMR1 5 TMR1 0 TMR1 2 TMR1 4 TMR1 1 TMR1 3 Data bus Timer 1 interrupt request Timer 2 interrupt request Timer 3 interrupt request Reset STP instruction TMR2 TMR2 2 Timer 4 interrupt requestTMR2 4 TMR2 3 TMR2 1 TMR1 6 Timer 5 interrupt requestTMR2 7 TMR2 5 Timer 6 interrupt requestTMR1 7 TMR2 6 XCIN XIN TIM2 TIM3 Selection gate : Connected to black side at reset. TMR1 : Timer mode register 1 TMR2 : Timer mode register 2 TMR3 : Timer mode register 3 CM : CPU mode register FF16 0716 TMR1 5 TMR3 0 Timer 1 latch (8) Timer 1 (8) Timer 2 latch (8) Timer 2 (8) Timer 3 latch(8) Timer 4 latch (8) Timer 3 (8) Timer 4 (8) Timer 5 latch (8) Timer 5 (8) Timer 6 (8) Timer 6 latch (8) Notes 1: HIGH pulse width of external clock inputs TIM2 and TIM3 needs 4 machine cycles or more. 2: When the external clock source is selected, timers 1, 2, and 3 are counted at a rising edge of input signal. 3: In the stop mode or the wait mode, external clock inputs TIM2 and TIM3 cannot be used.

M37207MF-XXXSP/FP, M37207M8-XXXSP M37207EFSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER and ON-SCREEN DISPLAY CONTROLLER SERIAL I/O This microcomputer has a built-in serial I/O which can either transmit or receive 8-bit data serially in clock synchronous mode. The serial I/O block diagram is shown in Figure 18. The synchronous clock I/O pin (SCLK ), and data I/O pins (SOUT , SIN), receive enable ____ signal output pin (SRDY ) also function as port P4. Bit 2 of the serial I/O mode register (address 00DE16) selects whether the synchronous clock is supplied internally or externally (from the pins S CLK1 , SCLK2 ). When an internal clock is selected, bits 1 and 0 select whether f(XIN) or f(XCIN) is divided by 8, 16, 32, or 64. To use pins for serial I/O, set the corresponding bits of the port P4 direction register (address 00C9 16) to “0.” The operation of the serial I/O is described below. The operation differs depending on the clock source; external clock or internal clock. Fig. 18. Serial I/O Block Diagram Serial I/O shift register (8) Data bus Serial I/O interrupt request Selection gate : Connected to black side at reset.Synchronous circuit Frequency divider 1/81/4 1/16 SM 1 SM 0 Serial I/O counter (8) SM5 : LSB MSB S SM2 1/2XIN 1/2 (Address 00DF16) XCIN CM7 1/2 (Note) Note : When the data is set in the serial I/O register (address 00DF16), the register functions as the serial I/O shift register. P43 latch SM6 SCL2 CSIO SRDY2 S CLK2 SOUT2 SM4 P41 latch SM7 SCL3 SM3 CSIO P40 latch SM7 SDA3 SM3 CSIO SM6 P40 latch SDA2 SIN2 SRDY1 P47 latch SIC3 PWM8 SIC7 S CLK1 P45 latch SIC4 SCL1 SIC5 SOUT1 P44 latch SIC4 SDA1 SIC5 SIN1 SIC6 PWM9 P46 latch CSIO CM : CPU mode register SM : Serial I/O mode register SIC : Serial I/O control register CSIO : Bit 1 of serial I/O control register

M37207MF-XXXSP/FP, M37207M8-XXXSP M37207EFSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER and ON-SCREEN DISPLAY CONTROLLER Fig. 19. Serial I/O Timing (for LSB first) ____ Internal clock : The SRDY signal goes to HIGH during the write cycle by writing data into the serial I/O register (address 00DD16). After the ____ write cycle, the SRDY signal goes to “L” (receive enable state). The ____ SRDY signal goes to “H” at the next falling edge of the transfer clock for the serial I/O register. The serial I/O counter is set to “7” during write cycle into the serial I/ O register (address 00DD16), and transfer clock goes HIGH forcibly. At each falling edge of the transfer clock after the write cycle, serial data is output from the S OUT pin. Transfer direction can be selected by bit 5 of the serial I/O mode register. At each rising edge of the transfer clock, data is input from the S IN pin and data in the serial I/O register is shifted 1 bit. After the transfer clock has counted 8 times, the serial I/O counter becomes “0” and the transfer clock stops at HIGH. At this time the interrupt request bit is set to “1.” External clock : When an external clock is selected as the clock source, the interrupt request is set to “1” after the transfer clock has counted 8 counts. However, transfer operation does not stop, so the clock should be controlled externally. Use the external clock of 1 MHz or less with a duty cycle of 50%. The serial I/O timing is shown in Figure 19. When using an external clock for transfer, the external clock must be held at “H” for initializing the serial I/O counter. When switching between an internal clock and an external clock, do not switch during transfer. Also, be sure to ini- tialize the serial I/O counter after switching. Notes 1:On programming, note that the serial I/O counter is set by writing to the serial I/O register with the bit managing in- structions such as SEB and CLB. 2: When an external clock is used as the synchronous clock, write transmit data to the serial I/O register when the trans- fer clock input level is HIGH. Synchronous clock Transfer clock Serial I/O register write signal Serial I/O output SOUT D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7 (See note) Serial I/O input S IN Note : When an internal clock is selected, the SOUT pin is at high-impedance after transfer is completed. Interrupt request bit is set to “1” Receive signal enable SRDY

M37207MF-XXXSP/FP, M37207M8-XXXSP M37207EFSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER and ON-SCREEN DISPLAY CONTROLLER Fig. 20. Serial I/O Mode Register Fig. 21. Serial I/O Control Register b7b6 b5b4b3 b2b1b0 Serial I/O mode register (SM) [Address 00DE16] B Name Functions After resetRW Serial I/O Mode Register 0, 1Internal synchronous clock selection bits (SM0, SM1) (See note 1) b1 b0 0 0: f(XIN)/4 or f(XCIN)/4 0 1: f(XIN)/16 or f(XCIN)/16 1 0: f(XIN)/32 or f(XCIN)/32 1 1: f(XIN)/64 or f(XCIN)/64

2 Synchronous clock

selection bit (SM2) 3, 7Ports P40, P41 function selection bits (SM3, SM7) P40/SOUT2 / SDA3/X CIN P40 SOUT2 SDA3 0: External clock 1: Internal clock 0 RW RW RW 4, 6Ports P42, P43 function selection bits (SM4, SM6)

5 Transfer direction

selection bit (SM5) 0: LSB first 1: MSB first 0R W P41/SCLK2 / SCL3/X COUT P41 SCLK2 SCL3 P4 2/SIN2/ SDA2/AD8 P42 SDA2 P42 SDA2 0R WP43/SRDY2 / SCL2/AD7 P43 SRDY2 SDA2 Notes 1: Either f(XIN) or f(XCIN) is selected by bit 7 of the CPU mode register. 2: When using ports P40–P4 3 as serial I/O pins, set bit 1 of the serial control register to “1.” (See note 2) (See note 2) b7b6 b5b4b3 b2b1b0 Serial I/O control register (SIC) [Address 020716] B Name Functions After resetRW Serial I/O Control Register

0 Input signal to sift

(SIC0) CSIO b0 0 0: Input signal from SIN1 0 1: Input signal from SOUT1 (See note 1) 1 0: Input signal from SIN2 1 1: Input signal from SOUT2 (See note 1)

1 Serial I/O pin switch

bit (CSIO) 0: SOUT1 ,SCLK1 , SIN1, SRDY1 1: SOUT2 ,SCLK2 , SIN2, SRDY2 0 RW RW Notes 1: When inputting data from the Sout pin, set “FF16” to the serial I/O register. 2: When using ports P44–P4 7 as serial I/O pins, set bit 1 of the serial I/O control register to “0.” 3, 7Ports P47 function selection bits (SM3, SM7) (See note 2) P4 7/SRDY1 /PWM8 P47 SRDY1 PWM8 0R W 4, 5Ports P44, P45 function selection bits (SM4, SM6) (See note 2)

6 Ports P46 function

(SIC6) (See note 2) P44/SOUT1 / SDA1 P44 SOUT1 SDA1 0R WP45/SCLK1 / SCL1 P45 SCLK1 SCL1 P4 6/SIN1/PWM9 P4 6 PWM9 0R Wb6

2 I2C-BUS connection

(SIC2) 0: SDA2, SCL2, SDA1, SCL1 1: SDA3, SCL3 0R W

M37207MF-XXXSP/FP, M37207M8-XXXSP M37207EFSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER and ON-SCREEN DISPLAY CONTROLLER Serial I/O Common Transmission/Reception Mode By writing “1” to bit 0 of the serial I/O control register, signals SIN and SOUT are switched internally to be able to transmit or receive the serial data. Figure 22 shows signals on serial I/O common transmission/recep- tion mode. Note : When receiving the serial data after writing “FF 16” to the serial I/O register. Fig. 22. Signals on Serial I/O Common Transmission/Reception Mode SIN2 SCLK1 SOUT1 SIN1 SCLK2 SOUT2 CSIO Clock “1” “1” “0” “0” “1” “1” Serial I/O shift register (8) SIC0 CSIO “0” “0” SIC0 : Bit 0 of serialI/O control register CSIO : Bit 1 of serial I/O control register

Table 2. Multi-master I2C-BUS Interface Functions ports (SCL1, SCL2, SDA1, SDA2). functions, is useful for the multi-master serial communications. face and Table 2 shows multi-master I2C-BUS interface functions. control register, the I2C status register and other control circuits.

M37207MF-XXXSP/FP, M37207M8-XXXSP M37207EFSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER and ON-SCREEN DISPLAY CONTROLLER (1) I2C Data Shift Register The I2C data shift register (S0 : address 00D916) is an 8-bit shift register to store receive data and write transmit data. When transmit data is written into this register, it is transferred to the outside from bit 7 in synchronization with the SCL clock, and each time one-bit data is output, the data of this register are shifted one bit to the left. When data is received, it is input to this register from bit 0 in synchronization with the SCL clock, and each time one-bit data is input, the data of this register are shifted one bit to the left. The I 2C data shift register is in a write enable status only when the ESO bit of the I2C control register (address 00DC16) is “1.” The bit counter is reset by a write instruction to the I2C data shift register. When both the ESO bit and the MST bit of the I2C status register (address 00F816) are “1,” the SCL is output by a write instruction to the I2C data shift register. Reading data from the I2C data shift regis- ter is always enabled regardless of the ESO bit value. Note: To write data into the I2C data shift register after setting the MST bit to “0” (slave mode), keep an interval of 8 machine cycles or more. Fig. 24. I 2C Data Shift Register Fig. 25. I2C Address Register (2) I2C Address Register The I2C address register (address 00DA16) consists of a 7-bit slave ___ address and a read/write bit. In the addressing mode, the slave ad- dress written in this register is compared with the address data to be received immediately after the START condition are detected. ____ n Bit 0: Read /Write Bit (RBW) Not used when comparing addresses, in the 7-bit addressing mode. In the 10-bit addressing mode, the first address data to be received is compared with the contents (SAD6 to SAD0 + RBW) of the I address register. The RBW bit is cleared to “0” automatically when the stop condition is detected. n Bits 1 to 7: Slave Address (SAD0–SAD6) These bits store slave addresses. Regardless of the 7-bit address- ing mode and the 10-bit addressing mode, the address data trans- mitted from the master is compared with the contents of these bits. b7 b6 b5 b4 b3 b2 b1 b0 I C data shift register1(S0) [Address 00D916] B Functions After reset R W I C Data Shift Register to This is an 8-bit shift register to store receive data and write transmit data. Indeterminate Note: 2 To write data into the I C data shift register after setting the MST bit to “0” (slave mode), keep an interval of 8 machine cycles or more. Name D0 to D7 RW b7 b6 b5 b4 b3 b2 b1 b0

0 Read/write bit

(RBW) to Slave address (SAD0 to SAD6) 0: Read 1: Write 0The address data transmitted from the master is compared with the contents of these bits. I2C Address Register I2C address register (S0D) [Address 00DA16] B Name Functions After resetRW RW

M37207MF-XXXSP/FP, M37207M8-XXXSP M37207EFSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER and ON-SCREEN DISPLAY CONTROLLER (3) I2C Clock Control Register The I2C clock control register (address 00DD16) is used to set ACK control, SCL mode and SCL frequency. n Bits 0 to 4: SCL Frequency Control Bits (CCR0–CCR4) These bits control the SCL frequency. Refer to Figure 26. n Bit 5: SCL Mode Specification Bit (FAST MODE) This bit specifies the SCL mode. When this bit is set to “0,” the stan- dard clock mode is set. When the bit is set to “1,” the high-speed clock mode is set. n Bit 6: ACK Bit (ACK BIT) This bit sets the SDA status when an ACK clock] is generated. When this bit is set to “0,” the ACK return mode is set and SDA goes to LOW at the occurrence of an ACK clock. When the bit is set to “1,” the ACK non-return mode is set. The SDA is held in the HIGH status at the occurrence of an ACK clock. However, when the slave address matches the address data in the reception of address data at ACK BIT = “0,” the SDA is automatically made LOW (ACK is returned). If there is a mismatch between the slave address and the address data, the SDA is automatically made HIGH (ACK is not returned). ] ACK clock: Clock for acknowledgement n Bit 7: ACK Clock Bit (ACK) This bit specifies a mode of acknowledgment which is an acknowl- edgment response of data transmission. When this bit is set to “0,” the no ACK clock mode is set. In this case, no ACK clock occurs after data transmission. When the bit is set to “1,” the ACK clock mode is set and the master generates an ACK clock upon comple- tion of each 1-byte data transmission.The device for transmitting address data and control data releases the SDA at the occurrence of an ACK clock (make SDA HIGH) and receives the ACK bit gener- ated by the data receiving device. Note: Do not write data into the I 2C clock control register during transmission. If data is written during transmission, the I2C clock generator is reset, so that data cannot be transmitted normally. Fig. 26. I2C Clock Control Register b7 b6 b5 b4 b3 b2 b1 b0 I2C clock control register (S2 : address 00DD16) I2C Clock Control Register to SCL frequency control bits (CCR0 to CCR4) SCL mode specification bit (FAST MODE) 0 : Standard clock mode 1 : High-speed clock mode 0Standard clock mode B Name Functions After resetRW ACK bit (ACK BIT) ACK clock bit (ACK) 0 : ACK is returned. 1 : ACK is not returned. 0 : No ACK clock 1 : ACK clock High speed clock mode Setup disabled Setup disabled00 to 02 Setup disabled 33303 Setup disabled 25004 100 400 (See note)05 83.3 16606 500/CCR value 1000/CCR value ... 17.2 34.51D 16.6 33.31E 16.1 32.31F (at f = 4 MHz, unit : kHz) Note: At 400 kHz in the high-speed clock mode, the duty is as below . “0” period : “1” period = 3 : 2 In the other cases, the duty is as below. “0” period : “1” period = 1 : 1 Setup value of CCR4–CCR0 RW RW RW RW

M37207MF-XXXSP/FP, M37207M8-XXXSP M37207EFSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER and ON-SCREEN DISPLAY CONTROLLER (4) I2C Control Register The I2C control register (address 00DC16) controls the data commu- nication format. n Bits 0 to 2: Bit Counter (BC0–BC2) These bits decide the number of bits for the next 1-byte data to be transmitted. An interrupt request signal occurs immediately after the number of bits specified with these bits are transmitted. When a START condition is received, these bits become “000 2” and the address data is always transmitted and received in 8 bits. n Bit 3: I 2C Interface Use Enable Bit (ESO) This bit enables usage of the multimaster I2C BUS interface. When this bit is set to “0,” the use disable status is provided, so the SDA and the SCL become high-impedance. When the bit is set to “1,” use of the interface is enabled. When ESO = “0,” the following is performed.

• PIN = “1,” BB = “0” and AL = “0” are set (they are bits of the I2C status register at address 00F816 ).
• Writing data to the I2C data shift register (address 00F616) is dis- abled. n Bit 4: Data Format Selection Bit (ALS) This bit decides whether or not to recognize slave addresses. When this bit is set to “0,” the addressing format is selected, so that ad- dress data is recognized. When a match is found between a slave address and address data as a result of comparison or when a gen- eral call (refer to “(5) I 2C Status Register,” bit 1) is received, trans- mission processing can be performed. When this bit is set to “1,” the free data format is selected, so that slave addresses are not recog- nized. Fig. 28. I 2C Control Register n Bit 5: Addressing Format Selection Bit (10BIT SAD) This bit selects a slave address specification format. When this bit is set to “0,” the 7-bit addressing format is selected. In this case, only the high-order 7 bits (slave address) of the I 2C address register (ad- dress 00F716) are compared with address data. When this bit is set to “1,” the 10-bit addressing format is selected, all the bits of the I2C address register are compared with address data. n Bits 6 and 7:Connection Control Bits between I2C-BUS Interface and Ports (BSEL0, BSEL1) These bits controls the connection between SCL and ports or SDA and ports (refer to Figure 28). Fig. 27. Connection Port Control by BSEL0 and BSEL1 “0” “1” BSEL0 “0” “1” BSEL1 SCL1/P45 SCL2/P43 Multi-master I2C-BUS interface SCL SDA SCL3/P41 “0” “1” CIIC (Note 2) “0” “1” BSEL0 “0” “1” BSEL1 SDA1/P4 4 SDA2/P4 2 SDA3/P4 0 “0” “1” CIIC (Note 2) Notes 1 : When using multi-master I2C-BUS interface, set bits 3 to 7 of the serial I/O mode register (address 00DE16) to “1.” 2 : CIIC is bit 2 of the serial I/O control register (address 020716) (refer to Figure 21). b7 b6 b5 b4 b3 b2 b1 b0 to Bit counter (Number of transmit/recieve bits) (BC0 to BC2) b2 b1 b0 0 0 0 : 8 0 0 1 : 7 0 1 0 : 6 0 1 1 : 5 1 0 0 : 4 1 0 1 : 3 1 1 0 : 2 1 1 1 : 1

3 I2C-BUS interface use

enable bit (ESO) 0 : Disabled 1 : Enabled

4 Data format selection bit

(ALS) 0 : Addressing mode 1 : Free data format

5 Addressing format selection

bit (10BIT SAD) 0 : 7-bit addressing format 1 : 10-bit addressing format 6, 7 Connection control bits between I C-BUS interface and ports b7 b6 Connection port (See note) 0 0 : None 0 1 : SCL1, SDA1 1 0 : SCL2, SDA2 1 1 : SCL1, SDA1 SCL2, SDA2 I2C control register (S1D : address 00DC16) I2C Control Register B Name Functions After resetRW Note: When using ports P11-P14 as I C-BUS interface, the output structure changes automatically from CMOS output to N-channel open-drain output. RW RW RW RW RW

M37207MF-XXXSP/FP, M37207M8-XXXSP M37207EFSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER and ON-SCREEN DISPLAY CONTROLLER (5) I2C Status Register The I2C status register (address 00DB16) controls the I2C-BUS inter- face status. The low-order 4 bits are read-only bits and the high- order 4 bits can be read out and written to. n Bit 0: Last Receive Bit (LRB) This bit stores the last bit value of received data and can also be used for ACK receive confirmation. If ACK is returned when an ACK clock occurs, the LRB bit is set to “0.” If ACK is not returned, this bit is set to “1.” Except in the ACK mode, the last bit value of received data is input. The state of this bit is changed from “1” to “0” by execut- ing a write instruction to the I 2C data shift register (address 00D916). n Bit 1: General Call Detecting Flag (AD0) This bit is set to “1” when a general call] whose address data is all “0” is received in the slave mode. By a general call of the master device, every slave device receives control data after the general call. The AD0 bit is set to “0” by detecting the STOP condition or START con- dition. ] General call:The master transmits the general call address “00 16” to all slaves. n Bit 2: Slave Address Comparison Flag (AAS) This flag indicates a comparison result of address data. In the slave receive mode, when the 7-bit addressing format is selected, this bit is set to “1” in one of the following conditions.

• The address data immediately after occurrence of a START condition matches the slave address stored in the high-order 7 bits of the I 2C address register (address 00DA16).
• A general call is received. In the slave reception mode, when the 10-bit addressing format is selected, this bit is set to “1” with the following condition.
• When the address data is compared with the I2C address register (8 bits consists of slave address and RBW), the first bytes match. The state of this bit is changed from “1” to “0” by executing a write instruction to the I2C data shift register (address 00D916). n Bit 3: Arbitration Lost] Detecting Flag (AL) In the master transmission mode, when a device other than the mi- crocomputer sets the SDA to “L,”, arbitration is judged to have been lost, so that this bit is set to “1.” At the same time, the TRX bit is set to “0,” so that immediately after transmission of the byte whose arbitra- tion was lost is completed, the MST bit is set to “0.” When arbitration is lost during slave address transmission, the TRX bit is set to “0” and the reception mode is set. Consequently, it becomes possible to receive and recognize its own slave address transmitted by another master device. ] Arbitration lost:The status in which communication as a master is disabled. n Bit 4: I 2C-BUS Interface Interrupt Request Bit (PIN) This bit generates an interrupt request signal. Each time 1-byte data is transmitted, the state of the PIN bit changes from “1” to “0.” At the same time, an interrupt request signal is sent to the CPU. The PIN bit is set to “0” in synchronization with a falling edge of the last clock (including the ACK clock) of an internal clock and an interrupt re- quest signal occurs in synchronization with a falling edge of the PIN bit. When the PIN bit is “0,” the SCL is kept in the “0” state and clock generation is disabled. Figure 30 shows an interrupt request signal generating timing chart. The PIN bit is set to “1” in any one of the following conditions.
• Executing a write instruction to the I2C data shift register (address 00F616).
• When the ESO bit is “0”
• At reset The conditions in which the PIN bit is set to “0” are shown below:
• Immediately after completion of 1-byte data transmission (includ- ing when arbitration lost is detected)
• Immediately after completion of 1-byte data reception
• In the slave reception mode, with ALS = “0” and immediately after completion of slave address or general call address reception
• In the slave reception mode, with ALS = “1” and immediately after completion of address data reception

M37207MF-XXXSP/FP, M37207M8-XXXSP M37207EFSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER and ON-SCREEN DISPLAY CONTROLLER n Bit 5: Bus Busy Flag (BB) This bit indicates the status of use of the bus system. When this bit is set to “0,” this bus system is not busy and a START condition can be generated. When this bit is set to “1,” this bus system is busy and the occurrence of a START condition is disabled by the START condi- tion duplication prevention function (Note). This flag can be written by software only in the master transmission mode. In the other modes, this bit is set to “1” by detecting a START condition and set to “0” by detecting a STOP condition. When the ESO bit of the I 2C control register (address 00DC16) is “0” and at reset, the BB flag is kept in the “0” state. n Bit 6:Communication Mode Specification Bit (transfer direction specification bit: TRX) This bit decides the direction of transfer for data communication. When this bit is “0,” the reception mode is selected and the data of a trans- mitting device is received. When the bit is “1,” the transmission mode is selected and address data and control data are output into the SDA in synchronization with the clock generated on the SCL. When the ALS bit of the I 2C control register (address 00DC16) is “0” in the slave reception mode is selected, the TRX bit is set to “1” (transmit) if the least significant bit (R/W bit) of the address data trans- mitted by the master is “1.” When the ALS bit is “0” and the R/W bit is “0,” the TRX bit is cleared to “0” (receive). The TRX bit is cleared to “0” in one of the following conditions.

• When arbitration lost is detected.
• When a STOP condition is detected.
• When occurence of a START condition is disabled by the START condition duplication prevention function (Note).
• With MST = “0” and when a START condition is detected.
• With MST = “0” and when ACK non-return is detected.
• At reset n Bit 7:Communication Mode Specification Bit (master/slave speci- fication bit: MST) This bit is used for master/slave specification for data communica- tion. When this bit is “0,” the slave is specified, so that a START condition and a STOP condition generated by the master are received, and data communication is performed in synchronization with the clock generated by the master. When this bit is “1,” the master is specified and a START condition and a STOP condition are gener- ated, and also the clocks required for data communication are gen- erated on the SCL. The MST bit is cleared to “0” in one of the following conditions.
• Immediately after completion of 1-byte data transmission when ar- bitration lost is detected
• When a STOP condition is detected.
• When occurence of a START condition is disabled by the START condition duplication preventing function (Note).
• At reset Note: The START condition duplication prevention function disables the START condition generation, reset of bit counter reset, and SCL output, when the following condition is satisfied:
• a START condition is set by another master device.

M37207MF-XXXSP/FP, M37207M8-XXXSP M37207EFSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER and ON-SCREEN DISPLAY CONTROLLER Fig. 30. Interrupt Request Signal Generation Timing Fig. 29. I2C Status Register SCL PIN IICIRQ b7 b6 b5 b4 b3 b2 b1 b0 I2C status register (S1) [Address 00DB16] I2C Status Register 6, 7 b7 b6 0 0 : Slave recieve mode 0 1 : Slave transmit mode 1 0 : Master recieve mode 1 1 : Master transmit mode B Name Functions After resetRW Communication mode specification bits (TRX, MST) 0 : Bus free 1 : Bus busy Bus busy flag (BB) 0 : Interrupt request issued 1 : No interrupt request issued I 2C-BUS interface interrupt request bit (PIN) 0 : Not detected 1 : Detected Arbitration lost detecting flag (AL) (See note) 0 : Address mismatch 1 : Address match Slave address comparison flag (AAS) (See note) 0 : No general call detected 1 : General call detected General call detecting flag (AD0) (See note) 0 : Last bit = “0 ” 1 : Last bit = “1 ” Last receive bit (LRB) (See note) Note : These bits and flags can be read out, but cannnot be written. IndeterminateR— RW 0 RW

satisfied, a START/STOP condition can be detected. START condition/STOP condition generation timing table. Table 4. START Condition/STOP Condition Detect Conditions Table 3. START Condition/STOP Condition Generation Timing notes the number of φ cycles. condition generation timing table. Set “2016” to the I2C status register (S1). Write a transmit data to the I2C data shift register. Set “F016” to the I2C status register (S1) again. notes the number of φ cycles.

M37207MF-XXXSP/FP, M37207M8-XXXSP M37207EFSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER and ON-SCREEN DISPLAY CONTROLLER (10) Address Data Communication There are two address data communication formats, namely, 7-bit addressing format and 10-bit addressing format. The respective ad- dress communication formats is described below. 7-bit addressing format To meet the 7-bit addressing format, set the 10BIT SAD bit of the I 2C control register (address 00DC16) to “0.” The first 7-bit ad- dress data transmitted from the master is compared with the high- order 7-bit slave address stored in the I2C address register (ad- dress 00DA16). At the time of this comparison, address compari- son of the RBW bit of the I2C address register (address 00DA16) is not made. For the data transmission format when the 7-bit ad- dressing format is selected, refer to Figure 34, (1) and (2). 10-bit addressing format To meet the 10-bit addressing format, set the 10BIT SAD bit of the I 2C control register (address 00DC16) to “1.” An address compari- son is made between the first-byte address data transmitted from the master and the 7-bit slave address stored in the I 2C address register (address 00DA16). At the time of this comparison, an ad- dress comparison between the RBW bit of the I2C address regis- ter (address 00DA16) and the R/W bit which is the last bit of the address data transmitted from the master is made. In the 10-bit addressing mode, the R/W bit which is the last bit of the address data not only specifies the direction of communication for control data but also is processed as an address data bit. When the first-byte address data matches the slave address, the AAS bit of the I 2C status register (address 00DB16) is set to “1.” After the second-byte address data is stored into the I2C data shift register (address 00D916), make an address comparison between the sec- ond-byte data and the slave address by software. When the address data of the 2nd bytes matches the slave address, set the RBW bit of the I2C address register (address 00DA16) to “1” by software. This processing can match the 7-bit slave address and R/W data, which are received after a RESTART condition is detected, with the value of the I 2C address register (address 00DA16). For the data transmis- sion format when the 10-bit addressing format is selected, refer to Figure 34, (3) and (4). (11) Example of Master Transmission An example of master transmission in the standard clock mode, at the SCL frequency of 100 kHz and in the ACK return mode is shown below. Set a slave address in the high-order 7 bits of the I2C address register (address 00DA16) and “0” in the RBW bit. Set the ACK return mode and SCL = 100 kHz by setting “8516” in the I2C clock control register (address 00DD16). Set “1016” in the I2C status register (address 00DB16) and hold the SCL at the HIGH. Set a communication enable status by setting “4816” in the I2C control register (address 00DC16). Set the address data of the destination of transmission in the high- order 7 bits of the I2C data shift register (address 00D916) and set “0” in the least significant bit. Set “F016” in the I2C status register (address 00DB16) to generate a START condition. At this time, an SCL for 1 byte and an ACK clock automatically occurs. Set transmit data in the I2C data shift register (address 00D916). At this time, an SCL and an ACK clock automatically occurs. When transmitting control data of more than 1 byte, repeat step Set “D016” in the I2C status register (address 00DB16). After this, if ACK is not returned or transmission ends, a STOP condition will be generated. (12) Example of Slave Reception An example of slave reception in the high-speed clock mode, at the SCL frequency of 400 kHz, in the ACK non-return mode, using the addressing format, is shown below. Set a slave address in the high-order 7 bits of the I2C address register (address 00DA16) and “0” in the RBW bit. Set the no ACK clock mode and SCL = 400 kHz by setting “2516” in the I2C clock control register (address 00DD16). Set “1016” in the I2C status register (address 00DB16) and hold the SCL at the HIGH. Set a communication enable status by setting “4816” in the I2C control register (address 00DC16). When a START condition is received, an address comparison is made.

• When all transmitted addresses are “0” (general call) : AD0 of the I2C status register (address 00DB16) is set to “1” and an interrupt request signal occurs.
• When the transmitted addresses match the address set in : AAS of the I2C status register (address 00DB16) is set to “1” and an interrupt request signal occurs.
• In the cases other than the above : AD0 and AAS of the I2C status register (address 00DB16) are set to “0” and no interrupt request signal occurs. Set dummy data in the I2C data shift register (address 00D916). When receiving control data of more than 1 byte, repeat step . When a STOP condition is detected, the communication ends.

M37207MF-XXXSP/FP, M37207M8-XXXSP M37207EFSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER and ON-SCREEN DISPLAY CONTROLLER Fig. 34. Address Data Communication Format S Slave address A Data A Data A/A PR/W 7 bits “0” 1 to 8 bits 1 to 8 bits S Slave address A Data A Data AP 7 bits “1” 1 to 8 bits 1 to 8 bits (1) A master-transmitter transmits data to a slave-receiver S Slave address 1st 7 bits A A Data 7 bits “0” 8 bits 1 to 8 bits (2) A master-receiver receives data from a slave-transmitter Slave address 2nd byte A Data A/A P 1 to 8 bits S Slave address 1st 7 bits A A 7 bits “0” 8 bits 7 bits (3) A master-transmitter transmits data to a slave-receiver with a 10-bit address Slave address 2nd byte Data 1 to 8 bits Sr Slave address 1st 7 bits A Data AP 1 to 8 bits“1” (4) A master-receiver receives data from a slave-transmitter with a 10-bit address S : START condition P : STOP condition A : ACK bit R/W : Read/Write bit Sr : Restart condition From master to slave From slave to master R/W R/W R/W R/W

Table 5. Relation Between the Low-order 6-bit Data and High-

M37207MF-XXXSP/FP, M37207M8-XXXSP M37207EFSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER and ON-SCREEN DISPLAY CONTROLLER Fig. 36. 8-bit PWM Timing (a) Pulses showing the weight of each bit 1 3 5 7 9 20 30 40 50 60 70 80 90 100 110 120 130 140 150 160 170 180 190 200 210 220 230 240 250 255 4 12 20 28 36 44 52 60 68 76 84 92 100 108 116 124 132 140 148 156 164 172 180 188 196 204 212 220 228 236 244 252 16 48 80 112 144 176 208 240 24 40 56 72 88 104 120 136 152 168 184 200 216 232 248 32 96 160 224 64 192 Bit 7 2 6 10 14 18 22 26 30 34 38 42 46 50 54 58 62 66 70 74 78 82 86 90 94 98 102 106 110 114 118 122 126 130 134 138 142 146 150 154 158 162 166 170 174 178 182 186 190 194 198 202 206 210 214 218 222 226 230 234 238 242 246 250 254 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 128 Bit 0 PWM output t = 4 ms T = 1024 ms f(XIN) = 8 MHz (b) Example of 8-bit PWM t 0016 (0) 0116 (1) 1816 (24) FF16 (255) T = 256 t

M37207MF-XXXSP/FP, M37207M8-XXXSP M37207EFSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER and ON-SCREEN DISPLAY CONTROLLER Fig. 37. 14-bit PWM (DA) Output Example (at f(XIN) = 8 MHz) 250 ns b7 b0b6 b5 b4 b3 b2 b1 0 0010110 b13 b6 0 0010110 b0b5 101000 Set “2C16” to DA-H register. [DA-H register] D H At writing of DA-L b0b6 b5 b4 b3 b2 b1 010100 Set “2816” to DA-L register. [DA-L register] D L At writing of DA-L Undefined These bits decide “H” level area of fundamental waveform. These bits decide smaller interval “tm” in which “H” leval area is [“H” level area of fundamental waveform + τ ]. Minimum resolution bit width 250 ns High-order 8-bit value of DA latch5“H” level area of fundamental waveform FF 00 D3FE FD … …… …D6 D4 02 01D5 14-bit PWM output 8-bit counter 250 ns5 44 FF 00 D3FE FD D6 D4 02 01D5 14-bit PWM output 8-bit counter 250 ns5 44 Fundamental waveform Waveform of smaller interval “tm” specified by low-order 6 bits Fundamental waveform of smaller interval “tm” which is not specified by low-order 6 bits is not changed.14-bit PWM output Low-order 6-bit output of DA latch 250 ns5 44 τ = 250 ns T = 4096 µs Repeat period t0 t1 t2 t3 t4 t5 t59 t60 t61 t62 t63 [DA latch] 2C 2B 2A … 03 02 01 00 2C 2B 2A … 03 02 01 002D 2D Latch transfer complete bit Transfer complete Transfer is not completed (Automatically set at writing)

M37207MF-XXXSP/FP, M37207M8-XXXSP M37207EFSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER and ON-SCREEN DISPLAY CONTROLLER Fig. 38. PWM Output Control Register 1 b7b6 b5b4b3 b2b1b0 PWM output control register 1 (PW) [Address 00D5 B After resetRW PWM Output Control Register 1 Name Functions DA, PWM count source selection bit (PW0) 0 : Count source supply 1 : Count source stop P60/PWM0 output selection bit (PW2) 0: P60 output 1: PWM0 output P61/PWM1 output selection bit (PW3) 0: P61 output 1: PWM1 output P62/PWM2 output selection bit (PW4) 0: P62 output 1: PWM2 output

5 P63/PWM3 output

selection bit (PW5) 0: P63 output 1: PWM3 output

6 P64/PWM4 output

selection bit (PW6) 0: P64 output 1: PWM4 output DA/PN4 output selection bit (PW1) 0 : DA output 1 : PN4 output

7 P65/PWM5 output

selection bit (PW7) 0: P65 output 1: PWM5 output 16] RW RW RW RW RW RW RW RW Fig. 39. PWM Output Control Register 2 b7b6 b5b4b3 b2b1b0 PWM output control register 2 (PN) [Address 00D6 B After resetRW PWM Output Control Register 2 Name Functions 16] DA output polarity selection bit (PN3) 0 : Positive polarity 1 : Negative polarity PWM output polarity selection bit (PN4) DA general-purpose output bit (PN5) 0 : Output LOW 1 : Output HIGH to 0Nothing is assigned. These bits are write disable bits. When these bits are read out, the values are “0.” 0 : Positive polarity 1 : Negative polarity RW RW RW

0 P66/PWM6 output

selection bit (PN0) 0 : P66 output 1 : PWM6 output 0R W

1 P67/PWM7 output

selection bit (PN1) 0 : P67 output 1 : PWM7 output 0R W

M37207MF-XXXSP/FP, M37207M8-XXXSP M37207EFSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER and ON-SCREEN DISPLAY CONTROLLER A-D COMPARATOR A-D comparator consists of 6-bit D-A converter and comparator. A-D comparator block diagram is shown in Figure 40. The reference voltage “Vref” for D-A conversion is set by bits 0 to 5 of the A-D control register 2 (address 020A16). The comparison result of the analog input voltage and the reference voltage “V ref” is stored in bit 4 of the A-D control register 1 (address 00EF 16). For A-D comparison, set “0” to corresponding bits of the direction register to use ports as analog input pins. Write the data for select of analog input pins to bits 0 to 2 of the A-D control register 1 and write the digital value corresponding to V ref to be compared to the bits 0 to 5 A-D control register 2. The voltage comparison starts by writing to the A-D control register 2, and it is completed after 16 machine cycles (NOP instruction 5 8). Fig. 40. A-D Comparator Block Diagram A-D control register 1 Bits 0 to 2 Comparator control Data bus Bit 4 Switch tree A-D control register 2 Resistor ladder Compa- rator Analog signal switch Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 A-D control register 1AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8

M37207MF-XXXSP/FP, M37207M8-XXXSP M37207EFSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER and ON-SCREEN DISPLAY CONTROLLER Fig. 41. A-D Control Register 1 Fig. 42. A-D Control Register 2 b7 b6 b5 b4 b3 b2 b1 b0 A-D control register 1 (ADM) [Address 00EF16] B After resetRW A-D Control Register 1 to Analog input pin selection bits (ADM0 to ADM2) Name Functions b2 b1 b0 0 0 0 : AD1 0 0 1 : AD2 0 1 0 : AD3 0 1 1 : AD4 1 0 0 : AD5 1 0 1 : AD6 1 1 0 : AD7 1 1 1 : AD8

4 Storage bit of comparison

result (ADM4) Input voltage < reference voltage 1: Input voltage > reference voltage Indeterminate 03, 5 to 7 Nothing is assigned. These bits are write disable bits. When these bits are read out, the values are “0.” RW b7 b6 b5 b4 b3 b2 b1 b0 A-D control register 2(ADC) [Address 020A16] B After reset RW A-D Control Register 2 to 6, 7 Indeterminate Name Functions D-A converter set bits (ADC0 to ADC5) b0b1b2 b3 b4 b5 Nothing is assigned. These bits are write disable bits. When these bits are reed out, the values are “ 0.” 000000 00000 0000 111 11111 111111 : 3/128Vcc : 5/128Vcc : 123/128Vcc : 125/128Vcc : 127/128Vcc : 1/128Vcc RW

Table 6 outlines the CRT display functions of this microcomputer. ters 5 3 lines. CRT display is controlled by the CRT control register. tained by using each output signal (R, G, B and I). smooth character patterns (refer to Figure 43). Write the display character code in the display RAM. Specify the display color by using the color register. Specify the vertical position by using the vertical position register. Specify the character size by using the character size register. ing data in the block for which display is terminated by software. the block diagram of the CRT display circuit. Table 6. Outline of CRT Display Functions

M37207MF-XXXSP/FP, M37207M8-XXXSP M37207EFSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER and ON-SCREEN DISPLAY CONTROLLER Fig. 43. CRT Display Character Configuration 12 dots 16 dots Fig. 44. CRT Control Register 1 b7 b6 b5 b4 b3 b2 b1 b0 CRT control register 1 (CC) [Address 00EA16] B Name Functions After resetR W CRT Control Register 1

0 All-blocks display control

bit (CC0) (See note) 0 : All-blocks display off 1 : All-blocks display on

1 Block 1 display control bit

(CC1) 0 : Block 1 display off 1 : Block 1 display on 2 0 : Block 2 display off 1 : Block 2 display on 0Block 2 display control bit (CC2) RW RW RW 7 0 Note: Display is controlled by logical product (AND) between the all-blocks display control bit and each block control bit. Fix this bit to “0.” R W 3 0 : Block 3 display off 1 : Block 3 display on 0Block 3 display control bit (CC3) RW 4 0 : Ordinary mode 1 : 1/2-character unit color specification mode 0Block 1 color specification mode switch bit (CC4) RW 5 0 : Oscillation stopped 1 : Oscillation enabled 0Display oscillation stop bit (CC5) RW 6 0 : Ordinary 256 count mode 1 : Double count mode 0Scanning line double count mode flag(CC6) RW

M37207MF-XXXSP/FP, M37207M8-XXXSP M37207EFSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER and ON-SCREEN DISPLAY CONTROLLER Fig. 45. Block Diagram of CRT Display Circuit CRT control register (Address 00EA16, 020816) Vertical position registers (Addresses 00E116 to 00E316) Character size register (Address 00E416) Horizontal position register (Address 00E016) Border selection register (Address 00E516) Display oscillation circuit OSC1 OSC2 Display position control circuit H SYNC VSYNC Display control circuit 13 bytes 5 24 characters 5 1 line + 11bytes 5 24 characters 5 2 lines Color registers (Addresses 00E616 to 00E9 16) CRT port control register (Address 00EC16) Data bus ROM for display 12 dots 5 16 dots 5 256 characters Shift register 12 bits Shift register 12 bits Output circuit R G B I OUT Border RAM RAM for display

M37207MF-XXXSP/FP, M37207M8-XXXSP M37207EFSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER and ON-SCREEN DISPLAY CONTROLLER (2) Display Position The display positions of characters are specified in units called a “block.” There are 3 blocks, blocks 1 to 3. Up to 24 characters can be displayed in each block (refer to (4) Memory for Display). The display position of each block can be set in both horizontal and vertical directions by software. The display position in the horizontal direction can be selected for all blocks in common from 64-step display positions in units of 4T C (TC = oscillating cycle for display). The display position in the vertical direction for each block can be selected from 128-step display positions in units of 4 scanning lines. Block 2 is displayed after the display of block 1 is completed (refer to Figure 46 (a)). Accordingly, if the display of block 2 starts during the display of block 1, only block 1 is displayed. Similarly, when multiline display, block 1 is displayed after the display of block 2 is completed (refer to Figure 46 (b)). The vertical position can be specified from 128-step positions (4 scan- ning lines per a step) for each block by setting values “00 16” to “7F16” to bits 0 to 6 in the vertical position register (addresses 00E116 to 00E316). Figure 48 shows the vertical position register. Fig. 46. Display Position (HR) CV1 CV2 Block 1 Block 2 (a)Example when each block is separated CV1 CV2 Block 1 Block 2 Block 1 (second) CV1 No display No display (b)Example when block 2 overlaps with block 1 Block 3 CV3

M37207MF-XXXSP/FP, M37207M8-XXXSP M37207EFSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER and ON-SCREEN DISPLAY CONTROLLER The display position in the vertical direction is determined by count- ing the horizontal sync signal (HSYNC ). At this time, when VSYNC and H SYNC are positive polarity (negative polarity), it starts to count the rising edge (falling edge) of HSYNC signal from after fixed cycle of rising edge (falling edge) of VSYNC signal. So interval from rising edge (falling edge) of VSYNC signal to rising edge (falling edge) of HSYNC signal needs enough time (2 machine cycles or more) for avoiding jitter. The polarity of H SYNC and VSYNC signals can select with the CRT port control register (address 00EC16). Fig. 48. Vertical Position Register i Fig. 47. Supplement Explanation for Display Position When bits 0 and 1 of the CRT port control register (address 00EC16) are set to “1” (negative polarity) VSYNC signal input VSYNC control signal in microcomputer 0.125 to 0.50 [ ms] ( at f(XIN) = 8MHz) Period of counting H SYNC signal (Note 2) H SYNC signal input Not count 12345 Notes 1 : The vertical position is determined by counting falling edge of HSYNC signal after rising edge of VSYNC control signal in the microcomputer. 2 : Do not generate falling edge of HSYNC signal near rising edge of VSYNC control signal in microcomputer to avoid jitter. 8 machine cycles or more 8 machine cycles or more b7 b6 b5 b4 b3 b2 b1 b0 Vertical position register i (CVi) (i = 1 to 3) [Addresses 00E116 to 00E316] B Name Functions After reset R W Vertical Position Register i to Vertical display start positions128 steps (0016 to 7F16) Indeterminate (CVi : CVi0 to CVi6) Nothing is assigned. This bit is a write disable bit. When this bit is read out, the value is “0.” RW

M37207MF-XXXSP/FP, M37207M8-XXXSP M37207EFSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER and ON-SCREEN DISPLAY CONTROLLER The horizontal position is common to all blocks, and can be set in 64 steps (where 1 step is 4TOSC , TOSC being the display oscillation pe- riod) as values “0016” to “3F16” in bits 0 to 5 of the horizontal position register (address 00E016). The structure of the horizontal position register is shown in Figure 49. Fig. 49. Horizontal Position Register b7 b6 b5 b4 b3 b2 b1 b0 Horizontal position register (HR) [Address 00E016] B Name Functions After resetRW Horizontal Position Register 0to Horizontal display start positions (HR0 to HR5) 64 steps (0016 to 3F16) 0 0Nothing is assigned. This bit is a write disable bit. When this bit is read out, the value is “0.” RW 7 0Fix this bit to “0.” R W

M37207MF-XXXSP/FP, M37207M8-XXXSP M37207EFSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER and ON-SCREEN DISPLAY CONTROLLER (3) Character Size The size of characters to be displayed can be from 4 sizes for each block. Use the character size register (address 00E416) to set a char- acter size. The character size of block 1 can be specified by using bits 0 and 1 of the character size register; the character size of block 2 can be specified by using bits 2 and 3; the character size of block 3 can be specified by using bits 4 and 5. Figure 51 shows the character size register. The character size can be selected from 4 sizes: minimum size, me- dium size, large size and extra large size. Each character size is determined by the number of scanning lines in the height (vertical) direction and the oscillating cycle for display (T C ) in the width (hori- zontal) direction. The minimum size consists of [1 scanning line] 5 [1TC ]; the medium size consists of [2 scanning lines] 5 [2TC ]; the large size consists of [3 scanning lines] 5 [3TC ]; and the extra large size consists of [4 scanning lines] 5 [4TC ]. Table 7 shows the relation between the set values in the character size register and the charac- ter sizes. Fig. 50. Display Start Position of Each Character Size (horizontal direction) Mini- mum Medium Large Horizontal display start position Extra large

position is common to all blocks even when the character size varies with each block (refer to Figure 50). Table 7. Relation between Set Values in Character Size Register and Character Sizes 6 IndeterminateNothing is assigned. This bit is a write disable bit. When this bit is read out, the value is indeterminate.

7 OUT signal output switch

Note: This erases a video signal on an entire screen.

M37207MF-XXXSP/FP, M37207M8-XXXSP M37207EFSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER and ON-SCREEN DISPLAY CONTROLLER (4) Memory for Display There are 2 types of memory for display : CRT display ROM (ad- dresses 1000016 to 12FFF16) used to store character dot data (masked) and CRT display RAM (addresses 060016 to 06D716) used to specify the colors and characters to be displayed. The following describes each type of display memory. ROM for display (addresses 1000016 to 12FFF16) The CRT display ROM contains dot pattern data for characters to be displayed. For characters stored in this ROM to be actually displayed, it is necessary to specify them by writing the character code inherent to each character (code based on the addresses in the CRT display ROM) into the CRT display RAM. The character code list is shown in Table 8. The CRT display ROM has a capacity of 12 K bytes. Since 32 bytes are required for 1 character data, the ROM can stores up to 384 kinds of characters. The CRT display ROM space is broadly divided into 2 areas. The [vertical 16 dots] 5 [horizontal (left side) 8 dots] data of display char- acters are stored in addresses 10000 16 to 107FF16, 1100016 to 117FF16 and 1200016 to 127FF16 ; the [vertical 16 dots] 5 [horizontal (right side) 4 dots] data of display characters are stored in addresses 10800 16 to 10FFF16, 1180016 to 11FFF16 and 1280016 to 12FFF16 (refer to Figure 52). Note however that the high-order 4 bits in the data to be written to addresses 10800 16 to 10FFF16, 1180016 to 11FFF 16 and 1280016 to 12FFF16 must be set to “1” (by writing data “FX16”). Fig. 52. Display Character Stored Data 10XXF 16, 11XXF16, or 12XXF 16 10XXF 16+80016, 11XXF 16+80016, or 12XXF 16+80016 000000 0000000 0000010 0000101 0001000 0001000 0001000 0010000 1111001 0100000 0100000 0100000 0000000 0000101 0000010 01111 000 0000 0000 0000 0000 0000 0000 0100 0100 0100 0010 0010 0010 0000 0000 0000 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 b7 b0 b7 b0 b3 10XX0 16, 11XX016, or 12XX0 16 10XX0 16+80016, 11XX0 16+80016, or 12XX0 16+80016 00000

Table 8. Character Code List (partially abbreviated)

contents of the CRT display RAM. register No. to the low-order 2 bits (bits 0 and 1) in address 068016. CRT display RAM is shown in Figure 53. Table 9. Contents of CRT Display RAM

M37207MF-XXXSP/FP, M37207M8-XXXSP M37207EFSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER and ON-SCREEN DISPLAY CONTROLLER [Color specification] b1 b0 0 0 : Color register 0 specification 0 1 : Color register 1 specification 1 0 : Color register 2 specification 1 1 : Color register 3 specification Color register specification on left side (In ordinary · 1/2-character unit color specification mode) Block 1 [Character specification] Specify 384 characters (“00016” to “17F16”) (Note) Character code 1 st character : 068016 24th character : 069716 1 st character : 060016 24th character : 061716 b3 b2 0 0 : Color register 0 specification 0 1 : Color register 1 specification 1 0 : Color register 2 specification 1 1 : Color register 3 specification Color register specification on right side (In 1/2-character unit color specification mode) (Block 3 : 064016 to 065716) (Block 3 : 06C016 to 06D716) Note : Set values except “07E16,” “07F16.” to Specify 384 characters (“00016” to “17F16”) (Note) Character code b1 b0 0 0 : Color register 0 specification 0 1 : Color register 1 specification 1 0 : Color register 2 specification 1 1 : Color register 3 specification Color register specification Block 2 [Character specification] 1 st character : 0620 24th character : 063716 to to [Color specification] 1 st character : 06A016 24th character : 06B716 to Fig. 53. Structure of RAM for Display

M37207MF-XXXSP/FP, M37207M8-XXXSP M37207EFSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER and ON-SCREEN DISPLAY CONTROLLER (5) Color Registers The color of a displayed character can be specified by setting the color to one of the 4 registers (CO0 to CO3: addresses 00E616 to 00E916) and then specifying that color register with the CRT display RAM. There are 4 color outputs; R, G, B and I. By using a combina- tion of these outputs, it is possible to set 2 4–1 (when no output) = 15 colors. However, since only 4 color registers are available, up to 4 colors can be disabled at one time. R, G, B and I outputs are set by using bits 0 to 3 in the color register. Bit 5 is used to specify whether a character output or blank output. Bits 4, 6 and 7 are used to specify character background color. Fig- ure 54 shows the structure of the color register. Fig. 54. Color Register n b7 b6 b5 b4 b3 b2 b1 b0 Color register n (CO0 to CO3) (n = 0 to 3) [Addresses 00E616 to 00E916] B Name Functions After resetR W Color Register n 0 0

1 B signal output

selection bit (COn1) 0 : No character is output 1 : Character is output

2 G signal output

selection bit (COn2) 0 : No character is output 1 : Character is output

3 R signal output

selection bit (COn3) 0 : No character is output 1 : Character is output

4 B signal output (background)

selection bit (COn4) 0 : No background color is output 1 : Background color is output

5 OUT signal output

control bit (COn5) 0 : Character is output 1 : Blank is output

6 G signal output (background)

selection bit (COn6) 0 : No background color is output 1 : Background color is output

7 R signal output (background)

selection bit (COn7) 0 : No background color is output 1 : Background color is output (See notes 1,2) (See notes 1, 2) Notes 1: When bit 5 = “0” and bit 4 = “1,” there is output same as a character or border output from the OUT pin. 2: When bit 5 = “0” and bit 4= “0,” there is no output from the OUT pin. RW RW RW RW RW RW RW RW I signal output selection bit (COn0) 0 : No character is output 1 : Character is output

frame in the same block, the border (1 dot) is protruded from the frame. Table 10. Colorling to Character Background by R,G,B Output Signals

Table 11. Display Example of Character Background Coloring (when green is set for a character and blue is set for background color)

01 BlackNo output

0 No output

color (green) are not mixed. background is not displayed. background is not displayed. Notes 1: When CO n5 = “0” and COn4 = “1,” there is output same as a character or border output from the OUT pin. When CO n5 = “0” and COn4 = “0,” there is no output from the OUT pin. 2:The portion “A” in which character dots are displayed is not mixed with any TV video signal. 3:The wavy-lined arrows in the table denote video signals.

M37207MF-XXXSP/FP, M37207M8-XXXSP M37207EFSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER and ON-SCREEN DISPLAY CONTROLLER

• The color on the left side : this is set to the color of the color register which is specified by bits 0 and 1 at the color specification addresses (addresses 068016 to 069716) in the CRT display RAM.
• The color on the right side : this is set to the color of the color register which is specified by bits 2 and 3 at the color specification addresses (addresses 0680 16 to 069716) in the CRT display RAM. Fig. 56. Difference between Ordinary Color Specification Mode and 1/2-character Unit Color Specification Mode Color of the color register specified by bits 0 and 1 at address 068016. Block 1 (a) Display in the ordinary mode Color of the color register specified by bits 0 and 1 at address 0681 16. Block 2 Color of the color register specified by bits 2 and 3 at address 0681 16. Color of the color register specified by bits 0 and 1 at address 0681 16. (b) Display in the 1/2-character unit color specification mode Color of the color register specified by bits 2 and 3 at address 0680 16. Color of the color register specified by bits 0 and 1 at address 0680 16. (6) 1/2-character Unit Color Specification Mode By setting “1” to bit 4 of CRT control register 1 (address 00EA16) it is possible to specify colors, in units of a 1/2-character size (16 dots high 5 6 dots wide), to characters in only block 1. In the 1/2-character unit color specification mode, colors of display characters in block 1 are specified as follows:

M37207MF-XXXSP/FP, M37207M8-XXXSP M37207EFSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER and ON-SCREEN DISPLAY CONTROLLER Fig. 57. Example of Border /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines (7) Character Border Function An border of 1 clock (1 dot) equivalent size can be added to a char- acter to be displayed in both horizontal and vertical directions. The border is output from the OUT pin. Border can be specified in units of block by using the border selec- tion register (address 00E5 16). The setting of the border takes prior- ity of the setting by bit 5 of the color register, however, the border of the character to which a background color has been set cannot be output. Figure 58 shows the border selection register. Table 12 shows the relationship between the values set in the border selection regis- ter and the character border function.

0 Border including character output

Table 12. Relationship between Set Value in Border Selection Register and Character Border Function

1 Border only output R, G, B, I output

0 Block 1 OUT output

1 Indeterminate

2 Block 2 OUT output

06, 7 Nothing is assigned. These bits are write disable bits.

3 IndeterminateRWBlock 2 OUT output

4 Block 3 OUT output

5 IndeterminateRWBlock 3 OUT output

M37207MF-XXXSP/FP, M37207M8-XXXSP M37207EFSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER and ON-SCREEN DISPLAY CONTROLLER (8) Multiline Display This microcomputer can ordinarily display 3 lines on the CRT screen by displaying 3 blocks at different vertical positions. In addition, it can display up to 16 lines by using CRT interrupts. A CRT interrupt request occurs at the point at which display of each block has been completed. In other words, when a scanning line reaches the point of the display position (specified by the vertical position registers) of a certain block, the character display of that block starts, and an interrupt occurs at the point at which the scan- ning line exceeds the block. Note: A CRT interrupt does not occur at the end of display when the block is not displayed. In other words, if a block is set to off display with the display control bit of the CRT control reg- ister 1 (address 00EA 16), a CRT interrupt request does not occur (refer to Figure 59). Fig. 59. Timing of CRT Interrupt Request Block 1 (on display) “CRT interrupt request” On display (CRT interrupt request occurs at the end of block display) Block 2 (on display) Block 1' (on display) Block 2' (on display) “CRT interrupt request” “CRT interrupt request” “CRT interrupt request” Block 1 (on display) “CRT interrupt request” Off display (CRT interrupt request does not occur at the end of block display) Block 2 (on display) Block 1' (off display) Block 2' (off display) “CRT interrupt request” No “CRT interrupt request” No “CRT interrupt request”

M37207MF-XXXSP/FP, M37207M8-XXXSP M37207EFSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER and ON-SCREEN DISPLAY CONTROLLER Fig. 60. Display Counter Fig. 61. Timing of CRT Interrupt Request and Display Counter Value The display block counter counts the number of times the display of a block has been completed, and its contents are incremented by 1 each time the display of one block is completed. To provide multi-line display, enable CRT interrupts by clearing the interrupt disable flag to “0” and setting the CRT interrupt enable bit (bit 4 of address 00FE 16) to “1.” After that, process the following sequence within the CRT interrupt processing routine: ead the value of the display block counter. The block for which display is terminated (i.e., the cause of CRT interrupt generation) can be determined by the value read in . Replace the display character data and vertical display position of that block with the character data (contents of CRT display RAM) and vertical display position (contents of vertical position register) to be displayed next. Figure 60 shows the structure of the display block counter. 0Block 1 Block 2 Count value Block 3 Block 1’ Interrupt position b7 b6 b5 b4 b3 b2 b1 b0 Display block counter (CBC) [Address 00EB16] B Name Functions After resetR W Display Block Counter to Number of blocks which are being displayed or has displayed (Incremented each time a block is displayed) IndeterminateRW 0Nothing is assigned. These bits are write disable bits. When these bits are read out, the values are “0.” R—4 to

M37207MF-XXXSP/FP, M37207M8-XXXSP M37207EFSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER and ON-SCREEN DISPLAY CONTROLLER (9) Scanning Line Double Count Mode 1 dot in a displayed character is normally shown with 1 scanning line. In the scanning double count mode, 1 dot can be shown with 2 scan- ning lines. As a result, the displayed dot is extended 2 times the normal size in the vertical direction only (that is to say, the height of a character is extended twofold.) In addition, because the scanning line count is doubled, the display start position of a character becomes also twofold position in the vertical direction. In other words, the contents of the vertical position register is as fol- lows:

• In ordinary mode 256 steps as values “00 16” to “FF16” (4 scanning lines per step)
• In scanning line double count mode 128 steps as values “0016” to “7F16” (8 scanning lines per step) If the contents of the vertical position register for a block are set in the range of “8016” to “FF16” in the scanning line double count mode, that block cannot be displayed (not output to the CRT screen). The scanning line double count mode is specified by setting bit 6 of the CRT control register 1 (address 00EA 16) to “1.” Since this function works in units of a screen, even if the mode is changed during display of 1 screen, the mode before the change remains until the display of the next screen. Fig. 62. Display in Ordinary Mode and in Scanning Line Double Count Mode Scanning line 32 lines A 5 2 Vertical position A 5 2 (a) Display in the ordinary mode (b) Display in the scanning line double count mode Vertical position A Scanning line 16 lines

and UP modes, providing a total of 6 modes. Table 13 shows the contents of each wipe mode. Table 13. Wipe Operation in Each Mode and Values of Wipe Mode Register

we obtain the wipe speed as shown in Table 14. Table 14. Wipe Speed Table 15. Wipe Mode and Wipe Resolution

2 Direction mode selection

7 0Nothing is assigned. This bit is a write disable bit. When this bit is read out, the value is indeterminate.

0 RWb6 b5

M37207MF-XXXSP/FP, M37207M8-XXXSP M37207EFSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER and ON-SCREEN DISPLAY CONTROLLER Fig. 65. Port Control Register (11) CRT Output Pin Control The CRT output pins R, G, B, I and OUT can also function as ports P52, P53, P54, P55 and P56. Set the corresponding bit of the port P5 control register (address 00CB16) to “0” to specify these pins as CRT output pins, or set it to “1” to specify it as a general-purpose port P5 pins. The input polarity of signals H SYNC and VSYNC and output polarity of signals R, G, B, I and OUT can be specified with the bits of the CRT port control register (address 00EC16). Set a bit to “0” to specify posi- tive polarity; set it to “1” to specify negative polarity. The CRT clock I/O pins OSC1, OSC2 are controlled with the port control register (address 0206 16). The CRT port control register is shown in Figure 64. The port control register is shown in Figure 65. Fig. 64. CRT Port Control Register b7 b6 b5 b4 b3 b2 b1 b0 CRT port control register (CRTP) [Address 00EC16] B Name Functions After resetR W CRT Port Control Register 0H SYNC input polarity switch bit (HSYC) 0 : Positive polarity 1 : Negative polarity 1 0 : Positive polarity 1 : Negative polarity

2 R, G, B output polarity

switch bit (R/G/B) 0 : Positive polarity 1 : Negative polarity

3 I output polarity switch bit

(I) 0 : Positive polarity 1 : Negative polarity

4 OUT output polarity

switch bit (OUT) 0 : Positive polarity 1 : Negative polarity

5 R signal output switch bit

(R) 0 : R signal output 1 : MUTE signal output

6 G signal output switch bit

(G) 0 : G signal output 1 : MUTE signal output

7 B signal output switch bit

(B) 0 : B signal output 1 : MUTE signal output VSYNC input polarity switch bit (VSYC) RW RW RW RW RW RW RW RW b7 b6 b5 b4 b3 b2 b1 b0 Port control register (P7D) [Address 020616] B Name Functions After resetR W Port Control Register 0, 1 Port P7 data input bits (P7D0, P7D1) When only OP1 = “0” and OP0 = ”1,” input data is valid. (See note) Indeterminate

2 D-A/AD3 function selection

bit (P7D2) RW RW 0Nothing is assigned. These bits are write disable bits. When these bits are read out, the values are indeterminate. 4P 4 0/XCIN, P41/XCOUT function selection bit (P7D4) 0 : P4 0, P41 1 : XCIN, XCOUT 0 RW Note: OP is the CRT clock selection register. 0: AD3 1: D-A 5 to 7

M37207MF-XXXSP/FP, M37207M8-XXXSP M37207EFSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER and ON-SCREEN DISPLAY CONTROLLER Fig. 66. Example of Raster Coloring Fig. 67. CRT Control Register 2 (12) Raster Coloring Function An entire screen (raster) can be colored by switching each of the R, G, and B pins to MUTE output. R, G, B are controlled with the CRT port control register; I is controlled with the CRT control register 2; OUT is controlled with the character size register. 15 raster colors can be obtained. If the OUT pin has been set to raster coloring output, a raster color- ing signal is always output during 1 horizontal scanning period. This setting is necessary for erasing a background TV image. If the R, G, and B pins have been set to MUTE signal output, a raster coloring signal is output in the part except a no-raster colored char- acter (in Figure 66, a character “O”) during 1 horizontal scanning period. This ensures that character colors do not mix with the raster color. In this case, MUTE signal is output from the OUT pin. An example in which a magenta character “I” and a red character “O” are displayed with blue raster coloring is shown in Figure 66. A'A “RED” “BLUE” H SYNC R B OUT Signals across A – A' b7 b6 b5 b4 b3 b2 b1 b0 CRT control register 2 (CBR) [Address 020816] B Name Functions After resetR W CRT Control Register 2

0 I signal output switch bit

(CBR0) 0: I signal output 1: MUTE signal output

1 I/TIM1 function switch bit

(CBR1) RW RW 0Nothing is assigned. These bits are write disable bits. When these bits are read out, the values are indeterminate. 0: I output or MUTE output 1: 1/2 clock ouput of timer 1 to

M37207MF-XXXSP/FP, M37207M8-XXXSP M37207EFSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER and ON-SCREEN DISPLAY CONTROLLER Fig. 68. CRT Clock Selection Register (13) Clock for Display As a clock for display to be used for CRT display, it is possible to select one of the following 3 types.

• Main clock supplied from the XIN pin
• Clock from the LC or RC supplied from the pins OSC1 and OSC2.
• Clock from the ceramic resonator or quartz-crystal oscillator sup- plied from the pins OSC1 and OSC2. This clock for display can be selected for each block by the CRT clock selection register (address 020916). When selecting the main clock, set the oscillation frequency to 8 MHz. b7 b6 b5 b4 b3 b2 b1 b0 CRT clock selection register (OP) [Address 020916] B Name Functions After reset R W CRT Clock Selection Register 0, 1 CRT clock selection bits (OP0, OP1) Since the main clock is used as the clock for display, the oscillation frequency is limited. Because of this, the character size in width (horizontal) direction is also limited. In this case, pins OSC1 and OSC2 are also used as input ports P70 and P71 respectively. The clock for display is supplied by connecting the following across the pins OSC1 and OSC2.
• a ceramic resonator only for CRT display and a feedback resistor
• a quartz-crystal oscillator only for CRT display and a feedback resistor (See note) to The clock for display is supplied by connecting RC or LC across the pins OSC1 and OSC2. Functions CRT oscillation frequency = f(XIN) Notes 1: It is necessary to connect other ceramic resonator or quartz-crystal oscillator across the pins XIN and XOUT . 2: CC6 is the scnanning line double count mode flag. 0 1 RW CC6 CC6 = “0” or “1” CC6 = “0” CC6 = “0” 1 0 —Do not set. 7 0Fix this bits to “0.” RW Nothing is assigned. These bits are write disable bits. When these bits are read out, the values are “0.”

M37207MF-XXXSP/FP, M37207M8-XXXSP M37207EFSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER and ON-SCREEN DISPLAY CONTROLLER INTERRUPT INTERVAL DETERMINATION FUNCTION This microcomputer incorporates an interrupt interval determination circuit. This interrupt interval determination circuit has an 8-bit binary up counter as shown in Figure 69. Using this counter, it determines an interval on the INT1 or INT2 (refer to Figure 72). The following describes how the interrupt interval is determined. 1. The interrupt input to be determined (INT1 input or INT2 input) is selected by using bit 2 in the interrupt interval determination con- trol register (address 00D8 16). When this bit is cleared to “0,” the INT1 input is selected ; when the bit is set to “1,” the INT2 input is selected. 2. When the INT1 input is to be determined, the polarity is selected by using bit 3 of the interrupt interval determination control register ; when the INT2 input is to be determined, the polarity is selected by using bit 4 of the interrupt interval determination control register. When the relevant bit is cleared to “0,” determination is made of the interval of a positive polarity (rising transition) ; when the bit is set to “1,” determination is made of the interval of a negative po- larity (falling transition). 3. The reference clock is selected by using bit 1 of the interrupt inter- val determination control register. When the bit is cleared to “0,” a 32 ms clock is selected ; when the bit is set to “1,” a 16 ms clock is selected (based on an oscillation frequency of 8MHz in either case). 4. Simultaneously when the input pulse of the specified polarity (rising or falling transition) occurs on the INT1 pin (or INT2 pin), the 8-bit binary up counter starts counting up with the selected reference clock (32 ms or 16 ms). 5. Simultaneously with the next input pulse, the value of the 8-bit binary up counter is loaded into the interrupt interval determina- tion register (address 00D7 16) and the counter is immediately re- set (“0016”). The reference clock is input in succession even after the counter is reset, and the counter restarts counting up from “00 16.” 6. When count value “FE16” is reached, the 8-bit binary up counter stops counting. Then, simultaneously when the next reference clock is input, the counter sets value “FF16” to the interrupt inter- val determination register. The reference clock is generated by setting bit 0 of PWM mode register 1 to “0.” Fig. 69. Block Diagram of Interrupt Interval Determination Circuit Data bus Control circuit Connected to black colored side at rest. Selection gate : (Address 00D716) 32ms RE1 16ms 8-bit binary up counter (8) Interrupt interval determination register (8) RE0 INT1 (Note) RE2 INT2 (Note) Note: The pulse width of external interrupt INT1 and INT2 needs 5 or more machine cycles. RE : Interrupt interval determination control register

M37207MF-XXXSP/FP, M37207M8-XXXSP M37207EFSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER and ON-SCREEN DISPLAY CONTROLLER Fig. 70. Interrupt Interval Determination Control Register INT1 or INT2 input Count interval Fig. 71. Measuring Interval b7 b6 b5 b4 b3 b2 b1 b0 interrupt interval determination control register (RE) [Address 00D816] B Name Functions After resetR W Interrupt Interval Determination Control Register

0 Interrupt interval

operation control bit (RE0) 0 : Stopped 1 : Operating

1 Reference clock selection

bit (RE1) 0 : 16 ms 1 : 32 ms (at f(XIN) = 8 MHz)

2 External interrupt input

pin selection bit (RE2) 0 : INT1 input 1 : INT2 input

3 INT1 pin input polarity

switch bit (RE3) 0 : Positive polarity input 1 : Negative polarity input

4 INT2 pin input polarity

switch bit (RE4) 0 : Positive polarity input 1 : Negative polarity input to RW RW RW RW RW R—Nothing is assigned. These bits are write disable bits. When these bits are read out, the values are “0.”

M37207MF-XXXSP/FP, M37207M8-XXXSP M37207EFSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER and ON-SCREEN DISPLAY CONTROLLER ROM CORRECTION FUNCTION This can correct program data in ROM. Up to 2 addresses (2 blocks) can be corrected, a program for correction is stored in the ROM cor- rection memory in RAM. The ROM memory for correction is 32 bytes 5 2 blocks. Block 1 : addresses 02C0 16 to 02DF16 Block 2 : addresses 02E016 to 02FF16 Set the address of the ROM data to be corrected into the ROM cor- rection address register. When the value of the counter matches the ROM data address in the ROM correction address, the main pro- gram branches to the correction program stored in the ROM memory for correction. To return from the correction program to the main pro- gram, the op code and operand of the JMP instruction (total of 3 bytes) are necessary at the end of the correction program. When the blocks 1 and 2 are used in series, the above instruction is not needed at the end of the block 1. The ROM correction function is controlled by the ROM correction enable register. Notes 1 : Specify the first address (op code address) of each instruction as the ROM correction address. 2 :Use the JMP instruction (total of 3 bytes) to return from the correction program to the main program. 3 :Do not set the same ROM correction address to the blocks 1 and 2. Fig. 72. ROM Correction Address Registers Fig. 73. ROM Correction Enable Register 021716ROM correction address 1 (high-order) 021816ROM correction address 1 (low-order) 021916ROM correction address 2 (high-order) 021A16ROM correction address 2 (low-order) b7 b6 b5 b4 b3 b2 b1 b0 ROM correction enable register (RCR) [Address 021B16] B After resetRW ROM Correction Enable Register

0 Block 1 enable bit (RC0)

0: Disabled 1: Enabled

1 Block 2 enable bit (RC1) 0: Disabled

1: Enabled to Nothing is assigned. These bits are write disable bits. When these bits are read out, the values are “0.” RW RW 2, 3 Fix these bits to“0.” 0 RW

M37207MF-XXXSP/FP, M37207M8-XXXSP M37207EFSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER and ON-SCREEN DISPLAY CONTROLLER Power source voltage 0 V Reset input voltage 0 V 4.5 V 0.6 V Poweron Vcc RESET Vss Microcomputer 3 0.1mF M51953AL RESET CIRCUIT When the oscillation of a quartz-crystal oscillator or a ceramic reso- nator is stable and the power source voltage is 5 V ± 10 %, hold the______ RESET pin at LOW for 2 µs or more, then return is to HIGH. Then, as shown in Figure 75, reset is released and the program starts from the address formed by using the content of address FFFF 16 as the high-order address and the content of the address FFFE16 as the low-order address. The internal state of microcomputer at reset are shown in Figure 75. An example of the reset circuit is shown in Figure 74. The reset input voltage must be kept 0.6 V or less until the power source voltage surpasses 4.5 V. Fig. 74. Example of Reset Circuit Fig. 75. Reset Sequence XIN f RESET Internal RESET SYNC Address Data 32768 count of XIN clock cycle (Note 3) Reset address from the vector table ? ? 01, S 01, S-101, S-2 FFFE FFFF AD H , AD L Notes 1 : f(XIN) and f(f) are in the relation : f(XIN) = 2·f (f). 2 A question mark (?) indicates an undefined state that depends on the previous state.

3 Immediately after a reset, timer 3 and timer 4 are

connected by hardware. At this time, “FF16” is set in timer 3 and “0716” is set to timer 4. Timer 3 counts down with f(XIN)/16, and reset state is released by the timer 4 overflow signal.

M37207MF-XXXSP/FP , M37207M8-XXXSP M37207EFSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER and ON-SCREEN DISPLAY CONTROLLER Fig. 76. Ceramic Resonator Circuit Example Fig. 77. External Clock Input Circuit Example (3) Low-Speed Mode If the internal clock is generated from the sub-clock (XCIN), a low power consumption operation can be realized by stopping only the main clock XIN. To stop the main clock, set bit 6 (CM6) of the CPU mode register (00FB16) to “1.” When the main clock XIN is restarted, the program must allow enough time to for oscillation to stabilize. Note that in low-power-consumption mode the XCIN-XCOUT drivability can be reduced, allowing even lower power consumption (20µA with f (XCIN) = 32kHz). To reduce the XCIN-XCOUT drivability, clear bit 5 (CM 5) of the CPU mode register (00FB16) to “0.” At reset, this bit is set to “1” and strong drivability is selected to help the oscillation to start. When an STP instruction is executed, set this bit to “1” by soft- ware before executing. CLOCK GENERATING CIRCUIT This microcomputer has 2 built-in oscillation circuits. An oscillation circuit can be formed by connecting a resonator between X IN and XOUT (XCIN and XCOUT ). Use the circuit constants in accordance with the resonator manufacturer’s recommended values. No external re- sistor is needed between X IN and XOUT since a feed-back resistor exists on-chip. However, an external feed-back resistor is needed between XCIN and XCOUT . When using XCIN-XCOUT as sub-clock, clear bits 7 and 6 of the mixing control register to “0.” To supply a clock signal externally, input it to the XIN (XCIN) pin and make the XOUT (XCOUT ) pin open. When not using XCIN clock, connect the XCIN to VSS and make the XCOUT pin open. After reset has completed, the internal clock φ is half the frequency of XIN. Immediately after poweron, both the XIN and XCIN clock start oscillating. To set the internal clock φ to low-speed operation mode, set bit 7 of the CPU mode register (address 00FB16) to “1.” Oscillation Control (1) Stop mode The built-in clock generating circuit is shown in Figure 78. When the STP instruction is executed, the internal clock φ stops at HIGH. At the same time, timers 3 and 4 are connected by hardware and “FF16” is set in timer 3 and “0716” is set in the timer 4. Select f(XIN)/16 or f(XCIN)/16 as the timer 3 count source (set bit 0 of the timer mode register 2 to “0” before the execution of the STP instruction). More- over, set the timer 3 and timer 4 interrupt enable bits to disabled (“0”) before execution of the STP instruction. The oscillator restarts when external interrupt is accepted. However, the internal clock φ keeps its HIGH until timer 4 overflows, allowing time for oscillation stabilization when a ceramic resonator or a quartz-crystal oscillator is used. (2) Wait mode When the WIT instruction is executed, the internal clock φ stops in the “H” level but the oscillator continues running. This wait state is released at reset or when an interrupt is accepted (Note). Since the oscillator does not stop, the next instruction can be executed at once. Note: In the wait mode, the following interrupts are invalid. (1) V SYNC interrupt (2) CRT interrupt (3) f(XIN)/4096 interrupt (4) Timer 1 and 2 interrupts using TIM2 pin input as count source (5) Timer 1 interrupt using f(XIN)/4096 or f(XCIN )/4096 as count source (6) Timer 3 interrupt using TIM3 pin input as count source (7) Multi-master I2C-BUS interface interrupt (8) Timer 4 interrupt using f(XIN)/2 or f(XCIN)/2 as count souce X CIN X IN C CIN Microcomputer X COUT R f R d C COUT XOUT C IN C OUT 26 25 30 31 X CIN Microcomputer External oscillation circuit or external pulse XCOUT XIN XOUT Open Open External oscillation circuit Vcc Vss Vcc Vss

M37207MF-XXXSP/FP, M37207M8-XXXSP M37207EFSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER and ON-SCREEN DISPLAY CONTROLLER Fig. 78. Clock Generating Circuit Block Diagram XCIN XCOUT P40/XCIN, P41/XCOUT function selection bit (Notes 1, 4) Internal system clock selection bit (Notes 1, 3) Internal system clock selection bit (Notes 1, 3) Main clock (XIN–XOUT ) stop bit (Notes 1, 3) R SQ STP instruction WIT instructionR S Q Reset Interrupt disable flag I Interrupt request R SQ Reset STP instruction Timing (Internal clock) Timer 3 count source selection bit (Notes 1,2) “1” Timer 3 count stop bit (Notes 1, 2) Timer 4 count stop bit (Notes 1, 2) Timer 3 Timer 4 1/2 1/8 XOUTXIN “1” “0” “0” Notes 1: The value at reset is “0.” Refer to the structure of timer mode register 2. Refer to the structure of CPU mode register (next page). Refer to the structure of port control register.

M37207MF-XXXSP/FP, M37207M8-XXXSP M37207EFSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER and ON-SCREEN DISPLAY CONTROLLER Fig. 79. State Transitions of System Clock Reset The example assumes that 8 MHz is being applied to the XIN pin and 32 kHz to the XCIN pin. The f indicates the internal clock. WIT instruction CM7 : Internal system clock selection bit 0 : XIN–XOUT selected (high-speed mode) 1 : XCIN–XCOUT selected (low-speed mode) CPU mode register (Address : 00FB 16) CM6 : Main clock (XIN–XOUT ) stop bit 0 : Oscillating 1 : Stopped 8MHz oscillating 32kHz oscillating f is stopped (HIGH) Timer operating 8MHz oscillating 32kHz oscillating f(f) = 4MHz 8MHz stopped 32kHz stopped f is stopped (HIGH) 8MHz oscillating 32kHz oscillating f is stopped (HIGH) Timer operating (Note 3) 8MHz oscillating 32kHz oscillating f(f) = 16kHz 8MHz stopped 32kHz stopped f is stopped (HIGH) 8MHz stopped 32kHz stopped f = stopped (HIGH) 8MHz stopped 32kHz oscillating f(f) = 16kHz 8MHz stopped 32kHz oscillating f is stopped (HIGH) Timer operating (Note 3) Interrupt STP instruction Interrupt (Note 1) WIT instruction Interrupt WIT instruction Interrupt STP instruction Interrupt (Note 2) STP instruction Interrupt (Note 2) XC = 1 XC = 0 CM6 = 1 CM6 = 0 External INT, timer interrupt, or SI/O interrupt External INT, or SI/O interrupt Notes 1: When the STP state is ended, a delay of approximately 8ms is automatically generated by timer 3 and timer 4. 2: The delay after the STP state ends is approximately 2s. 3: When the internal clock f divided by 8 is used as the timer count source, the frequency of the count source is 2kHz. The program must allow time for 8MHz oscillation to stabilize High-speed operation start mode WIT instruction 8MHz oscillating 32kHz oscillating f is stopped (HIGH) Timer operating 8MHz oscillating 32kHz oscillating f(f) = 4MHz 8MHz stopped 32kHz stopped f is stopped (HIGH) Interrupt STP instruction Interrupt (Note 1) CM7 = 1 CM7 = 0 External INT, timer interrupt, or SI/O interrupt External INT Port control register (Address : 0206 16) XC: P40/XCIN, P41/XCOUT function selection bit 0 : P40, P41 1 : XCIN, XCOUT

M37207MF-XXXSP/FP, M37207M8-XXXSP M37207EFSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER and ON-SCREEN DISPLAY CONTROLLER ADDRESSING MODE The memory access is reinforced with 17 kinds of addressing modes. Refer to SERIES 740 <Software> User’s Manual for details. MACHINE INSTRUCTIONS There are 71 machine instructions. Refer to SERIES 740 <Soft- ware> User’s Manual for details. PROGRAMMING NOTES (1) The divide ratio of the timer is 1/(n+1). (2) Even though the BBC and BBS instructions are executed imme- diately after the interrupt request bits are modified (by the pro- gram), those instructions are only valid for the contents before the modification. At least one instruction cycle is needed (such as an NOP) between the modification of the interrupt request bits and the execution of the BBC and BBS instructions. (3) After the ADC and SBC instructions are executed (in the decimal mode), one instruction cycle (such as an NOP) is needed before the SEC, CLC, or CLD instruction is executed. (4) An NOP instruction is needed immediately after the execution of a PLP instruction. (5) In order to avoid noise and latch-up, connect a bypass capacitor (≈ 0.1 µF) directly between the V CC pin–VSS pin and the VCC pin– CNV SS pin, using a thick wire. AUTO-CLEAR CIRCUIT When a power source is supplied, the auto-clear function will oper- ate by connecting the following circuit to the RESET pin. Fig. 81. Auto-clear Circuit Example Fig. 80. Display Oscillation Circuit DISPLAY OSCILLATION CIRCUIT The CRT display clock oscillation circuit has a built-in clock oscilla- tion circuits, so that a clock for CRT display can be obtained simply by connecting an LC, an RC, a quartz-crystal oscillator or a ceramic resonator across the pins OSC1 and OSC2. Which of the sub-clock or the display oscillation circuit is selected by setting bits 0 and 1 of the CRT clock selection register (address 0209 16). OSC2OSC1 L C1 C2 RESET Vss Vcc Circuit example 1 RESET Vss Vcc Circuit example 2 Note : Make the level change from LOW to HIGH at the point at which the power source voltage exceeds the specified voltage.

M37207MF-XXXSP/FP, M37207M8-XXXSP M37207EFSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER and ON-SCREEN DISPLAY CONTROLLER Name of Programming Adapter PCA4762 PCA7417 Product M37207EFSP M37207EFFP DATA REQUIRED FOR MASK ORDERS The following are necessary when ordering a mask ROM produc- tion: (1) Mask ROM Order Confirmation Form (2) Mark Specification Form (3) Data to be written to ROM, in EPROM form (32-pin DIP type 27C101, three identical copies) PROM Programming Method The built-in PROM of the One Time PROM version (blank) and the built-in EPROM version can be read or programmed with a general- purpose PROM programmer using a special programming adapter. The PROM of the One Time PROM version (blank) is not tested or screened in the assembly process nor any following processes. To ensure proper operation after programming, the procedure shown in Figure 82 is recommended to verify programming. Fig. 82. Programming and Testing of One Time PROM Version Programming with PROM programmer Screening (Caution) (150°C for 40 hours) Verification with PROM programmer Functional check in target device Caution : The screening temperature is far higher than the storage temperature. Never expose to 150°C exceeding 100 hours.

M37207MF-XXXSP/FP, M37207M8-XXXSP M37207EFSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER and ON-SCREEN DISPLAY CONTROLLER Min. 4.5 0.8VCC 0.7VCC 7.9 6.0 Typ. 5.0 8.0 Max. 5.5 VCC VCC

0.4 VCC

0.3 VCC

0.2 VCC

8.1 100 400 Power source voltage (Note 4), During CPU, CRT operation Power source voltage HIGH input voltage P0 0–P07, P10–P17, P20–P27, P30–P36, P60–P67, P70, P71, HSYNC , VSYNC ,______ RESET, XIN, XCIN, OSC1, P40–P47 (including when using serial I/O) HIGH input voltage SDA3, SCL3, S DA2, SCL2, SDA1, SCL1 (When using I2C-BUS) LOW input voltage P0 0–P07, P10–P17, P20–P27, P30, P31, P35, P40–P47, P70, P71 LOW input voltage SDA3, SCL3, SDA2, SCL2, SDA1, SCL1 (When using I2C-BUS) LOW input voltage H SYNC , VSYNC , RESET, P32–P34, P36, P41, P42, P44–P46, XIN, XCIN, OSC1 When using serial I/O; SOUT2 , SCLK2 , SIN2, SOUT1 , SCLK1 , SIN1 HIGH average output current (Note 1)R, G, B, I, OUT, D-A, P00–P07, P10–P17, P20–P27, P30, P31 LOW average output current (Note 2)R, G, B, I, OUT, D-A, P00–P07, P10–P17, P20–P23, P30–P36 LOW average output current (Note 2)P46, P47, P60–P67 LOW average output current (Note 3)P24–P27 LOW average output current (Note 2)P40–P45 Oscillation frequency (for CPU operation) (Note 5) XIN Oscillation frequency (for sub-clock operation) (Note 7)XCIN Oscillation frequency (for CRT display) (Note 6) OSC1 Input frequency TIM2, TIM3, INT1, INT2 Input frequency S CLK1 , SCLK2 Input frequency SCL1, SCL2, SCL3 Symbol VCC VI VI VO VO IOH IOL1 IOL2 IOL3 IOL4 Pd Topr Tstg ABSOLUTE MAXIMUM RATINGS Conditions All voltages are based on VSS . Output transistors are cut off. T a = 25 °C Ratings –0.3 to 6 –0.3 to 6 –0.3 to VCC + 0.3 –0.3 to VCC + 0.3 –0.3 to 13 0 to 1 (Note 1) 0 to 2 (Note 2) 0 to 1 (Note 2) 0 to 10 (Note 3) 0 to 6 (Note 2) 550 –10 to 70 –40 to 125 Unit V V V V V mA mA mA mA mA mW Parameter V V V V V V V mA mA mA mA mA MHz kHz MHz kHz MHz kHz RECOMMENDED OPERATING CONDITIONS (Ta = –10 °C to 70 °C, VCC = 5 V ± 10 %, unless otherwise noted) VCC VSS VIH1 VIH2 VIL1 VIL2 VIL3 IOH IOL1 IOL2 IOL3 IOL4 f(XIN) f(XCIN) fOSC fhs1 fhs2 fhs3 Symbol Parameter UnitLimits Power source voltage VCC Input voltage CNV SS Input voltage P0 0–P07, P10–P17, P20–P27, P30–P36, P40–P47, P60–P67, P70, P71,OSC1, XIN, HSYNC ,______ VSYNC , RESET, XCIN, AD1–AD8 Output voltage P0 0–P07, P10–P17, P20–P27, P30–P36, P40–P45, R, G, B, I, OUT, D-A, XOUT , XCOUT , OSC2 Output voltage P4 6, P47, P60–P67 Circuit current R, G, B, I, OUT, P00–P07, P10–P17, P20–P27, P30, P31, D-A Circuit current R, G, B, I, OUT, P00–P07, P10–P17, P20–P23,P30–P36, D-A Circuit current P4 6, P47, P60–P67 Circuit current P2 4–P27 Circuit current P4 0–P45 Power dissipation Operating temperature Storage temperature

M37207MF-XXXSP/FP, M37207M8-XXXSP M37207EFSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER and ON-SCREEN DISPLAY CONTROLLER ICC VOH VOL VT+–VT– IIZH IIZL IOZH R BS Power source current HIGH output voltage R, G, B, I, OUT, P00–P07, P10–P17, P20–P27, D-A, P30, P31 LOW output voltage R, G, B, I, OUT, P00–P07, P10–P17, P20–P23, P30–P36, D-A LOW output voltage P46, P47, P60–P67 LOW output voltage P24–P27 LOW output voltage P40–P45 Hysteresis RESET Hysteresis (Note 8) HSYNC , VSYNC , P32, P33, P34, P36, P40–P46, HIGH input leak current RESET, P00–P07, P10–P17, P20–P27, P30–P36, P40–P47, AD1–AD8 LOW input leak current RESET, P00–P07, P10–P17, P20–P27, P30–P36, P40–P46, P60–P67, AD1–AD8 HIGH output leak currentP46, P47, P60–P67 I2C-BUS·BUS switch connection resistor (between SCL1 and SCL2, SDA1 and SDA2) Min. 2.4 ELECTRIC CHARACTERISTICS (VCC = 5 V ± 10 %, VSS = 0 V, f(XIN) = 8 MHz, Ta = –10 °C to 70 °C, unless otherwise noted) Limits Typ. 100 0.5 0.5 Max. 200 100 0.4 0.4 3.0 0.4 0.6 0.7 1.3 130 Symbol Parameter Test conditions Unit mA µA mA µA V V V µA µA µA Ω Wait mode Stop mode System operation CRT OFF CRT ON VCC = 5.5 V, f(XIN) = 8 MHz Notes 1:The total current that flows out of the IC must be 20 mA or less. 2:The total input current to IC (IOL1 + IOL2 + IOL4 ) must be 30 mA or less. 3:The total average input current for ports P24–P27 to IC must be 20 mA or less. 4:Connect 0.022 m F or more capacitor externally between the power source pins VCC –VSS so as to reduce power source noise. Also connect 0.068 m F or more capacitor externally between the pins VCC –CNV SS . 5:Use a quartz-crystal oscillator or a ceramic resonator for the CPU oscillation circuit. 6:Use a RC or an LC for the CRT oscillation circuit. 7:When using the sub-clock, set fCLK < fCPU /3. 8:P32–P34 ,P36 have the hysteresis when these pins are used as interrupt input pins or timer input pins. P40–P46 have the hysteresis when these pins are used as serial I/O pins. VCC = 5.5 V, f(XIN) = 0, f(XCIN) = 32kHz, CRT OFF, Low-power dissipation mode set VCC = 5.5 V, f(XIN) = 8 MHz VCC = 5.5 V, f(XIN) = 0, f(XCIN) = 32kHz, Low-power dissipation mode set (CM 5 = “0,” CM6 = “1”) VCC = 5.5 V, f(XIN) = 0, f(XCIN) = 0 VCC = 4.5 V IOH = –0.5 mA VCC = 4.5 V IOL = 0.5 mA VCC = 4.5 V IOL = 0.5 mA VCC = 4.5 V IOL = 10.0 mA VCC = 4.5 V IOL = 3 mA IOL = 6 mA VCC = 5.0 V VCC = 5.0 V VCC = 5.5 V VI = 5.5 V VCC = 5.5 V VI = 0 V VCC = 5.5 V VO = 12 V VCC = 4.5 V

M37207MF-XXXSP/FP, M37207M8-XXXSP M37207EFSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER and ON-SCREEN DISPLAY CONTROLLER MULTI-MASTER I 2C-BUS BUS LINE CHARACTERISTICS Bus free time Hold time for START condition “L” period of SCL clock Rising time of both SCL and SDA signals Data hold time “H” period of SCL clock Falling time of both SCL and SDA signals Data set-up time Set-up time for repeated START condition Set-up time for STOP condition tBUF tHD:STA tLOW tR tHD:DAT tHIGH tF tSU:DAT tSU:STA tSU:STO Min. 4.7 4.0 4.7 4.0 250 4.7 4.0 Max. 1000 300 Min. 1.3 0.6 1.3 20+0.1C b 0.6 20+0.1Cb 100 0.6 0.6 Max. 300 0.9 300 µs µs µs ns µs µs ns ns µs µs Unit Standard clock mode High-speed clock mode ParameterSymbol Note: Cb = total capacitance of 1 bus line Fig. 83. Definition diagram of timing on multi-master I2C-BUS Resolution Absolute accuracy Max. bits LSB Min. Limits Typ. UnitTest conditionsParameterSymbol — ±1 Note: When Vcc = 5 V, 1 LSB = 5/64 V. A-D COMPARATOR CHARACTERISTICS (VCC = 5 V ± 10 %, VSS = 0 V, f(XIN) = 8 MHz, Ta = –10 °C to 70 °C, unless otherwise noted) SDA SCL P tBUF S tHD :STA tLOW tR tHD :DAT tHIGH tF tSU :DAT tSU :STA Sr P tSU :STOtHD :STA S Sr P : Start condition : Restart condition : Stop condition

M37207MF-XXXSP/FP, M37207M8-XXXSP M37207EFSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER and ON-SCREEN DISPLAY CONTROLLER PACKAGE OUTLINE 64P4B 80P6N–A

M37207MF-XXXSP/FP, M37207M8-XXXSP M37207EFSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER and ON-SCREEN DISPLAY CONTROLLER GZZ–SH08–83B < 48B0 >

740 FAMILY MASK ROM CONFIRMATION FORM

SINGLE-CHIP MICROCOMPUTER M37207MF-XXXSP/FP MITSUBISHI ELECTRIC Mask ROM number Date : Supervisorsignature Receipt Section head signature h Customer Company name Date issued Date : TEL ( ) Note : Please fill in all items marked h . Submitted by Supervisor Issuance signature h 1. Confirmation Specify the name of the product being ordered and the type of EPROMs submitted. Three EPROMs are required for each pattern. If at least two of the three sets of EPROMs submitted contain identical data, we will produce masks based on this data. We shall assume the responsibility for errors only if the mask ROM data on the products we produce differs from this data. Thus, extreme care must be taken to verify the data in the submitted EPROMs. Checksum code for entire EPROM (hexadecimal notation) 27C101 EPROM address

000016 Product name

ASCII code : ‘M37207MF –’000F16 FFFF 16 Set “FF16” in the shaded area. Write the ASCII codes that indicates the product name of “M37207MF–” to addresses 000016 to 000F16. (1) (2) EPROM type (indicate the type used) 080016 Character ROM 1-a 1080016 1280016 h 2. Mark specification Mark specification must be submitted using the correct form for the type package being ordered fill out the appropriate mark specification form (64P4B for M37207MF-XXXSP, 80P6N for M37207MF-XXXFP) and attach to the mask ROM confirmation form. (1/3) Do you set “FF 16” in the shaded area (set “F16” in the low-order 4-bit shaded area) ? Do you write the ASCII codes that indicates the product name of “M37207MF–” to addresses 0000 16 to 000F16 ? EPROM data check item (Refer the EPROM data and check “ ” in the appropriate box) fi Yes fi Yes l l 1000016 1180016 Character ROM 2-a data ROM 62K bytes 1100016 ROM 1-b 1200016 1300016 1FFFF 16 Character ROM 3-a Character ROM 2-b Character ROM 3-b Character Microcomputer name : M37207MF-XXXSP M37207MF-XXXFP

M37207MF-XXXSP/FP, M37207M8-XXXSP M37207EFSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER and ON-SCREEN DISPLAY CONTROLLER GZZ–SH08–83B <48B0 > SINGLE-CHIP MICROCOMPUTER M37207MF-XXXSP/FP MITSUBISHI ELECTRIC ‘M’= 164D 16‘3’= 33 16‘7’= 3 7 16‘2’= 3 2 16‘0’= 30 16‘7’= 3 7 16‘M’= 4D 16‘F’= 46 000016 000116 000216 000316 000416 000516 000616 000716 Address ‘–’= 162D 16FF 16FF 16FF 16FF 16FF 16FF 16FF 000816 000916 000A16 000B16 000C 16 000D 16 000E16 000F16 Address Addresses 000016 to 000F16 store the product name, and addresses 1000016 to 12FFF16 store the character pattern. If the name of the product contained in the EPROMs does not match the name on the mask ROM confirmation form, the ROM processing is disabled. Write the data correctly. Inputting the name of the product with the ASCII code ASCII codes ‘M37207MF-’ are listed on the right. The addresses and data are in hexadecimal notation. Inputting the character ROM Input the character ROM data by dividing it into character ROM1, character ROM2 and character ROM3. For the character ROM data, see the next page and on. Writing the product name and character ROM data onto EPROMs (2/3)

M37207MF-XXXSP/FP, M37207M8-XXXSP M37207EFSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER and ON-SCREEN DISPLAY CONTROLLER GZZ–SH08–83B< 48B0 > SINGLE-CHIP MICROCOMPUTER M37207MF-XXXSP/FP MITSUBISHI ELECTRIC The structure of character ROM (divided of 125 16 dots font) Example Character code “k16” ÜÜCharacter ROM address 1000016+m000 16+n016+016 b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0 0016 0416 0416 0A16 0A16 1116 1116 1116 2016 2016 3F16 4016 4016 4016 0016 0016 F016 F016 F016 F016 F016 F016 F016 F016 F816 F816 F816 F416 F416 F416 F016 F016 Character ROM1 F16 (3/3) 1000016+m000 16+n016+116 1000016+m000 16+n016+216 1000016+m000 16+n016+316 1000016+m000 16+n016+416 1000016+m000 16+n016+516 1000016+m000 16+n016+616 1000016+m000 16+n016+716 1000016+m000 16+n016+816 1000016+m000 16+n016+916 1000016+m000 16+n016+A16 1000016+m000 16+n016+B16 1000016+m000 16+n016+C 16 1000016+m000 16+n016+D 16 1000016+m000 16+n016+E16 1000016+m000 16+n016+F16 1080016+m000 16+n016+016 1080016+m000 16+n016+116 1080016+m000 16+n016+216 1080016+m000 16+n016+316 1080016+m000 16+n016+416 1080016+m000 16+n016+516 1080016+m000 16+n016+616 1080016+m000 16+n016+716 1080016+m000 16+n016+816 1080016+m000 16+n016+916 1080016+m000 16+n016+A 16 1080016+m000 16+n016+B 16 1080016+m000 16+n016+C 16 1080016+m000 16+n016+D 16 1080016+m000 16+n016+E 16 1080016+m000 16+n016+F16 Character ROM addressCharacter ROM data Character ROM data Character ROM2

M37207MF-XXXSP/FP, M37207M8-XXXSP M37207EFSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER and ON-SCREEN DISPLAY CONTROLLER GZZ–SH10–49B < 61A0 > SINGLE-CHIP MICROCOMPUTER M37207M8-XXXSP MITSUBISHI ELECTRIC Mask ROM number Date : Supervisorsignature Receipt Section head signature h Customer Company name Date issued Date : TEL ( ) Note : Please fill in all items marked h . Submitted by Supervisor Issuance signature h 1. Confirmation Specify the name of the product being ordered and the type of EPROMs submitted. Three EPROMs are required for each pattern. If at least two of the three sets of EPROMs submitted contain identical data, we will produce masks based on this data. We shall assume the responsibility for errors only if the mask ROM data on the products we produce differs from this data. Thus, extreme care must be taken to verify the data in the submitted EPROMs. Checksum code for entire EPROM (hexadecimal notation) 27C101 EPROM address ASCII code : ‘M37207M8 –’000F16 FFFF 16 Set “FF16” (“F16” in the high-order 4-bit shaded area) in the shaded area. Write the ASCII codes that indicate the product name of “M37207M8–” to addresses 000016 to 000F16. (1) (2) EPROM type (indicate the type used) 800016 Character ROM 1-a 1080016 h 2. Mark specification Mark specification must be submitted using the correct form for the type of package being ordered. Fill out the appropriate mark specification form (64P4B for M37207M8-XXXSP) and attach to the mask ROM confirmation form. (1/3) Is “FF16” in the shaded area (set “F16” in the high-order 4-bit shaded area) ? Are the ASCII codes that indicates the product name of “M37207M8–” to addresses 0000 16 to 000F16 ? EPROM data check item (Confirm the EPROM data and check “ ” the appropriate box) fi Yes fi Yes l l 1000016 1180016 Character ROM 2-a data ROM 32 K bytes 1100016 ROM 1-b 1200016 1FFFF 16 Character ROM 2-b Character Microcomputer name : M37207M8-XXXSP

M37207MF-XXXSP/FP, M37207M8-XXXSP M37207EFSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER and ON-SCREEN DISPLAY CONTROLLER GZZ–SH10–49B <61A0 > SINGLE-CHIP MICROCOMPUTER M37207M8-XXXSP MITSUBISHI ELECTRIC ‘M’= 164D 16‘3’= 33 16‘7’= 3 7 16‘2’= 3 2 16‘0’= 30 16‘7’= 3 7 16‘M’= 4D 16‘8’= 38 000016 000116 000216 000316 000416 000516 000616 000716 Address ‘–’= 162D 16FF 16FF 16FF 16FF 16FF 16FF 16FF 000816 000916 000A16 000B16 000C 16 000D 16 000E16 000F16 Address Addresses 000016 to 000F16 store the product name, and addresses 1000016 to 11FFF16 store the character pattern. If the name of the product contained in the EPROMs does not match the name on the mask ROM confirmation form, the ROM processing is disabled. Please make sure the data is written correctly. How to input the name of the product with the ASCII code : ASCII codes ‘M37207M8-’ are listed on the right. The addresses and data are in hexadecimal notation. Inputting the character ROM Input the character ROM data by dividing it into character ROM1 and character ROM2. For the character ROM data, see the next page and on. How to Write the Product Name and Character ROM Data onto EPROMs (2/3)

M37207MF-XXXSP/FP, M37207M8-XXXSP M37207EFSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER and ON-SCREEN DISPLAY CONTROLLER 9090 GZZ–SH10–49B< 61A0 > SINGLE-CHIP MICROCOMPUTER M37207M8-XXXSP MITSUBISHI ELECTRIC The structure of character ROM (divided of 125 16 dots font) Example Character code “k16” ÜÜCharacter ROM address 1000016+m000 16+n016+016 b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0 0016 0416 0416 0A16 0A16 1116 1116 1116 2016 2016 3F16 4016 4016 4016 0016 0016 F016 F016 F016 F016 F016 F016 F016 F016 F816 F816 F816 F416 F416 F416 F016 F016 Character ROM1 F16 (3/3) 1000016+m000 16+n016+116 1000016+m000 16+n016+216 1000016+m000 16+n016+316 1000016+m000 16+n016+416 1000016+m000 16+n016+516 1000016+m000 16+n016+616 1000016+m000 16+n016+716 1000016+m000 16+n016+816 1000016+m000 16+n016+916 1000016+m000 16+n016+A16 1000016+m000 16+n016+B16 1000016+m000 16+n016+C 16 1000016+m000 16+n016+D 16 1000016+m000 16+n016+E16 1000016+m000 16+n016+F16 1080016+m000 16+n016+016 1080016+m000 16+n016+116 1080016+m000 16+n016+216 1080016+m000 16+n016+316 1080016+m000 16+n016+416 1080016+m000 16+n016+516 1080016+m000 16+n016+616 1080016+m000 16+n016+716 1080016+m000 16+n016+816 1080016+m000 16+n016+916 1080016+m000 16+n016+A 16 1080016+m000 16+n016+B 16 1080016+m000 16+n016+C 16 1080016+m000 16+n016+D 16 1080016+m000 16+n016+E 16 1080016+m000 16+n016+F16 Character ROM addressCharacter ROM data Character ROM data Character ROM2

M37207MF-XXXSP/FP, M37207M8-XXXSP M37207EFSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER and ON-SCREEN DISPLAY CONTROLLER 9191 64P4B (64-PIN SHRINK DIP) MARK SPECIFICATION FORM

M37207MF-XXXSP/FP, M37207M8-XXXSP M37207EFSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER and ON-SCREEN DISPLAY CONTROLLER 80P6N (80-PIN QFP) MARK SPECIFICATION FORM

M37207MF-XXXSP/FP, M37207M8-XXXSP M37207EFSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER and ON-SCREEN DISPLAY CONTROLLER APPENDIX Pin Configuration (TOP VIEW) Outline 64P4B P65/PWM5 P41/SCLK2 /SCL3/XCOUT OSC1/P7 0/AD4 OSC2/P7 1/AD5 P36/INT2/AD2 P35/AD1 P34/INT1 D-A/AD3 P60/PWM0 P61/PWM1 P66/PWM6 P67/PWM7 P33/TIM3 P32/TIM2/AD6 P31 P30 P47/SRDY1 /PWM8 P46/SIN1/PWM9 P43/SRDY2 /SCL2/AD7 P42/SIN2/SDA2/AD8 P40/SOUT2 /SDA3/XCIN VCC H SYNC VSYNC R/P52 G/P53 B/P54 I/P55/TIM1 OVERFLOW P07 P11 P13 P15 P16 P17 P20 P22 P23 P24 P25 P26 P27 P21 P62/PWM2 P63/PWM3 P64/PWM4 P45/SCLK1 /SCL1 P44/SOUT1 /SDA1 OUT/P5 6 P00 P04 P05 P06 M37207MF-XXXSP, M37207M8-XXXSP M37207EFSP f CNV SS RESET XOUT XIN VSS P01 P02 P03 P10 P12 P14

M37207MF-XXXSP/FP, M37207M8-XXXSP M37207EFSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER and ON-SCREEN DISPLAY CONTROLLER Pin Configuration (TOP VIEW) Outline 80P6N-A NC: Unconnected P07 RESET CNV SS XIN P04 P05 P06 NC NC NC NC NC NC NC NC NC NC NC NC NC 19 20 NC P65/PWM5 P60/PWM0 P61/PWM1 P66/PWM6 P67/PWM7 P33/TIM3 P32/TIM2/AD6 P31 P30 P46/SIN1/PWM9 P62/PWM2 P63/PWM3 P64/PWM4 P45/SCLK1 /SCL1 f XOUT VSS OSC1/P7 0/AD4 OSC2/P7 1/AD5 P36/INT2/AD2 P35/AD1 P34/INT1 D-A/AD3 VCC H SYNC VSYNC R/P52 G/P53 B/P54 I/P55/TIM1 OVERFLOW P11 P13 P15 P16 P17 P20 P22 P23 P24 P25 P26 P27 P21 OUT/P5 6 P00 P01 P02 P03 P10 P12 P14 M37207MF-XXXFP, M37207EFFP NC NC P47/SRDY1 /PWM8 P44/SOUT1 /SDA1 P43/SRDY2 /SCL2/AD7 P42/SIN2/SDA2/AD8 P41/SCLK2 /SCL3/XCOUT P4f/SOUT2 /SDA3/XCIN

M37207MF-XXXSP/FP, M37207M8-XXXSP M37207EFSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER and ON-SCREEN DISPLAY CONTROLLER Memory Map 000016 00C0 16 00FF16 01FF16 033F16 080016 SFR area Not used Not used FFFF 16 FFDE 16 FF00 16 030016 Interrupt vector area Not used 1000016 11FFF 16 1FFFF 16 ROM for display (8 K bytes) for M37207M8 Special page ROM (32 K bytes) for M37207M8 RAM for display (144 bytes) (See note) Zero page Note: Refer to Table 9. Contents of CRT display RAM. 020416 021B16 02C0 16 02FF16 2 page register Not used 06D7 16 060016 Not used ROM correction memory (64 bytes) Block 1: addresses 02C016 to 02DF16 Block 2: addresses 02E016 to 02FF16 800016 04FF16 12FFF 16 ROM for display (12 K bytes) for M37207MF ROM (62 K bytes) for M37207MF RAM (512 bytes) for M37207M8 RAM (960 bytes) for M37207MF

M37207MF-XXXSP/FP, M37207M8-XXXSP M37207EFSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER and ON-SCREEN DISPLAY CONTROLLER Memory Map of Special Function Register (SFR) n SFR Area (addresses C016 to DF16) D0 16 D1 16 D2 16 D3 16 D4 16 D5 16 D6 16 D7 16 D8 16 D9 16 DA 16 DB 16 DC 16 DD 16 DE 16 DF 16 C0 16 C1 16 C2 16 C3 16 C4 16 C5 16 C6 16 C7 16 C8 16 C9 16 CB 16 CC 16 CD 16 CE 16 CF 16 CA 16 Address Port P5 (P5) Port P5 control register (D5) DA-H register (DA-H) DA-L register (DA-L) PWM0 register (PWM0) Port P1 (P1) Port P1 direction register (D1) Port P3 (P3) Port P3 direction register (D3) Port P2 (P2) Port P2 direction register (D2) Register Port P0 (P0) Port P0 direction register (D0) PWM1 register (PWM1) PWM2 register (PWM2) PWM3 register (PWM3) PWM4 register (PWM4) PWM output control register 1 (PW) PWM output control register 2 (PN) Serial I/O mode register (SM) Serial I/O regsiter (SIO) Bit allocation State immediately after reset : “0” immediately after reset : Undefined immediately after reset <State immediately after reset> : “1” immediately after reset : Fix this bit to “0” (do not write “1”) < Bit allocation> Function bit : No function bit : Fix this bit to “1” (do not write “0”) Name : I2C data shift register (S0) I2C control register (S1D) I2C clock control register (S2) I2C status register (S1) I2C address register (S0D) PW0PW1PW2PW3PW4PW5PW6PW7 PN2PN3PN4 b7 b0 0016 b7 b0 0016 0016 0 ???? ? ? SM0SM1SM2SM3SM5SM6 0 0016 0016 0016 0016 SAD0SAD1SAD2SAD3SAD4SAD5SAD6 RBW LRBAD0AASALPINBBTRXMST BC0BC1BC2ESOALSBSEL0BSEL1 CCR0CCR1CCR2CCR3CCR4ACK 10BIT SAD D1D2D3D4D5D6D7 D0 FAST MODE ACK BIT PN1 PN0 0016 0016 0016 0016 00 0 01 0 0? 0016 RE1RE2RE3RE4RE5 RE0 Port P4 (P4) Port P4 direction register (D4) Port P6 (P6) Port P6 direction register (D6) Interrupt interval determination register (??) Interrupt interval determination control register (RE)

M37207MF-XXXSP/FP, M37207M8-XXXSP M37207EFSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER and ON-SCREEN DISPLAY CONTROLLER b7 b0 Bit allocation State immediately after reset b7 b0 : “0” immediately after reset : Undefined immediately after reset <State immediately after reset> : “1” immediately after reset : Fix this bit to “0” (do not write “1”) <Bit allocation> Function bit : No function bit : Fix this bit to “1” (do not write “0”) Name : F016 F116 F216 F316 F416 F516 F616 F716 F816 F916 FA 16 FB 16 FC 16 FD 16 FE 16 FF16 E016 E116 E216 E316 E416 E516 E616 E716 E816 E916 EB 16 EC 16 ED 16 EE 16 EF 16 EA 16 Address CRT control register 1 (CC) CRT port control register (CRTP) Wipe start register (??) A-D control register 1 (ADM) Timer 1 (TM1) Vertical register 2 (CV2) Color register 0 (CO0) Color register 1 (CO1) Character size register (CS) Border selection register (MD) Register Horizontal register (HR) Vertical register 1 (CV1) Timer 2 (TM2) Timer 3 (TM3) Timer 4 (TM4) Timer mode register 1 (TMR1) Timer mode register 2 (TMR2) PWM5 register (PWM5) PWM8 register (PWM8) PWM9 register (PWM9) Interrupt request register 1 (IREQ1) Interrupt request register 2 (IREQ2) Interrupt control register 1 (ICON1) Interrupt control register 2 (ICON2) Color register 2 (CO2) Color register 3 (CO3) Wipe mode register (SL) CPU mode register (CPUM) n SFR Area (addresses E016 to FF16) HR0HR1HR2HR3HR4HR5 CV10CV11CV12CV13CV14CV15CV16 CV20CV21CV22CV23CV24CV25CV26 CS10CS11CS20CS21 MD10MD20 CO01CO02CO03CO05 CO11CO12CO13CO15 CO21CO22CO23CO25 CO31CO32CO33CO35 CC0CC1CC2 VSYCR/G/BIRGB HSYC SL0SL1 ADM0ADM1ADM2ADM4 TMR10TMR11TMR12TMR13TMR14 CM2 TM1RTM2RTM3RTM4RCRTRVSCRIICR CK0MSR IT1RIT2RS1R TM1ETM2ETM3ETM4ECRTEVSCEIICE IT1EIT2ESIEMSE 0016 ?00 000 00 FF16 0716 FF16 0716 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 SL2SL3SL4SL5SL6 TMR15TMR16TMR17 CM7 CM6 CM5 TM56R TM56ETM56C CK001 11 001 0 CV30CV31CV32CV33CV34CV35CV36 ?0 ?????? CS30CS31CS7 MD11MD21MD31 MD30 CO00 CO11 CO22 CO33 CO04 CO14 CO24 CO34 CO06 CO16 CO26 CO36 CO07 CO17 CO27 CO37 0016 0016TMR20TMR21TMR22TMR23TMR24TMR25TMR26TMR27 Vertical register 3 (CV3) Display block counter (CBC) PWM6 register (PWM6) PWM7 register (PWM7)

M37207MF-XXXSP/FP, M37207M8-XXXSP M37207EFSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER and ON-SCREEN DISPLAY CONTROLLER Address Register n SFR Area (addresses 20416 to 21B16) 21016 21116 21216 21316 21416 21516 21616 21716 21816 21916 21A16 21B16 ROM correction address 1 (high-order) ROM correction address 1 (low-order) ROM correction address 2 (high-order) ROM correction address 2 (low-order) ROM correction enable register (RCR) b7 b0 Bit allocation State immediately after reset b7 b0 : “0” immediately after reset : Undefined immediately after reset <State immediately after reset> : “1” immediately after reset : Fix this bit to “0” (do not write “1”) < Bit allocation> Function bit : No function bit : Fix this bit to “1” (do not write “0”) Name : ??P7D0 0016 0016 000 0 00 OP1OP0 0016 0016 0 0016 0016 P7D1P7D2P7D4 CBR0CBR1 ADC0ADC1ADC2ADC3ADC4ADC5 SIC0SIC1SIC2SIC3SIC4SIC5SIC8SIC7 TMR30 00RC1RC0 0016 0016 0016 0016 ??? ?00 00 20416 20516 20616 20716 20816 20916 20A16 20B16 20C 16 20D 16 20E16 20F16 Timer 5 (T5) Timer 6 (T6) Port control register (P7D) Serial I/O control register (SIC) CRT control register 2 (CBR) CRT clock selection register (OP) A-D control register (ADC) Timer mode register (TMR3)

M37207MF-XXXSP/FP, M37207M8-XXXSP M37207EFSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER and ON-SCREEN DISPLAY CONTROLLER Internal State of Processor Status Register and Program Counter at Reset b7 b0 b7 b0 Register Processor status register (PS) Bit allocation State immediately after reset Program counter (PCH ) Program counter (PCL) Contents of address FFFF16 Contents of address FFFE16 : “0” immediately after reset : Undefined immediately after reset <State immediately after reset> : “1” immediately after reset : Fix this bit to “0” (do not write “1”) < Bit allocation> Function bit : No function bit : Fix this bit to “1” (do not write “0”) Name :

M37207MF-XXXSP/FP, M37207M8-XXXSP M37207EFSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER and ON-SCREEN DISPLAY CONTROLLER Structure of Register The figure of each register structure describes its functions, contents at reset, and attributes as follows: Values immediately after reset release Bit attributes (Note 1) (Note 2)Bits 2: Bit attributes••••••The attributes of control register bits are classified into 3 types : read-only, write-only and read and write. In the figure, these attributes are represented as follows : : Bit in which nothing is assigned Notes 1: Values immediately after reset release ?••••••Indeterminate after reset release cannot be set. b7b6 b5b4b3 b2b1b0 B After resetRW CPU Mode Register 0, 1 3, 4 Name Functions Processor mode bits (CM0, CM1) 0 0: Single-chip mode 0 1: 1 0: Not available 1 1: Fix these bits to “1.” 0Stack page selection bit (Note) (CM2) b1 b0 0: 0 page 1: 1 page 10 0 5 Nothing is assigned. This bit is write disable bit. When this bit is read out, the value is “0.” 6, 7 0Clock switch bits (CM6, CM7) 0 0: f(XIN) = 8 MHz 0 1: f(XIN) = 12 MHz 1 0: f(XIN) = 16 MHz 1 1: Do not set b7 b6 CPU mode register (CPUM) (CM) [Address FB16] RW RW RW RW RW [Example]

M37207MF-XXXSP/FP, M37207M8-XXXSP M37207EFSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER and ON-SCREEN DISPLAY CONTROLLER Port Pi Direction Register Port P3 Direction Register Addresses 00C116, 00C316, 00C516, 00CD16 Address 00C716 b7 b6 b5 b4 b3 b2 b1 b0 Port Pi direction register (Di) (i=0,1,2, 6) [Addresses 00C116, 00C3 16, 00C516, 00CD16] B Name Functions After resetR W Port Pi Direction Register 0 0 : Port Pi 0 input mode 1 : Port Pi0 output mode 1 0 : Port Pi1 input mode 1 : Port Pi1 output mode 2 0 : Port Pi2 input mode 1 : Port Pi2 output mode 3 0 : Port Pi 3 input mode 1 : Port Pi3 output mode 4 0 : Port Pi 4 input mode 1 : Port Pi4 output mode 5 0 : Port Pi 5 input mode 1 : Port Pi5 output mode 6 0 : Port Pi 6 input mode 1 : Port Pi6 output mode 7 0 : Port Pi7 input mode 1 : Port Pi7 output mode Port Pi direction register RW RW RW RW RW RW RW RW b7 b6 b5 b4 b3 b2 b1 b0 Port P3 direction register (D3) [Address 00C716] B Name Functions After resetRW Port P3 Direction Register 0 0 : Port P3 0 input mode 1 : Port P30 output mode 1 0 : Port P31 input mode 1 : Port P31 output mode 2 0 : Port P3 2 input mode 1 : Port P32 output mode Port P3 direction register Nothing is assigned. This bit is a write disable bit. When this bit is read out, the value is “0.” RW RW RW 3 0 : Port P33 input mode 1 : Port P33 output mode 0R W 6 0R W 0 : Port P34 input mode 1 : Port P34 output mode 0R W 0 : Port P35 input mode 1 : Port P35 output mode 0R W 0 : Port P36 input mode 1 : Port P36 output mode

M37207MF-XXXSP/FP, M37207M8-XXXSP M37207EFSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER and ON-SCREEN DISPLAY CONTROLLER Port P5 Control Register PWM Output Control Register 1 Address 00CB 16 Address 00D516 b7 b6 b5 b4 b3 b2 b1 b0 Port P5 control register (D5) [Address 00CB16] B Name Functions After resetR W Port P5 Control Register 3 0 : G signal output 1 : Port P53 output RW RW RW 0, 1, Port P53 output signal selection bit (G) 4 0 : B signal output 1 : Port P54 output 0R WPort P54 output signal selection bit (B) 0R W 0 : R signal output 1 : Port P52 output Port P52 output signal selection bit (R) 5 0 : I/TIM1 OVERFLOW signal output 1 : Port P55 output Port P55 output signal selection bit (I) 6 0 : OUT signal output 1 : Port P56 output Port P56 output signal selection bit (OUT) Nothing is assigned. These bits are write disable bits. When these bits are read out, the values are “0.” b7b6 b5b4b3 b2b1b0 PWM output control register 1 (PW) [Address 00D5 B After resetRW PWM Output Control Register 1 Name Functions DA, PWM count source selection bit (PW0) 0 : Count source supply 1 : Count source stop P60/PWM0 output selection bit (PW2) 0: P60 output 1: PWM0 output P61/PWM1 output selection bit (PW3) 0: P61 output 1: PWM1 output P62/PWM2 output selection bit (PW4) 0: P62 output 1: PWM2 output selection bit (PW5) 0: P63 output 1: PWM3 output selection bit (PW6) 0: P64 output 1: PWM4 output DA/PN4 output selection bit (PW1) 0 : DA output 1 : PN4 output selection bit (PW7) 0: P65 output 1: PWM5 output 16] RW RW RW RW RW RW RW RW

M37207MF-XXXSP/FP, M37207M8-XXXSP M37207EFSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER and ON-SCREEN DISPLAY CONTROLLER Interrupt Interval Determination Control Register Address 00D616 Address 00D816 PWM Output Control Register b7b6 b5b4b3 b2b1b0 PWM output control register 2 (PN) [Address 00D6 B After resetRW PWM Output Control Register 2 Name Functions 16] DA output polarity selection bit (PN3) 0 : Positive polarity 1 : Negative polarity PWM output polarity selection bit (PN4) DA general-purpose output bit (PN5) 0 : Output LOW 1 : Output HIGH to 0Nothing is assigned. These bits are write disable bits. When these bits are read out, the values are “0.” 0 : Positive polarity 1 : Negative polarity RW RW RW selection bit (PN0) 0 : P66 output 1 : PWM6 output 0R W selection bit (PN1) 0 : P67 output 1 : PWM7 output 0R W b7 b6 b5 b4 b3 b2 b1 b0 interrupt interval determination control register (RE) [Address 00D816] B Name Functions After resetR W Interrupt Interval Determination Control Register operation control bit (RE0) 0 : Stopped 1 : Operating bit (RE1) 0 : 16 ms 1 : 32 ms (at f(XIN) = 8 MHz) pin selection bit (RE2) 0 : INT1 input 1 : INT2 input switch bit (RE3) 0 : Positive polarity input 1 : Negative polarity input switch bit (RE4) 0 : Positive polarity input 1 : Negative polarity input to RW RW RW RW RW R—Nothing is assigned. These bits are write disable bits. When these bits are read out, the values are “0.”

M37207MF-XXXSP/FP, M37207M8-XXXSP M37207EFSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER and ON-SCREEN DISPLAY CONTROLLER I2C Adress Register I2C Data Shift Register Address 00D916 Address 00DA16 b7 b6 b5 b4 b3 b2 b1 b0 I C data shift register1(S0) [Address 00D916] B Functions After reset R W I C Data Shift Register to This is an 8-bit shift register to store receive data and write transmit data. Indeterminate Note: 2 To write data into the I C data shift register after setting the MST bit to “0” (slave mode), keep an interval of 8 machine cycles or more. Name D0 to D7 RW b7 b6 b5 b4 b3 b2 b1 b0 (RBW) to Slave address (SAD0 to SAD6) 0: Read 1: Write 0The address data transmitted from the master is compared with the contents of these bits. I2C Address Register I2C address register (S0D) [Address 00DA16] B Name Functions After resetRW RW

M37207MF-XXXSP/FP, M37207M8-XXXSP M37207EFSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER and ON-SCREEN DISPLAY CONTROLLER I2C Control Register I2C Status Register Address 00DC 16 Address 00DB 16 b7 b6 b5 b4 b3 b2 b1 b0 I2C status register (S1) [Address 00DB16] I2C Status Register 6, 7 b7 b6 0 0 : Slave recieve mode 0 1 : Slave transmit mode 1 0 : Master recieve mode 1 1 : Master transmit mode B Name Functions After resetRW Communication mode specification bits (TRX, MST) 0 : Bus free 1 : Bus busy Bus busy flag (BB) 0 : Interrupt request issued 1 : No interrupt request issued I 2C-BUS interface interrupt request bit (PIN) 0 : Not detected 1 : Detected Arbitration lost detecting flag (AL) (See note) 0 : Address mismatch 1 : Address match Slave address comparison flag (AAS) (See note) 0 : No general call detected 1 : General call detected General call detecting flag (AD0) (See note) 0 : Last bit = “0 ” 1 : Last bit = “1 ” Last receive bit (LRB) (See note) Note : These bits and flags can be read out, but cannnot be written. IndeterminateR— RW 0 RW b7 b6 b5 b4 b3 b2 b1 b0 to Bit counter (Number of transmit/recieve bits) (BC0 to BC2) b2 b1 b0 0 0 0 : 8 0 0 1 : 7 0 1 0 : 6 0 1 1 : 5 1 0 0 : 4 1 0 1 : 3 1 1 0 : 2 1 1 1 : 1 enable bit (ESO) 0 : Disabled 1 : Enabled (ALS) 0 : Addressing mode 1 : Free data format bit (10BIT SAD) 0 : 7-bit addressing format 1 : 10-bit addressing format 6, 7 Connection control bits between I C-BUS interface and ports b7 b6 Connection port (See note) 0 0 : None 0 1 : SCL1, SDA1 1 0 : SCL2, SDA2 1 1 : SCL1, SDA1 SCL2, SDA2 I 2C control register (S1D : address 00DC16) I2C Control Register B Name Functions After resetRW Note: When using ports P11-P14 as I C-BUS interface, the output structure changes automatically from CMOS output to N-channel open-drain output. RW RW RW RW RW

M37207MF-XXXSP/FP, M37207M8-XXXSP M37207EFSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER and ON-SCREEN DISPLAY CONTROLLER Serial I/O Mode Register I2C Clock Control Register Address 00DD 16 Address 00DE16 b7 b6 b5 b4 b3 b2 b1 b0 I2C clock control register (S2 : address 00DD16) I2C Clock Control Register to SCL frequency control bits (CCR0 to CCR4) SCL mode specification bit (FAST MODE) 0 : Standard clock mode 1 : High-speed clock mode 0Standard clock mode B Name Functions After resetRW ACK bit (ACK BIT) ACK clock bit (ACK) 0 : ACK is returned. 1 : ACK is not returned. 0 : No ACK clock 1 : ACK clock High speed clock mode Setup disabled Setup disabled00 to 02 Setup disabled 33303 Setup disabled 25004 100 400 (See note)05 83.3 16606 500/CCR value 1000/CCR value ... 17.2 34.51D 16.6 33.31E 16.1 32.31F (at f = 4 MHz, unit : kHz) Note: At 400 kHz in the high-speed clock mode, the duty is as below . “0” period : “1” period = 3 : 2 In the other cases, the duty is as below. “0” period : “1” period = 1 : 1 Setup value of CCR4–CCR0 RW RW RW RW b7b6 b5b4b3 b2b1b0 Serial I/O mode register (SM) [Address 00DE16] B Name Functions After resetRW Serial I/O Mode Register 0, 1Internal synchronous clock selection bits (SM0, SM1) (See note 1) b1 b0 0 0: f(XIN)/4 or f(XCIN)/4 0 1: f(XIN)/16 or f(XCIN)/16 1 0: f(XIN)/32 or f(XCIN)/32 1 1: f(XIN)/64 or f(XCIN)/64 selection bit (SM2) 3, 7Ports P40, P41 function selection bits (SM3, SM7) P40/SOUT2 / SDA3/X CIN P40 SOUT2 SDA3 0: External clock 1: Internal clock 0 RW RW RW 4, 6Ports P42, P43 function selection bits (SM4, SM6) selection bit (SM5) 0: LSB first 1: MSB first 0R W P41/SCLK2 / SCL3/X COUT P41 SCLK2 SCL3 P4 2/SIN2/ SDA2/AD8 P42 SDA2 P42 SDA2 0R WP43/SRDY2 / SCL2/AD7 P43 SRDY2 SDA2 Notes 1: Either f(XIN) or f(XCIN) is selected by bit 7 of the CPU mode register. 2: When using ports P40–P4 3 as serial I/O pins, set bit 1 of the serial control register to “1.” (See note 2) (See note 2)

M37207MF-XXXSP/FP, M37207M8-XXXSP M37207EFSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER and ON-SCREEN DISPLAY CONTROLLER Vertical Position Register i Horizontal Position Register Addresses 00E116, 00E316 Address 00E016 b7 b6 b5 b4 b3 b2 b1 b0 Horizontal position register (HR) [Address 00E016] B Name Functions After resetRW Horizontal Position Register 0to Horizontal display start positions (HR0 to HR5) 64 steps (0016 to 3F16) 0 0Nothing is assigned. This bit is a write disable bit. When this bit is read out, the value is “0.” RW 7 0Fix this bit to “0.” R W b7 b6 b5 b4 b3 b2 b1 b0 Vertical position register i (CVi) (i = 1 to 3) [Addresses 00E116 to 00E316] B Name Functions After reset R W Vertical Position Register i to Vertical display start positions128 steps (0016 to 7F16) Indeterminate (CVi : CVi0 to CVi6) Nothing is assigned. This bit is a write disable bit. When this bit is read out, the value is “0.” RW

M37207MF-XXXSP/FP, M37207M8-XXXSP M37207EFSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER and ON-SCREEN DISPLAY CONTROLLER Border Selection Register Character Size Register Address 00E416 Address 00E516 b7 b6 b5 b4 b3 b2 b1 b0 Character size register (CS) [Address 00E416] B Name Functions After resetR W Character Size Register 0, 1 Character size of block 1 selection bits (CS10, CS11) b1 b0 0 0 : Minimum size 0 1 : Medium size 1 0 : Large size 1 1 : Extra large size Indeterminate 2, 3 Character size of block 2 selection bits (CS20, CS21) Indeterminate RW RW 6 IndeterminateNothing is assigned. This bit is a write disable bit. When this bit is read out, the value is indeterminate. 4, 5 Character size of block 2 selection bits (CS30, CS31) IndeterminateRW (CS7) 0 : OUT signal output 1 : MUTE signal output (See note) IndeterminateRW Note: This erases a video signal on an entire screen. b3 b2 0 0 : Minimum size 0 1 : Medium size 1 0 : Large size 1 1 : Extra large size b5 b4 0 0 : Minimum size 0 1 : Medium size 1 0 : Large size 1 1 : Extra large size b7 b6 b5 b4 b3 b2 b1 b0 Border selection register (MD) [Address 00E516] B Name Functions After resetR W Border Selection Register border selection bit (MD10) 0 : Same output as character output 1 : Border output Indeterminate border selection bit (MD20) 0 : Same output as character output 1 : Border output Indeterminate RW RW RW 06, 7 Nothing is assigned. These bits are write disable bits. When these bits are read out, the values are “0.” Block 1 OUT output switch bit (MD11) 0 : Border including character 1 : Border only switch bit (MD21) 0 : Border including character 1 : Border only border selection bit (MD30) 0 : Same output as character output 1 : Border output IndeterminateRW switch bit (MD31) 0 : Border including character 1 : Border only

M37207MF-XXXSP/FP, M37207M8-XXXSP M37207EFSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER and ON-SCREEN DISPLAY CONTROLLER b7 b6 b5 b4 b3 b2 b1 b0 CRT control register 1 (CC) [Address 00EA16] B Name Functions After resetR W CRT Control Register 1 bit (CC0) (See note) 0 : All-blocks display off 1 : All-blocks display on (CC1) 0 : Block 1 display off 1 : Block 1 display on 2 0 : Block 2 display off 1 : Block 2 display on 0Block 2 display control bit (CC2) RW RW RW 7 0 Note: Display is controlled by logical product (AND) between the all-blocks display control bit and each block control bit. Fix this bit to “0.” R W 3 0 : Block 3 display off 1 : Block 3 display on 0Block 3 display control bit (CC3) RW 4 0 : Ordinary mode 1 : 1/2-character unit color specification mode 0Block 1 color specification mode switch bit (CC4) RW 5 0 : Oscillation stopped 1 : Oscillation enabled 0Display oscillation stop bit (CC5) RW 6 0 : Ordinary 256 count mode 1 : Double count mode 0Scanning line double count mode flag(CC6) RW CRT Contol Register 1 Color Register n Address 00EA16 Addresses 00E616, 00E916 b7 b6 b5 b4 b3 b2 b1 b0 Color register n (CO0 to CO3) (n = 0 to 3) [Addresses 00E616 to 00E916] B Name Functions After resetR W Color Register n 0 0 selection bit (COn1) 0 : No character is output 1 : Character is output selection bit (COn2) 0 : No character is output 1 : Character is output selection bit (COn3) 0 : No character is output 1 : Character is output selection bit (COn4) 0 : No background color is output 1 : Background color is output control bit (COn5) 0 : Character is output 1 : Blank is output selection bit (COn6) 0 : No background color is output 1 : Background color is output selection bit (COn7) 0 : No background color is output 1 : Background color is output (See notes 1,2) (See notes 1, 2) Notes 1: When bit 5 = “0” and bit 4 = “1,” there is output same as a character or border output from the OUT pin. 2: When bit 5 = “0” and bit 4= “0,” there is no output from the OUT pin. RW RW RW RW RW RW RW RW I signal output selection bit (COn0) 0 : No character is output 1 : Character is output

M37207MF-XXXSP/FP, M37207M8-XXXSP M37207EFSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER and ON-SCREEN DISPLAY CONTROLLER CRT Port Control Register Display Block Counter Address 00EB16 Address 00EC16 b7 b6 b5 b4 b3 b2 b1 b0 Display block counter (CBC) [Address 00EB16] B Name Functions After resetR W Display Block Counter to Number of blocks which are being displayed or has displayed (Incremented each time a block is displayed) IndeterminateRW 0Nothing is assigned. These bits are write disable bits. When these bits are read out, the values are “0.” R—4 to b7 b6 b5 b4 b3 b2 b1 b0 CRT port control register (CRTP) [Address 00EC16] B Name Functions After resetR W CRT Port Control Register 0H SYNC input polarity switch bit (HSYC) 0 : Positive polarity 1 : Negative polarity 1 0 : Positive polarity 1 : Negative polarity switch bit (R/G/B) 0 : Positive polarity 1 : Negative polarity (I) 0 : Positive polarity 1 : Negative polarity switch bit (OUT) 0 : Positive polarity 1 : Negative polarity (R) 0 : R signal output 1 : MUTE signal output (G) 0 : G signal output 1 : MUTE signal output (B) 0 : B signal output 1 : MUTE signal output VSYNC input polarity switch bit (VSYC) RW RW RW RW RW RW RW RW

M37207MF-XXXSP/FP, M37207M8-XXXSP M37207EFSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER and ON-SCREEN DISPLAY CONTROLLER A-D Control Register 1 Wipe Mode Register Address 00ED16 Address 00EF16 b7 b6 b5 b4 b3 b2 b1 b0 Wipe mode register (SL) [Address 00ED16] B Name Functions After resetR W Wipe Mode Register 0, 1 Wipe mode selection bits (SL0, SL1) b1 b0 0 0 : Wipe is not available 0 1 : Mode 1 1 0 : Mode 2 1 1 : Mode 3 bits (SL2) RW RW 7 0Nothing is assigned. This bit is a write disable bit. When this bit is read out, the value is indeterminate. 3, 4 Wipe unit selection bits (SL3, SL4) 0 RW 0: DOWN mode 1: UP mode b4 b3 0 0 : 1H unit 0 1 : 2H unit 1 0 : 3H unit 1 1 : Do not set 5, 6 Stop mode selection bits (SL5, SL6) 0 0 : Stop at the 312nd H 0 1 : Stop at the 156th H 1 0 : Stop at the 256th H 1 1 : Stop at the 128th H b7 b6 b5 b4 b3 b2 b1 b0 A-D control register 1 (ADM) [Address 00EF16] B After resetRW A-D Control Register 1 to Analog input pin selection bits (ADM0 to ADM2) Name Functions b2 b1 b0 0 0 0 : AD1 0 0 1 : AD2 0 1 0 : AD3 0 1 1 : AD4 1 0 0 : AD5 1 0 1 : AD6 1 1 0 : AD7 1 1 1 : AD8 result (ADM4) Input voltage < reference voltage 1: Input voltage > reference voltage Indeterminate 03, 5 to 7 Nothing is assigned. These bits are write disable bits. When these bits are read out, the values are “0.” RW

M37207MF-XXXSP/FP, M37207M8-XXXSP M37207EFSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER and ON-SCREEN DISPLAY CONTROLLER Timer Mode Register 2 Timer Mode Register 1 Address 00F416 Address 00F516 b7b6 b5b4b3 b2b1b0 Timer mode register 1 (TMR1) [Address 00F416] B After reset W Timer Mode Register 1 Name Functions Timer 1 count source selection bit 1 (TMR10, TMR15) b5 b0 0 0: f(XIN)/16 or f(XCIN)/16 (See note) 0 1: f(XIN)/4096 or f(XCIN)/4096 (See note) 1 0: f(XcIN) 1 1: External clock from TIM2 pin Timer 2 count source selection bit 1 (TMR11) Count source selected by bit 4 of TM1 1: External clock from TIM2 pin Timer 1 count stop bit (TMR12) 0: Count start 1: Count stop Timer 2 count stop bit (TMR13) 0: Count start 1: Count stop Timer 2 count source selection bit 2 (TMR14) R WR WR WR WR WR0: f(XIN)/16 or f(XCIN)/16 (See note) 1: Timer 1 overflow selection bit 2 (TMR16) 0: Timer 2 overflow 1: Timer 4 overflow 0W R (TMR17) 0W R 0: f(XIN)/16 or f(XCIN)/16 (See note) 1: Timer 5 overflow Note: Either f(XIN) or f(XCIN) is selected by bit 7 of the CPU mode register. b7b6 b5b4b3 b2b1b0 Timer mode register 2 (TMR2) [Address 00F516] B After resetRW Timer Mode Register 2 Name Functions Timer 3 count source selection bit (TMR20) 0 RW (TMR21) 0R W Timer 3 count stop bit (TMR22) 0: Count start 1: Count stop Timer 4 count stop bit (TMR23) 0: Count start 1: Count stop (TMR25) 0: Count start 1: Count stop (TMR26) 0: Count start 1: Count stop RW RW RW RW RW7 Timer 5 count source selection bit 1 (TMR27) 0: Count source selected by bit 0 of TMR3 1: Count source selected by bit 6 of TMR1 0 : f(XIN)/16 or f(XCIN)/16 (See note) 1 : External clock from TIM3 pin 0 : Timer 3 overflow signal 1 : f(XIN)/16 or f(XCIN)/16 (See note) Note: Either f(XIN) or f(XCIN) is selected by bit 7 of the CPU mode register. (TMR24) 0R W0: Count source selected by bit 1 of TMR2 1 : f(XIN)/2 or f(XCIN)/2 (See note)

M37207MF-XXXSP/FP, M37207M8-XXXSP M37207EFSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER and ON-SCREEN DISPLAY CONTROLLER CPU Mode Register Address 00FB16 b7b6 b5b4b3 b2b1b0 B After resetRW CPU Mode Register 0, 1 Name Functions Processor mode bits (CM0, CM1) 0 0: Single-chip mode 0 1: 1 0: Not available 1 1: Fix these bits to “1.” 1Stack page selection bit (CM2) (See note 1) b1 b0 0: 0 page 1: 1 page

6 Main Clock (XIN–XOUT )

(CM6) RW RW XCOUT drivability selection bit (CM5) 0: LOW drive 1: HIGH drive 0: Oscillating 1: Stopped

7 Internal system clock

(CM7) RW0: X IN–XOUT selected (high-speed mode) 1: XCIN–XCOUT selected (high-speed mode) Notes 1: This bit is set to “1” after the reset release. 2: The internal system clock f stops at HIGH.

4 Internal system clock

(CM4) (See note 2) 0: Output is stopped 1: Internal system clock f output RW

M37207MF-XXXSP/FP, M37207M8-XXXSP M37207EFSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER and ON-SCREEN DISPLAY CONTROLLER Interrupt Reguest Register 2 Interrupt Reguest Register 1 Address 00FC16 Address 00FD16 b7b6 b5b4b3 b2b1b0 Interrupt request register 1 (IREQ1) [Address 00FC B Name Functions After resetRW Interrupt Request Register 1 0 0 : No interrupt request issued 1 : Interrupt request issued Timer 1 interrupt request bit (TM1R) request bit (TM2R) request bit (TM3R) request bit (TM4R) request bit (CRTR) 5V SYNC interrupt request bit (VSCR) 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 ] 0 ] 0 ] 0 ] 0 ] 0 ] Multi-master I2C-BUS interface interrupt request bit (IICR) 0 : No interrupt request issued 1 : Interrupt request issued 16] R R R R R R R 7 Nothing is assigned. This bit is a write disable bit. When this bit is read out, the value is “0.” —R0 b7b6 b5b4b3 b2b1b0 Interrupt request register 2 (IREQ2) [Address 00FD B Name Functions After resetRW Interrupt Request Register 2 request bit (ITIR) 0 : No interrupt request issued 1 : Interrupt request issued request bit (IT2R) request bit (SIR) 4 f(XIN)/4096 interrupt request bit (MSR) 3,6 Nothing is assigned. These bits are write disable bits. When these bits are read out, the values are “0.” 7 Fix this bit to “0.” 0 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued ] : “0” can be set by software, but “1” cannot be set. 0 ] 0 ] 0 ] 0 ] 0 : No interrupt request issued 1 : Interrupt request issued 16] R R R R RW request bit (TM56R) 0 : No interrupt request issued 1 : Interrupt request issued 0 ]R

M37207MF-XXXSP/FP, M37207M8-XXXSP M37207EFSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER and ON-SCREEN DISPLAY CONTROLLER Interrupt Control Register 2 Interrupt Control Register 1 Address 00FE16 Address 00FF16 b7b6 b5b4b3 b2b1b0 Interrupt control register 1 (ICON1) [Address 00FE16] B Name Functions After resetRW Interrupt Control Register 1 enable bit (TM1E) 0 : Interrupt disabled 1 : Interrupt enabled enable bit (TM2E) enable bit (TM3E) bit (CRTE) 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 RW RW RW RW RW R R Timer 4 interrupt enable bit (TM4E) 0 : Interrupt disabled 1 : Interrupt enabled bit (VSCE) 0 : Interrupt disabled 1 : Interrupt enabled 0R W Multi-master I2C-BUS interface interrupt enable bit (IICE) 0 : Interrupt disabled 1 : Interrupt enabled W —Nothing is assigned. This bit is a write disable bit. When this bit is read out, the value is “0.” b7b6 b5b4b3 b2b1b0 Interrupt control register 2 (ICON2) [Address 00FF16] B Name Functions After resetRW Interrupt Control Register 2 enable bit (IT1E) 0 : Interrupt disabled 1 : Interrupt enabled bit (IT2E) enable bit (SIE) 3, 6Fix these bits to “0.” 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 0 RW RW RW RW 4 f(XIN)/4096 interrupt enable bit (MSE) 0 : Interrupt disabled 1 : Interrupt enabled 0R W enable bit (TM56E) 0 : Interrupt disabled 1 : Interrupt enabled 0R W switch bit (TM56C) 0 : Timer 5 1 : Timer 6 0R W

M37207MF-XXXSP/FP, M37207M8-XXXSP M37207EFSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER and ON-SCREEN DISPLAY CONTROLLER Serial I/O Control Register Port Control Register Address 020616 Address 020716 b7 b6 b5 b4 b3 b2 b1 b0 Port control register (P7D) [Address 020616] B Name Functions After resetR W Port Control Register 0, 1 Port P7 data input bits (P7D0, P7D1) When only OP1 = “0” and OP0 = ”1,” input data is valid. (See note) Indeterminate bit (P7D2) RW RW 0Nothing is assigned. These bits are write disable bits. When these bits are read out, the values are indeterminate. 4P 4 0/XCIN, P41/XCOUT function selection bit (P7D4) 0 : P4 0, P41 1 : XCIN, XCOUT 0 RW Note: OP is the CRT clock selection register. 0: AD3 1: D-A 5 to 7 b7b6 b5b4b3 b2b1b0 Serial I/O control register (SIC) [Address 020716] B Name Functions After resetRW Serial I/O Control Register (SIC0) CSIO b0 0 0: Input signal from SIN1 0 1: Input signal from SOUT1 (See note 1) 1 0: Input signal from SIN2 1 1: Input signal from SOUT2 (See note 1) bit (CSIO) 0: SOUT1 ,SCLK1 , SIN1, SRDY1 1: SOUT2 ,SCLK2 , SIN2, SRDY2 0 RW RW Notes 1: When inputting data from the Sout pin, set “FF16” to the serial I/O register. 2: When using ports P44–P4 7 as serial I/O pins, set bit 1 of the serial I/O control register to “0.” 3, 7Ports P47 function selection bits (SM3, SM7) (See note 2) P4 7/SRDY1 /PWM8 P47 SRDY1 PWM8 0R W 4, 5Ports P44, P45 function selection bits (SM4, SM6) (See note 2) (SIC6) (See note 2) P44/SOUT1 / SDA1 P44 SOUT1 SDA1 0R WP45/SCLK1 / SCL1 P45 SCLK1 SCL1 P4 6/SIN1/PWM9 P4 6 PWM9 0R Wb6 (SIC2) 0: SDA2, SCL2, SDA1, SCL1 1: SDA3, SCL3 0R W

M37207MF-XXXSP/FP, M37207M8-XXXSP M37207EFSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER and ON-SCREEN DISPLAY CONTROLLER CRT Clock Selection Register CRT Control Register 2 Address 020816 Address 020916 b7 b6 b5 b4 b3 b2 b1 b0 CRT control register 2 (CBR) [Address 020816] B Name Functions After resetR W CRT Control Register 2 (CBR0) 0: I signal output 1: MUTE signal output (CBR1) RW RW 0Nothing is assigned. These bits are write disable bits. When these bits are read out, the values are indeterminate. 0: I output or MUTE output 1: 1/2 clock ouput of timer 1 to b7 b6 b5 b4 b3 b2 b1 b0 CRT clock selection register (OP) [Address 020916] B Name Functions After reset R W CRT Clock Selection Register 0, 1 CRT clock selection bits (OP0, OP1) Since the main clock is used as the clock for display, the oscillation frequency is limited. Because of this, the character size in width (horizontal) direction is also limited. In this case, pins OSC1 and OSC2 are also used as input ports P70 and P71 respectively. The clock for display is supplied by connecting the following across the pins OSC1 and OSC2.

• a ceramic resonator only for CRT display and a feedback resistor
• a quartz-crystal oscillator only for CRT display and a feedback resistor (See note) to The clock for display is supplied by connecting RC or LC across the pins OSC1 and OSC2. Functions CRT oscillation frequency = f(XIN) Notes 1: It is necessary to connect other ceramic resonator or quartz-crystal oscillator across the pins XIN and XOUT . 2: CC6 is the scnanning line double count mode flag. 0 1 RW CC6 CC6 = “0” or “1” CC6 = “0” CC6 = “0” 1 0— Do not set. 7 0Fix this bits to “0.” RW Nothing is assigned. These bits are write disable bits. When these bits are read out, the values are “0.”

M37207MF-XXXSP/FP, M37207M8-XXXSP M37207EFSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER and ON-SCREEN DISPLAY CONTROLLER Timer Mode Register 3 A-D Control Register 2 Address 020A16 Address 020B16 b7 b6 b5 b4 b3 b2 b1 b0 A-D control register 2(ADC) [Address 020A16] B After reset RW A-D Control Register 2 to 6, 7 Indeterminate Name Functions D-A converter set bits (ADC0 to ADC5) b0b1b2 b3 b4 b5 Nothing is assigned. These bits are write disable bits. When these bits are reed out, the values are “ 0.” 000000 00000 0000 111 11111 111111 : 3/128Vcc : 5/128Vcc : 123/128Vcc : 125/128Vcc : 127/128Vcc : 1/128Vcc RW b7b6 b5b4b3 b2b1b0 Timer mode register 3 (TMR3) [Address 020B16] B After resetRW Timer Mode Register 3 Name Functions Timer 5 count source selection bit 3 (TMR30) 0R W 0R — 0 : f(XIN)/16 or f(XCIN)/16 (See note) 1 : f(XCIN) Note: Either f(XIN) or f(XCIN) is selected by bit 7 of the CPU mode register. to Nothing is assigned. These bits are write disable bits. When these bits are read out, the values are “0.”

M37207MF-XXXSP/FP, M37207M8-XXXSP M37207EFSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER and ON-SCREEN DISPLAY CONTROLLER ROM Correction Enable Register Address 021B16 b7 b6 b5 b4 b3 b2 b1 b0 ROM correction enable register (RCR) [Address 021B16] B After resetRW ROM Correction Enable Register 0: Disabled 1: Enabled 1: Enabled to Nothing is assigned. These bits are write disable bits. When these bits are read out, the values are “0.” RW RW 2, 3 Fix these bits to“0.” 0 RW

© 1997 MITSUBISHI ELECTRIC CORP. New publication, effective Dec. 1997. Specifications subject to change without notice. Notes regarding these materials

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Rev. Rev. No. date

1.0 First Edition 971212

1.1 Correct note (P76) 980731

M37207MF-XXXSP/FP, M37207M8-XXXSP, M37207EFSP/FP DATA SHEET (1/1) Revision Description REVISION DESCRIPTION LIST