M37100M8

M37100M8 MITSUBISHI | Alldatasheet

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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER

DESCRIPTION

The M37100M8-XXXSP/FP is a single-chip microcomputer PIN CONFIGURATION (TOP VIEW) designed with CMOS silicon gate technology. It is housed vec a! in a 64-pin shrink plastic molded DIP or a 80-pin plastic posewas +E oer , povewns ~ B] E--s molded QFP. This single-chip microcomputer is useful for vosed| pews ae the high-tech channel-selection system for TVs and VCRs. | Poy/PwMe2~ ES} [al our In addition to its simple instruction set, the ROM, RAM, and Pevewe ~ [E F~ Heme ' P6o/T +E] [El — Verne 1/0 addresses are placed on the same memory map to en- 2, EH Eq--pay open a able easy programming. | Pa +B] fal ~ Po. 2, +f El- Po, it v0 pen Pas fE~ Po, FEATURES aa mE EP, | v0 en © Memory size ae 2 Boe "25 +» [E] gs => POs ROM esses coeeeteeeeeeieneeess 16384 bytes bot 68 Boe © Instruction execution time | Pds/Soura = x aan | “oss 2s (minimum instructions at 4MHz frequency) vor! Coenen 6S sce, |vopen © Single power supply =r 5VE10% eaycount ~ Ei] cr © Power dissipation normal operation mode | meg 2: ee P39 +*| fet. (at 4MHz frequency, CRT display off): 27.6mW roe enn | © Subroutine nesting “+--+ B6levels (Max.) ps | psa/ints + [l-- Ps, | © Interruptessssessseseeeeeeeeeeeeeeeneeeseneeesess Stypes, Svectors, cNVes Bl BI~P5vS0 | vo poa 4 Rewetinoet RESET ~~] = P5./Soure © 8-bit timers: 3 (2 when used as serial 1/O,) Coctnpt XE EB) esictke | Ps © Programmable 1/0 ports Cleek ewioxt— Xour LB] [a] ~P5,/Srove | (Ports PO, P1, P2, P3, P4, PS, P6)::s--er seen AB Some tmcton Xow > B [BI osc? frig © Serial 1/0 (Bebit) onseeseeeeneeeseseeeessneetnnsceeteenesennneee Sekar -l Foo" seater @ PWM function <--rs-ssscessreceeseeeessnneerseeseeeeesoee | 4ebitX mo B-bitx2 Outline 64P4B © Comparator :ssstssssiesseinsstinseenetessetneeenereeseeesed vese © Generating function for clock input of EAROM 32212 © Two clock generating circuits obeeeee 28 bof (One is for main clock, the other is for clock function) ee TT ttt @ 63-character on screen display function ARPMEFMAANAPEI EE! . nc of = Vere Number of character" 21 charactersX3 lines °2,--G] O O Bx Character configuration ::+++-+++-++++--- 12X16 dots Pe aed Kinds of character ::--1::sssssseeecssssssssseeessssnennseeees 96 Par] ial-+ 0, Paso) l= Po, Horizontal character border function P20] ]- Po, 2, =] Bs] Po, Pas] z Fro, APPLICATION NC $ fs) ++ Po, xc Gj oe TV, VCR P34/Suora >] 8 B5}= Por much Fs ne P34/Soura => Cl x NC Pad Sun = x fale Pty Payad = (a F flr, P2,/COUNT =} 3 ial= Pt, Po, = fal= is Pao fel=- Pi. ne fa} PIs PSyINT, =a] fa) Pe Paylin =] fal Pr NC ial Ps, TEAST ESTES try ote brigtit © bese gaze" gg ez sz Outline 80P6 NC : No connection a % MITSUBISHI 2-153

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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER FUNCTIONS OF M37100M8-XXXSP/FP ‘Number of basic instructions _ 3 ~ Instruction execution time 2us (minimum instructions, at 4MHz frequency) Clock trequency _ ~ [ane Tm eee - Memory sce [fom — tones ” PO vo B-bitX1 (middle-voltage N-channel open drain) PI, P2 vo 8-bitX2 ~ ~ ~ a v0 bax a Pay “V0 T-bitXT — InpwOutput ports (8,6, 8, OUT Output [ 1-biXS (for ORT display function) | Verne. Hsync Input ‘1-bitX2 (for CRT display function) P52, PSs vo 2-bitX1 (can be used as an input for either INTz or INTs) PSs, PSy~PS; vo 5-bitX1 ~ Pb, P6r vo 2ebitXT ” P6.~P6s vo ‘4-bitX1 (middie-voltage N-channel open drain) - Serial 1/0 8-bitX2 ~ Timers B-bit timerX3 (XZ, when used as serial 1/04) ‘Subroutine nesting - ‘SBlevels (max.) Two built-in circuits (externally connected ceramic or quartz crystal Clock generating circuit oscillator), both circuits have oton feedback resistors. ‘ ™ Suppyvetage BvE10% - ] CRT display function ON | 38. 5mW (clock frequency Xw=4MHz, forr=6MHz) : at low-speed operation ‘CRT display function OFF | 0.33mW (clock frequency Xow™=32kKHz) at stop mode . ~__[Nec= 1A (when clock is stopped) 12V (input/output PO, P62~P6s, input RESET, CNVss) Input/Output characteristics | come (PO, P1, P2, P3, P5, P6:~ P6s : N-channel open drain input/ , Output current 0.5mA, —0.5mA (P47 : CMOS input/output, R, G, B, I, OUT, P6o~P6: : CMOS output) Operating temperature range _ =10~706 Device structure ‘CMOS silicon gate process : HTOONE SOP soph pists ded OFF Kinds of character 96 (12X16 dots) a

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER PIN DESCRIPTION Pir | Name tnpul Functions " “mn Output Veo. ‘Supply voltage Power supply inputs 5V+10% to Vcc, and OV to Ves. Vss CNVss | CNVss This ts connect to Ves. RESET | Reset input | Input | To enter the reset state, the reset input pin must be kept at a “L for more than 2us (under normal Veo | | conditions). it more time is needed for the crystal oscillator to stabilize, this “L’ condition should be main. | | | tained for the required time Xw | Clock input Input ‘These are I/O pins of internal clock generating circuit for main clock. To control generating frequency, an - extemal ceramic or a quartz crystal oscillator is connected betwoen the Xw and Xour pins and external Xour —_| Clock output Output | condensers are connected. It an external clock is used, the clock source should be connected to the Xn pin and the Xour pin should be left open. 6 | Timing output Output | This is the timing output pin. In single-chip mode, the output can be controlled by selecting the option Xen Clock input for clock | Input | These are the 1/0 pins of the clock generating cicult forthe clack function. To control generating trequen- function / cy, an external ceramic or a quartz crystal oscillator is connected between the Xciw and Xcour pins and ex- —— ternal condensers are connected, If an extemal clock is used, the clock source should be connected to the Xcour Clock output for clock | Output | Xaw pin and the Xcour pin should be left open. function” P0.~PO; | 1/0 port PO VO | Port POis an8-bit /O port with directional registers allowing each 1/0 bit to be individually programmed as | input or output. At reset, this port is set to input mode. The output structure is middle-voltage N-channel | open drain, Pto~Pty | 1/0 port Pt 10 | Port PI is an 8-bit 1/0 port and has basically the same functions as port PO but the output structure is N-channel open drain. it can be bul in pull-up transister at each pin by selecting the option. P2o~P2; | VO port P2 VO | Port P2is an8-bit /O port and has basically the same functions 9s poet Pt P3p~P3; | 1/0 port P3 vo Port P3 is an 8-bit I/O port and has basically the same functions as port P1. When serial I/O, is used. P3;, Ps, PSs, and P3, work a8 Smova, CLK, Soura, and Sina pins, respectively. P33, works as an analog input for Comparator and Paz works a8 a counter input. PA, VO port 4 VO | Port P4; is an I-bit I/O port and has basically the same functions as port PO, but the output structure is | GMOS output 1, B, G, R,| CRT output ‘Output | This is an 5-bit output pin for CRT display. out The output polarity can be changed by selecting the option. At reset, inactive polarty is selected | The output structure is CMOS output. Heync | Heme input Input | This is the horizontal synchronizing signal input for CRT display. The input polarity can be changed by selecting the option Verne | Vere input Input | This is the vertical synchronizing signal input for CRT display. The input polarity can be changed by select- ing the option P52, P53 | 1/0 port PS VO | These Ports have basically the same functions as port P1, and are in common with interrupt input pins. P5,, ‘These ports have basically the same functions as port P1. When serial |/Og is used, P5;, PSs, PSs and P5, P54~P5; work as Srove, CLKs, Sours and Sma pins, respectively. P6o~P6s | 1/0 port P6 VO | Port P is a 6-bit /O port and has basically the same functions as port PO. The output structure of PBp, PS; is CMOS output and the output structure of PB,~Pés is middle-vottage N-channel open drain. Pf, PB, PBs, PSs, P, PBs can be programmed to function as timer output pin (T), PWM output pins (PWM', PWM2, PWM, PWMS and PWMS), respectively Osci, Clock input for CRT display | Input This is the I/O pins of the clock generating circuit for the CRT display function. 0862 | Clack asputtr CRT dspiy | Output | To control generating frequency, extemal condensers and registers are connected. sw

Figure 1. Addresses C000; to FFFFis are assigned to the duce the object size required. The RAM, I/O port, timer, (special page). By using the special page addressing RAM address area and consist of 320 bytes. page can be called with only 2 bytes, Addresses FFF4,5to during subroutine calls and interrupts.

. SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER its on sone Dishuay ConTRoLten 00D0\\5 [Horizontal position register 00E8,6 [Port PS - 00D1;¢ | Vertical position register of blook 1 _ Q0E91¢ | Port P3 directional register 00D216 | Vertical position register of block 2 QOEA [Pot P4 00D3;¢ | Vertical position register of block 3 O0EB;. | Port P4 directional register 00D41¢ | Color register 0 _ Q0EC;¢ | Port PS _ 00D5;6 { Color register 1 ODED. | Port PS directional register 0006 | Color register 2 OEE: [Port PE 00D71¢ | Color register 3 QOEF 6 | Port P6 directional register 00D8\\5 {CRT control register - 00F0;. | PWM1-H register 00D94¢ | Display block counter _ 00F11, [PWM1-L register OODA;g | Serial 1/0, mode register O0F2;5 | PWM2 register _ 00DB;s | Special mode register 00F3;¢ | PWMS register - 00DC;6 | Serial 1/0, register _ 00F4,_ | PWM4 register 00DD,¢ | Counter 0 _ 00F5, | PWM control register O0DE\\6, O0F6;6 | Serial 1/0, mode register O0DF is O0F7;¢ | Serial 1/0, register 00E0,¢ | Port PO 00F8,¢ | PWMS register 7 Q0Et16 | Port PO directional register 00F9:¢ | PWM output control register Q0E2;¢ | Port P1 _ OOFA,s | Timer 1 00E3j¢ | Port P1 directional register OOF B,5 [Interrupt control register 2 00E4;¢ | Port P2 OOFCig| Timer 2 _ Q0ES5;_ { Port P2 directional register OOFD,¢ | Timer 3 00E7;¢ LA-D control register OOFF1¢ [Timer contro! register Fig. 2 SFR (Special Function Register) memory map ee

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER —_ SSS CENTRAL PROCESSING UNIT (CPU) STACK POINTER (S) The CPU consists of 6 registers and is shown in Figure 3. The stack pointer (S) is an 8-bit register. It is used during subroutine calls and interrupts. ACCUMULATOR (A) When there is an interrupts, the high-order contents of the The 8-bit accumulator (A) is the main register of the micro- program counter is pushed into the address formed by set- computer. Data operations such as data transfer, Input/Out- _ting the high-order eight bits to 00,, and the low-order put, etc., are executed mainly through accumulator. eight bits to the content of the stack pointer. Next the stack pointer is decremented by one and the low-order content INDEX REGISTER X (X) ‘of the program counter is pushed into the address formed The index register X is an 8-bit register. by setting the high-order eight bits to 00;5 and the low- In the index addressing mode, the value of the OPERAND _order eight bits to the content of the stack pointer. Then the added to the contents of the register X, specifies the real _stack pointer is again decremented by one, the content of address. When the T flag in the processor status register is the processor status register is pushed into the address set to “1”, the index register X itself becomes the address _formed by setting the high-order eight bits to 00,5 and the for the second OPERAND. low-order eight bits to the content of the stack pointer, and then the stack pointer is decremented by one once more. INDEX REGISTER Y (Y) The push operation described above is performed auto- The index register Y is an 8-bit register. matically when an interrupt occurs. The RTI instruction is In the index addressing mode, the value of the OPERAND _used to return from an interrupt routine. added to the contents of the register Y specifies the real address. z ° 7 ° Accumulator DEGaaned Processor status register Z 9 Carry flag | | UU Zero flag fa s | Break tlag Fig. 3 Register structure SS MITSUBISHI 2-159 Jee

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER OO rrr When an RTI instruction is executed, control is returned by 4, Decimal mode flag (D) reversing the above operation while incrementing the stack The decimal mode flag is used to define whether addition pointer by one. The PHA instruction is used to push the and subtraction are executed in binary or decimal. If the accumulator because it is not saved automatically. When decimal mode flag is set to “1”, the operations are ex- the PHA instruction is executed, the content of the accumu- _ecuted in decimal, if the flag is set to “0”, the operations lator is pushed into the address formed by setting the high- are executed in binary. Decimal correction is automatically order eight bits to 00;¢ and the low-order eight bits to the executed. The SED and CLD instructions are used to set content of the stack pointer. Then the content of the stack and clear this flag, respectively. pointer is decremented by one. The PLA instruction is used to restore the accumulator. When the PLA instruction is ex- 5, Break Flag (B) ecuted, the stack pointer is incremented by one and the The operation of a BRK instruction is similar to an interrupt. Content of the address formed by setting the high-order The BRK instruction is a non-maskable software interrupt eight bits to 0015 and the low-order eight bits to the content _that is used during program debugging. The break flag can of the stack pointer is stored in the accumulator. The pro- _ be checked only by checking the content of the processor cessor status register is pushed and restored in the same status register (PS) saved during an interrupt. The content manner with the PHP and PLP instructions. With subroutine of the processor status register (PS) is saved after setting calls, only the program counter is pushed. Therefore, regis- _flag B to “1” when the BRK instruction is used as an inter- ters that must be preserved must be pushed by the prog- _rupt. It is cleared to “0” for other interrupts. ram. Use the RTS instruction to return from a subroutine. 6. Index X mode flag (T) PROGRAM COUNTER (PC) When the T flag is “1", operations between memories are The 16-bit program counter consists of two 8-bit registers executed directly without passing through the accumulator PC, and PC,. The program counter is used to indicate the Operations between memories involving the accumulator address of the next instruction to be executed. are executed when the T flag is “0” (i.e., operation results between memories 1 and 2 are stored in the accumulator) PROCESSOR STATUS REGISTER (PS) The address of memory 1 is specified by the contents of The processor status register is composed entirely of flags the index register X, and that of memory 2 is specified by used to indicate the condition of the processor immediately the normal addressing mode. The SET and CLT instructions after an operation. Branch operations can be performed by _are used to set and clear the index X mode flag, respec- testing the Carry flag (C), Zero flag (Z), Overflow flag (V) tively. or the Negative flag (N). Each bit of the register is ex- plained below. 7. Overflow flag (V) The overflow flag functions when one byte is added or sub- 1. Carry flag (C) tracted as a singed binary number. When the result ex- The carry flag contains the carry or borrow generated by ceeds +127 or —128, the overflow flag is set to “1”. When the Arithmetic and Logical operation Unit (ALU) im- the BIT instruction is executed, bit 6 of the memory location mediately after an operation. It also changed by the shift is input to the overflow flag. The overtiow flag is clear by and rotate instructions. The set carry (SEC) and clear carry the CLV instruction and there is no set instruction (CLC) instructions allow direct access for setting and clearing this flag. 8. Negative flag (N) The negative flag is set whenever the result of a data trans- 2. Zero flag (Z) fer or operation is negative (bit 7 is set to “1"), Whenever This flag is used to indicate if the immediate operation _the BIT instruction is executed, bit 7 of the memory location generated a zero result or not. If the result is zero, the zero_is input to the negative flag. There are no instructions for flag will be set to “1”. If the result is not zero, the zero flag directly setting or clearing the negative flag will be set to “0”. 3. Interrupt disable flag (1) This flag is used to disable all interrupts. This is accom- plished by setting the flag to “1”. When an interrupt, this flag is automatically set to “1” to prevent other interrupts from interfering until the current interrupt is compleated. The SEI and CLI instructions are used to set and clear this flag, respectively. eee

INTERRUPTS and 1 of interrupt control register 2. Interrupts are vectored interrupts with priorities shown in register. Table 1. Reset is also included in the table because its op- _ All interrupts except the BRK instruction interrupt have an specified in the vector table. The interrupt request flag is and timer control register. Falling edge active or rising edge active for each of the terrupt request bit can be clear with a program, but not set. and 5 of the PWM control register. Whether the INT; and program. interrupts are to be accepted can be selected by bits 0 est priority. Figure 5 shows interrupts control. Table 1. Interrupt vector address and priority. INT, of GAT display interrupt _ | 2 | _FFFDye, FFFC;. | INT; external interrupt (phase programmable) .

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER __ntn ONSCREEN DISPLAY CONTROLLER 7 _ 0 7 0 CELT [-[ J interrupt controt register 1 [TT TL [oF] tnterupt controt register 2 Td 7 | ! (address OOFE,.) To — (address 00FB,_) i 0 : Interrupt disable 0 : INT, interrupt 1 ‘Interrupt enabled 1! CRT display interrupt | | INT,/serial /Og interrupt request bit a INT,/serial I/Og interrupt selection bit 0 : Interrupt disable 0: INT? interrupt. | 1! Interrupt requested 1! Serial 1/Og interrupt

0 Interrupt cisable

\\ 1! Interuptenabied 7 oO Tne vst vox ierategve ot [YY] nn eter 0 : Interrupt disable — tt (address OOFF,5) 1: Interrupt requested | | |__ sme interupt enn 0 : Interrupt disable 1 J Interrupt enabled | |< Interrupt enabled | L___Fimer 3 interrupt request bit | | L ——- rimer2 interrupt request bit One eee

0 Inerrupt cisabie arene toeae

| Lo -INT,/CRT display interrupt enable bt | 0 “interrupt cisable | J = Interrupt enabled |___wr,onr apy itarupt request it 0 interrupt cise

1 Interupt requested

Fig. 4 Structure of registers related to interrupt mnsrapta ug ——_* 1 BRK warcton =) —~ Interrupt request Fig. 5 Interrupt control To SSSSSSSSSSSSSSSS MITSUBISHI

2162 PRES

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER TIMER . The M37100M8-XXXSP/FP has three timers; timer 1, timer | | Timer contol register 2 and timer 3. | 1 (Address OOF F<) A block diagram of timer 1 through 3 is shown in Figure 7 | | | The count source for timer 1 through 3 can be selected by | rece moe Pe using bit 2, 3 and 4 of the timer control register (address | Ot: Microprocessor mode OOFF,5), as shown in Figure 6. All of the timers are down mn 10 : Not used count timers and have 8-bit latches. When a timer reaches i 11 : Eva-chip mode "0" and the next count pulse is input to a timer, the con- | tents of the reload latch are loaded into the timer. The divi- ~ ter bow source selection Bi sion ratio of the timer is 1/(n+1), where n is the contents 1 Timer 3 overtiow of timer latch. The timer interrupt request bit which is in the interrupt con- | Timer 2 count source selection bit trol register 1 or timer control register (located at addres- | 0: $ divided by 4 ses OOFE;s and OOFFy, respectively) is set at the next | | 1 Clock forthe clock function (Xow) count pulse after the timer reaches “0” (see interrupt | timer 3 count source selection bit (Note) section). 0 : Timer 2 overflow The starting and stopping of timer 2 is controlled by bit 5 of 1:3, port input the timer control register. If the bit 5 is “0”, the timer starts counting, and the bit 5 is “1”, the timer stops | ~ Ter anne bre At a reset or stop mode, FFs is automatically set in timer 2 1S Gount stop and 0746 in timer 3 After a STP instruction is executed, timer 3, timer 2, and the ~ Timer 3 interrupt enable bit clock (¢ divided by 4) are connected in series (regardless 0 = Interrupt disable of the status of bit 2 through 4 of the timer control register) 1 Interrupt enabled This state is canceled if timer 3 interrupt request bit is set — Timer interrupt request bt to “1”, or if the system is reset. Before the STP instruction 0 ¢ Interrupt disable is executed, bit 5 of the timer control register (timer 2 1 : Interrupt requested count stop bit) must be set to “0” Note : In case that P3, port input is selected as the timer 3 count For more details on the STP instruction, refer to the oscilla- source, the counter is decreased at a rising edge of input tion circuit section. signal, Fig. 6 Structure of timer control register eS

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER Data bus O Timer 2 latch Reset Xen (8) ‘STP instruction Xin TMs internal lock $ (Normally Xm divided by 4)| | | Timer 3 latch (8) O76 L 7 —- ro > rimer 3 tert request bit pd ™ a | j Timer 1 latch (8) ste Tener 1 oF serial 0, iterupt D 7 request bi | | | PG, latch oo — | PCo/T SM. A _olKs pote sie | PB i | L\\. [Ssncreonos (.) Sera /O, counter _ (3) sth SM: Soura | TM =: Timer control register Pas | | SM _: Serial I/O, mode register ‘SM> | PM : PWM output mode register osm mse | — Serial 1/0, oe Select gate ba. register (8) at reset, shaded side is connected. f—SM3 ose ‘ Ps Fig. 7 Block diagram of timer 1 through 3 2-164 fe MTsvEsH ELECTRIC

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER SERIAL V/O spectively. The serial I/O, mode register (address 00F6,.) M37100M8-XXXSP/FP has two serial I/O (serial I/O, and —_is an 8-bit register. Bit 0 and 1 of this register is used to serial |/Og). select a synchronous clock source. When these bits are (00) or (01), an external clock from P3, is selected. When SERIAL VO, these bits are (10), the overflow signal divided by two from The block diagram of serial I/O, is shown in Figure 8. In __ timer 1 becomes the synchronous clock. Therefore, chang- the serial I/O, mode the receive ready signal (Spoya), syn- ing the timer period will change the transfer speed. When chronous input/output clock (CLK,), and the serial 1/O, the bits are (11), the internal clock ¢ divided by 4 becom- (Sours: Swa) pins are used as P3;, PSs, P3s, and PG, re- _es the clock, Of _ oiviaer Xn | 4 # divided by 4 Xe from internal clock # (Address OOFA;.) | | Prescaler totimer t or aD oo serial /O, interrupt bit fo'pg pT ay (LEK i oe | OC A, Sowa “ae | P35 qJ a mil ———— Serial |/O, mode register (Address 00°65) Internal system clock generation selection ———! | Synchronous clock selection bit 0 : Xin-Xour selection (normal mode) oo: 1! Xoww-Xcour selection (low-speed mode) | 11: | Extemal elock 10 : Timert overtiow signal divided by 2 Clock (X-Xour) stop bit ——— | 11 : Timing ¢ divided by 4 0 : Oscitlate

1 Stop Serial 1/0, port selection bit (P3,, P35)

0 : Normal I/O port P6,/T output function selection bit ———_—_— 1: Serial 1/0 port 0 : Sync. mode (EAROM clock input signal generation) 1! Asynchronous mode — Srov, Signal output selection bit (P3;)

0 Normal 1/0 port

Output of clock port selection bit (PB) 1: Spy, output pin 0: P& (Normal I/O port) iit Fig. 8 Block diagram of serial I/O, MITSUBISHI 2-165 oaleee

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER esse eisai setslieestelindshseth desist Bits 2 and 3 decide whether parts of P3 will be used as a __signal becomes tow signaling that the M37100M8-XXXSP is serial I/O, or not. When bit 2 is “1", P3g becomes an I/O _ ready to receive the external serial data. The Saova signal pin of the synchronous clock. When an internal syncnronous —_goes “H” at the next falling edge of the transfer clock. The clock is selected, the clock is output from P3g. If the exter- serial I/O, counter is set to 7 when data is stored in the se- nal synchronous clock is selected, the clock is input to P35. _rial I/O, register. At each falling edge of the transfer clock, And P3s will be a serial output, and P3, will be a serial in- _serial data is output to P3s. During the rising edge of this Put. To use P3, as a serial input, set the directional register _ clock, data can be input from P3, and the data in the serial bit which corresponds to P3,, to “O". For more information _1/O, register will be shifted 1 bit. Data is output starting on the directional register, refer to the I/O pin section. with the LSB. After the transfer clock has counted 8 times, To use the serial I/O, bit 2 needs to be set to“1", if itis the serial 1/O, register will be empty and the transfer clock “0” P3. will function as a normal I/O. Interrupts will be will remain at a high level. At this time the interrupt request generated from the serial |/O, counter instead of timer 1. bit will be set Bit 3 determines if P3; is used as an output pin for the re- External Clock- If an externa! clock is used, the interrupt ceive data ready signal (bit 3="1", Spova) or used as a request bit will be set after the transfer clock has counted 8 normal I/O pin (bit 3="0"). times but the transfer clock will not stop. Due to this The function of serial 1/O, differs depending on the clock —_ reason, the external clock must be controlled from the out- source; external clock or internal clock. side. The external clock should not exceed 250kHz at a Internal Clock- The Spova signal becomes “H" during trans- duty cycle of 50%. mission or while dummy data is stored in the serial 1/O, Timing diagrams are shown in Figure 9, and connection be- register. After the falling edge of write signal, the Spoy, tween two M37100M8-XXXSP's are shown in Figure 10. ‘Synchronous clock J Transter clock ini f l | Ly f \\ Serial 1/0 register write signal | \\ Serial 1/0 output 7 - erate ee > 2 Co) 9 3 3 EL Serial 1/0 input ; é i Receivable signal \\ i Srova ' Interrupt request bit set Fig. 9 Serial 1/0, timing Sending side Receiving side Serial 1/O, mode register P3, Srova P3, Serial 1/0, mode register bit 3 bit 0 bit 3 bito bE TTo] LETT) Set the directional Set the directional register for P3 pin PSs Synchronous clock Pa register for P3, pin in input mode. in input mode P3, Serial data Py Fig. 10 Example of serial 1/0, connection SS MITSUBISHI 2-166 whe ELECTRIC

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER — Ee SERIAL I/O, clock is selected, the clock is output from P5g. If the exter- The block diagram of serial 1/Og is shown in Figure 11. In _nal synchronous clock is selected, the clock is input to P5.. the serial 1/Og mode the receive ready signal (Spoys), syn- And P5g will be a serial output, and P5, will be a serial in- chronous input/output clock (CLKs), and the serial 1/0, _ put. To use PS, as a serial input, set the directional register (Sours, Sine) pins are used as P57, PSs, P5s, and P54, re- bit which corresponds to P54, to “0”. For more information spectively. The serial I/Og mode register (address OODA;s) _—_on the directional register, refer to the I/O pin section is an 8-bit register. Bit 1 of this register is used to select a To use the serial I/Os, bit 2 needs to be set to“1", if it is synchronous clock source. When this bit is “0”, an external “0” PS. will function as a normal I/O. Bit 3 determines if P5; clock from P3, is selected. When this bit is “1”, the over- _ is used as an output pin for the receive data ready signal flow signal divided by two from clock counter 0 becomes (bit 3="1", Saove) or used as a normal 1/0 pin (bit 3="0") the synchronous clock Bit 4 is the special mode select bit. Serial 1/Og can be set Clock counter 0 is a 8-bit down counter to provide synchro- _to special mode by using this bit. Bits 0, 5, 6, and 7 are nous clock for serial I/Os. This counter divides internal used for special mode. For details, see the section of spe- clock ¢. Structure of clock counter 0 is the same of timers. _cial mode. Therefore, changing the timer period will change the trans- _n the normal mode, operations of serial |/Og are the same fer speed as that of serial 1/O,. For details, see the section of serial Bits 2 and 3 decide whether parts of P5 will be used asa I/O serial 1/Og or not. When bit 2 is “1”, PSs becomes an I/O pin of the synchronous clock. When an internal synchronous Xu Internat clock ures _ Xen OFFA (Kadress 0000; «) Snove = PS; P85; output I = D Sync ‘Serial V0, re [ Leircuit CLKe/SCL Cj Ce CLK _ | as I | ‘output ro _) Sours/SDA | Ces circuit > TdT oat se | ET -— e O OES Serial 1/Op register (8) ! LIT TLTLILI IT) Serial |/Og mode register (Address 00DA;¢) L_ 7 J ‘Special mode register (Address 00DB;.) 7 0 Fig. 11 Block diagram of serial I/Os SS SEE MITSUBISHI 2-167 eee

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER SPECIAL MODE (Pc BUS:INTER IC BUS*) data SDA to “1”. This procedure transmits the stop signal. M37100M8-XXXSP/FP has a special serial 1/O circuit that Figure 12 shows master transmission timing explained can be reception or transmission of serial data in conformity above. with ?C (Inter IC) bus format. (2) Master reception °C bus is a two line directional serial bus developed by —_ Master reception is carried out in the interrupt routine after Philips to transfer and control data among internal ICs of a. data is transferred by master transmission. For master machinery. transmission and interrupt thereafter, see the preceding M37100M8-XXXSP/FP's special serial I/O is not included _ section (1) Master transmission. the clock synchronisation function and the arbitration de- In the interrupt routine, setmaster reception ACK provided tectable function at multimaster. (36,6) in the serial I/Os mode register (address 0ODB,s), Operations of master transmission and master reception and write “FFy,” in the serial I/O, register (address with special serial I/O are explained in the following: 00DC;<). This sets data line SDA to “H” and to perform 8- (1) Master transmission clock master reception. Then, “L” is transmitted to data line To generate an interrupt at the end of transmission, set bit SDA for ACK receiving. In the ACK provided mode, the 1 of interrupt control register 2 (address O0FB,,) to “1” so above ACK is automatically sent out. as to serial |/Og interrupt is selected. Then set bit 0 of in- Repeat the above receiving operation for a necessary num- terrupt control register 1 (address OOFE;.) to “1” so as to _ber of times. Then return to the master transmission mode serial 1/Og interrupt is enabled. Clear the interrupt disable and transmit the stop signal by the same procedure for the flag | to “0” by using the CLI instruction. master transmission. The output signals of master transmission SDA and SCL are _Figure 13 shows master reception timing, output from ports PS; and PS. Set all bits (bits § and 6) (3) Wait function corresponding to P5; and PS. of the port PS register Wait function 1 is held SCL line up “L” level after falling of (address OOEC,,) and the port P5 direction register the 8th clock. (address 00ED,.) to “1” Wait function 2 is he!d SCL line up “L” level after falling of Set the transmission clock. The transmission clock uses the _the Sth clock. covertlow signal divided by 2 from clock counter 0. Set The wait function is reset by setting bit 5, 6 of the special appropriate value in clock counter 0. (For instance, if 4 is mode register to "1" set in clock counter 0 when f(Xiw) is 4MHz, the master transmission clock frequency is 100kHz) ¥ :Purchase of Mitsubishi Electric Corporation's IC compo- Set contents of the special mode register (address nents converys a license under the Philips I?C Patent 00DB,¢). (Usually, 03,5.) Set the bit 4 of serial |/Og mode Rights to use these components in an I?C system, provided register (address OODAie). Figure 14 shows the bit con- __ that the system conforms to the I°C Standard Specification figurations of special mode register and serial /Og mode _ as defined by Philips. register. Initial setting is completed by the above procedure. Write data to be transmitted in the serial |/Og register (address 00DC;.).Immediately after this, clear bits 0 and 1 of special mode reigister (to “0") to make both SDA and SCL output to “L”. This is for arbitration. The start signal has been completed. The hardware automatically sends out data of 9-clock cy- cle. The 9th clock is for ACK receiving and the output level becomes “H” at this clock. If other master outputs the start signal to transmit data simultaneously, it is not detected as an arbitration-lost When the ACK bit has been transmitted, bit 1 of the timer control register is set to “1” (issue of interrupt request) , notifying the end of data transmission. To transmit data successively, write data to be sent to the serial 1/Og register, and set the interrupt enabled state again. By repeating this procedure, unlimited number of bytes can be transmitted. To terminate data transfer, clear bits 0 and 1 of the special mode register to “0”, set bit 1 clock SCL to 1, then set bit 1 — MITSUBISHI eons Ee

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER OE PowSDA {v7 X vey vs X v4 X v9 X ve X ot X bo Yacx) (© Geico) ese ULL ASU pel8 1 FI0OOO0OROY 1 eswsee ———J VUUUU UU Fig. 12 Master transmission timing Reception data en DA -== Pos (oYoaKoseeaXeKeyoohos (TT TTT Tee eS USL P5808 $7 psvsoe ——_ UU UU Fig. 13 Master reception timing CLLEELT LJ. Seta vOs mode register PULTE Special mode register T (address 00DA\\«) TT ‘Ty (address 00DB;.) | Transmission and reception mode select bit | Data line control bit (Note 2) 0 : Reception mode 0 : SDA outputs “L”. | 1: Transmission mode 1. SDA outputs “H”. | \\__ synchronous clock select bit | —— Clock line control bit (Note 2) 0 : External clock 0 : SCL outputs “L". i 1 : Clock counter 0 divided by 2 1: SCL outputs “H” L - Serial /Og select bit |____. ack recognition bit (Note 1) 0 : Parallel port | | 0 : ACK was received. 1: Serial 1/0 port | i 1: ACK is not received. -———— Srove signal output select bit |_________.. wait function 1 enable bit (Note 3) 0 : Parallel port i | 0 : Wait function 1 is disabled, 1: Srove signal output pin | 1: Wait function 1 is enabled. \\ | ———— Specia! mode select bit = —— Wait function 2 enable bit (Note 3) 0 : Normal serial 1/0 0 : Wait function 2 is disabled. 1: Special mode 1: Wait function 2 is enabled. _________ Ack operation select bit — ———— Wait function 1 acceptance and 0 : ACK is not sent or received. operation display bit (Note 4) | 1 ACK is sent and received 0 Wait function 1 isnot functioning L ur signal ootot vt (note 1) 1 Wait function 1 is functioning,

0 Star signa is not detected wait tunction 2 acceptance and

1: Start signal was detected, ‘operation display bit (Note 4) 0 : Wait function 2 is not functioning [Lg Stop signal detect bit (Note 1) 1: Wait function 2 is functioning, 0 ! Stop signal is not detected. 1 = Stop signal was detected. Note 1: This biti for read only. When “1” is written to this bit itis reset 2 : The “L” or “H” output to the SDA or SCL line is the value to be output from this port, not the value currently held by the SDA or SCL line. 3: Wait function 1 maintains the SCL line to “L” after the 8th bit clock putse has fallen in the special mode. Wait function 2 maintains the line to" aftr the 9th bit clock pulse has fallen

4 The wat function is canceled by writing “1” to these bits

Fig. 14 Structure of registers related to serial I/Op a MITSUBISHI oe 2169

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER PWM OUTPUT CIRCUIT shown in Figure 16 (b). Changes in the contents of the (1) Introduction PWM latch allows the selection of 64 lengths of high- The M37100M8-XXXSP is equipped with one 14-bit level area outputs varying trom 0/64 to 63/64. An PWM and four 6-bit PWMs. The 14-bit resolution gives length of entirely high-level output cannot be output, PWM1 the minimum resolution bit width of 500ns (for ie. 64/64. Xim= 4MHz) and a repeat period of 819278. PWM2, —(5)_ 14-bit PWM operation PWM3, PWM4 and PWMS have a 6-bit resolution with The timing diagram of the 14-bit PWM1 is shown in Fi- minimum resolution bit width of 16s and repeat period gure 17, The 14-bit PWM divides the data within the of 1024s. Accuracy and operation range is certified of PWM latch into the lower 6 bits and higher 8 bits. PWM are Voc = 4.5 ~ 5.5V regardless of input fre- ‘A high-level area within a length N timers = is output quency. every short area of t=256 * =128ys as determined by Block diagram of the PWM is shown in Figures 15 data N of the higher 8 bits. (Refer to PWM output @ in The PWM timing generator section applies individual the lower part of Figure 17.) control signals to PWM 1~5, using clock input Xin di- Thus, the time for the high-level area is equal to the vided by 2 or Xcin divided by 2 as a reference signal. time set by the lower 8 bits or that puls 7. As a result, (2) Data setting the short-area period t (=128us, approx. 7.8kHz) be- The output pins PWM1, PWM2, PWM3, PWM4 and comes an approximately repetitive period. PWM65 are in common with pins P6,, P62, P63, P6, and (6) Output after reset P65 of port P6 (i.e. for PWM output, PWM output selec- At reset the output of port P6 is in the high impedance tion bits and the P6 directional register D6, ~ D6s state and the contents of the PWM register and latch should be set). When PWM1 is used for output, first set are undefined. Note that after setting the PWM regis- the higher 8-bit of the PWM1-H register (address ter, its data is transferred to the latch 00F0;.), then the lower 6-bit of the PWM1-L register (address 00F1,¢). When one of the PWM2~ PWM5 is used for output, set the 6-bit in the PWM2~PWM5 reg- _—Table 2. Relation between the 6 lower-order bits ister, respectively. Note that the higher 2 bits of these of data and the space set by the ADD bit 8-bit registers are ignored when used 6-bit register. (3) Transferring data from registers to latches 000000 | Nothing The data written to the PWM registers is transferred to OOOCOr maz the PWM latches at the repetition of the PWM period. 000010 | m=164 The signals output to the PWM pins correspond to the OO O100 | ma 8,244086 contents of these latches. When data at addresses DTD O00 | Ra? FW Ee 00F016~00F 4,5 and OOF8;5 is read, data in these latch- es has already been read allowing the data output by the PWM to be confirmed. When the 6-bit latch is being read, the upper 2 bits of the register becomes undefined. However, bit 7 of the PWM1-L register indi- cated the completion of the data transfer from the PWM1 register to the PWM1 latch. If bit 7 is “0”, the transfer has been completed, if bit 7 is “1”, the transfer has not yet begun. (4) Operation of the 6-bit PWMs The timing diagram of the two 6-bit PWMs (PWM2~ PWM5) is shown in Figure 16. One period (T) is com- posed of 64 (2°) segments. There are six different pulse types configured from bits 0~5 representing the significance of each bit. These are output within one period in the circuit internal sec- tion, Refer to Figure 16 (a) Six different pulses can be output from the PWM. Thesé can be selected by bits 0 through 5. Depending ‘on the content of the 6-bit PWM latch, pulses from 5~0 is selected. The PWM output is the difference of the sum of each of these pulses. Several examples are

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER a NE OO - - pweiek register Selection gate : connected to black Coauress OOF) 4 al colored side when reset. PWMI-H register () CLIT TT) (address 00FO,«) bit? bits Ex /— Pass gate [Iittit] &, | i a7 o TO Cc: PWM latch MSB (14-bit) LSB [LLTTTTITT TTT tt) J. he P06 pe PM, a (4MHz) | 2) (2MH2) pM, (1024,s period) PS: D6: — “pO PovPwee PNA Fey Cane Y | L 5» D6, g | 9 é Pw latch j PAM latch | bi ot © peyewns CLT TT) CITT TT ) PN = | MsB tsB MSB Use PMs a | & &) bits bito bits ito \\ [TTT TTI CTTTTT) Pba 06. PWN2 register PWM3 register (adsors fF20} | __ Crates Sora) i —— ona 0 P6y/PwM4 = . . I — Ps D6; | eo PHA latch PWM latch | bi on _-O Pe/Pwns LIT TTT) LITT TT) en.&—O+—p>, I~ MSB SB MBB TSB De PN, 4 1 eo) — 9) bit 5. bit 0 bit bit 0 LETT TT I LITT TT ) PWM4 register PWM5 register (address 00F 415) (address 00F8;5) PM : PWM control register — PN : PWM output control register 6 : Port P6 directional register bata bus 6 : Pont P6 register Fig. 15 Block diagram of the PWM circuit a

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER ovz3a5e7@ 12 6 0 1% 2% » % 0 4 & 8 56 6 6 BitS aid Bit3 } | } Bit2 | } eitt | ato WhenOs | rn i When ols fl When 18,5, (24) When 28:6 ven2 When 3B, (59) Wwen 3s (63) at re as | When output is lower 6 bits of PWM1 t= 128us T= 8192us When output is PWM2 ~ PWMS t= tees T= 10248 when f( Xi) =4MHz (b) Example of 6-bit PWM output Fig. 16 6-bit PWM timing diagram _ MITSUBISHI aie oeees

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER EE Data in address 00F Osc is 6Ay6 Data in adgross O0FO.g is £7816 register PWMI-L aaa i at) T853;6 TAA TAS TEFS;6

1 When bite of PWMI-L 180 register

T= 8192u8 to latch transter will not occur T64x1281.8) — : - = 128. —_— _ t= 128us ee _— — (Example!) 6A [6B GA 6B GA $8 6B 6B 6A 6B Joa [oe GA 6B 6B 6B 6A SB GA 6B 6A 6B 6B 68 6A [6B 6A PWM! output U i lower 6 bits output_] 5. 5 54315 5 5 513'5 5 5 5413/5 5 5 (When H: 6c, Lhe) 68\\¢ 36times BA 2 —— (1907) (106) times (Example?) 6, [6a 6a GA 6B 5A 6B 6A 5B 6A 6A 6A 6B 6A 6B GA 5B GA GA 6A 58 6A 6B 6A 6B |6a 5a PWM output lower 6 bits A out 4 3 4 4 3LJa 4 sLJa (winen #1: 6Ase 6Bie~ 2h times GAyeS2times | |-__-s» 10664424 ee TE 128 (256X0. 54s) —~ Minimum bit resolution width] r =0, 5s i PWM1 output fee]! cot eeles? — Toot or ealeg lea! 67! — {0201 8-bit counter 1021 O11 OO] FFIFE'FDIFC! —~ '97/96195! —- 102! 01'00|FFIFE'FOIFC: — 97196 1951 — High/low-level of the ADD | High-level area output, the length section is determined by ‘of which is specified PWM-H the data contained in {he lower 6 bit 256 + (12808) standard Fig. 17 14-bit PWM timing diagram ee

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER 7 0 7 0 | | PWM cont register | |. PWM output contrat register ia | (Address 00F5;6) a || | (Address 00F 946) | | iy | | pwM1, PWM2, PWM3, PWM4, PWM5. | '_ pwMt output polarity selection bit | | count source selection bit PWN2 output polarity selection bit 0 : Supply 1 isi | PMG output poary selection bit | | P6,/PWM1 output selection bit PWM4 output polarity selection bit | | 0 : Paraltel port 4 PWMS output polarity selection bit |

1 Pw cut Phoned

1 Negative

~~ P6x/PWM2 output selection bt | 0 : Parallel port 1: PWM2 output —_————— P6./PWMS output selection bit | 0 2 Paale! pot | 63/PWM3 output selection bit 1 PMS cup 0 : Parallel port | 1: PWM output | Le INT, input reverse bit 0 : INT (leading-edge interrupt request) | 1 5 INT (trailing-edge interrupt request) int, input reverse it 0 : INT (leading-edge interrupt request) i 1 = INT (trailing-edge interrupt request) ——— P65/T output selection decision bit (reading only) 0 : Parte! pont | 1 Outputs 172 mat of timer —— P6./PWM output selection Bit

0 Paatet port

Fig. 18 Structure of registers related to PWM. MITSUBISHI ais ote

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER PORT P6,/TIMER 1 OUTPUT From the time that the contents of SM, was changed to the Bit 0 of port P6 outputs 1/2 the frequency of timer 1 when point where switching completes, the contents of neither bit 4 (SM,) of the serial I/O, mode register (address SM, nor P6) may be changed. Use of the synchronous 00F6\\s) is set to “1”. The output switching can be accom- mode prevents the generation of a pulse shorter than the plished with either of two procedures, synchronous mode or _ timer output during switching. Figure 19 (a) gives an exam- asynchronous mode, depending on the setting of bit 5 ple of timing in the synchronous mode. Use of the synchro- (SMs) of the serial 1/0, mode register. nous mode allows generation of an EAROM clock input sig- When SM, is set to “0” the synchronous mode is set. In nal through the use of a simple program. such a case, after SM, has been changed, synchronization When SMs is set to “1”, the asynchronous mode is set. In is set to the 1/2 frequency of timer 1 and switching be- this case, the output switching occurs directly after SM, has tween the port latch and timer takes place. It is possible to been changed. Figure 19 (b) gives an example of timing in ascertain whether switching actually occurred by reading _the asynchronous mode. the value of bit 6 of the PWM control register. Rw i i en SM. i a 6 ee 1 ! a V20tT1 \\ (Note 1) PMs Latch output i Timer output i 6 latch H P6,/T output i (a) Synchronous mode (SM;=0) SM. ee a 1/208 71 \\ i PM, Lah oo : Timer output ; i PB» latch 1 — — — (b) Asynchronous mode (SM;=1) Note 1 : Output switching occurs at the trailing edge of timer 1 divided signal when the value of the P6, latch is “0” and at the leading edge of timer 1 divided signal when the value of the Pb latch is “1” Fig. 19 P69/T switching timing diagram — — MITSUBISHI Pe 2-178

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER eee eeaeeaeuaayqywTEESee COMPARATOR CIRCUIT Table 3. Relationship between the contents of The comparator circuit is shown in Figure 20. The compara- A-D control register and internal voltage tor circuit consists of the switch tree, ladder resistor, com- A-D control register a . ————| Internal analog voltage Parator, comparator control circuit, A-D control register bit2 | bitt | dito | a” (address 00E7,¢), and analog signal input pin (P33/A-D) } o | o | o 1 W6Veco—1/32Vece The analog input pin is common with the digital input/out- 0 pot | 0 2M6Vec=1/32Vec put terminal to the data bus. ° 9 1 3/18Veo—1/32Vec The 5-bit A-D control register can generate 1/16Vcc-step ° 1 O {| 0 | _4/6Vec—1/32Vec . oO 1 i} 1 5/16Vcco—1/32Vce internal analog voltage, based on the settings of bits 0 to 3. 3 1 7 3 TeV tb. Table 3 gives the relation between the descriptions of AO F—9 fp ev nieve control register bits 0 to 3 and the generated internal ana- 1 0 O10 ft 86Vee=17/32Vec log voltage. The comparator result of the analog input vole | —7 0 0 1) 96Vco=1/32Vc0 tage and the internal analog voltage is stored in the A-D 1 0] 0 10/16Vec—1/32Vec control register, bit 4. 1 0 1 1) WABVec=1/32Vec The data is compared by setting the directional register 14 o | 0 _ 12 6Vce—1/32Vce corresponding to port P3; to “0” (port P3, enters the input 1 | ao 1 13/16Veo—1/32Vec mode), to allow port P3,/A-D to be used as the analog in- Sop tt | 0 | NB Vee 1/32Ve0 put pin. The digital value corresponding to the internal ana- 1 1 1 1 ISM6Veo~1/32Vec. log voltage to be compared is then written in the A-D con- trol register (address 00E7;¢), bits 0 to 3. The voltage com- parision starts as soon as the writing is completed. 4-cycle (required for comparating) later, the result of comparision is stored in the A-D control register, bit 4. Bit 4 is "1" when analog input voltage > internal analog voltage and “0” when analog input voltage < internal analog voltage. When voltage is compared to by setting bits 0 to 3 of the comparator register "0", bit 4 of the A-D control register be- comes “1” regardiess of the analog input voltage. Output of lone O0EBe) comparator | 4 result A-D control register cwreuit (Address OO) p3, Q-——_ 4 7 waste PS — fle [n Ta | | ‘ ee Internal analog voltage Ves Vic Fig. 20 Comparator Circuit Eee 2-17 4 MITSUBISHI § ELECTRIC

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER CRT DISPLAY FUNCTIONS The CRT display circuit has an extended display mode. This mode allows multiple lines (more than 3 lines) to be (1) Outline of CRT Display Functions displayed on the screen by interrupting the display each Table 4 outlines the CRT display functions. The M37100M8- time one line is displayed and rewriting data in the block XXXSP incorporates a 21 columns X 3 lines CRT display for which display is terminated by software. control circuit. CRT display is controlled by the CRT display Figure 23 shows a block diagram of the CRT display control control register, circuit. Figure 22 shows the structure of the CRT display Up to 96 kinds of characters can be displayed, and colors control register. can be specified for each character. Four colors can be displayed on one screen. A combination of up to 1 colors can be obtained by using each output signal (R, G, B, and Table 4. Outline of CRT display functions » “Parameter Functions Characters are displayed in a 12X16 dot configuration to Number of display character | 2lcharactersX 3tines obtain smooth character patterns. (See Figure 21) Character configuration | 12X16 dots (See Figure 21) The following shows the procedure how to display charac- Kinds of character | 9 __ ters on the CRT screen. Character size _| 4 size selectable Z @ Set the character to be displayed in display RAM Color | Kinds of cotor_| 18(max) . _ _ ® Set the display color by using the color register. | __ Coloring unit _|acharacter _. i "Poss ple lines) @ Specify the color register in which the display color is Display expansion _{ Possible (multiple set by using the display RAM @® Specify the vertical position and character size by us- ing the vertical position register. © Specify the horizontal position by using the horizontal position register. 7 ® Write the display enable bit to the designated block || | ORT control register display flag of the CRT control register. When this is | rrEy (address OOEAss) done, the CRT starts operation according to the input Ppt ek Display of all blocks control bit (Note 1) of the Veync signal. | 0 : Display of all blocks off bee 12 dots —————— ' 0: Display of block 1 off | 1: Display of block 1 on [TT Tp ty | | oso eto 2 coat Tt] [| [| ] | 0 : Display of block 2 off | | 1: Display of block 2 on | | fi | td | \\ 0 : Display of block 3 off | 1 Display of block 3 on oS Sees OU atc t ctor soact mode etch it oS Sees 1 sa ehret ! | 1: Half character width color select mode = SEE ‘mae 16 dots 0: Interrupt is disabled |_| ERE i | | 1 Interrupt request occurs at every line display | | | | | 0 + Normal made (256 lines) 1 : Double count mode | oo! anne | | Hal Hl Note 1 : Display of all blocks contro bit indicates the CT | a logical sum (AND) of each block display control bit | 2: The multiple lines display interrupt request [|| | | a | Secure only when CPU is operating at he ntr- CEE ELCEL nal clock frequency when {(Xw)=4MHz : Fig. 21 CRT digplay character configuration Fig. 22 Structure of CRT control register Sinan MITSUBISHI oot a7

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER OCI 082 Hamme Varne Data bus e) fe) oO [e) | (Address 000815) Clock generating . an ‘Character { >] cas | Yost stn ite i | register Display position controt circuit (Address 000045) —_ — | ~ YF | RAM tor daplay i ROM for display sebit 213 ta-bit x16X96 | | Display | control (Address 00D4,.~00D7;5) | Shit register oor register a a | | & & & & 8 R G B ' OUT Fig. 23. Block diagram of CRT display control circuit Ss ES MITSUBISHI e178 Ae

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER (2) Display Position If when one block is displaying, some other block is dis- The display positions of characters are specified in units played at the same display position ((c) in Figure 26), the called a “block.” There are three blocks, block 1 to block 3. __ former block is overridden and the latter is displayed, Up to 21 characters can be displayed in one block. (See The vertical position can be specified from 64-step posi- (4) RAM for Display.) tions (four scanning lines per step) for each block by set- The display position of each block in both horizontal and _ting values 00;¢~3F ys to bits O~5 in the vertical position vertical directions can be set by software. register (addresses 00D1,.~00D3,6). Figure 24 shows the The horizontal direction Is common to all blocks, and is __ structure of the vertical position register. selected from 64-step display positions in units of 4Tc (Tc The horizontal direction is common to all blocks, and can =oscillation cycle for display). be specified from 64-step display positions (4Tc per step The display position in the vertical direction is selected (Tc oscillation cycle for display)) by setting values 00i6~ from 64-step display positions for each block in units of four __3F yg to bits O~S in the horizontal position register (address scanning lines. 00D0,¢). If the display start position of a block overlaps with some Figure 25 shows the structure of the horizontal position reg- other block ((b) in Figure 26), a block of the smaller block ister. No. (1~3) is displayed. 7 0 7 t) anand ates position register U0? LOT | Horizontal position register (Address 00D1,5~0003:6) | ] | | (Address 00005) | l The vertical display start position L ‘The: horizontal display start position | | 64-step positions (00,6~3F i) 64-step positions (00,6~3F 6) 00 : Small size output selection bit 01 : Medium size 0 : The same as R, G, B is output 10 : Large size | 1: Border is output 11: Extra large size | ———-— Border output switch bit © : Border including character Fig. 24 Structure of vertical position registers 1 + Border only Fig. 25 Structure of horizontal position register a

9 MITSUBISHI 2-179

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER SON COISCREEN DISPLAY CONTROLLER am (HR) 1 ov, £ ==> cv, £-—} cv, L-~ [a —«d (a) Example when each block is separated Py (HR) 1 CV, ! ov, Yd fe i i (b) Example when the display start position of a block overlaps with some other block | ff ~ (HR) | ( Oo . Poe Ce DE cv, +-~ [en (c) Example when one block is displaying some other block is superimposed. Fig. 26 Display position SSSSsSSSSSSSSSSSSSSssSsssssee

(3) Character Size display oscillation (=Tc) in the width (horizontal) direction. ning lines in the height (vertical) direction and the cycle of sizes. Table 5. The relationship between the set values of the character size bits and the character sizes

cifying part and display color specifying part for each block. Table 6. The contents of the CRT display RAM

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER aN EOE Block 1 (Character specification} 4st column : 200016 2 _ 0 CI TTT) 2th columa : 2014 ; Specify 96 characters at 00;6~SFie (Color specification} ‘1st column : 2080,6 3 0 ' Clty 21th column : 2094,5 TT] [1 ermer halt color register specication in the normal mode ar in the all character with coor select mode 00 : Color register O specification | Ot : Color register + specification \\ 10 ! Gol register 2 speciation | 11 Golr register 3 speciation in the half character width color select mode 00 : Color register 0 specification 01 : Color register 1 specification 10 : Color register 2 specification

11 Golr register 3 speciation

Block 2,3 (Character specitication) Ist column : 2020; 7 - _,2 ; ITITTTt I 21th column : 2034;5 ~T CET 1 tT 1 character code Specify 96 characters at 00;5~5Fie (Address 2040;¢~2054;¢ in the case of block 3) (Color specification) 1st column : 20A0;6 10 u 21th col 20B4;6 nn L1 cater register spectication 00 : Color register 0 specification Ot: Color register 1 specification ir ~! ) (Address 20C0;.~20D4;¢ in the case of block 3; 10 : Color register 2 specification

11 Color register 3 specification

Fig. 28 Structure of the CRT display RAM a MITSUBISHI JaRe on 188

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER —_ gs (5) Color Registers 7 0 The color of a displayed character can be specified by set- | PO O5 > | oor gists (Adress 00D444~C007,) ting the color to one of the four color registers (CO0~CO3: 7) addresses 00D4,5~00D7;s) and then specifying that color | | I pin output bit register with the CRT display RAM. \\ ! © No character is output There are four color outputs: R, G, B, and |. By using a | | 1} Character is output combination of these outputs, it is possible to set 2*-1 | B pin output bit (when no output) =15 colors. However, because only four | ! 0 : No character is output color registers are available, up to four colors can be dis- 1: Character is output played at one time. R, G, B, and | outputs are set by using bits 0~3 in the color | pin output bit register. Bit 4 in the color register is used to set a charac: 0 : No characteris output 9 7 ron 9 10 si ~ 1: Character is output ter or blank output; bit 5 is used to specify whether a char- acter output or blank output. Figure 29 shows the structure \\ R pin output bit of the color register. (0! No character is output 1: Character is output (6) Half Character Width Color Select Mode L___ 47 pin output bit (Note) By setting “1” to bit 4 in the CRT control register (address (0! No character or blank is output 00D8 5) it is possible to specify colors in units of a half 1: Character or blank is output character size (vertical 16 dotsXhorizontal 6 dots) for char- acters in block 1 only. ‘0 T pin output contro! bit (Note) 0 : OUT pin outputs character In the half character width color select mode, colors of dis- 1: OUT pin outputs blank play characters in block 1 are specified as follows: © The left half of the character is set to the color of the Note | Wen the character outing function is sed, the fi contents of these two bits (bits 4 and 5) are nullified, color register that is specified by bits 0 and 1 at the rd the OUT pin output becomes on border cata, color register specifying addresses in the CRT display RAM (addresses 2080:5~2094;5). Fig. 29 Structure of color registers @ The right half of the character is set to the color of the color register that is specified by bits 2 and 3 at the color register specifying address in the CRT display RAM (addresses 2080;.~209416) Color of the color register specified by Color of the color register specitied by Block 1 bit 0 and bit 1 of address 2080s, bit 0 and bit 1 of address 2081;6 (a) Display in the normal mode H H Color ofthe color register | Color of the color register Color of the color register 1 Color of the color register : Hi specified by bit O and bit1 1 specified by bit 2 and bit | specified by bit 0 and bit1 | specified by bit 2 and bit3 | Block 1 ‘ H H Hi of address 2080, 1 of address 2080, of address 208115 $ of address 208116 { 1 (b) Display in the half character width color select mode Fig. 30 Difference between normal color select mode and half character width color select mode SSS 2-184 9 MITSUBISHt ELECTRIC

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER (7) Multiline Display For multiline display, it is necessary to enable the CRT in- The M37100M8-XXXSP can normally display three lines on terrupt (by clearing the interrupt disable flag to “0” and set- the CRT screen by displaying three blocks at different hori- _ ting the CRT interrupt enable bit (bit 6 at address OOFE1s) zontal positions. to “1"), then execute the following processing in the CRT In addition, it allows up to 16 lines to be displayed by using _interrupt handling routine. a CRT interrupt and display block counter. @ Read the value of the display block counter. The CRT interrupt works in such a way that when display of | @ The block for which display is terminated (i.e., the ‘one block is terminated, an interrupt request is generated. cause of CRT interrupt generation) can be determined In other words, character display for a certain block is initi- by the value read in ©. ated when the scanning line reaches the display position @_ Replace the display character data and display position for that block (specified with vertical and horizontal position of that block with the character data (contents of CRT registers) and when the range of that block is exceeded, display RAM) and display position (contents of vertical an interrupt is applied. position and horizontal position registers) to be dis- The display block counter is used to count the number of played next. blocks that have just been displayed. Each time the display Figure 31 shows the structure of the display block of one block is terminated, the contents of the counter are counter. incremented by one. 2 0 CLIL Display block counter Le 1 (address 00094) | tnaicates number of locks that are being displayed or were displayed Fig. 31 Structure of display block counter Count value Interrupt position | 0 Pe ee en ae --4f--y Fig. 32 Timing of CRT interrupt and count value of display block counter a

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER (8) Scanning Line Double Count Mode Count mode is 32 from 00; to 1F ye, oF eight scanning lines One dot in a displayed character is normally shown by one per step. Scanning line. In the scanning line double count mode, one _If the contents of the vertical position register for a block dot can be shown by two scanning lines. As a result, the are set in the address range of 206 to 3F;5 in the scanning displayed dot is extended two times the normal size in the line double count mode, that block cannot be displayed vertical direction only. (That is to say, the height of a char- (not output to the CRT screen) acter is extended twofold.) In the scanning line double count mode can be specified In addition, because the scanning line count is doubled, the by setting bit 6 in the CRT control register (address display start position of a character is also extended two- 00D8,g) to “1” fold in the vertical direction. In other words, whereas the Because this function works in units of screen, even when Contents set in the vertical position register in the normal the mode is changed the mode about the scanning line mode are 64 steps from 001g to 3F1¢, or four scanning lines Count during display of one screen, the double count mode Per step, the number of steps in the scanning line double only becomes valid from the time the next screen is dis- played. Vertical position A AY ) | Vertical position AX2 > Scanning line 16 tines Ax2 } (a) Display in the normal mode (b) Display in the scanning line double count mode Fig. 33 Display in the normal mode and in the scanning line double count mode 2186 ate MiguasH ELECTRIC

register and the character border function. Table 7. The relationship between the value set in the horizontal position register and the character border function Mls display by character data.

MITSUBISHI! MICROCOMPUTERS M37100M8-XXXSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER (10) Clock Oscillating Circuit for Display The clock signal for display can be obtained by connecting a resistor and a capacitor between the 1/O ports of the oscillating circuit (OSC1 and OSC2). Figure 35 shows an example of circuit M37100MB-XXXSP oscr_oscz we Fig. 35 Example of oscillating circuit for display (11) Programming Notes 1. Use STA instruciton for data transfer to the following registers related to OSD functions. ® Horizontal position register (address 00D0;«) @® Vertical position registers (address 00D1,.~00D3,¢) ® Color registers (address 00D4,;5~00D716) @® CRT control register (address 00D86) 2. Do not display the display OFF blocks having different character sizes on a block display 3. The highest vertical position (the vertical display start position bits are “00,_") can not be used. 4. The interrupt to tell the end of block display is not caused and the display block counter is not in- cremented until the display of the block has been com- pleted terminated 5. The display block counter (00D9;¢) is reset while Vsyuc is “H” (when the option is positive in polarity) to “FF ie" 6. If, during the display of a block, the display position of another block comes, the display of the subsequent block (having a larger vertical position register value) is preferred. 7. When two or more blocks are displayed in the same vertical position, the display priority is CV1, CV2, and CV3 in this order. This is not affected by turning on/off of block display. — MITSUBISHI ao 188 tee

Figure 37. It starts the program from the address formed by __the crystal oscillator oscillation is stable and then returned address and the content of the address FFFE;. as the low —_shown in Figure 36.

20 Serial Og mode register (SBMDAw)~[ 00m

28 Counter 0 (DD) [ FF

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER RESET SYNC t heroes | XDD EHD | the vector table | KX 2K XX AKAD) ———- Note 1 : Frequency relation of f(Xim) and ¢ is (Xn) =4- 4. 8~12 clock cycles 2: The mark "?~ means that the address is changing Fig. 37 Timing diagram at reset

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER VO PORTS (7) Port P6 (1) Port PO This is an 6-bit input/output port with function similar to Port PO is an 8-bit I/O port with N-channel open drain port PO. The output structure of PG, P6, is CMOS out- and middle voltage output. put and the output structure of P6,~ P6; is N-channel As shown in the memory map (Figure 2), port PO can open drain and middle voltage. be accessed at zero page memory address O0E0;.. P6o~P6; have program selectable dual functions. Port PO has a directional register (address 00E1;6) This port is unaffected by the processor mode bits. which can be used to program each individual bit as (8) Function pins for CRT display function input (“0”) or as output (“1"). If the pins are program- The horizontal synchronizing signal is input from Hsync med as output, the output data is latched to the port The vertical synchronizing signal is input from Vsywc. register and then output. When data is read from the 1, B, G, R, OUT are output pins for CRT display. output port the output pin level is not read, only the Refer to the section on CRT display functions for de- latched data in the port register is read. This allows a tails. previously output value to be read correctly even (9) # pin. though the output voltage level is shifted up or down. The internal system clock (1/4 the frequency of the Pins set as input are in the floating state and the signal oscillator connected between the Xw and Xour pins) levels can thus be read. When data is written into the can be output from this pin by selecting the option input port, the data is latched only to the port latch and At low-speed mode, Xcw divided by 2 is*output from the pin still remains in the floating state this pin. Depending on the contents of the processor mode bits (bit 0 and bit 1 at address OOFF;.), three different modes can be selected; single-chip mode, eva-chip mode and microprocessor mode. In these modes it functions as address (A;~Ap) output port (excluding single-chip mode). For more details, see the processor mode information. (2), Port Pt In single-chip mode, port P1 has the same function as port PO but the output structure is not middle voltage. It can be built in pull-up register at each pin by selecting the option. In other modes, it functions as address (Ajs ~Ag) output port. Refer to the section on processor modes for details. (3) Port P2 In single-chip mode, port P2 has the same function as port P1. In other modes, it functions as data (Do~ D7) input/output port. Refer to the section on processor modes for details. (4) Port P3 In single-chip mode, port P3 has the same function as port P1. P3,~P3; have program selectable dual func- tions. P35, P3; function as control signals input/output port except in the single-chip mode. Refer to the sec- tion on processor modes for details. (5) Port P4 This is an 1-bit 1/O port with function similar to port PO, but the output structure is CMOS output This port is unatfected by the processor mode bits. (6) Port PS This is an 7-bit 1/O port with function similar to port P1. P5,~PS5, have program selectable dual functions. P52, P53 are shared with external interrupt input pins (INT), INT2). This port is unaffected by the processor mode bits. oe

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER with ON-SCREEN DISPLAY CONTROLLER Port PO, P62~P6s _ N-channel open drain output > J * | — <| | used as PWM output pins. e 9 Mask option 9&7] D Port P3, PS. - De Soop Port P3, PS _'p-5 Tt <I} Note : P3, P5 may also be Port P4,, P6o, P6; > i ° = CMOS Tri-state output — <] ) > al Note : 6 may also be used as timer Hsync. Vsvne © Schmitt ¢, R, G, B, |, OUT ‘ ichmitt input I ‘CMOS output Data bus —<} —O) Herne, Verne 5 Data bus b O ¢, R, G, B, 1, OUT Fig. 38 Ports PO~P6, Hsync, Vsync. % A, G, B, | and OUT block diagram MITSUBISHI 2-182 Jaeee

: SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER PROCESSOR MODE {1} Single-chip mode (00) By changing the contents of the processor mode pit (bit 0 The microcomputer will automatically be in the single- and 1 at address OOFF;s), three different operation modes chip mode when started from reset, if CNVss is con- can be selected; single-chip mode, microprocessor mode nected to Ves. Ports PO~ P3 will work as original 1/0 and evaluation chip (eva-chip) mode. In the microp- ports. rocessor mode and eva-chip mode, ports PO~P3 can be (2). Microprocessor mode (01) used as multiplexed 1/0 for address, data and control sig- The microcomputer will be placed in the microp- nals, as well as the normal functions of the I/O ports. rocessor mode when CNVss is connected to Vss and Figure 40 shows the functions of ports PO~P3. the processor mode bits are set to “01” The memory map for the single-chip mode is illustrated in In this mode, the internal ROM is inhibited so the ex- Figure 1 and for other modes, in Figure 39. ternal memory is required. By connecting CNVss to Vss, all three modes can be In this mode, port PO and P1 are used as the system selected through software by changing the processor mode address bus and the original function of the I/O pins is bits. Supplying 10V to CNVss places the microcomputer in lost. Port P2 becomes the data bus (D;~Do) and loses the eva-chip mode. The three different modes are ex- its normal output functions. Port P3, and P3, become plained as follows: the SYNC and R/W pins, respectively and the normal |/ © functions are lost (3) Eva-chip mode (11)

00005 When 10V is supplied to CNVss pin, the microcomputer

[Notused | In this mode, the internal ROM is inhibited so the ex- 00POr6 miscellaneous miscellaneous ternal memory is required _ registers registers The lower 8 bits of address data for port PO is output 8 when ¢ goes to “H” state. When ¢ goes to the “L coe rr i state, PO retains its original output functions. miscellaneous miscellaneous Port P1’s higher 8 bits of address data are output when 01006 ~ state it retains its original output functions. Port P2 re- | sotuses | [| ntuea | state, and works as a data bus of D;~Dp (including in- struction code) while at the “L" state. Pins P3, and P3y 20006 output the SYNC and R/W control signals, respectively 20D416 [ova] while gis in the “H” state. When in the “L” state, P3, 2000 - and P3p retain their original {/O function. [ccNousea | [7 Notusea_] side. When this pin is in the “H” state, the CPU reads 38000 on tr aplay 2 data, and when in the “L” state, the CPU writes data 30FFi6 _ isplay 2 The SYNC is a synchronous signal which goes to the | noses | Not used “H” state when it fetches the OP CODE. ‘000. > - The relationship between the input level of CNVss and i_tff7 Uy the processor mode is shown in Table 8. yyy Uys Note : The standards of M37100M8-XXXSP/FP is Z, Y Z thy LLL, VY assured only in single-chip mode. Use in the

000016 PIII T ITT 4s microprocessor mode or the eva-chip mode

Vis sy YI LL only at program development. JILL A Ad hf SISSS LSS, FFFF ie Z Microprocessor mode Eva-chip mode The shaded area is external memory area Fig. 39 Example memory area in processor mode ee MITSUBISHI — ote on 198

Table 8. Relationship between CNVss pin input level and processor mode

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER with ON-SCREEN DISPLAY CONTROLLER Xen Xcour [e) @) BD; (oe) (e) T™. j (internal clock) C | Reset Fig. 42 Block diagram of clock generating circuit a 2-196 fe MISES ELECTRIC

MITSUBISHI! MICROCOMPUTERS SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER eee hOesm—r—r—— WT instruction ? inti 4MHz oscillation instruction ‘STP instruction aoxtte oscillation ‘Mite osciation ate stop ¢=stop(high-level) 32kHz oscillation 32kHz stop Interrupt Interrupt( Note 1) yesteal INT] (exeraT [Finer ero {31/0 interupt $170 interupts su=0 smn cans oxen WIT instruction STP instuction 2 oscitaton \\ “A ~ 32kH2 oscillation ans osciiion ‘ual ap gost0p sk ceca snes Timer operation(Note 3) ———— = =—— “stop Interrupt Interrupt(Note 1) Extra INT] jExternal INT} ied interrupt 4810 interrupts 1/0 iterupt- sMge0 sm! m Wt instuetion STP instuction 2 to — ° ~—— 4MHz stop 4MHz stop 2kHz oscillation ¢=ttop 32kHz oscillation 32kHz stop = 16KH: = Timer operation(Note 3)//, ———> orton —.- soap Interrupt Interrupt( Note 2) rexternal INT] [Beem Note + Approximately sms of latency time ore automatically generated upon release from the STP instruction due to connections of timer 2 and 3. 2. Approximately 500ms of latency time exists after the release of the STP instruction. 3. | When the internal clock 1/8 frequency is connected as a timer count source the count source becomes 2kHz Fig.43 Transition of states for the system clock Sess MITSUBISHI oat e197

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER <An example of flow for system> Power on reset § Clock X and clock for clock function Xe oscillation

5 Intemal system clock start (X—1/4~ #)

& | program start trom RESET vector E ‘ E — - = |. Normal program | +Operating at 4 MHz | Internal clock # source switching X( 4 MHz)--Xo(32, 768kHz)(SMy : 0-1) 5 | Clock x halt(xXe in operation) a Internal clock halt( WIT instruction) = H Timer 3 (clock count) overtiow

83 Internat clock operation start (WIT instruction released)

a [ cecroosns ae é Clock processing routine | = Operating at 32. 768kHz Internal clock halt (WIT instruction) Interrupts from NT. timer 2, timer } or seriat I/Oq, INTz or serial /Op,

5 Internal clock operation start (WIT instruction released)

3 Program start from interrupt vector

pes Clock X oscillation start 8 ‘ mn g Oscillation rise time routine (software) | +-Operating at 32. 768kHz = 1 § Internal clock ¢ source switching (X_-*X)(SM, 1+ 0) 2 so Normal program | —-Operating at 4MHz s | STP instruction preparation (pushing registers) 3 — ~ 2 4 2 i Timer 2 timer 3 interrupt disable, (IM4= 0, TMe= 0 ) 2) Timer 2 count stop bit resetting (TMs = 0 ) = | Clock X and clock for clock function Xo halt (STP instruction) = — { RAM backup status § —|_ Interrupts trom INT, serial /Oq, INTo, serial Op g | Clock for clock fupetion Xe oscillation start $ | __ Timer 3 overtiow (Xc/8—timer 2 ~+timer 3) 3 (Automatically connected by the hardware) = Internal system clock start (Xc--1/2-+#) | __ Program start from interrupt vector 5 | : - | [Normal program MITSUBISHI 2-198 ate

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER PROGRAMMING NOTES (1) Processor status register 1. Except for the interrupt inhibit flag (1) being set to “4”, the content of the processor status register (PS) is unpredictable after a reset. Therefore, flags affect- ing program execution must be initialized. The T flag and D flag which affect arithmetic opera- tions, must always be initialized 2. A-NOP instruction must be used after the execution of a PLP instruciton (2) Interrupts ven though the BBC and BBS instructions are ex- ecuted just after the interrupt request bits are modified (by the program), those instructions are only valid for the contents before the modification. Also, at least one instruction cycle must be used (such as a NOP) be- tween the modification of the interrupt request bits and the execution of the BBC and BBS instructions. (3) Decimal operations 1. Decimal operations are performed by setting the de- cimal mode flag (D) and executing the ADC or SBC instruction. In this case, there must be at least one instruction following the ADC or SBC instruction be- fore executing the SEC, CLC, or CLD instruction. 2. The N (Negative), V (Overflow), and Z (Zero) flags are ignored during decimal mode. (4). Timers The frequency dividing ratio of timer is 1/(n+1). (5) STP instruction The STP instruction must be executed after setting the timer 2 count stop bit (bit 5 at address OFF.) to supply (“0”). DATA REQUIRED FOR MASK ORDERING Please send the following data for mask orders. + mask ROM order confirmation form + mask specification form + ROM data----EPROM 3 sets Write the following option on the mask confirmation form (1) Port P1 pull-up transistor bit (2). Port P2 pull-up transistor bit (3) Xiw and Xoin Oscillation feed-back registers (4) CRT display signal input/output polarity (5) ¢ output ee

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER ABSOLUTE MAXIMUM RATINGS Sma] Parameter en Faings Vee | Supply voltage __| —0.3~6 vw [input voltage RESET. CNVss =0,3~13 v Input voltage PO)~PO;, Ple~Pt;, P2o~P2;, a P3o~P3;, P47, PS;~PSr, vy With respect to Vss =0.3~Voc+0.3 v P6~P6s, Hswnc. Vey Output transistors are Xin, Xow, OSCT + “Xm Xen OSCt —~| at “of” state oo Vo Output voltage PO:~POr, Pé:~Pbs =0.3~13 Vv ‘Output voltage Pto~PI>, P2o~P2y, Par, | Vo P3y~PSr, P5:~P5y, Po. P61, Xour. # 5 =0.3~Vect0.3 |v Xcour, OSC2, R, G, 8, |. OUT i a lon | Circuit current P60, P6:, P4;, R. G, B, |, OUT ~ | _0~10(Note 1) | mA P51~P5), Pop, PBs. R. G. 8,1, OUT Vos 7¥ 0~15(Note 2) Pa [Power dissipation [Tas at 1000(Note 3) mw Topr | Operating temperature oe ~~ =10~70 ims Tstg Storage temperature [ =40~125 c Note 1 : The total of lo» should be 20mA(max). 2: The total of lors and lov2 should be 50mA(max). 3. 600mW in case of the flat package RECOMMENDED OPERATING CONDITIONS (Vec=5V10%, Ta=—10~70 unless otherwise noted) sym Pema ee | |_(Note 4) [low-speed mode (Xow) =s2KH2 | 3.0 | —0 [HT input voltage PO)~PO,, Pto~Pt7, P2o~P2r, Ty P3)~P3}, Pay, PSy~PS;, View P6o~P6s, RESET, Xv, Xe 0. 8Vce Veo v Heme, Voenc “L" input voltage POy~P0;, Plo~P17, P2o~P2;, _ P51, P54, PSs, P51, POo~PBs y, “L" input voltage P32, P3s, P52, PSs, PSs, RESET, Lo | « Xin. Xe. Hsyne. Verne =U" average output current PO;~POr, Pio~Pty, loucevg) P2—~P2), PO~PS, PA, | | A, G, B, 1, OUT ew me | Toncavg) | H” average output currant Pay, Péy,Pé;,R, G,B, OUT | (Xm) | Oscillating frequency (Note 5) 3.6 4 | 4.4 | Muz | Oscitating trequency - Tas [32] a8 | He | Oscillating frequency patsy Tune | Note 4 : Apply 0.022uF or greater capacitance externally to the Voc power supply pin so as to reduce power source noise. 5: Use a ceramic resonator or a quartz crystal oscillator to generate of main clock.

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER ELECTRICAL CHARACTERISTICS (vec=5v+10%, Vos= 0, Ta=—10~70C, (Xx) =4MHz) Symbol Paramet “Test conditions Limits om rameter 5 j—_timits ni ym . Min. Typ Max. Vou | -H* output voltage Pé;, PB, P6,, R. G,B, |, OUT Veo=45V, lon ==0.5mA Taal v - Par, Pb, Pr, RG. B ~ 0. 4}. Voo=4.5¥ | Vou HT output voltage # ; le =-2.5mA - 2A L a “L* output voltage PO)~POr, P25~P2r, P8o~P37, Veom4.5V Vou P4;, P5:~P57, Pby~Pbs, | ton 0.5ma O4 v 8, G,B,1, OUT _ ' _ oe to oma {oof v “L™ output voltage ¢ Voo=4. SV T 2 | v fou | Erewoutvottage # ; lenesme +t, | Vig = Vie | Hysteresis RESET Voo=5.0V i as | 07) Vv Vet — Vr-| Hysteresis P32, PQs, P52, PSs, PSs, Hswnc, Vewnc Voc=5.0V O5 | 13 | Vv | Pull-up transister (Note 6) Voo™5.0V i] Pto~ Pty, P2o~ P2p v=ov _ 1s 30 60 il Ko “H" input leak current PO5~PO;, Pio~PIr, P2o~P2; Verh sv P8q~P3;, Paz, PS:~P5r, PE~Pbs, | OO 5 Lowa nF Vo=5.5V : RESET, Hsywo. Vsync ee eee eee ee jo = Voo=5. 5V { lozn +H” input leak current P0p~PO;, P6s~PEs voct2v 7 10 | HA =U" input leak current POp~POr, Pto~Pt, P2o~P2>, | Voc=5.5V loz P3o~P3r, Par, PS:~PS. P6o~ PBs, 58 | wa Vo=0V | | Hye, Verne: RESET Vea | RAM retention volge Atstop mode Tes) Vv Voc=5.5V {(Xiy)=4MHz- 5 10 [At system operation and CAT display off _ ] 8 Voc™5.5V (Xin) =4MHz At system operation and CRT display on 7 | 4 i ma Voo=5.8V (Xa) =4MHz \\ 4 | [At wait mode | Xin—Xour stop Veo=5.5V 60 200 loc ‘Supply current 1(Xeyy) =32kHz Atsystem operation _| Vee=3V_| _s . Xn—Xour stop Voo=5-5V 25 | 100 (Xow) =32kHz —+—— uA At wait mode Voc=3V 5 | Vec=5.5V [| 1 10 AN stop mode - |__| Vec=3V 0.6 Note 6 : Pull-up transistor is mask option. EE * MITSUBISHI PRE aoa)