M368L6423HUN

K4H641638N SAMSUNG | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 10

Technical content

DDR SDRAMGeneral Information December 2007 DDR SDRAM Product Guide December 2007 Memory Division

DDR SDRAMGeneral Information December 2007 A. DDR SDRAM Component Ordering Information 28 : 128Mb, 4K/64ms 56 : 256Mb, 8K/64ms 51 : 512Mb, 8K/64ms 1G: 1Gb, 8K/64ms 2G: 2Gb, 8K/64ms 04 : x 4 06 : x 4 Stack 07 : x 8 Stack 08 : x 8 16 : x16 3 : 4 Banks 3. Product 4. Density & Refresh 5. Organization 6. Bank M A B C D E F G H T N G C L I P 9. Package Type 8. Revision 10. Temperature & Power 1. SAMSUNG Memory : K 2. DRAM : 4 Revision Bank Organization Density & Refresh Product DRAM SAMSUNG Memory Interface (V DD, VDDQ) Package Type Temperature & Power 1 2 3 4 5 6 7 8 9 10 11 Speed H : DDR SDRAM : Commercial Temp.( 0°C ~ 70°C) & Normal Power : Commercial Temp.( 0°C ~ 70°C) & Low Power : Industrial Temp.( -40°C ~ 85°C) & Normal Power : Industrial Temp.( -40°C ~ 85°C) & Low Power : TSOP II : sTSOP II : FBGA : 1st Gen. : 2nd Gen. : 3rd Gen. : 4th Gen. : 5th Gen. : 6th Gen. : 7th Gen. : 8th Gen. : 9th Gen. 11. Speed K 4 H X X X X X X X - X X X X : DDR400 (200MHz @ CL=3, tRCD=3, tRP=3) : DDR333 (166MHz @ CL=2.5, tRCD=3, tRP=3)*1 : DDR266 (133MHz @ CL=2 , tRCD=3, tRP=3) : DDR266 (133MHz @ CL=2.5, tRCD=3, tRP=3) CC 8 : SSTL-2 (2.5V, 2.5V) 7. Interface ( VDD, VDDQ) J N : 11st Gen. : 14th Gen. U V Z : TSOP II (Lead-free) : sTSOP II (Lead-free)*1 : FBGA (Lead-free)*1 L H F : TSOP II (Lead-free & Halogen-free) : FBGA (Lead-free & Halogen-free)*1 : FBGA for 64Mb DDR (Lead-free & Halogen-free)*1 : sTSOP II (Lead-free & Halogen-free)*1 Note 1: All of Lead-free or Halogen-free product are in Note 1: "B3" has compatibility with "A2" and "B0" compliance with RoHS

DDR SDRAMGeneral Information December 2007 B. DDR SDRAM Component Product Guide Density Bank Part Number Package*1 & Power*2 & Speed*3 Org. Interface Refresh Power (V) Package Avail. 64Mb N-die 4Banks K4H641638N LCCC/CB3 LLCC/LB3 4M x 16 SSTL_2 4K/64m 2.5 ± 0.2V 66pinTSOPII Now FCCC/CB3 FLCC/LB3 60ball FBGA CS 256Mb H-die 4Banks K4H560438H UCA2/CB0 ULA2/LB0 64M x 4 SSTL_2 8K/64m 2.5 ± 0.2V*4 66pinTSOPII Now ZCCC/CB3 ZLCC/LB3 60ball FBGA K4H560838H UCCC/CB3 ULCC/LB3 32M x 8 60ball FBGA ZCCC/CB3 ZLCC/LB3 60ball FBGA K4H561638H UCCC/CB3 ULCC/LB3 16M x 16 66pinTSOPII ZCCC/CB3 ZLCC/LB3 60ball FBGA 256Mb J-die 4Banks K4H560438J LCB3/CB0 LLB3/LB0 64M x 4 SSTL_2 8K/64m 2.5 ± 0.2V*4 66pinTSOPII CS K4H560838J LCCC/CB3 LLCC/LB3 32M x 8 66pinTSOPII CS K4H561638J LCCC/CB3 LLCC/LB3 16M x 16 66pinTSOPII CS 512Mb D-die 4Banks K4H510438D UCB0 ULB0 128M x 4 SSTL_2 8K/64m 2.5 ± 0.2V*4 66pinTSOPII Now ZCCC ZLCC 60ball FBGA K4H510838D UCCC/CB3 ULCC/LB3 64M x 8 66pinTSOPII ZCCC/CB3 ZLCC/LB3 60ball FBGA K4H511638D UCCC/CB3 ULCC/LB3 32M x 16 66pinTSOPII ZCCC/CB3 ZLCC/LB3 60ball FBGA Note 2 : - Commercial Temp. (0°C <Ta< 70°C) C Commercial Temperature, Normal Power L Commercial Temperature, Low Power Note 4 : DDR400 DDR333/266 VDD/VDDQ 2.6V ± 0.1V 2.5V ± 0.2V Note 3 : - "B3" has compatibility with "A2" and "B0" 133Mhz 166Mhz 200Mhz CL = 2 DDR266(A2) - - CL = 2.5 DDR266(B0) DDR333(B3) - CL = 3 - - DDR400(CC) U V Z : TSOP II (Lead-free) : sTSOP II (Lead-free) : FBGA (Lead-free) L H F : TSOP II (Lead-free & Halogen-free) : FBGA (Lead-free & Halogen-free) : FBGA for 64Mb DDR (Lead-free & Halogen-free) : sTSOP II (Lead-free & Halogen-free) Note 1 :

DDR SDRAMGeneral Information December 2007 Note 2 : - Industrial Temp. (-40°C <Ta< 85°C) I Industrial Temperature, Normal Power P Industrial Temperature, Low Power Note 4 : DDR400 DDR333/266 VDD/VDDQ 2.6V ± 0.1V 2.5V ± 0.2V Note 3 : - "B3" has compatibility with "A2" and "B0" 133Mhz 166Mhz 200Mhz CL = 2 DDR266(A2) - - CL = 2.5 DDR266(B0) DDR333(B3) - CL = 3 - - DDR400(CC) U V Z : TSOP II (Lead-free) : sTSOP II (Lead-free) : FBGA (Lead-free) L H F : TSOP II (Lead-free & Halogen-free) : FBGA (Lead-free & Halogen-free) : FBGA for 64Mb DDR (Lead-free & Halogen-free) : sTSOP II (Lead-free & Halogen-free) Note 1 : C. Industrial temp DDR SDRAM Component Product Guide Density Bank Part Number Package*1 & Power*2 & Speed*3 Org. Interface Refresh Power (V) Package Avail. 256Mb H-die 4Banks K4H561638J UICC/IB3/IB0 UPCC/PB3/PB0 16M x 16 SSTL_2 8K/64m 2.5 ± 0.2V*4 66pinTSOPII Now ZIB3/IB0 ZPB3/PB0 60ball FBGA 256Mb J-die 4Banks K4H561638J LICC/IB3 LPCC/PB3 16M x 16 SSTL_2 8K/64m 2.5 ± 0.2V*4 66pinTSOPII CS 512Mb D-die 4Banks K4H510838D UIB3/IB0 UPB3/PB0 64M x 8 SSTL_2 8K/64m 2.5 ± 0.2V*4 66pinTSOPII Now ZIB3/IB0 ZPB3/PB0 60ball FBGA K4H511638D UIB3/IB0 UPB3/PB0 32M x 16 66pinTSOPII ZIB3/IB0 ZPB3/PB0 60ball FBGA

DDR SDRAMGeneral Information December 2007 3 : DIMM 4 : SODIMM 68 : x64 184pin Unbuffered DIMM 81 : x72 184pin ECC unbuffered DIMM 83 : x72 184pin Registered DIMM 12 : x72 184pin Low Profile Registered DIMM 70 : x64 200pin Unbuffered SODIMM 63 : x64 172pin Micro DIMM T TSOP II (400mil) N sTSOP G FBGA : 16M 17 : 16M (for 128Mb/512Mb) 32 : 32M 33 : 32M (for 128Mb/512Mb) 64 : 64M 65 : 64M (for 128Mb/512Mb) 28 : 128M 29 : 128M (for 128Mb/512Mb) 56 : 256M 57 : 256M (for 512Mb) 51 : 512M 1 s t G e n . 3 r d G e n . 5 t h G e n . 7 t h G e n . 9 t h G e n . 0 : Mother PCB 2 : 2nd Rev. S : Reduced layer PCB L : DDR SDRAM (2.5V VDD) 1. Memory Module : M 2. DIMM Configuration 3. Data Bits 4. Feature 5. Depth 12. Speed 11. Temp & Power 10. PCB Revision & Type 9. Package 8. Component Revision Composition Component PCB revision & Type Component Revision Refresh, # of Banks in Comp. & Interface Depth Feature Data bits DIMM Configuration Memory Module Package Power Speed 0 : x 4 3 : x 8 4 : x16 8 : x 4 Stack 9 : x 8 Stack M X X X L X X X X X X X - X X X 7. Composition Component 1 2 3 4 5 6 7 8 9 10 11 12 1 : 4K/ 64ms Ref., 4Banks & SSTL-2 2 : 8K/ 64ms Ref., 4Banks & SSTL-2 6. Refresh, # of Banks in comp. & Interface M B D F H 1 : 1st Rev. 3 : 3rd Rev. : DDR400 (200MHz @ CL=3, tRCD=3, tRP=3) : DDR333 (166MHz @ CL=2.5, tRCD=3, tRP=3) : DDR266 (133MHz @ CL=2 , tRCD=3, tRP=3) : DDR266 (133MHz @ CL=2.5, tRCD=3, tRP=3) CC C L : Commercial Temp.( 0°C ~ 70°C) & Normal Power : Commercial Temp.( 0°C ~ 70°C) & Low Power U V Z : TSOP II *1 (Lead-Free) : sTSOP II*1 (Lead-Free) : FBGA*1 (Lead-Free) (Note 1 : All of Lead-free product are in compliance with RoHS) D. DDR SDRAM Module Ordering Information 2nd Gen. 4th Gen. 6th Gen. 8th Gen 11th Gen. A C E G J

DDR SDRAMGeneral Information December 2007 E. DDR SDRAM Module Product Guide Org. Den- sity Part Number Speed Composition Comp. Version Voltage Internal Banks External Banks PKG*1 Feature Avail. 184Pin DDR Unbuffered DIMM 32Mx 64 256MB M368L3223HUS CCC/CB3 32Mx 8 * 8pcs 256Mb H-die 2.5 ± 0.2V*3 4 66pin TSOP(II) SS,1250mil Now M368L3223JUS CCC/CB3 32Mx 8 * 8pcs 256Mb J-die 64Mx 64 512MB M368L6423HUN CCC/CB3 64Mx 8 * 16pcs 256Mb H-die DS,1250mil Now M368L6423JUN CCC/CB3 64Mx 8 * 16pcs 256Mb J-die M368L6523DUS*2 CCC/CB3 64Mx 8 * 8pcs 512Mb D-die SS,1250mil Now 128Mx 64 1GB M368L2923DUN*2 CCC/CB3 64Mx 8 * 16pcs 512Mb D-die 2 DS,1250mil Now 184Pin DDR Low Profile Registered DIMM 64Mx 72 512MB M312L6420HUS CB0 64Mx 4 * 18pcs 256Mb H-die 2.5 ± 0.2V*3 4 66pin TSOP(II) DS,1200mil Now M312L6420JUS CB0 64Mx 4 * 18pcs 256Mb J-die M312L6523DZ3*2 CCC/CB3 64Mx 8 * 9pcs 512Mb D-die 60ball FBGA SS,1125mil Now 128Mx 72 1GB M312L2920DUS*2 CB0 128Mx 4 * 18pcs 512Mb D-die 1 66pin TSOP(II) DS,1200mill Now M312L2923DZ3*2 CCC/CB3 64Mx 8 * 18pcs 512Mb D-die 2 60ball FBGA DS,1125mil Now 200Pin DDR SODIMM 32Mx 64 256MB M470L3224HU0 CB3 16Mx 16 * 8pcs 256Mb H-die 2.5 ± 0.2V*3 42 66pin TSOP(II) DS,1250mi Now M470L3224JU0 CB3 16Mx 16 * 8pcs 256Mb J-die 64Mx 64 512MB M470L6524DU0*2 CB3 32Mx 16 * 8pcs 512Mb D-die Now 128Mx 64 1GB M470L2923DV0*2 CB3 64Mx 8 * 16pcs 512Mb D-die 54pin sTSOP(II) Now Note 2 : All of DDR components support both Leaded and Lead-free. And 256Mb H-die, J- die and 512Mb D-die Lead-free is default PKG Type. U : TSOP II (Lead-Free) V : sTSOP II (Lead-Free) Z : FBGA (Lead-Free) Note 1 : (All of DDR DIMMs can support Lead-free) Note 3 : DDR400 DDR333/266 VDD/VDDQ 2.6V ± 0.1V 2.5V ± 0.2V

DDR SDRAMGeneral Information December 2007 F. Package Dimension 66Pin TSOP(II) Package Dimension (1.50) (1.50) #66 #34 #33 10.16 ± 0.10 (R 0.15) 22.22 ± 0.10 0.210 ± 0.05 0.665 ± 0.05 (R 0.15) 0.65TYP 0.30 (10°) (10°) (10.76) 0.125 +0.075 - 0.035 (10°) (10°) 11.76 ± 0.20 (0.80)(0.80) (0.50)(0.50) (4°) 0.45 ~ 0.75 (0° ∼ 8°) 0.25TYP(R 0.25) (R 0.25) ± 0.08 1.00 ± 0.10

0.05 MIN

1.20 MAX

0.10 MAX

0.075 MAX[ [

Unit : mm NOTE 1. ( ) IS REFERENCE 2. [ ] IS ASS’Y OUT QUALITY

DDR SDRAMGeneral Information December 2007 60Ball FBGA (For 256Mb) 8.0 0 ± 0.10 14.00 ± 0.10 0.35 ± 0.05 1.10 ± 0.10 8.00 ± 0.10 A B C D E F G H J K L M 0.80 0.50 1.00 x 11 = 11.00 14.00 ± 0.10 60 - ∅ 0.45 SOLDER BALL TOP VIEW BOTTOM VIEW 1.00 #A1 1.60 #A1 MARK ∅0.20 M AB (Datum A) (Datum B) 0.80 x 8 = 6.40 A B 123456789 (Post Reflow 0.50 ± 0.05) ENCAPSULANT AREA 60Ball FBGA (For 64Mb) 8.0 0 ± 0.10 12.00 ± 0.10 0.32 ± 0.05 1.10 ± 0.10 8.00 ± 0.10 A B C D E F G H J K L M 0.80 0.50 1.00 x 11 = 11.00 12.00 ± 0.10 60 - ∅ 0.45 SOLDER BALL 1.00 #A1 1.60 #A1 MARK ∅0.20 M AB 0.80 x 8 = 6.40 A 123456789 (Post Reflow 0.50 ± 0.05) Units : Millimeters (Datum A) (Datum B) B Units : Millimeters TOP VIEW BOTTOM VIEW

DDR SDRAMGeneral Information December 2007 10.00 ± 0.10 0.80 x8 = 6.40 WINDOW MOLD AREA B 5.50 1.00 x 11 = 11.00 A (Datum B) 12.00 ± 0.10 A B C D E F G H J K L M 60-∅0.45 ± 0.05 0.20M AB 1.00MAX 12.00 ± 0.10 12.00 ± 0.10 10.00 ± 0.10 #A1 0.45 ± 0.05 1.60 #A1 MARK(option) 0.80 4-CORNER MARK(option) (Datum A) (0.90)(0.90) (1.80) 0.50 3.20 60Ball FBGA (For 512Mb) 987654321 1.00

DDR SDRAMGeneral Information December 2007 For further information, semiconductor@samsung.com