M368L1624DTL

M368L1624DTL SAMSUNG | Alldatasheet

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184pin Unbuffered DDR SDRAM MODULEM368L1624DTL Rev. 0.1 May. 2002 128MB DDR SDRAM MODULE Unbuffered 184pin DIMM (16Mx64 based on 16Mx16 DDR SDRAM) 64-bit Non-ECC/Parity Revision 0.1 May. 2002

184pin Unbuffered DDR SDRAM MODULEM368L1624DTL Rev. 0.1 May. 2002

Revision History

Revision 0 (Jan. 2002) 1. First release for internal usage Revision 0.1 (May. 2002) 1.Change pin location of A13 from pin 103 to pin 167

184pin Unbuffered DDR SDRAM MODULEM368L1624DTL Rev. 0.1 May. 2002 GENERAL DESCRIPTION PIN DESCRIPTION * These pins are not used in this module. Pin Name Function A0 ~ A1 2 Address input (Multiplexed) BA0 ~ BA1 Bank Select Address DQ0 ~ DQ63 Data input/output DQS0 ~ DQS7 Data Strobe input/output CK1,CK1 , CK2, CK2 Clock input CKE0 Clock enable input CS0 Chip select input RAS Row address strobe CAS Column address strobe WE Write enable DM0 ~ DM7 Data - in mask VDD Power supply (2.5V) VDDQ Power Supply for DQS(2.5V) VSS Ground VREF Power supply for reference VDDSPD Serial EEPROM Power Supply ( 2.3V to 3.6V ) SDA Serial data I/O SCL Serial clock SA0 ~ 2 Address in EEPROM VDDID VDD identification flag NC No connection PIN CONFIGURATIONS (Front side/back side) Pin Front Pin Front Pin Front Pin Back Pin Back Pin Back VREF DQ0 VSS DQ1 DQS0 DQ2 VDD DQ3 NC NC VSS DQ8 DQ9 DQS1 VDDQ CK1 /CK1 VSS DQ10 DQ11 CKE0 VDDQ DQ16 DQ17 DQS2 VSS DQ18 VDDQ DQ19 DQ24 VSS DQ25 DQS3 VDD DQ26 DQ27 VSS *CB0 *CB1 VDD *DQS8 *CB2 VSS *CB3 BA1 DQ32 VDDQ DQ33 DQS4 DQ34 VSS BA0 DQ35 DQ40 VDDQ /WE DQ41 /CAS VSS DQS5 DQ42 DQ43 VDD */CS2 DQ48 DQ49 VSS /CK2 CK2 VDDQ DQS6 DQ50 DQ51 VSS VDDID DQ56 DQ57 VDD DQS7 DQ58 DQ59 VSS NC SDA SCL 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 VSS DQ4 DQ5 VDDQ DM0 DQ6 DQ7 VSS NC NC NC VDDQ DQ12 DQ13 DM1 VDD DQ14 DQ15 CKE1 VDDQ *BA2 DQ20 A12 VSS DQ21 A11 DM2 VDD DQ22 DQ23 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 VSS DQ28 DQ29 VDDQ DM3 DQ30 VSS DQ31 *CB4 *CB5 VDDQ *CK0 */CK 0 VSS *DM8 A10 *CB6 VDDQ *CB7 VSS DQ36 DQ37 VDD DM4 DQ38 DQ39 VSS DQ44 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 /RAS DQ45 VDDQ /CS0 */CS1 DM5 VSS DQ46 DQ47 */CS3 VDDQ DQ52 DQ53 *A13 VDD DM6 DQ54 DQ55 VDDQ NC DQ60 DQ61 VSS DM7 DQ62 DQ63 VDDQ SA0 SA1 SA2 VDDSPD SAMSUNG ELECTRONICS CO., Ltd. reserves the right to change products and specifications without notice. KEYKEY M368L1624DTL DDR SDRAM 184pin DIMM 16Mx64 DDR SDRAM 184pin DIMM based on 16Mx16 The Samsung M368L1624DTL is 16M bit x 64 Double Data Rate SDRAM high density memory modules. The Samsung M368L1624DTL consists of four CMOS 16M x 16 bit with 4banks Double Data Rate SDRAMs in 66pin TSOP- II(400mil) packages mounted on a 184pin glass-epoxy sub- strate. Four 0.1uF decoupling capacitors are mounted on the printed circuit board in parallel for each DDR SDRAM. The M368L1624DTL is Dual In-line Memory Modules and intended for mounting into 184pin edge connector sockets. Synchronous design allows precise cycle control with the use of system clock. Data I/O transactions are possible on both edges of DQS. Range of operating frequencies, programmable latencies and burst lengths allow the same device to be useful for a variety of high bandwidth, high performance memory sys- tem applications.

• Performance range
• Power supply : Vdd: 2.5V ± 0.2V, Vddq: 2.5V ± 0.2V
• Double-data-rate architecture; two data transfers per clock cycle
• Bidirectional data strobe(DQS)
• Differential clock inputs(CK and CK
• DLL aligns DQ and DQS transition with CK transition
• Programmable Read latency 2, 2.5 (clock)
• Programmable Burst length (2, 4, 8)
• Programmable Burst type (sequential & interleave)
• Edge aligned data output, center aligned data input
• Auto & Self refresh, 7.8us refresh interval(8K/64ms refresh)
• Serial presence detect with EEPROM
• PCB : Height 1250 mil, double sided component Part No. Max Freq. Interface M368L1624DTL-C(L)B3 166MHz(6ns@CL=2.5) SSTL_2M368L1624DTL-C(L)A2 133MHz(7.5ns@CL=2) M368L1624DTL-C(L)B0 133MHz(7.5ns@CL=2.5) FEATURE

184pin Unbuffered DDR SDRAM MODULEM368L1624DTL Rev. 0.1 May. 2002 FUNCTIONAL BLOCK DIAGRAM DQ8 DQ9 DQ10 DQ11 LDM I/O 6 I/O 4 I/O 1 I/O 3 DQ12 DQ13 DQ14 DQ15 I/O 2 I/O 0 I/O 5 I/O 7 UDM I/O 8 I/O 10 I/O 15 I/O 13 I/O 12 I/O 14 I/O 11 I/O 9 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ0 DQ24 DQ25 DQ26 DQ27 LDQS I/O 6 I/O 4 I/O 1 I/O 3 DQ28 DQ29 DQ30 DQ31 I/O 2 I/O 0 I/O 5 I/O 7 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 I/O 8 I/O 10 I/O 15 I/O 13 I/O 12 I/O 14 I/O 11 I/O 9 DQ56 DQ57 DQ58 DQ59 I/O 6 I/O 4 I/O 1 I/O 3 DQ60 DQ61 DQ62 DQ63 I/O 2 I/O 0 I/O 5 I/O 7 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ40 DQ41 DQ42 DQ43 I/O 6 I/O 4 I/O 1 I/O 3 DQ44 DQ45 DQ46 DQ47 I/O 2 I/O 0 I/O 5 I/O 7 I/O 8 I/O 10 I/O 15 I/O 13 I/O 12 I/O 14 I/O 11 I/O 9 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ32 I/O 8 I/O 10 I/O 15 I/O 13 I/O 12 I/O 14 I/O 11 I/O 9 DM1 CS CS CS CS LDQSDQS1 DM0 DQS0 DM3 DQS3 DM2 DQS2 DM5 DQS5 DM4 DQS4 DM6 DQS6 DM7 DQS7 UDQS LDM UDM UDQS LDM UDM LDQS UDQS A0 - A13 A0-A13: DDR SDRAMs D0 - D3 BA0 - BA1 BA0-BA1: DDR SDRAMs D0 - D3 RAS RAS: SDRAMs D0 - D3 CAS CAS: SDRAMs D0 - D3 CKE0 CKE: SDRAMs D0 - D3 WE WE : SDRAMs D0 - D3 UDM UDQS LDM LDQS Clock Wiring CK0/ CK0 Clock Input SDRAMs CK1/ CK1 NC

2 SDRAMs

CK2/CK2 Notes: 1. DQ-to-I/O wiring is shown as recom- mended but may be changed. 2. DQ/DQS/DM/CKE/ CS relationships must be maintained as shown. 3. DQ, DQS, DM/DQS resistors: 22 Ohms. CS0 Cap will replace DRAM3 *If two DRAMs are loaded, *Clock Net Wiring Card Edge Dram1 Cap Cap Dram5 Cap R=120 Ω Cap Serial PD A1 A2 SA0 SA1 SA2 SCL SDAWPVSS D0 - D3 D0 - D3 VDD /VDDQ D0 - D3 D0 - D3VREF VDDSPD SPD

184pin Unbuffered DDR SDRAM MODULEM368L1624DTL Rev. 0.1 May. 2002 Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability. POWER & DC OPERATING CONDITIONS (SSTL_2 In/Out) Notes 1. Includes ± 25mV margin for DC offset on V REF, and a combined total of ± 50mV margin for all AC noise and DC offset on V REF, bandwidth limited to 20MHz. The DRAM must accommodate DRAM current spikes on V REF and internal DRAM noise coupled TO V REF, both of which may result in V REF noise. V REF should be de-coupled with an inductance of ≤ 3nH. 2.V TT is not applied directly to the device. V TT is a system supply for signal termination resistors, is expected to be set equal to VREF, and must track variations in the DC level of V REF 3. V ID is the magnitude of the difference between the input level on CK and the input level on CK. 4. These parameters should be tested at the pin on actual components and may be checked at either the pin or the pad in simulation. The AC and DC input specifications are relative to a VREF envelop that has been bandwidth limited to 200MHZ. 5. The value of V IX is expected to equal 0.5*V DDQ of the transmitting device and must track variations in the dc level of the same. 6. These charactericteristics obey the SSTL-2 class II standards. Recommended operating conditions(Voltage referenced to V SS=0V, T A=0 to 70 °C) Parameter Symbol Min Max Unit Note Supply voltage(for device with a nominal V DD of 2.5V) VDD 2.3 2.7 I/O Supply voltage VDDQ 2.3 2.7 V I/O Reference voltage VREF VDDQ/2-50mV VDDQ/2+50mV V 1 I/O Termination voltage(system) VTT VREF-0.04 VREF+0.04 V 2 Input logic high voltage VIH(DC) VREF+0.15 VDDQ +0.3 V 4 Input logic low voltage VIL(DC) -0.3 VREF-0.15 V 4 Input Voltage Level, CK and CK inputs VIN(DC) -0.3 VDDQ +0.3 V Input Differential Voltage, CK and CK inputs VID(DC) 0.3 VDDQ +0.6 V 3 Input crossing point voltage, CK and CK inputs VIX(DC) 1.15 1.35 V 5 Input leakage current II -2 2 uA Output leakage current IOZ -5 5 uA Output High Current(Normal strengh driver) ;V OUT = VTT + 0.84V IOH -16.8 mA Output High Current(Normal strengh driver) ;V OUT = VTT - 0.84V IOL 16.8 mA Output High Current(Half strengh driver) ;V OUT = VTT + 0.45V IOH -9 mA Output High Current(Half strengh driver) ;V OUT = VTT - 0.45V IOL 9 mA Parameter Symbol Value Unit Voltage on any pin relative to V SS VIN, VOUT -0.5 ~ 3.6 V Voltage on V DD & VDDQ supply relative to V SS VDD , VDDQ -1.0 ~ 3.6 V Storage temperature TSTG -55 ~ +150 °C Power dissipation PD 6 W Short circuit current IOS 50 mA Absolute Maximum Rate

184pin Unbuffered DDR SDRAM MODULEM368L1624DTL Rev. 0.1 May. 2002 DDR SDRAM module IDD spec table * Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap. Symbol B3(DDR333@CL=2.5) A2(DDR266@CL=2) B0(DDR266@CL=2.5) Unit Notes IDD0 360 320 320 mA IDD1 500 460 460 mA IDD2P 12 12 12 mA IDD2F 100 80 80 mA IDD2Q 80 72 72 mA IDD3P 140 120 120 mA IDD3N 220 180 180 mA IDD4R 800 680 680 mA IDD4W 760 620 620 mA IDD5 720 660 660 mA IDD6 Normal 12 12 12 mA Low power 6 6 6 mA Optional IDD7A 1400 1200 1200 mA AC Operating Conditions Parameter/Condition Symbol Min Max Unit Note Input High (Logic 1) Voltage, DQ, DQS and DM signals VIH(AC) VREF + 0.31 V 3 Input Low (Logic 0) Voltage, DQ, DQS and DM signals. VIL(AC) VREF - 0.31 V 3 Input Differential Voltage, CK and CK inputs VID(AC) 0.7 VDDQ+0.6 V 1 Input Crossing Point Voltage, CK and CK inputs VIX(AC) 0.5*VDDQ-0.2 0.5*VDDQ+0.2 V 2 Note 1. VID is the magnitude of the difference between the input level on CK and the input on CK. 2. The value of V IX is expected to equal 0.5*V DDQ of the transmitting device and must track variations in the DC level of the same. 3. These parameters should be tested at the pim on actual components and may be checked at either the pin or the pad in simula - tion. the AC and DC input specificatims are refation to a Vref envelope that has been bandwidth limited 20MHz. AC OPERATING TEST CONDITIONS (VDD=2.5V, V DDQ=2.5V, T A= 0 to 70 °C) Parameter Value Unit Note Input reference voltage for Clock 0.5 * V DDQ V Input signal maximum peak swing 1.5 V Input Levels(V IH/VIL) VREF+0.3 1/VREF-0.3 1 V Input timing measurement reference level VREF V Output timing measurement reference level Vtt V Output load condition See Load Circuit

184pin Unbuffered DDR SDRAM MODULEM368L1624DTL Rev. 0.1 May. 2002 Output Load Circuit (SSTL_2) Output Z0=50 Ω CLOAD =30pF VREF =0.5*V DDQ RT =50Ω Vtt=0.5*V DDQ Input/Output CAPACITANCE (VDD=2.5V, VDDQ =2.5V, T A= 25°C, f=1MHz) Parameter Symbol Min Max Unit Input capacitance(A 0 ~ A12, BA 0 ~ BA 1,RAS,CAS, WE ) CIN1 29 34 pF Input capacitance(CKE 0) CIN2 29 34 pF Input capacitance( CS0 ) CIN3 26 30 pF Input capacitance( CLK 1, CLK 2) CIN4 30 32 pF Data & DQS input/output capacitance(DQ 0~DQ 63) COUT 8 9 pF Input capacitance(DM 0~DM 8) CIN5 8 9 pF

184pin Unbuffered DDR SDRAM MODULEM368L1624DTL Rev. 0.1 May. 2002 AC Timming Parameters & Specifications (These AC charicteristics were tested on the Component) Parameter Symbol -TCB3 (DDR333) -TCA2 (DDR266A) -TCB0 (DDR266B) Unit Note Min Max Min Max Min Max Row cycle time tRC 60 65 65 ns Refresh row cycle time tRFC 72 75 75 ns Row active time tRAS 42 70K 45 120K 45 120K ns RAS to CAS delay tRCD 18 20 20 ns Row precharge time tRP 18 20 20 ns Row active to Row active delay tRRD 12 15 15 ns Write recovery time tWR 15 15 15 ns Last data in to Read command tWTR 1 1 1 tCK Col. address to Col. address delay tCCD 1 1 1 tCK Clock cycle time CL=2.0 tCK 7.5 12 7.5 12 10 12 ns 5 CL=2.5 6 12 7.5 12 7.5 12 ns 5 Data strobe edge to ouput data edge tDQSQ - 0.45 - 0.5 - 0.5 ns 5 DQS-in setup time tWPRES 0 0 0 ns 2 DQS-in hold time tWPRE 0.25 0.25 0.25 tCK DQS falling edge to CK rising-setup time tDSS 0.2 0.2 0.2 tCK DQS falling edge from CK rising-hold time tDSH 0.2 0.2 0.2 tCK DQS-in high level width tDQSH 0.35 0.35 0.35 tCK DQS-in low level width tDQSL 0.35 0.35 0.35 tCK Address and Control Input setup time(fast) tIS 0.75 0.9 0.9 ns 6 Address and Control Input hold time(fast) tIH 0.75 0.9 0.9 ns 6 Address and Control Input setup time(slow) tIS 0.8 1.0 1.0 ns 6 Address and Control Input hold time(slow) tIH 0.8 1.0 1.0 ns 6 Input Slew Rate(for input only pins) tSL(I) 0.5 0.5 0.5 V/ns 6 Input Slew Rate(for I/O pins) tSL(IO) 0.5 0.5 0.5 V/ns 7

184pin Unbuffered DDR SDRAM MODULEM368L1624DTL Rev. 0.1 May. 2002 1. Maximum burst refresh cycle : 8 2. The specific requirement is that DQS be valid(High or Low) on or before this CK edge. The case shown(DQS going from High_Z to logic Low) applies when no writes were previously in progress on the bus. If a previous write was in progress, DQS could be High at this time, depending on tDQSS. 3. The maximum limit for this parameter is not a device limit. The device will operate with a great value for this parameter, but system performance (bus turnaround) will degrade accordingly. 4. A write command can be applied with t RCD satisfied after this command. 5. For registered DIMMs, t CL and t CH are ≥ 45% of the period including both the half period jitter (t JIT(HP) ) of the PLL and the half period jitter due to crosstalk (t JIT(crosstalk) ) on the DIMM. 6. Input Setup/Hold Slew Rate Derating This derating table is used to increase t IS/tIH in the case where the input slew rate is below 0.5V/ns. Input setup/hold slew rate based on the lesser of AC-AC slew rate and DC-DC slew rate. 7. I/O Setup/Hold Slew Rate Derating This derating table is used to increase t DS/tDH in the case where the I/O slew rate is below 0.5V/ns. I/O setup/hold slew rate based on the lesser of AC-AC slew rate and DC-DC slew rate. Parameter Symbol -TCB3 (DDR333) -TCA2 (DDR266A) -TCB0 (DDR266B) Unit Note Min Max Min Max Min Max Mode register set cycle time tMRD 12 15 15 ns DQ & DM setup time to DQS tDS 0.45 0.5 0.5 ns 7,8,9 DQ & DM hold time to DQS tDH 0.45 0.5 0.5 ns 7,8,9 Control & Address input pulse width tIPW 2.2 2.2 2.2 ns DQ & DM input pulse width tDIPW 1.75 1.75 1.75 ns Power down exit time tPDEX 6 7.5 7.5 ns Exit self refresh to non-Read command tXSNR 75 75 75 ns 4 Exit self refresh to read command tXSRD 200 200 200 tCK Refresh interval time tREFI 7.8 7.8 7.8 us 1 Output DQS valid window tQH tHP -tQHS - tHP -tQHS - tHP -tQHS - ns 5 Clock half period tHP tCLmin or tCHmin - tCLmin or tCHmin - tCLmin or tCHmin - ns Data hold skew factor tQHS 0.55 0.75 0.75 ns Active to Read with Auto precharge command tRAP 20 20 20 Autoprecharge write recovery + Precharge time tDAL (tWR/tCK) (tRP/tCK) (tWR/tCK) (tRP/tCK) (tWR/tCK) (tRP/tCK) tCK 11 Input Setup/Hold Slew Rate ΔtIS ΔtIH (V/ns) (ps) (ps) 0.5 0 0 0.4 +50 +50 0.3 +100 +100 I/O Setup/Hold Slew Rate ΔtDS ΔtDH (V/ns) (ps) (ps) 0.5 0 0 0.4 +75 +75 0.3 +150 +150

184pin Unbuffered DDR SDRAM MODULEM368L1624DTL Rev. 0.1 May. 2002 8. I/O Setup/Hold Plateau Derating This derating table is used to increase tDS/tDH in the case where the input level is flat below VREF ± 310mV for a duration of up to 2ns. 9. I/O Delta Rise/Fall Rate(1/slew-rate) Derating This derating table is used to increase t DS/tDH in the case where the DQ and DQS slew rates differ. The Delta Rise/Fall Rate is calated as 1/SlewRate1-1/SlewRate2. For example, if slew rate 1 = 5V/ns and slew rate 2 =.4V/ns then the Delta Rise/Fall Rate =-0/5ns/V. Input S/H slew rate based on larger of AC-AC delta rise/fall rate and DC-DC delta rise/fall rate. 10. This parameter is fir system simulation purpose. It is guranteed by design. 11. For each of the terms, if not already an integer, round to the next highest integer. tCK is actual to the system clock cyc le time. I/O Input Level ΔtDS ΔtDH (mV) (ps) (ps) ± 280 +50 +50 Delta Rise/Fall Rate ΔtDS ΔtDH (ns/V) (ps) (ps) 0 0 0 ±0.25 +50 +50 ±0.5 +100 +100 The following table specifies derating values for the specifications listed if the single-ended clock skew rate is less than 1.0 V/ns. CK slew rate (Single ended) ΔtIH/tIS (ps) ΔtDSS/tDSH (ps) ΔtAC/tDQSCK (ps) ΔtLZ(min) (ps) ΔtHZ(max) (ps) 1.0V/ns 0 0 0 0 0 0.75V/ns +50 +50 +50 -50 +50 0.5V/ns +100 +100 +100 -100 +100 <Reference>

184pin Unbuffered DDR SDRAM MODULEM368L1624DTL Rev. 0.1 May. 2002 Command Truth Table (V=Valid, X=Don ′t Care, H=Logic High, L=Logic Low) COMMAND CKEn-1 CKEn CS RAS CAS WE BA0,1 A10/AP A11 ,A12 A9 ~ A 0 Note Register Extended MRS H X L L L L OP CODE 1, 2 Register Mode Register Set H X L L L L OP CODE 1, 2 Refresh Auto Refresh H H L L L H X Self Refresh Entry L 3 Exit L H L H H H X H X X X 3 Bank Active & Row Addr. H X L L H H V Row Address Read & Column Address Auto Precharge Disable H X L H L H V L Column Address (A0~A8) Auto Precharge Enable H 4 Write & Column Address Auto Precharge Disable H X L H L L V L Column Address (A0~A8) Auto Precharge Enable H 4, 6 Burst Stop H X L H H L X 7 Precharge Bank Selection H X L L H L V L X All Banks X H 5 Active Power Down Entry H L H X X X XL V V V Exit L H X X X X Precharge Power Down Mode Entry H L H X X X X L H H H Exit L H H X X X L V V V DM H X X 8 No operation (NOP) : Not defined H X H X X X X L H H H 9 Note : 1. OP Code : Operand Code. A 0 ~ A12 & BA0 ~ BA 1 : Program keys. (@EMRS/MRS) 2. EMRS/ MRS can be issued only at all banks precharge state. A new command can be issued 2 clock cycles after EMRS or MRS. 3. Auto refresh functions are same as the CBR refresh of DRAM. The automatical precharge without row precharge command is meant by "Auto". Auto/self refresh can be issued only at all banks precharge state. 4. BA 0 ~ BA 1 : Bank select addresses. If both BA 0 and BA 1 are "Low" at read, write, row active and precharge, bank A is selected. If BA 0 is "High" and BA 1 is "Low" at read, write, row active and precharge, bank B is selected. If BA 0 is "Low" and BA 1 is "High" at read, write, row active and precharge, bank C is selected. If both BA 0 and BA 1 are "High" at read, write, row active and precharge, bank D is selected. 5. If A 10/AP is "High" at row precharge, BA 0 and BA 1 are ignored and all banks are selected. 6. During burst write with auto precharge, new read/write command can not be issued. Another bank read/write command can be issued after the end of burst. New row active of the associated bank can be issued at t RP after the end of burst. 7. Burst stop command is valid at every burst length. 8. DM sampled at the rising and falling edges of the DQS and Data-in are masked at the both edges (Write DM latency is 0). 9. This combination is not defined for any function, which means "No Operation(NOP)" in DDR SDRAM.

184pin Unbuffered DDR SDRAM MODULEM368L1624DTL Rev. 0.1 May. 2002 Tolerances : ± 0.005(.13) unless otherwise specified. The used device is 16Mx16 DDR SDRAM, TSOP. SDRAM Part NO : K4H561638D PACKAGE DIMENSIONS 5.25 ± 0.005 5.077 Units : Inches (Millimeters) 0.050 0.0078 ±0.006 (0.20 ±0.15)

0.100 Min

(2.30 Min) 0.393 (10.00) (1.270 ) 0.100 (2.50 ) Detail B A B (128.950) (133.350 ± 0.13 ) 0.250 (6.350 ) Detail A 0.157 (4.00 ) 0.071 (1.80) 0.039 ± 0.002 (1.000 ± 0.050) (3.80) 2.175 (6.62) (64.77) (49.53) (17.80) 2.55 1.95 0.26 2.500 0.7

0.10 M C B A

0.10 M C A

0.1496 (3.00) 0.118 R (2.00) 0.0787 (4.00) 0.1575 1.25 ± 0.006 (31.75 ±0.15) (4.00) (2X) 0.157

0.098 Max

0.050 ± 0.0039 (1.270 ± 0.10) (2.47 Max) M B (3.00) 0.118