M366S3354BTS-C7A

M366S3354BTS SAMSUNG | Alldatasheet

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Technical content

256MB, 512MB, 1GB Unbuffered DIMM Rev. 1.1 February 2004 SDRAM SDRAM Unbuffered Module 168pin Unbuffered Module based on 512Mb B-die 62/72-bit Non ECC/ECC Revision 1.1 February 2004 * Samsung Electronics reserves the right to change products or specification without notice.

256MB, 512MB, 1GB Unbuffered DIMM Rev. 1.1 February 2004 SDRAM

Revision History

Revision 0.0 (October, 2003) - First release Revision1.0 (January, 2004) - Finalized Revision 1.1 (February, 2004) - Corrected typo.

256MB, 512MB, 1GB Unbuffered DIMM Rev. 1.1 February 2004 SDRAM

Ordering Information

Part Number Density Organization Component Composition Component Package Height M366S3354BTS-C7A 256MB 32M x 64 32Mx16(K4S511632B) * 4EA 54-TSOP(II) 1,000mil M366S6553BTS-C7A 512MB 64M x 64 64Mx8(K4S510832B) * 8EA 1,375mil M374S6553BTS-C7A 512MB 64M x 72 64Mx8(K4S510832B) * 9EA 1,375mil M366S2953BTS-C7A 1GB 128M x 64 64Mx8(K4S510832B)*16EA 1,375mil M374S2953BTS-C7A 1GB 128M x 72 64Mx8(K4S510832B)*18EA 1,375mil @CL3 @CL2 Maximum Clock Frequency 133MHz(7.5ns) 100MHz(10ns) CL-tRCD-tRP(clock) 3 - 3 - 3 2 - 2 - 2 Feature

• Burst mode operation
• Auto & self refresh capability (8192 Cycles/64ms)
• LVTTL compatible inputs and outputs Single 3.3V ± 0.3V power supply
• MRS cycle with address key programs Latency (Access from column address) Burst length (1, 2, 4, 8) Data scramble (Sequential & Interleave) All inputs are sampled at the positive going edge of the system clock
• Serial presence detect with EEPROM 168Pin Unbuffered DIMM based on 512Mb B-die (x8, x16)

256MB, 512MB, 1GB Unbuffered DIMM Rev. 1.1 February 2004 SDRAM * SAMSUNG ELECTRONICS CO., Ltd. reserves the right to change products and specifications without notice. PIN CONFIGURATIONS (Front side/back side) Pin Front VSS DQ0 DQ1 DQ2 DQ3 VDD DQ4 DQ5 DQ6 DQ7 DQ8 VSS DQ9 DQ10 DQ11 DQ12 DQ13 VDD DQ14 DQ15 CB0 CB1 VSS NC NC VDD WE DQM0 Pin Front DQM1 CS0 DU VSS A10/AP BA1 VDD VDD CLK0 VSS DU **CS2 DQM2 DQM3 DU VDD NC NC CB2 CB3 VSS DQ16 DQ17 Pin Front DQ18 DQ19 VDD DQ20 NC *VREF CKE1 VSS DQ21 DQ22 DQ23 VSS DQ24 DQ25 DQ26 DQ27 VDD DQ28 DQ29 DQ30 DQ31 VSS CLK2 NC NC SDA SCL VDD Pin 100 101 102 103 104 105 106 107 108 109 110 111 112 Back VSS DQ32 DQ33 DQ34 DQ35 VDD DQ36 DQ37 DQ38 DQ39 DQ40 VSS DQ41 DQ42 DQ43 DQ44 DQ45 VDD DQ46 DQ47 CB4 CB5 VSS NC NC VDD CAS DQM4 Pin 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 Back DQM5 CS1 RAS VSS BA0 A11 VDD CLK1 A12 VSS CKE0 CS3 DQM6 DQM7 *A13 VDD NC NC CB6 CB7 VSS DQ48 DQ49 Pin 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 Back DQ50 DQ51 VDD DQ52 NC *VREF REGE VSS DQ53 DQ54 DQ55 VSS DQ56 DQ57 DQ58 DQ59 VDD DQ60 DQ61 DQ62 DQ63 VSS **CLK3 NC SA0 SA1 SA2 VDD 1. * These pins are not used in this module. 2. Pins 82,83,165,166,167 should be NC in the system which does not support SPD. 3. Pins 21,22,52,53,105,106,136,137are used only ECC(x72) Module. 4. ** About these pins, Refer to the Block Diagram of each. Note : Pin Description Pin Name Function Pin Name Function A0 ~ A12 Address input (Multiplexed) DQM0 ~ 7 DQM BA0 ~ BA1 Select bank V DD Power supply (3.3V) DQ0 ~ DQ63 Data input/output V SS Ground CB0 ~ CB7 Check bit (Data-in/data-out) V REF Power supply for reference CLK0 ~ 3 Clock input REGE Register enable CKE0, CKE1 Clock enable input SDA Serial data I/O CS0 ~ CS3 Chip select input SCL Serial clock RAS Row address strobe SA0 ~ 2 Address in EEPROM CAS Colume address strobe DU Don ′t use WE Write enable NC No connection

256MB, 512MB, 1GB Unbuffered DIMM Rev. 1.1 February 2004 SDRAM PIN CONFIGURATION DESCRIPTION Pin Name Input Function CLK System clock Active on the positive going edge to sample all inputs. CS Chip select Disables or enables device operation by masking or enabling all inputs except CLK, CKE and DQM CKE Clock enable Masks system clock to freeze operation from the next clock cycle. CKE should be enabled at least one cycle prior to new command. Disable input buffers for power down in standby. CKE should be enabled 1CLK+tss prior to valid command. A0 ~ A12 Address Row/column addresses are multiplexed on the same pins. Row address : RA0 ~ RA12 Column address : (x8 : CA0 ~ CA9, CA11), (x16 : CA0 ~ CA9) BA0 ~ BA1 Bank select address Selects bank to be activated during row address latch time. Selects bank for read/write during column address latch time. RAS Row address strobe Latches row addresses on the positive going edge of the CLK with RAS low. Enables row access & precharge. CAS Column address strobe Latches column addresses on the positive going edge of the CLK with CAS low. Enables column access. WE Write enable Enables write operation and row precharge. Latches data in starting from CAS, WE active. DQM0 ~ 7 Data input/output mask Makes data output Hi-Z, tSHZ after the clock and masks the output. Blocks data input when DQM active. (Byte masking) REGE Register enable The device operates in the transparent mode when REGE is low. When REGE is high, the device operates in the registered mode. In registered mode, the Address and con- trol inputs are latched if CLK is held at a high or low logic level. the inputs are stored in the latch/flip-flop on the rising edge of CLK. REGE is tied to VDD through 10K ohm Resistor on PCB. So if REGE of module is floating, this module will be operated as reg- istered mode. DQ0 ~ 63 Data input/output Data inputs/outputs are multiplexed on the same pins. CB0 ~ 7 Check bit Check bits for ECC. VDD/VSS Power supply/ground Power and ground for the input buffers and the core logic.

256MB, 512MB, 1GB Unbuffered DIMM Rev. 1.1 February 2004 SDRAM 256MB, 32Mx64 Module (M366S3354BTS) (Populated as 1 bank of x16 SDRAM Module) FUNCTIONAL BLOCK DIAGRAM DQM4 CS0 DQM0 DQM1 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 LDQM CS UDQM DQM5 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 LDQM CS UDQM A0 ~ A12, BA0 & 1 CKE0 RAS CAS WE SDRAM U0 ~ U3 SDRAM U0 ~ U3 SDRAM U0 ~ U3 SDRAM U0 ~ U3 SDRAM U0 ~ U3 10Ω DQn Every DQpin of SDRAM DQM6 CS2 DQM2 DQM3 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 LDQM CS UDQM DQM7 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ57 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 LDQM CS VDD Vss Two 0.1uF per each SDRAM To all SDRAMs Capacitors CLK1/3 U0/U210Ω CLK0/2 10Ω U1/U3 15pF 10pF Serial PD SDASCL A1 A2A0 SA1 SA2SA0 WP 47KΩ UDQM

256MB, 512MB, 1GB Unbuffered DIMM Rev. 1.1 February 2004 SDRAM FUNCTIONAL BLOCK DIAGRAM 512MB,64Mx64 Non ECC Module(M366S6553BTS)(Populated as 1 bank of x8 SDRAM Module) VDD Vss A0 ~ A12, BA0 & 1 CKE0 RAS CAS WE SDRAM U0 ~ U7 SDRAM U0 ~ U7 SDRAM U0 ~ U7 SDRAM U0 ~ U7 SDRAM U0 ~ U7 10Ω DQn Every DQpin of SDRAM DQM0 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQM CS CS0 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQM CS DQM1 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQM CS DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQM CS DQM5 DQM4 DQM2 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQM CS CS2 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQM CS DQM3 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQM CS DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 DQM CS DQM7 DQM6 One 0.1uF and one 0.22 uF Cap. per each SDRAM To all SDRAMs Serial PD SDASCL A1 A2A0 SA1 SA2SA0 WP 47KΩ CLK2/3 10Ω 10pF U0/U2 U4/U610Ω CLK0/2 U1/U3 U5/U7 3.3pF*1

256MB, 512MB, 1GB Unbuffered DIMM Rev. 1.1 February 2004 SDRAM FUNCTIONAL BLOCK DIAGRAM 512MB, 64Mx72 ECC Module (M374S6553BTS) (Populated as 1 bank of x8 SDRAM Module) VDD Vss One 0.1uF and one 0.22 uF Cap. per each SDRAM To all SDRAMs A0 ~ A12, BA0 & 1 CKE0 RAS CAS WE SDRAM U0 ~ U8 SDRAM U0 ~ U8 SDRAM U0 ~ U8 SDRAM U0 ~ U8 SDRAM U0 ~ U8 10Ω DQn Every DQpin of SDRAM

• • CLK1/3 10Ω 10pF U0/U3 U5/U710Ω CLK0/2 U1/U4 U6/U8 3.3pF*1 *1 : For 4 loads, CLK2 only. Serial PD SDASCL A1 A2A0 SA1 SA2SA0 WP 47KΩ DQM1 DQM5 DQM3 DQM2 CS2 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQM CS DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQM CS DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQM CS DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQM CS DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7 DQM CS DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQM CS DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQM CS DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 DQM CS DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQM CS DQM0 CS0 DQM4 DQM6 DQM7

256MB, 512MB, 1GB Unbuffered DIMM Rev. 1.1 February 2004 SDRAM FUNCTIONAL BLOCK DIAGRAM 1GB, 128Mx64 Non ECC Module (M366S2953BTS) (Populated as 2 bank of x8 SDRAM Module) A0 ~ A12, BA0 & 1 CKE0 RAS CAS WE SDRAM U0 ~ U15 SDRAM U0 ~ U15 SDRAM U0 ~ U15 SDRAM U0 ~ U15 SDRAM U0 ~ U7 10Ω DQn Every DQpin of SDRAM CKE1 SDRAM U8 ~ U15 10KΩ VDD VDD Vss Two 0.1uF Capacitors per each SDRAM To all SDRAMs U0/U1/U2/U3 U4/U5/U6/U710Ω CLK0/1/2/3 U8/U9/U10/U11 U12/U13/U14/U15 3.3pF Serial PD SDASCL A1 A2A0 SA1 SA2SA0 WP 47KΩ DQM0 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQM CS CS0 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQM CS DQM1 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQM CS DQ1 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQM CS DQM5 DQM4 DQM2 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQM CS CS2 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQM CS DQM3 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQM CS DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 DQM CS DQM7 DQM6 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQM CS DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQM CS DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 U10 DQM CS DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 U11 DQM CS DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 U12 DQM CS DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 U13 DQM CS DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 U14 DQM CS DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 U15 DQM CS CS1 CS3

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256MB, 512MB, 1GB Unbuffered DIMM Rev. 1.1 February 2004 SDRAM FUNCTIONAL BLOCK DIAGRAM 1GB, 128Mx72 ECC Module (M374S2953BTS) (Populated as 2 bank of x8 SDRAM Module) A0 ~ A12, BA0 & 1 CKE0 RAS CAS WE SDRAM U0 ~ U17 SDRAM U0 ~ U17 SDRAM U0 ~ U17 SDRAM U0 ~ U17 SDRAM U0 ~ U8 10Ω DQn Every DQpin of SDRAM CKE1 SDRAM U9 ~ U17 10KΩ VDD DQM1 DQM5 DQM3 DQM2 CS2 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQM CS DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQM CS DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQM CS DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQM CS DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7 DQM CS DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQM CS DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQM CS DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 DQM CS DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQM CS DQM0 CS0 DQM4 DQM6 DQM7 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQM CS DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 U10 DQM CS DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 U11 DQM CS DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 U14 DQM CS DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 U15 DQM CS DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 U16 DQM CS DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 U17 DQM CSDQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 U12 DQM CS DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 U13 DQM CS CS1 CS3 VDD Vss Two 0.1uF Capacitors per each SDRAM To all SDRAMs U1/U3/U0/U4 U6/U7/U5/U810Ω CLK0/1/2/3 U10/U12/U9/U13 U15/U16/U14/U17 3.3pF*1 U2/U11 *1 : For 4 loads, CLK2 & CLK3 only. Serial PD SDASCL A1 A2A0 SA1 SA2SA0 WP 47KΩ

256MB, 512MB, 1GB Unbuffered DIMM Rev. 1.1 February 2004 SDRAM ABSOLUTE MAXIMUM RATINGS Parameter Symbol Value Unit Voltage on any pin relative to Vss V IN, VOUT -1.0 ~ 4.6 V Voltage on VDD supply relative to Vss V DD, VDDQ -1.0 ~ 4.6 V Storage temperature T STG -55 ~ +150 °C Power dissipation P D 1.0 * # of component W Short circuit current I OS 50 mA Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability. Note : DC OPERATING CONDITIONS AND CHARACTERISTICS Recommended operating conditions (Voltage referenced to VSS = 0V, TA = 0 to 70°C) Parameter Symbol Min Typ Max Unit Note Supply voltage V DD 3.0 3.3 3.6 V Input high voltage V IH 2.0 3.0 V DDQ+0.3 V 1 Input low voltage V IL -0.3 0 0.8 V 2 Output high voltage V OH 2.4 - - V I OH = -2mA Output low voltage V OL -- 0 . 4 V I OL = 2mA Input leakage current I LI -10 - 10 uA 3 1. VIH (max) = 5.6V AC.The overshoot voltage duration is ≤ 3ns. 2. VIL (min) = -2.0V AC. The undershoot voltage duration is ≤ 3ns. 3. Any input 0V ≤ VIN ≤ VDDQ. Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs. Notes : CAPACITANCE (VDD = 3.3V, TA = 23°C, f = 1MHz, VREF = 1.4V ± 200 mV) Parameter Sym- bol M366S3354BTS M366S6553BTS M366S2953TS UnitMin Max Min Max Min Max Input capacitance (A0 ~ A12) Input capacitance (RAS, CAS, WE) Input capacitance (CKE) Input capacitance (CLK) Input capacitance (CS) Input capacitance (DQM0 ~ DQM7) Data input/output capacitance (DQ0 ~ DQ63) CIN1 CIN2 CIN3 CIN4 CIN5 CIN6 COUT pF pF pF pF pF pF pF Pin Sym- bol M374S6553BTS M374S2953BTS UnitMin Max Min Max Input capacitance (A0 ~ A12) Input capacitance (RAS, CAS, WE) Input capacitance (CKE) Input capacitance (CLK) Input capacitance (CS) Input capacitance (DQM0 ~ DQM7) Data input/output capacitance (DQ0 ~ DQ63) CIN1 CIN2 CIN3 CIN4 CIN5 CIN6 COUT pF pF pF pF pF pF pF

256MB, 512MB, 1GB Unbuffered DIMM Rev. 1.1 February 2004 SDRAM DC CHARACTERISTICS (Recommended operating condition unless otherwise noted, TA = 0 to 70°C) Parameter Symbol Test Condition Version Unit Note7A Operating current (One bank active) ICC1 Burst length = 1 tRC ≥ tRC(min) IO = 0 mA 400 mA 1 Precharge standby current in power-down mode ICC2P CKE ≤ VIL(max), tCC = 10ns 8 mAICC2PS CKE & CLK ≤ VIL(max), tCC =∞ 8 Precharge standby current in non power-down mode ICC2N CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns Input signals are changed one time during 20ns 80 mA ICC2NS CKE ≥ VIH(min), CLK ≤ VIL(max), tCC =∞ Input signals are stable 40 Active standby current in power-down mode ICC3P CKE ≤ VIL(max), tCC = 10ns 25 mAICC3PS CKE & CLK ≤ VIL(max), tCC =∞ 25 Active standby current in non power-down mode (One bank active) I CC3N CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns Input signals are changed one time during 20ns 120 mA ICC3NS CKE ≥ VIH(min), CLK ≤ VIL(max), tCC =∞ Input signals are stable 100 mA Operating current (Burst mode) ICC4 IO = 0 mA Page burst 4Banks activated t CCD = 2CLKs 520 mA 1 Refresh current I CC5 tRC ≥ tRC(min) 800 mA 2 Self refresh current I CC6 CKE ≤ 0.2V 12 mA M366S3354BTS (32M x 64,256MB Module) (Recommended operating condition unless otherwise noted, TA = 0 to 70°C) Parameter Symbol Test Condition Version Unit Note7A Operating current (One bank active) ICC1 Burst length = 1 tRC ≥ tRC(min) IO = 0 mA 720 mA 1 Precharge standby current in power-down mode ICC2P CKE ≤ VIL(max), tCC = 10ns 16 mAICC2PS CKE & CLK ≤ VIL(max), tCC =∞ 16 Precharge standby current in non power-down mode ICC2N CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns Input signals are changed one time during 20ns 160 mA ICC2NS CKE ≥ VIH(min), CLK ≤ VIL(max), tCC =∞ Input signals are stable 80 Active standby current in power-down mode ICC3P CKE ≤ VIL(max), tCC = 10ns 50 mAICC3PS CKE & CLK ≤ VIL(max), tCC =∞ 50 Active standby current in non power-down mode (One bank active) I CC3N CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns Input signals are changed one time during 20ns 240 mA ICC3NS CKE ≥ VIH(min), CLK ≤ VIL(max), tCC =∞ Input signals are stable 200 mA Operating current (Burst mode) ICC4 IO = 0 mA Page burst 4Banks activated t CCD = 2CLKs 800 mA 1 Refresh current I CC5 tRC ≥ tRC(min) 1,600 mA 2 Self refresh current I CC6 CKE ≤ 0.2V 24 mA M366S6553BTS (64M x 64, 512MB Module) Notes : 1. Measured with outputs open. 2. Refresh period is 64ms.

256MB, 512MB, 1GB Unbuffered DIMM Rev. 1.1 February 2004 SDRAM M374S6553ETS (64M x 72, 512MB Module) DC CHARACTERISTICS (Recommended operating condition unless otherwise noted, TA = 0 to 70°C) Parameter Symbol Test Condition Version Unit Note7A Operating current (One bank active) ICC1 Burst length = 1 tRC ≥ tRC(min) IO = 0 mA 810 mA 1 Precharge standby current in power-down mode ICC2P CKE ≤ VIL(max), tCC = 10ns 18 mAICC2PS CKE & CLK ≤ VIL(max), tCC =∞ 18 Precharge standby current in non power-down mode ICC2N CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns Input signals are changed one time during 20ns 180 mA ICC2NS CKE ≥ VIH(min), CLK ≤ VIL(max), tCC =∞ Input signals are stable 90 Active standby current in power-down mode ICC3P CKE ≤ VIL(max), tCC = 10ns 55 mAICC3PS CKE & CLK ≤ VIL(max), tCC =∞ 55 Active standby current in non power-down mode (One bank active) I CC3N CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns Input signals are changed one time during 20ns 270 mA ICC3NS CKE ≥ VIH(min), CLK ≤ VIL(max), tCC =∞ Input signals are stable 225 mA Operating current (Burst mode) ICC4 IO = 0 mA Page burst 4Banks activated t CCD = 2CLKs 900 mA 1 Refresh current I CC5 tRC ≥ tRC(min) 1,800 mA 2 Self refresh current I CC6 CKE ≤ 0.2V 27 mA (Recommended operating condition unless otherwise noted, TA = 0 to 70°C) Parameter Symbol Test Condition Version Unit Note7A Operating current (One bank active) ICC1 Burst length = 1 tRC ≥ tRC(min) IO = 0 mA 960 mA 1 Precharge standby current in power-down mode ICC2P CKE ≤ VIL(max), tCC = 10ns 32 mAICC2PS CKE & CLK ≤ VIL(max), tCC =∞ 32 Precharge standby current in non power-down mode ICC2N CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns Input signals are changed one time during 20ns 320 mA ICC2NS CKE ≥ VIH(min), CLK ≤ VIL(max), tCC =∞ Input signals are stable 160 Active standby current in power-down mode ICC3P CKE ≤ VIL(max), tCC = 10ns 100 mAICC3PS CKE & CLK ≤ VIL(max), tCC =∞ 100 Active standby current in non power-down mode (One bank active) I CC3N CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns Input signals are changed one time during 20ns 480 mA ICC3NS CKE ≥ VIH(min), CLK ≤ VIL(max), tCC =∞ Input signals are stable 400 mA Operating current (Burst mode) ICC4 IO = 0 mA Page burst 4Banks activated t CCD = 2CLKs 1,040 mA 1 Refresh current I CC5 tRC ≥ tRC(min) 1,840 mA 2 Self refresh current I CC6 CKE ≤ 0.2V 48 mA M366S2953BTS (128M x 64, 1GB Module) Notes : 1. Measured with outputs open. 2. Refresh period is 64ms.

256MB, 512MB, 1GB Unbuffered DIMM Rev. 1.1 February 2004 SDRAM (Recommended operating condition unless otherwise noted, TA = 0 to 70°C) Parameter Symbol Test Condition Version Unit Note7A Operating current (One bank active) ICC1 Burst length = 1 tRC ≥ tRC(min) IO = 0 mA 1,080 mA 1 Precharge standby current in power-down mode ICC2P CKE ≤ VIL(max), tCC = 10ns 36 mAICC2PS CKE & CLK ≤ VIL(max), tCC =∞ 36 Precharge standby current in non power-down mode ICC2N CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns Input signals are changed one time during 20ns 360 mA ICC2NS CKE ≥ VIH(min), CLK ≤ VIL(max), tCC =∞ Input signals are stable 180 Active standby current in power-down mode ICC3P CKE ≤ VIL(max), tCC = 10ns 110 mAICC3PS CKE & CLK ≤ VIL(max), tCC =∞ 110 Active standby current in non power-down mode (One bank active) I CC3N CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns Input signals are changed one time during 20ns 540 mA ICC3NS CKE ≥ VIH(min), CLK ≤ VIL(max), tCC =∞ Input signals are stable 450 mA Operating current (Burst mode) ICC4 IO = 0 mA Page burst 4Banks activated t CCD = 2CLKs 1,170 mA 1 Refresh current I CC5 tRC ≥ tRC(min) 2,070 mA 2 Self refresh current I CC6 CKE ≤ 0.2V 54 mA M374S2953BTS (128M x 72, 1GB Module) Notes : 1. Measured with outputs open. 2. Refresh period is 64ms. DC CHARACTERISTICS

256MB, 512MB, 1GB Unbuffered DIMM Rev. 1.1 February 2004 SDRAM 3.3V 1200Ω 870Ω Output 50pF VOH (DC) = 2.4V, IOH = -2mA VOL (DC) = 0.4V, IOL = 2mA Vtt = 1.4V 50Ω Output 50pF Z0 = 50Ω (Fig. 2) AC output load circuit (Fig. 1) DC output load circuit AC OPERATING TEST CONDITIONS (VDD = 3.3V ± 0.3V, TA = 0 to 70°C) Parameter Value Unit AC input levels (Vih/Vil) 2.4/0.4 V Input timing measurement reference level 1.4 V Input rise and fall time tr/tf = 1/1 ns Output timing measurement reference level 1.4 V Output load condition See Fig. 2 OPERATING AC PARAMETER Notes : (AC operating conditions unless otherwise noted) Parameter Symbol Version Unit Note Row active to row active delay t RRD(min) 15 ns 1 RAS to CAS delay t RCD(min) 20 ns 1 Row precharge time t RP(min) 20 ns 1 Row active time tRAS(min) 45 ns 1 tRAS(max) 100 us Row cycle time t RC(min) 65 ns 1 Last data in to row precharge t RDL(min) 2 CLK 2 Last data in to Active delay t DAL(min) 2 CLK + tRP - Last data in to new col. address delay t CDL(min) 1 CLK 2 Last data in to burst stop t BDL(min) 1 CLK 2 Col. address to col. address delay t CCD(min) 1 CLK 3 Number of valid output data CAS latency=3 2 ea 4 CAS latency=2 1 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then rounding off to the next higher integer. 2. Minimum delay is required to complete write. 3. All parts allow every cycle column address change. 4. In case of row precharge interrupt, auto precharge and read burst stop.

256MB, 512MB, 1GB Unbuffered DIMM Rev. 1.1 February 2004 SDRAM 1. Parameters depend on programmed CAS latency. 2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter. 3. Assumed input rise and fall time (tr & tf) = 1ns. If tr & tf is longer than 1ns, transient time compensation should be considered, i.e., [(tr + tf)/2-1]ns should be added to the parameter. Notes : AC CHARACTERISTICS (AC operating conditions unless otherwise noted) Parameter Symbol Unit Note Min Max CLK cycle time CAS latency=3 tCC 7.5 1000 ns 1 CAS latency=2 10 CLK to valid output delay CAS latency=3 tSAC 5.4 ns 1,2 CAS latency=2 6 Output data hold time CAS latency=3 tOH ns 2 CAS latency=2 3 CLK high pulse width t CH 2.5 ns 3 CLK low pulse width t CL 2.5 ns 3 Input setup time t SS 1.5 ns 3 Input hold time t SH 0.8 ns 3 CLK to output in Low-Z t SLZ 1n s 2 CLK to output in Hi-Z CAS latency=3 tSHZ 5.4 ns CAS latency=2 6 REFER TO THE INDIVIDUAL COMPONENET, NOT THE WHOLE MODULE.

256MB, 512MB, 1GB Unbuffered DIMM Rev. 1.1 February 2004 SDRAM SIMPLIFIED TRUTH TABLE (V=Valid, X=Don′t care, H=Logic high, L=Logic low) Command CKEn-1 CKEn CS RAS CAS WE DQM BA0,1 A10/AP A0 ~ A9, A11, A12 Note Register Mode register set H X L L L L X OP code 1,2 Refresh Auto refresh H H LL LHX X Self refresh Entry L 3 Exit L H LH HH XX HX XX 3 Bank active & row addr. H X L L H H X V Row address Read & column address Auto precharge disable HX L H L H X V L Column address Auto precharge enable H 4,5 Write & column address Auto precharge disable H XL HLLX V L Column address Auto precharge enable H 4,5 Burst stop H X L H H L X X 6 Precharge Bank selection HX L L H L X VL X All banks XH Clock suspend or active power down Entry H L HX XX X XLV VV Exit L H X X X X X Precharge power down mode Entry H L HX XX X X LH HH Exit L H HX XX X LV VV DQM H V X 7 No operation command H X HX XX XX LH HH 1. OP Code : Operand code A0 ~ A12 & BA0 ~ BA1 : Program keys. (@ MRS) 2. MRS can be issued only at all banks precharge state. A new command can be issued after 2 clock cycles of MRS. 3. Auto refresh functions are as same as CBR refresh of DRAM. The automatical precharge without row precharge command is meant by "Auto". Auto/self refresh can be issued only at all banks precharge state. 4. BA 0 ~ BA1 : Bank select addresses. If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected. If BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank B is selected. If BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank C is selected. If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected. If A10/AP is "High" at row precharge, BA0 and BA1 is ignored and all banks are selected. 5. During burst read or write with auto precharge, new read/write command can not be issued. Another bank read/write command can be issued after the end of burst. New row active of the associated bank can be issued at tRP after the end of burst. 6. Burst stop command is valid at every burst length. 7. DQM sampled at positive going edge of a CLK and masks the data-in at the very CLK (Write DQM latency is 0), but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2) Notes : X

256MB, 512MB, 1GB Unbuffered DIMM Rev. 1.1 February 2004 SDRAM PACKAGE DIMENSIONS : 32Mx64 (M366S3354BTS) 0.250 (6.350) Detail A 0.123 ± 0.005 (3.125 ± 0.125) 0.250 (6.350) Detail B 0.123 ± 0.005 (3.125 ± 0.125) 0.079 ± 0.004 (2.000 ± 0.100) 0.079 ± 0.004 (2.000 ± 0.100) Tolerances : ± .005(.13) unless otherwise specified The used device is 32Mx16 SDRAM, TSOPII SDRAM Part No. : K4S511632B 0.050 0.039 ± 0.002 0.008 ±0.006 (0.200 ±0.150) (1.000 ± 0.050) (1.270) Detail C

0.100 Max

0.050 ± 0.0039 (1.270 ± 0.10)

0.200 Min

(5.08 Min) (2.54 Max) 5.250 5.014 Units : Inches (Millimeters) R 0.079 (R 2.000) 0.250 (6.350) 1.450 (36.830) 2.150 (54.61) 0.118 (3.000) 0.350 0.700 (17.780) (8.890) A B C 0.250 (6.350) .450 (11.430) 4.550 (115.57) 0.157 ± 0.004 (4.000 ± 0.100) (127.350) (133.350) 1.000 (25.40) 0.118 (3.000) 0.0984 ±0.008 (2.500 ±0.2) (2.500 ±0.2) 0.0984 ±0.008

256MB, 512MB, 1GB Unbuffered DIMM Rev. 1.1 February 2004 SDRAM PACKAGE DIMENSIONS : 64Mx64 (M366S6553BTS) 0.050 ± 0.0039 (1.270 ± 0.10) 0.250 (6.350) Detail A 0.123 ± 0.005 (3.125 ± 0.125) 0.250 (6.350) Detail B 0.123 ± 0.005 (3.125 ± 0.125) 0.079 ± 0.004 (2.000 ± 0.100) 0.079 ± 0.004 (2.000 ± 0.100)

0.165 Min

(4.19 Min) (2.54 Max) Tolerances : ± .005(.13) unless otherwise specified The used device is 64Mx8 SDRAM, TSOPII SDRAM Part No. : K4S510832B 5.250 5.014 Units : Inches (Millimeters) R 0.079 (R 2.000) 0.250 (6.350) 1.450 (36.830) 2.150 (54.61) 0.118 (3.000) 0.350 0.700 (17.780) (8.890) A B C 0.250 (6.350) .450 (11.430) 4.550 (115.57) 0.157 ± 0.004 (4.000 ± 0.100) 0.089 (2.26) (127.350) (133.350) 1.375 (34.925) 0.118 (3.000) 0.050 0.039 ± 0.002 0.008 ±0.006 (0.200 ±0.150) (1.000 ± 0.050) (1.270) Detail C 0.0984 ±0.008 (2.500 ±0.2) (2.500 ±0.2) 0.0984 ±0.008

256MB, 512MB, 1GB Unbuffered DIMM Rev. 1.1 February 2004 SDRAM PACKAGE DIMENSIONS : 64Mx72 (M374S6553BTS) 0.050 ± 0.0039 (1.270 ± 0.10) 0.250 (6.350) Detail A 0.123 ± .005 (3.125 ± .125) 0.250 (6.350) Detail B 0.123 ± .005 (3.125 ± .125) 0.079 ± .004 (2.000 ± .100) 0.079 ± .004 (2.000 ± .100) (4.19 Min) (2.54 Max) Tolerances : ± .005(.13) unless otherwise specified The used device is 64Mx8 SDRAM, TSOPII SDRAM Part No. : K4S510832B 5.250 5.014 Units : Inches (Millimeters) R 0.079 (R 2.000) 0.250 (6.350) 1.450 (36.830) 2.150 (54.61) 0.118 (3.000) 0.350 0.700 (17.780) (8.890) A B C 0.250 (6.350) .450 (11.430) 4.550 (115.57) 0.157 ± 0.004 (4.000 ± 0.100) 0.089 (2.26) (127.350) (133.350) 1.375 (34.925) 0.118 (3.000) 0.050 0.039 ± 0.002 0.008 ±0.006 (0.200 ±0.150) (1.000 ± 0.050) (1.270) Detail C 0.0984 ±0.008 (2.500 ±0.2) (2.500 ±0.2) 0.0984 ±0.008

256MB, 512MB, 1GB Unbuffered DIMM Rev. 1.1 February 2004 SDRAM PACKAGE DIMENSIONS : 128Mx64 (M366S2953BTS)

0.150 Max

0.050 ± 0.0039 (1.270 ± 0.10) 0.250 (6.350) Detail A 0.123 ± 0.005 (3.125 ± 0.125) 0.250 (6.350) Detail B 0.123 ± 0.005 (3.125 ± 0.125) 0.079 ± 0.004 (2.000 ± 0.100) 0.079 ± 0.004 (2.000 ± 0.100) (4.19 Min) (3.81 Max) Tolerances : ± .005(.13) unless otherwise specified The used device is 64Mx8 SDRAM, TSOPII SDRAM Part No. : K4S510832B 5.250 5.014 Units : Inches (Millimeters) R 0.079 (R 2.000) 0.250 (6.350) 1.450 (36.830) 2.150 (54.61) 0.118 (3.000) 0.350 0.700 (17.780) (8.890) A B C 0.250 (6.350) .450 (11.430) 4.550 (115.57) 0.157 ± 0.004 (4.000 ± 0.100) (127.350) (133.350) 1.375 (34.925) 0.118 (3.000) 0.050 0.039 ± 0.002 0.008 ± 0.006 (0.200 ± 0.150) (1.000 ± 0.050) (1.270) Detail C 0.0984 ±0.008 (2.500 ±0.2) (2.500 ±0.2) 0.0984 ±0.008

256MB, 512MB, 1GB Unbuffered DIMM Rev. 1.1 February 2004 SDRAM PACKAGE DIMENSIONS : 128Mx72 (M374S2953BTS) 0.050 ± 0.0039 (1.270 ± 0.10) 0.250 (6.350) Detail A 0.123 ± 0.005 (3.125 ± 0.125) 0.250 (6.350) Detail B 0.123 ± 0.005 (3.125 ± 0.125) 0.079 ± 0.004 (2.000 ± 0.100) 0.079 ± 0.004 (2.000 ± 0.100) (4.19 Min) (3.81 Max) Tolerances : ± 0.005(.13) unless otherwise specified The used device is 64Mx8 SDRAM, TSOPII SDRAM Part No. : K4S510832B 5.250 5.014 Units : Inches (Millimeters) R 0.079 (R 2.000) 0.250 (6.350) 1.450 (36.830) 2.150 (54.61) 0.118 (3.000) 0.350 0.700 (17.780) (8.890) A B C 0.250 (6.350) .450 (11.430) 4.550 (115.57) 0.157 ± 0.004 (4.000 ± 0.100) (127.350) (133.350) 1.375 (34.925) 0.118 (3.000) 0.050 0.039 ± 0.002 0.008 ±0.006 (0.200 ±0.150) (1.000 ± 0.050) (1.270) Detail C 0.0984 ±0.008 (2.500 ±0.2) (2.500 ±0.2) 0.0984 ±0.008