M366S3323CT0

M366S3323CT0-C75 SAMSUNG | Alldatasheet

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M366S3323CTO PC133 Unbuffered DIMM M366$83323CT0 SDRAM DIMM 32Mx64 SDRAM DIMM based on 16Mx8, 4Banks, 4K Refresh, 3.3V Synchronous DRAMs with SPD GENERAL DESCRIPTION FEATURE ‘The Samsung M366S3323CTO Is a 32M bit x 64 Synchronous + Performance range Mecceasetena cantile a) tulony ohloe tahhn 8 oh ait [ PartNo. MaxFroq.(speeq) | eee oon hice wm aeonn debne esta. ane Hsearsmeacrs tremger setamas | [ Po1s3@CL3 & Pctod@ct | 4panks Synchronous DRAMS In TSOP-II 400ml package and a [_wa6eSS325CT0-C75 | PCIS2@CL3 & PCICOBCLS 2K EEPROM In 8-pin TSSOP package on a 168-pin glass-epoxy + Burst mode operation substrate. Two 0.1uF decoupling capacitors are mounted on the * Auto & Sef refresn capability (4096 Cycies/64ms) printed circult board in parallel for each SDRAM. + LVTTL compatible Inputs and outputs The M366S3323CTO Is a Dual In-line Memory Module anc Is * Single 3.3V = 0.3v power supply Intended for mounting into 166-pin edge connector sockets. * MRS cycie with adaress key programs ‘Synchronous design allows precise cycle control with the use of Latency (Access from column address) system clock. I/O transactions are possible on every clock cycle. Burst length (1, 2, 4, 6 & Ful page) Data scramble (Sequential & interleave} Range of operating frequencies, programmable latencies allows “ the same device to be useful for a variety of high bandwidtn, hign A em eek ens ste postive gong £09= ofthe performance memory system ications. stem cloc ny eysiem app + Serial presence detect with EEPROM + PCB : Height (1,37Smil), double sided component PIN CONFIGURATIONS (Front side/back side) PIN NAMES ; vs oes iil vee fit Couey te pene Hosa sess nes ons) 2 pao}]3c Csa |58 patg|e6 pasz}114 Csi }142 past BAO ~ 5At 3 pai]3: ou |s3 voo |s7 pasz|115 RAS |143 voo | |Dao~ba63 [Ddatainpurouput |

4 DQ2/32 Vss |60 DQ20/88 DQ34/116 vss |144 DQS52 CLKO ~ CLK3 [ciock input

Clas fe leo heros we lie ae lias oye [ckeED~CKE |Ciock enable input 6 voo ]34 a2 |62 ‘vrer|90 voo 118 AR | 146 “Vrer 7 pas}3s as |e cker|91 oase}ii9 as |e? NC [cso~cs3__|cnipsetectinput_ |

8 Das }36 AB | 64 vss }92 Das7|120 a7 |148 ves | [RAS [Rowadcress stove |

8 poe |s7 as) 6 az 23 vase] 121 As [us oass| [eas [counnasoess sone |

10 Da7 | 36 A1WAP| 66 DQ22]94 Da3e]122 SAO |150 DASE

11 pas |3° Bal |67 Da23]95 Daso]123 Alt |151 Dass [we [writeenable

12 Ves |40 veo |68 ves |96 vss |124 veo |152 vss pawo~7 [oom —————Cid

13° DQ3] 41 vVoo | 63 DQ24]37 DQ41/125 CLK1]/153 DQS56 [vco | Power supply (3.3) 14 pate] 42 cLKo | 70 pa2s|96 Dasz]126 “A12 |154 DQ|ST Ives erouna 15 paii|43 vss |71 Da26]399 Da43/127 vss |155 DasE 16 vaiz| 44 ou |72 paz7|1co vas4|:28 cxeo}i56 pase] |vaer [Power supply torreference |

17 DQi3|45 CS2 |73 Voo |/101 Da4s|129 CS3 |157 veo [soa Senaigwaio

18 voo | 46 Dam2|74 Daze ]102 voo |130 Dame|158 DasD [sc. | Senaicock ~*d| 19 pai4| 47 DaM3| 75 Da|29]103 Da|46}131 DaM7} 15° DA61 =

20 DQ1IS| 48 DU | 76 0Q30 104 DQ47/132 “A13 |160 DA|62 [sao~2 | Acdress in EEPROM

21 *cBO] 49 voo |77 Da31|105 “CBs ]133 veo |161 Dass [we | writeprotection =| zz -opi|sc nc |72 vss |1ce -ces [ise wo fis ves | [ou [oontuse ze Ne [sz cesz [eo ‘ne (ics Ne lise -ces |iea no] [NC [Noconnection | 24 nc |52 "c52]60 NC |108 NC |136 “CBs |164 NC No connection

25 NC |53 "C83 |} 61 wp |109 NC [137 “CB7 |165 “SAG

“Th jot wsec If this module. 26 voo |S4 vss | 82 “SDA|110 voo [138 Ves |166 “SAI $0 Tyene bins aveutd be 000 ba tne ayeeae 27 WE |55 Dai6}63 “SCL|111 CaS [139 DQ48|167 ““SA2 ‘which does not support SPD.

28 DQMO|56 DQI7}&4 voo |112 DaM4|140 0Q49|168 voo

SAMSUNG ELECTRONICS CO., Ltd. reserves ihe right to change products and specifications without notice. Se PSimsunid REV. 0.1 July. 2000 ELECTRONICS:

M366S3323CT0O PC133 Unbuffered DIMM SS PIN CONFIGURATION DESCRIPTION a ee ee [eck | Ssemcmer [pave repos pg cape ean a rps Disables or enables device operation by masking or enabling alll Inputs except = | Chip select CLK, CKE and D@M. Masks system clock to freeze operation from the next clock cycle. CKE should be enabled at least one cycle prior to new command. Disabte input bu*lers for power down In standby. CKE should be enabled 1CLK+tss prior to valid command. Row/column adoresses are multiplexed on the same pins. Row address - RAO ~ RA11, Column address - CAQ ~ CAS Selects bank to be activated during row address iatcn time. en ee Latches row addresses on the positive going edge of the CLK with RAS low. rs Rowe strobe Enables row access & precharge. Latches column addresses on the positive going edge of the CLK with CAS low. ao a Enables wrte operation and row precharge Latches cata in starting trom CAS, WE active tin Makes data output Hi-Z, texz after the clock and masks the output. Blocks data Input wnen DOM active. (Byte maseing) Daa papas 9 nape oF Be SAREE WP pin Is connected to Vss through 47KQ Resistor. Wnite protection When WP Is “high”, EEPROM Programming will be Inhibited anc the entire memory willl be wihe-protecied [Weoves [Foner asmvirena [Power ard gona brie npuivann awnecremge = Coen al PSimsunid REV. 0.1 July. 2000 ELECTRONS

M366S3323CTO PC133 Unbuffered DIMM FUNCTIONAL BLOCK DIAGRAM csi cso ee DaMa « a Dans — Dem cS | [eau es pam cS | [oom 5 DQ -—; Da0 pao Da32°— pad Dao Dat — 9a1 —| a1 Da33 — pai i— a1 ba2 0Q@2 vo FF Da2 us Da34 ba2 on 0Q2 ut2 DQ3— 0Q3 [J 203 Da3s°— Da3 i 283 DQ + 0a4 [J bas Da36-— Dae 204 DAS Das I bas Da37 -—] pas i oes DAs —j DQ6 [-—j as DQ38-— DAé J 286 DQ7 -—] Daz paz Da3e-—{ Da? Daz DeMt« — bes a pam ts || pam ts Daw tS | Dam CS Das -— pao pao paso — pao pao 0@3-— Dai t+— a1 Dai Dat — a1 DQI0-— 0G2 ui }—f 0G2_— us DQ42— DG2 us F——] OG2_ ut DQ11-—j Da3 J 293 Dae3 — 0a3 i 293 0Q12-— pas i] 294 Da44:— Das J 29s DQ13—j Das J 29s Dass — Das i] 29s DQ14 | Das iJ 296 Da4é — pas i oas DQ1s —{ Da7 paz Dae? -—_Da7 Daz CS3 : cs2 pam cs || pam Cs pam cs | pam cS Da16-— baa pao Dass 4 pac pa Da17:— pai — pat DQ49.- Dai i— pai pais Dba2 | bQ2 u1o DQ@so Daz ue J] G2 ute pais pa3 i] 223 DQs1 4 Da3 J 233 Da20°-— pas J bes DG@s2.—4 Das i bas Da2i— pas I] bas DQ@s3 4 Das J bas Da22-— paé i] bas DQs4— Dae i] bas 0aQ23 -—_pa7 Daz DQss —{ pa7. Daz Dams — DQM? « -—I paw ts | | pew ts oem tS | | pam Cs Da24°— Dao pao Da@s6 — da0 paa Da2s — Dat i— pat 0Qs7 0a1 t+— bat DaQ26 Daz ae es Daz ou1t DQ@ss 0Q2 wr DQ2 uis 0a27 *— Da3 J 923 D@ss | 0a3 f—J bas Da26 — Dad I] bes DQé0 | Da4 i 224 Da2s:— Das [J Das DQs1 —4 Das i] bas Da3x0 — 0aé i] 998 0Q62 | 006 J bas pa3i — a7 paz Da@s3 —| 907 baz AQ ~An, BAG & 1 o> SDRAM UC ~ U1S Serial PD RAS *———® SDRAM U0 ~ UIS wo SCL lao _as_aal we TAS °———> SDRAM U0 ~ U1S j 247Ka WE °———> SDRAM UC ~ U1S = TOKO SAG SAT SA2 ¢ CKEC o> SDRAM U0~ U7 CKE1 lL, SDRAM US ~ U1S ton WOU 1/U2/U3 DaQno— > Every Dapin of SDRAM 100 U4/US/UBUT U8/U9/U 1011 voo LI > ui2ZuIyUtaUIS Two 0.1u* Capacitors - T_T. pereach SDRAM O all SDRAMs 3 FL Ves < Ps nn PSimsunid REV. 0.1 July. 2000 ELECTRONICS

M366S3323CTO PC133 Unbuffered DIMM ABSOLUTE MAXIMUM RATINGS [Watpewmanpnreanemve [ _mver[se-ee «fv —_—id [vatge cn veosuppyreatvenvis | vonveo [__ve-ee fv —_—| CS Ss Note : Permanent device damage may occur if "ABSOLUTE MAXINUM RATINGS” are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device retiability. DC OPERATING CONDITIONS AND CHARACTERISTICS Recommended operating conditions (Voltage referenced to Vss = OV, TA = 0 to 70°C) [Seyvetege waves | so | ss | se | v |_| [mpigeionvotoge | ww [a2 | a | ee | v | 2 | Outpaagenenvetogs | vm [aa | _- | _- | v | rama [oapuegeiow erage | va | - | - | ea |v | warama_| [mpiatagecures fw |e | - | w | w | 3 _| Note : 1. Vin (max) = 5.6V AC. The overshoot voltage duration Is < ns. 2. Vit (min) = -2.0V AC. The undershoot voltage Ouration is < 3ns. 3. Any Input OV < Vins Von Input leakage currents Include HI-Z output leakage for aif bi-directional butters with Tri-State outputs CAPACITANCE (oo = 3.3v, Ta= 23°C, f= 1MHz, Var = 1.4V2200 mv) Adress (AG ~ A11, BAG ~ BA1) Caco 70 $5 pF RAS. CAS. WE cw 70 35 pF CKE (CKEO ~ CKE1) COKE 45 ss pF Clock (CLKO ~ CLK3) couK 35 40 pF CS (CSO. CS2} ces 25 x pF DQM (DQMO ~ DaM7) Cpa 15 20 pF Da (Dad ~ Da63) Cour 10 15 pF nn PSimsunid REV. 0.1 July. 2000 ELECTRONICS

M366S3323CTO PC133 Unbuffered DIMM DC CHARACTERISTICS (Recommended operating condition unless otherwise noted, Ta= 0 to 70°C) Test conation [as tec=7.sne | tcc=1one | Burst lengin =1 Operating current > tacimin\\ . tect | teez tro[min) 1.200 Iocan | CKE2 Vin(min), CS = Vinimin), toc = 10ns Precharge standby currentin input signals are changed one time during 20ns non power-down mode leans | CXE= Vinimin), CLK < Viimax}, toc = = noes Input signals are stable cosy | CXE = Vintmin), CS = Vinimin), toc = 10ns Active standby current in SSN | input signals are changes one time during 20ns non power-down mode (One bank active) Iccang | CXE= ViMtmin), CLK < Va(max), toc = = Input signals are stable = Oma Operating current loca | P3Q2 Durst (Burst mode) 4Banks activated toc = 2CLKs Retresh curent [cos [ecztncimny 2c so [ma | 2 | Self refresh current CKE <02v Pe ms | Notes : 1. Measured with outputs open. 2. Refresh period Is 64ms. 3. Uniess otherwise noticed, input swing level is CVOS(VIH/Vit=Vo0o/Vssq). nn PSimsunid REV. 0.1 July. 2000 ELECTRONICS

M366S3323CTO PC133 Unbuffered DIMM AC OPERATING TEST CONDITIONS (vco = 3.3v =0.3V, Ta=0 to 70°C) a [aerpaiewe mm dw CY a [ouputmngnesnvenenieeeneme [dv [owpumascenaton deg CS | 23v | Vite 14V = 12002 = sen | VoH (OC) = Z.4V, lou = -2mA - . Output « “T77""" Vou (OC) = O.4V, lot = 2MA Output o~*_ 70 = S02 __ evan = T SOpF if [ T SOpF (Fig. 1) DC output load circutt (Fig. 2) AC output load cireutt OPERATING AC PARAMETER {AC operating conditions unless otherwise noted) Rwateoerenecny ide |e |e | faasiecaseay decry | a ee [Row prctageare tinny [af ee now actve! [_tsiminy [as [se Ts Ts low active time [ena [ee we [Rowgoetme Stns [ed ee fiactaosinwpeaage denim [ae fiatcominioacbeaeay | aim | acim [Lastataintonew col.aacressaetay | teceiminy | tT cx fiataosinionusteep my | ie [oot aesio cn ares oany corny [a ae Ss Number of valid output data a Notes: + The minimum number of clock cycles Is determined by aividing the minimum time required with clock cycle time and then rounding off to the next higher integer. 2. Minimum delay Is required to complete write 3. All parts allow every cycle column address change. 4. In case of row precharge Interrupt, auto precharge and read burst stop. Se PSimsunid REV. 0.1 July. 2000 ELECTRONICS:

M366S3323CT0O PC133 Unbuffered DIMM ee _ el AC CHARACTERISTICS (Ac operating conditions untess otherwise noted) REFER TO THE INDIVIDUAL COMPONENET, NOT THE WHOLE MODULE. eee = po [| leixoceme [caterers [ee [72 | oes | sooo we J 7 CLK to valid . Samiacoy | csmmmors | we | - | ose | [oe [|e | Output data . feuxninpacewan | [ve | | se | | » | 3 feuxew pusewen | m [ze | | se | [| | 3 freweetstne [we [ve | | 2 |» | 3 [imeutnoistme | tm Ps Pe [cuxtoouputincowz | tz ft ft Pw CLK to output . fsse™ [comms | m= | of | te tel | Notes: | parameters depend on programmed CAS latency. 2. If clock rising time Is longer than ins, (tr2-0.5)ns should be addec to the parameter. 3. Assumed Input rise and fall time (tr & of) = ins. Ittr & tt Is longer than ins, transient time compensation should be considered, Le., [{tr + fy2-t)ns should be added to the parameter. Ce en PSimsunid REV. 0.1 July. 2000 ELECTRONS

M366S3323CT0O PC133 Unbuffered DIMM SS SIMPLIFIED TRUTH TABLE AM, AS- Ae [Register [oaeregeiersee | [ x [ute fe te[ x] opcoe | 2] tlidila = pete [| ac ; Pe[ | fu [ x [x] x] = [eancactearowsar | w» |x ]ililwla[x|v] awe | | ssn se [es =u ase Las feurststoe Te fe fw fet xf x Te acive power down fetv [vv] | [em foe fa [x[x[x [x] x | _ precharge power sown moce Pete [ual | ] aw Pepe T&T | fet v[v]v] | | foo seo epacatan command [x [x] x] x] _ (V-Valid, X-Don'’t care, H=Logic high, L=Logic low) Notes : + OP Code : Operand code Ag ~ Att & BA ~ BAt : Program keys. (@ MRS) 2. MRS can be Issued only at all banks precharge state Anew command can be issued after 2 clock cycles of MRS. 3. Auto refresh *unctions are as same a6 CBR refresh o° DRAM. ‘The automatical precharge wrhout row precharge command Is meant by “Auto”. Auto!se? refresh can be issued only at all banks precharge state. 4. BAo ~ 5A: : Bank select addresses. i both BAo and 5A1 are "Low" at read, write, row active and precharge, Dank A Is selected. i? both BAo Is "Low" and 5A1 Is “High” at read, write, row active and precharge, bank B Is selected. I both BAo Is "High" and 5A: Is “Low” at read, write, row active and precnarge, bank C ts selected. If both BAo and SA1 are “High” at read, write, row active and precharge, bank D is selected I AXO/AP Is "High" at row precharge, BAo and 5A1 Is ignored and all banks are selected 5. During burst read or write with auto precharge, new read/write command can not be Issued. Another bank read/write command can be issued after the end of burst. New row active of the associated ban can be Issued at tre after the enc of burst. 6. Burst stop command Is valid at every burst length. 7. DQM sampled at positive going edge of a CLX anc masks the cata-in at the very CLK (Write DQM latency Is 0), but makes Hi-Z state the data-out of 2 CLK cycies after. (Read DQM latency Is 2) Coen al PSimsunid REV. 0.1 July. 2000 ELECTRONS

M366S3323CT0O PC133 Unbuffered DIMM ee _ el PACKAGE DIMENSIONS Unts : Inches (Milimeters) 5.250 (133.380) 0.985 atte 5.014 e225. 3.000) (127.350) | Ro975 : / (R2000) . | 79.487 29.004 y (4.000 2 9.100) el§ ae — ° ‘Ie * ; " Ta Car Int EMT yA — Ft = A fast We Ns cle 118D1A20.004_/ 5 2 2 ¥a.b0001a ¢ 0.109) 76.350) EK 0.350 2 els (11.430) (15.87)

2.150 Max

or 5 (3.81 Max 4 = ole D.as0 + 0.9035 (1.270 20.19) 9.259 9.250 par 1 ala 0.12320995 1 0.123+0.005 pons +0.006 9.075 + 0.994 | 0.975 +0.004 py Detail A Detall B Detail C Tolerances : = .005{.13) unless otherwise specified ‘The used device Is 16M@x6 SDRAM, TSOP SORAM Part No. : K4S260632C-TC75 Ce en PSimsunid REV. 0.1 July. 2000 ELECTRONS