M35501FP MITSUBISHI | Alldatasheet

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Technical content

DESCRIPTION

The M35501FP generates digit signals for fluorescent display when connected to the output port of a microcomputer. There are up to 16 digit pins available, and more can be added by connect- ing additional M35501FPs. The number of fluorescent displays can be increased easily by connecting the M35501FP to the CMOS FLD (VFD; Vacuum Fluorescent Display) output pins of an 8-bit microcomputer in MITSUBISHI’s 38B5 Group. The M35501FP is suitable for fluorescent display control on household electric appliances, audio products, etc. Outline: 24P2E-A 24-pin plastic-molded SSOP PIN CONFIGURATION (TOP VIEW) M35501FP FLD (VFD) DIGIT EXPANDER MITSUBISHI IC’S Fig. 1 Pin configuration of M35501FP 123456789 1 0 1 1 1 2 131415161718192021222324 M35501FP SEL CLK VSS VCC OVF IN OVF OUT DIG15 DIG14 DIG13 DIG12 DIG11 DIG10 DIG8 DIG9 DIG7 DIG6 DIG5 DIG4 DIG3 DIG2 DIG1 DIG0 VEE RESET fi fi fi fi fi fi ‹ ‹ fi

FEATURES

  • Up to 16 pins can be selected
  • More digits available by connecting additional M35501FPs
  • Output structure: high-breakdown voltage, P-channel open- drain; built-in pull-down resistor between digit output pins and VEE pin

FLD (VFD) DIGIT EXPANDER MITSUBISHI IC’S FUNCTIONAL BLOCK Fig. 2 Functional block diagram PIN DESCRIPTION Table 1 Pin description Pin VCC , VSS RESET CLK SEL OVF IN OVF OUT DIG15– DIG 0 VEE Name Power source input Reset input Clock input Select input Overflow signal input Overflow signal output Digit output Pull-down power source input Function Apply 4.0–5.5 V to Vcc, and 0V to Vss. Reset internal shift register (built-in power-on reset circuit). Digit output varies according to rising edge of clock input. Use when specifying the number of digits. Input “H” when using one M35501FP. Connect to OVF OUT pin of additional M35501FPs when using multiple M35501FPs (to use 17 digits or more). Leave open when using one M35501FP . Connect to OVF IN pin of additional M35501FPs when using multiple M35501FPs (to use 17 digits or more). Output the digit output waveform of fluorescent display. Leave open when not in use (VEE level output). Apply voltage to DIG0–DIG 15 pull-down resistors. Output Structure CMOS input level Built-in pull-up resistor CMOS input level Built-in pull-down resistor CMOS input level Built-in pull-down resistor CMOS input level CMOS output High-breakdown-voltage P-channel open-drain output Built-in pull-down resistor Fig. No. VEE DIG15 DIG14 DIG13 DIG12 DIG11 DIG10 DIG9 DIG8 DIG7 DIG6 DIG5 DIG4 DIG3 DIG2 DIG1 DIG0

4 Power-on

232221201918171615141312111098

FLD (VFD) DIGIT EXPANDER MITSUBISHI IC’S PORT BLOCK Fig. 3 Port block diagram (1) DIG0–DIG15 VEE Pull-up transistor Pull-down transistor (2) SEL, CLK (3) RESET (4) OVFIN (5) OVFOUT Shift register Shift register

FLD (VFD) DIGIT EXPANDER MITSUBISHI IC’S USAGE Three usages of the M35501FP are described below. (1) 16-Digit Mode: 16 digits selected The number of digits is set to 16 by fixing the OVFIN pin to “H” and the SEL pin to “L.” Figure 5 shows the output waveform. (2) Optional Digit Mode: 1-16 digits selectable When the number of CLK pin rising edges during an “H” period of the SEL pin is n and the OVFIN pin is fixed to “H,” the number of digits set is n. If n is 16 or more, all 16 digits are set. Figure 6 shows the output waveform. Fig. 4 Digit setting (3) Cascade Mode: 17 digits or more selectable 17 digits or more can be used by connecting two M35501FPs or more. Figure 7 shows an example using three M35501FPs, offering 33 to 48 digit outputs. Cascade mode will not operate if all M35501FPs are in 16-digit mode (SEL = “L”). Use the most significant M35501FP in the optional digit mode for DIG output. Figure 8 shows the output waveform. SEL pin CLK pin n

FLD (VFD) DIGIT EXPANDER MITSUBISHI IC’S DIGIT OUTPUT WAVEFORM Fig. 5 16-digit mode output waveform Fig. 6 Optional digit mode output waveform “L”SEL CLK DIG0 DIG1 DIG2 DIG13 DIG14 DIG15 OVF OUT “L” SEL CLK DIG0 DIG1 DIG2 DIG3 DIG4 DIG15 OVF OUT “L” RESET

FLD (VFD) DIGIT EXPANDER MITSUBISHI IC’S Fig. 7 Cascade mode connection example: 17 digits or more selected Fig. 8 Cascade mode output waveform DIG 0 CLK SEL RESET OVF IN(1) OVF IN(2) OVF IN(3) OVF OUT (1) OVF OUT (2) OVF OUT (3) DIG 14 DIG 15 DIG 1 DIG 16 CLK SEL RESET DIG 30 DIG 31 DIG 17 DIG 32 CLK SEL RESET DIG 46 DIG 47 DIG 33 RESET CLK Select signal CLK DIG0 DIG1 DIG2 DIG15 OVF OUT (1) RESET DIG16 DIG17 DIG31 OVF OUT (2)

FLD (VFD) DIGIT EXPANDER MITSUBISHI IC’S The number of fluorescent displays can be increased by connecting the M35501FP to the CMOS FLD output pins on a 38B5 Group mi- crocomputer. This FLD controller can control up to 32 digits using the 32 timing mode of the 38B5 Group microcomputer. Fig. 9 Connection example with 38B5 Group microcomputer (1 to 16 digits) Fig. 10 Connection example with 38B5 Group microcomputer (17 to 32 digits) M38B5X P27–P20 P07–P00 P17–P10 P37–P30 P83–P80 P84 CLK SEL M35501 Digits DIG0–DIG15 Segment (high-breakdown-voltage: 36 pins + CMOS: 4 pins) Fluorescent Display (FLD) (1 pin used as CLK.) M38B5X P27–P20 P07–P00 P17–P10 P37–P30 P83–P80 CLK SEL P84 CLK SEL OVF OUT OVF IN OVF OUTOVF IN M35501 M35501 Segment (high-breakdown-voltage: 36 pins + CMOS: 4 pins) (1 pin is used as CLK.) Fluorescent Display (FLD) Digits DIG0–DIG15 Digits DIG 16–DIG31

FLD (VFD) DIGIT EXPANDER MITSUBISHI IC’S RESET CIRCUIT To reset the controller, the RESET pin should be held at “L” for 2 µs or more. Reset is released when the RESET pin is returned to “H” and the power source voltage is between 4.0 V and 5.5 V. Notes1: Perform the reset release when CLK input signal is “L.” 2: When setting the number of digits by SEL signal, optional digit counter is set to “0” by reset. Fig. 11 Digit output waveform when reset signal is input CLK DIG0 DIG1 DIG2 DIG3 RESET

FLD (VFD) DIGIT EXPANDER MITSUBISHI IC’S POWER-ON RESET Reset can be performed automatically during power on (power-on reset) by the built-in power-on reset circuit. When using this cir- cuit, set 100 µs or less for the period in which it takes to reach minimum operation guaranteed voltage from reset. If the rising time exceeds 100 µs, connect the capacitor between the RESET pin and V SS at the shortest distance. Consequently, the RESET pin should be held at “L” until the minimum operation guaranteed voltage is reached. Fig. 12 Power-on reset circuit Power-on reset circuit Pull-up transistor RESET pin (Note) VDD Internal reset signal Power-on Applied voltage to the RESET pin must be VDD or less. Note: This symbol represents a parasitic diode. Reset released Power-on reset circuit output voltage Reset state

FLD (VFD) DIGIT EXPANDER MITSUBISHI IC’S IOH(peak) IOH(peak) IOL(peak) IOH(avg) IOH(avg) IOL(avg) CLK VCC VSS VEE VIH VIH VIL VIL VCC VEE VI VI VO VO Pd Topr Tstg Power source voltage Pull-down power source voltage Input voltage CLK, SEL, OVF IN Input voltage RESET Output voltage DIG 0–DIG 15 Output voltage OVFOUT Power dissipation Operating temperature Storage temperature Ratings –0.3 to 7.0 VCC –45 to VCC +0.3 –0.3 to VCC +0.3 –0.3 to VCC +0.3 VCC –45 to VCC +0.3 –0.3 to VCC +0.3 250 –20 to 85 –40 to 125 V V V V V V mW

  • All voltages are based on VSS .
  • Output transistors are off. ConditionsParameterSymbol Unit Power source voltage Power source voltage Pull-down power source voltage “H” input voltage CLK, SEL, OVF IN “H” input voltage RESET “L” input voltage CLK, SEL, OVF IN “L” input voltage RESET Limits Min. 4.0 VCC –43 0.8VCC 0.8VCC Typ. 5.0 Max. 5.5 V SS VCC VCC 0.2VCC 0.2VCC V V V V V V V ParameterSymbol Unit “H” peak output current DIG0 – DIG15 (Note 1) “H” peak output current OVFOUT (Note 1) “L” peak output current OVFOUT (Note 1) “H” average current DIG0 – DIG15 (Note 2) “H” average current OVFOUT (Note 2) “L” average current OVFOUT (Note 2) Clock input frequency Limits Min. Typ. Max. –36 –10 –18 –5.0 5.0 mA mA mA mA mA mA MHz RECOMMENDED OPERATING CONDITIONS (VCC = 4.0 to 5.5 V, Ta = –20 to 85 °C, unless otherwise noted) ParameterSymbol Unit Notes 1: The peak output current is the peak current flowing in each port. 2: The average output current is an average value measured over 100 ms. Ta = 25 °C ABSOLUTE MAXIMUM RATINGS RECOMMENDED OPERATING CONDITIONS (VCC = 4.0 to 5.5 V, Ta = –20 to 85 °C, unless otherwise noted)

FLD (VFD) DIGIT EXPANDER MITSUBISHI IC’S “H” output voltage “H” output voltage “L” output voltage Hysteresis “H” input current “H” input current “L” input current “L” input current Output load current Output leakage current Power source VOH VOH VOL VT+—V T– IIH IIH IIL IIL ILOAD ILEAK ICC IOH = –18 mA IOH = –10 mA IOL = 10 mA VCC = 5.0 V VI = VCC VI = VCC VCC = 5.0 V VI = VSS VI = VSS VCC = 5.0 V VEE = VCC –43 V VOL = VCC Output transistors are off. V EE = VCC –43 V VOL = VCC –43 V Output transistors are off. ELECTRICAL CHARACTERISTICS (VCC = 4.0 to 5.5 V, Ta = –20 to 85 °C, unless otherwise noted) Test conditionsParameterSymbol DIG output DIG 0–DIG 15 OVF OUT OVF OUT CLK, OVF IN RESET OVF IN RESET CLK, SEL OVF IN CLK, SEL RESET DIG0 – DIG15 DIG0–DIG15 Limits Min. VCC –2.0 VCC –2.0 –60 500 Typ. 0.4 –130 650 Max. 2.0 5.0 140 –5.0 –185 800 –10 V V V V µA µA µA µA µA µA µA Unit VCC = 5.0 V, CLK = 100 kHz Output transistors are off.

FLD (VFD) DIGIT EXPANDER MITSUBISHI IC’S tw(RESET) tc(CLK ) twH (CLK ) twL (CLK ) tsu(SEL ) th(SEL ) th(CLK ) Fig. 13 Timing diagram Reset input “L” pulse width Clock input cycle time Clock input “H” pulse width Clock input “L” pulse width Select input setup time Select input hold time Clock input setup time Limits Min. 500 200 200 500 500 500 Typ. Max. µs ns ns ns ns ns ns TIMING REQUIREMENTS (VCC = 4.0 to 5.5 V, Ta = –20 to 85 °C, unless otherwise noted) ParameterSymbol Unit 0.2VCC 0.8VCC tc(CLK) twL(CLK) twH(CLK) CLK 0.2VCC 0.8VCC tw(RESET) RESET SEL CLK tsu(SEL) th(SEL) vcc vss vcc vss vcc vss vcc vss th(CLK)

© 1998 MITSUBISHI ELECTRIC CORP. New publication, effective Feb. 1998. Specifications subject to change without notice. Notes regarding these materials

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Rev. Rev. No. date

1.0 First Edition 980216

REVISION DESCRIPTION LIST M35501FP DATA SHEET (1/1) Revision Description