M35500BGP

M35500AFP MITSUBISHI | Alldatasheet

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MITSUBISHI <DIGITAL ASSP> M35500AFP/BGP FLD(VFD) CONTROLLER DESCRIPTION/FEATURES (Ports P0 to P7 are also used as ordinary output ports) 0 to DIG17), –7 mA (SEG0 to SEG7) PIN CONFIGURATION (TOP VIEW) (in serial input pin and clock pin, 2 MHz sampling) Fig. 1. Pin configuration of M35500AFP/BGP Package type: 44P6N-A/44P6X M 3 5 5 0 0 A F P M B G P D I G 1 S E G 1 D I G 1 S E G 1 D I G 1 S E G 1 D I G 1 S E G 1 D I G 1 S E G 1 D I G 1 S E G 1 D I G 9/ S E G 1 D I G 8/ S E G 1 D I G 6/ P D I G 7/ P D I G 5/ P D I G 1 S E G 9 D I G 1 S E G 8 S E G 7 S E G 6 S E G 5 S E G 4 S E G 3 S E G 2 S E G 1 S E G 0 VD D 4 4 VD D XO U T VS S XI N R E S E T A N 5 A N 4 A N 3 A N 2 A N 1 A N 0 D I G 4/ P D I G 3/ P D I G 2/ P D I G 1/ P D I G 0/ P VE E VE E SC L K SO U T SI N C S 1 2

MITSUBISHI <DIGITAL ASSP> M35500AFP/BGP FLD(VFD) CONTROLLER FUNCTIONAL BLOCK Fig. 2. Functional block diagram FUNCTIONAL BLOCK DIAGRAM (Package: 44P6N-A) Display RAM Display control circuit A-D Serial I/O Mode register Command analytic circuit Transfer counter Byte end Memory address Selector/A-D control circuit Trigger AN 5 – AN0 DIG8/SEG 17 – DIG17/SEG 8 SEG 7 – SEG0 6 7 8 9 10 11 434241403938373635343332313029282726 17VEE Clock generating circuit 2 4 XOUT Noise filter 16VEE VDD 44 DIG7/P7 DIG6/P6 DIG5/P5 DIG4/P4 DIG3/P3 DIG2/P2 DIG1/P1 DIG0/P0 XIN VDD VSS RESET CS SIN SOUT SCLK Noise filter

MITSUBISHI <DIGITAL ASSP> M35500AFP/BGP FLD(VFD) CONTROLLER Table. 1. Pin description Function

• Apply voltage of 5 V to VCC , and 0 V to VSS .
• Applies voltage supplied to pull-down resistors.
• RC oscillator pins for system clock.
• Reset input pin for active “L”.
• Internal pull-up resistors connected between the RESET and VCC pins.
• Serial transfer is possible by inputting “L” signal.
• Clock for serial transfer is input.
• Read a clock twice with 2 MHz sampling clock and judge if it is a noise or not.
• Serial data is output.
• During reset it is in high-impedance state.
• Serial data is input. Read a clock twice with 2 MHz sampling clock and judge if it is a noise or not.
• Pin for ordinary output or digit output.
• At reset this port is set to V EE level through a pull-down resistor.
• Pin for digit output or segment output.
• At reset this port is set to VEE level through a pull-down resistor.
• Pin for segment output.
• At reset this port is set to VEE level through a pull-down resistor. Output Output N-channel open-drain P-channel open-drain P-channel open-drain P-channel open-drain Pin VCC , VSS VEE XIN XOUT RESET ____ CS SCLK SOUT SIN DIG0/P0 – DIG7/P7 DIG8/SEG 17 – DIG17/SEG 8 SEG 0 – SEG7 Name Power source Pull-down power source Clock input Clock output RESET input Chip select Serial clock Serial output Serial input Digit/Port Digit/Segment Segment Input Input CMOS input CMOS input CMOS input Noise filter CMOS input Noise filter PORT BLOCK Fig. 3. Port block diagram PIN DESCRIPTION (2) Digit pin latch VEE Dimmer signal (Note) Shift signal from high-order Shift signal to low-order (3) Segment pin latch VEE Dimmer signal (Note) Segment data (6) SIN, SCLK pin Serial input Serial clock input Noise filter (1) Digit/Port pin Digit/Segment pin Data bus Segment data latch VEE Dimmer signal (Note) Shift signal from high-order Shift signal to low-order ] High-breakdown-voltage P-channel transistor Note: Dimmer signal is for setting the Toff time. SOUT signal (4) SOUT pin (5) CS pin CS input A-D conversion input (7) A-D input Noise filter

MITSUBISHI <DIGITAL ASSP> M35500AFP/BGP FLD(VFD) CONTROLLER COMMAND STYLE Fig. 4. Command style Port data setting (Command 3) 100 P3 – P0/P7 – P4 output data Display data setting (Command 0) 111 Number of segment setting 0 0 : 16 or less 0 1 : 17 or more b0b1b2b3b4b5b6b7 Digit selection (Command 2) 10 Digit start pin setting 0 0 0 0 : D17 0 0 0 1 : D16 0 0 1 0 : D15 0 0 1 1 : D14 0 1 0 0 : D13 0 1 0 1 : D12 0 1 1 0 : D11 0 1 1 1 : D10 1 0 0 0 : D9 1 0 0 1 : D8 1 0 1 0 : D7 Display state setting (Command 1) 110 Display ON or OFF setting 1 : ON 0 : OFF Number of digit setting 0 0 : 7 0 1 : 8 1 0 : 9 1 1 : 10 Display duty setting 1 1 : 15/16 1 0 : 14/16 0 1 : 6/16 0 0 : 5/16 Port selection (Note) 0 : P3 – P0 1 : P7 – P4 Note: When a digit or a port has to be selected, a digit output is selected for having higher priority.

MITSUBISHI <DIGITAL ASSP> M35500AFP/BGP FLD(VFD) CONTROLLER Byte protocol Command protocol Display data setting (Command 0) CLK SIN SOUT Command 0 Data 1 Data 2 X A-D data 0 A-D data j CS CLK SIN SOUT X b0 b1 b2 b3 b4 b5 b6 b7 b0 b1 b2 b3 b4 b5 b6 b7 Other setting except display data setting (Command 1 to 3) CLK SIN SOUT Command X Note: SOUT is in high-impedance state during CS signal is “H”. Note 1: The serial data which is transmitted after executing command 0 is recognized as a display data. “A-D data 6 or more” data is defined as an undefined “X”. Note 2: Set the CS signal to “H” level after transferring a display data. X Data i CS CS SERIAL I/O PROTOCOL Fig. 5. Serial I/O protocol

MITSUBISHI <DIGITAL ASSP> M35500AFP/BGP FLD(VFD) CONTROLLER SEG 0-7 SEG 8-15 SEG 0-7 SEG 8-15 SEG 0-7 SEG 8-15 SEG 0-7 SEG 8-15 AD AD AD AD AD AD 5XX XX XXX 16 or less segments (2-byte transfer) DIG n-2 DIG 0DIG n SEG 0-7 SEG 8-15 SEG 0-7 DIG n-1 DIG n-3 SEG 0-7 dummy data SEG 0-7 SEG 0-7 SEG 0-7 AD AD AD AD AD AD 5XX XX XXX 8 or less segments (2-byte transfer) DIG n-2 DIG 0DIG n SEG 0-7 SEG 0-7 DIG n-1 DIG n-3 CS CLK S IN SOUT Command 0 SEG 0-7 SEG 8-15 SEG 16-17 SEG 0-7 SEG 8-15 SEG 16-17 SEG 0-7 SEG 8-15 SEG 16-17 SEG 0-7 SEG 8-15 SEG 16-17 AD AD AD AD AD AD 5X XX XXX 17 or more segments (3-byte transfer) DIG n-1 DIG n-2 DIG 0DIG n AD valid data X CS CLK SIN SOUT CS CLK SIN SOUT Command 0 Command 0 AD valid data AD valid data dummy data dummy data dummy data dummy data Note: 2 bytes “X” data is output before outputting AD valid data. Note: 2 bytes “X” data is output before outputting AD valid data. Note: 2 bytes “X” data is output before outputting AD valid data. SERIAL COMMUNICATION FORMAT (DISPLAY DATA, A-D OUTPUT) Fig. 6. Serial communication format

MITSUBISHI <DIGITAL ASSP> M35500AFP/BGP FLD(VFD) CONTROLLER FLD DISPLAY TIMING Fig. 7. FLD display timing diagram Toff Tdisp Digit Segment Tdisp = 384 ms (oscillation frequency f(XIN) = 4.0 MHz) Toff= 264 ms ( 5/16 5 Tdisp) 240 ms ( 6/16 5 Tdisp) 48 ms (14/16 5 Tdisp) 24 ms (15/16 5 Tdisp) G n G n-1 G 1 Segment output Tdisp Tscan = 0ns PORT DIG DIG DIG16 DIG15 DIG14 DIG13 DIG12 DIG11 DIG10 DIG9 DIG8 DIG7 DIG6 DIG5 DIG4 DIG3 DIG2 DIG1 DIG0 SEG SEG 0 SEG 1 SEG 2 SEG 3 SEG 4 SEG 5 SEG 6 SEG 7 SEG 8 SEG 9 SEG 10 SEG 11 SEG 12 SEG 13 SEG 14 SEG 15 SEG 16 SEG 17 G10 S10 S11 S12 S13 S14 S15 S16 G10 S10 S11 S12 S13 S14 S15 S16 S17 S18 Grid : 7 Segment : 8 Grid : 10 Segment : 8 Grid : 10 Segment : 16 Grid : 7 Segment : 18 Fig. 8. Segment/Digit setting example SEGMENT/DIGIT SETTING EXAMPLE

MITSUBISHI <DIGITAL ASSP> M35500AFP/BGP FLD(VFD) CONTROLLER b 7b 0 D i g i t A D D R E S S D 1 D 1 D i g i t D i g i t D i g i t D i g i t D i g i t D i g i t D 1 2 F1 D i g i t D i g i t D i g i t 9 S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G BIT ALLOCATION FOR DISPLAY RAM Fig. 9. Bit allocation for display RAM

MITSUBISHI <DIGITAL ASSP> M35500AFP/BGP FLD(VFD) CONTROLLER RESET CIRCUIT To reset the controller, the RESET pin should be held at a “L” level for 2 µs or more. Then the RESET pin is returned to an “H” level (the power source voltage should be between 4.0 V and 5.5 V, and XIN oscillation is stable), reset is released. Make sure that the reset input voltage is 0.5 V or less for 4.0 V of V CC . Fig. 10. Reset circuit example ( N o t e ) 0 . 2 VC C 0 V 0 V P o w e r o n VC CR E S E T N o t e . R e s e t r e l e a s e v o l t a g e :V C C = 4 . 0 V CLOCK GENERATING CIRCUIT Oscillating circuit is built up by connecting pins XIN and XOUT as short as possible and connecting a capacitor between pins XIN (XOUT ) and VSS . When supplying a clock externally, input it to XIN pin and leave XOUT pin open. C O S C XI N XO U T XI N XO U T VC C VS S E x t e r n a l o s c i l l a t i o n c i r c u i t O p e n Fig. 11. RC generating circuit Fig. 12. External clock input circuit HANDLING OF UNUSED PINS Handle unused pins as the follow. Pin Segment Digit Analog input Handling Open Open Connect to V CC or VSS through a resistor. Table. 2. Handling of unused pins

MITSUBISHI <DIGITAL ASSP> M35500AFP/BGP FLD(VFD) CONTROLLER ΣIOH(peak) ΣIOH(avg) IOH(peak) IOH(peak) IOL(peak) IOH(avg) IOH(avg) IOL(avg) f(XIN) f(SCLK ) VCC VSS VEE VIH VIH VIL VIL VCC VEE VI VI VI VO VO Pd Topr Tstg Power source voltage Pull-down power source voltage Input voltage AN 0 – AN5 Input voltage CS, SIN, SCLK Input voltage RESET Output voltage DIG 0 – DIG17 SEG 0 – SEG17 Output voltage SOUT Power dissipation Operating temperature Storage temperature Ratings –0.3 to 7.0 VCC –45 to VCC +0.3 –0.3 to VCC +0.3 –0.3 to VCC +0.3 –0.3 to VCC +0.3 VCC –45 to VCC +0.3 VCC –50 to VCC +0.3 –0.3 to VCC +0.3 600 –20 to 85 –40 to 125 V V V V V V V mW

• All voltage are based on VSS .
• Output transistors are cut off. ConditionsParameterSymbol Unit Power source voltage Power source voltage Pull-down power source voltage “H” input voltage CS, S IN, SCLK “H” input voltage RESET “L” input voltage CS, S IN, SCLK “L” input voltage RESET Limits Min. 4.0 VCC –38 0.75VCC 0.8VCC Typ. 5.0 Max. 5.5 V CC VCC VCC 0.25VCC 0.2VCC V V V V V V V ParameterSymbol Unit “H” total peak output current DIG0 – DIG17, SEG0 – SEG 17 (Note 1) “H” total peak output current DIG0 – DIG17, SEG0 – SEG 17 “H” peak output current DIG 0 – DIG17 (Note 2) “H” peak output current SEG 0 – SEG 7 (Note 2) “L” peak output current S OUT “H” peak output current DIG 0 – DIG17 (Note 3) “H” peak output current SEG 0 – SEG 7 (Note 3) “L” peak output current S OUT Main clock input oscillation frequency (Note 4) Serial I/O external clock frequency Limits Min. Typ. 4.0 250 Max. –240 –120 –40 –20 –18 5.0 5.2 mA mA mA mA mA mA mA mA MHz kHz RECOMMENDED OPERATING CONDITIONS (VCC = 4.0 to 5.5 V, Ta = –20 to 85 °C, unless otherwise noted) ParameterSymbol Unit Notes 1:The total output current is the sum of all the currents flowing through all the applicable ports. The total average current is an average value measured over 100 ms. The total peak current is the peak value of all the currents. 2:The peak output current is the peak current flowing in each port. 3:The average output current is an average value measured over 100 ms. 4:When the oscillation frequency has a 50 % duty cycle.
• All voltage are based on VSS .
• Output transistors are cut off.
• A waveform: 450 µs or more frequency and 30 µs or less pulse width.
• Connect only capacitor load (CL = 200pF).
• All voltage are based on VSS .
• Output transistors are cut off. Ta = 25 °C ABSOLUTE MAXIMUM RATINGS RECOMMENDED OPERATING CONDITIONS (VCC = 4.0 to 5.5 V, Ta = –20 to 85 °C, unless otherwise noted)

MITSUBISHI <DIGITAL ASSP> M35500AFP/BGP FLD(VFD) CONTROLLER Tconv VIA IIA R LADDER VRAM ICC “H” output voltage “L” output voltage Hysteresis “H” input voltage “L” input voltage Output load current Output leakage current VOH VOL VT+—V T– IIH IIL ILOAD ILEAK IOH = –18 mA IOH = –7 mA IOL = 5 mA VCC = 5.0 V VI = VCC VI = VSS VEE = VCC –36 V VOL = VCC Output transistors “off” V EE = VCC –38 V VOL = VCC –38 V Output transistors “off” ELECTRICAL CHARACTERISTICS (VCC = 4.0 to 5.5 V, Ta = –20 to 85 °C, unless otherwise noted) Test conditionsParameterSymbol DIG output SEG output S OUT SIN, SCLK , CS RESET, XIN SIN, SCLK , CS RESET X IN SIN, SCLK , CS RESET X IN DIG0 – DIG17 SEG 0 – SEG 17 DIG0 – DIG17 SEG 0 – SEG 17 Limits Min. VCC –2.0 VCC –2.0 250 Typ. 0.5 0.5 4.0 –150 –4.0 500 Max. 2.0 5.0 5.0 –5.0 750 –10 V V V V V µA µA µA µA µA µA µA µA Unit RAM hold voltage Power source current When clock is stopped VCC = 5 V, f(XIN) = 4.2 MHz Output transistors “off” at A-D converter operating ELECTRICAL CHARACTERISTICS (VCC = 4.0 to 5.5 V, Ta = –20 to 85 °C, unless otherwise noted) Test conditionsParameterSymbol Limits Min. 2.0 Typ. 0.5 Max. 5.5 1.0 V mA Unit Resolution Absolute accuracy (excluding quantization error) Conversion time Analog input voltage Analog port input current Ladder resistor VCC = 5.12 V A-D CONVERTER CHARACTERISTICS (VCC = 4.0 to 5.5 V, Ta = –20 to 85 °C, unless otherwise noted) Test conditionsParameterSymbol Limits Min. Typ. 0.5 Max. 100 VCC 5.0 Bits LSB tc(XIN) V µA kΩ Unit

MITSUBISHI <DIGITAL ASSP> M35500AFP/BGP FLD(VFD) CONTROLLER tw(RESET) tc(XIN) twH (XIN) twL (XIN) tc(SCLK ) twH (SCLK ) twL (SCLK ) tsu(SIN-SCLK ) th(SCLK -SIN) tsu(CS) th(CS) tre(SCLK ) td(SCLK -SOUT ) tv(SCLK -SOUT ) tr(Pch) C OSC Fig. 13. Standard characteristic example of f(XIN)–COSC Reset input “L” pulse width Main clock input cycle time (XIN input) Main clock input “H” pulse width Main clock input “L” pulse width Serial clock input cycle time (Note) Serial clock input “H” pulse width (Note) Serial clock input “L” pulse width (Note) Serial input setup time (Note) Serial input hold time (Note) Serial input setup time Serial input hold time Serial clock interval time Limits Min. 238 50 t c(XIN) 50 tc(XIN) 50 tc(XIN) Typ. Max. µs ns ns ns CLKs CLKs CLKs CLKs CLKs ns ns ns TIMING REQUIREMENTS (VCC = 4.0 to 5.5 V, Ta = –20 to 85 °C, unless otherwise noted) ParameterSymbol Unit Note: The unit means a number of noise filter sampling clock (2 5 tc(XIN)). Serial I/O output delay time (Note 1) Serial I/O output valid time High-breakdown-voltage P-channel open-drain output rising time External capacitor size (Note 2) Limits Min. Typ. 1.8 Max. CLKs CLKs µs pF SWITCHING CHARACTERISTICS (VCC = 4.0 to 5.5 V, Ta = –20 to 85 °C, unless otherwise noted) ParameterSymbol Unit C L = 100pF VEE = VCC –36 V Test conditions M e a s u r i n g c o n d i t i o n T a C VC C V 0 2 0 4 0 5 0 7 0 8 F r e q u e n c y f ( XI N ) [ M H z ] E x t e r n a l c a p a c i t o r s i z e C O S C p F Note 1: The unit means a number of noise filter sampling clock (2 5 tc(XIN)). 2: An external capacitor size varies with a mounted condition.

MITSUBISHI <DIGITAL ASSP> M35500AFP/BGP FLD(VFD) CONTROLLER 0 . 2 VC C t d ( SC L K- SO U 0 . 2 VC C 0 . 8 VC C 0 . 8 VC C t s u ( SI N - SC L K) t h ( SC L K- SI N ) t v ( SC L K- SO U tC ( SC L tw L( SC L K) tw H ( SC L SO U T SI N SC L K 0 . 2 VC C 0 . 8 VC C tw ( R E S E T ) R E S E T C S SC L K t r e c ( SC L K)t s u ( C S ) t h ( C S ) Fig. 14. Output switching characteristics measurement circuit diagram P c h a n n e l o u t p u t p o r t C L VE E S e r i a l I O c l o c k o u t p u t p o r t C L R L Fig. 15. Timing diagram

MITSUBISHI <DIGITAL ASSP> M35500AFP/BGP FLD(VFD) CONTROLLER PACKAGE OUTLINE QFP44-P-1010-0.80 0.59 Weight(g) JEDEC CodeEIAJ Package Code Lead Material Alloy 42 44P6N-A Plastic 44pin 105 10mm body QFP Symbol Min Nom Max A b c D E H E L y Dimension in Millimeters H D A1 0.20.1 0.5 ––I2 1.3 ––M D 10.6 ––M E 10.6 10°0° 0.1 1.4 0.80.60.4 13.112.812.5 13.112.812.5 0.8 10.210.09.8 10.210.09.8 0.20.150.13 0.450.350.3 2.8 3.05 e e e E c H E 44 34 H D D M D M E A F A1 A2 Ly Recommended Mount Pad Detail F x – – 0.2 b x M

MITSUBISHI <DIGITAL ASSP> M35500AFP/BGP FLD(VFD) CONTROLLER © 2000 MITSUBISHI ELECTRIC CORP. New publication, effective Mar. 2000. Specifications subject to change without notice. Notes regarding these materials

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• Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non-flammable material or (iii) prevention against any malfunction or mishap. Weight(g) JEDEC CodeEIAJ Package Code Lead Material Cu Alloy 44P6X Plastic 44pin 105 10mm body QFP Symbol Min Nom Max A b c D E H E L y Dimension in Millimeters H D A1 0.2 0.5 ––I2 1.3 ––M D 10.6 ––M E 10.6 10°0° 1.4 0.80.60.4 13.112.8 13.112.812.5 12.5 0.8 10.110.09.9 10.110.09.9 0.20.1750.15 0.450.3 2.0 0.375 0.10 2.3 e e e E c H E 44 34 H D D M D M E A F A1 A2 Ly Recommended Mount Pad Detail F x – – 0.2 0.1 b x M

Rev. Rev. No. date

1.0 First Edition; As M35500AFP/AGP 11/15/97

2.0 The followings are updated: 01/07/00

Product M35500AGP is switched to M35500BGP. Page 3, Table 1: RC oscillator Page 9: Fig. 11. RC generating circuit Page 12, TIMING REQUIREMENTS: Limits of tc(SCLK) and twL(SCLK) Page 12, SWITCHING CHARACTERISTICS: Limits and Unit of tv(SCLK-SOUT) 2.1 Page 15: The 44P6X package outline is added. 03/09/00 REVISION HISTORY M35500AFP/BGP DATA SHEET (1/1) Revision Description