M35052

M35052 MITSUBISHI | Alldatasheet

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SCREEN CHARACTER and PATTERN DISPLAY CONTROLLERS MITSUBISHI MICROCOMPUTERS

DESCRIPTION

The M35052-XXXSP/FP is TV screen display control IC which can be used to display information such as number of channels, the date and messages and program schedules on the TV screen. In particular, owing to the built-in SYNC-SEP (synchronous separa- tion) circuit, the synchronous correction circuit, the Decoder circuit, and to the Encoder circuit, external circuits can be decrease and character turbulence that occurs when superimposing can be reduced. The processor can conform to the EDS broadcast service and is suit- able for AV systems such as VTRs, LDs, and so on. It is a silicon gate CMOS process and M35052-XXXSP is housed in a 20-pin shrink DIP package, M35052-XXXFP is housed in a 20-pin shrink SOP package. For M35052-001SP/FP that is a standard ROM version of M35052- XXXSP/FP respectively, the character pattern is also mentioned.

FEATURES

• Display locations available Cycle : approximately 1 second, or approximately 0.5 seconds Duty : 25%, 50%, or 75%
• Coloring Background coloring (composite video signal)
• Blanking Total blanking (14 5 18 dots) Border size blanking Character size blanking
• Synchronizing signal Composite synchronizing signal generation (PAL, NTSC, M-PAL)
• 2 output ports (1 digital line)
• Oscillation stop function It is possible to stop the oscillation for synchronizing signal generation
• Built-in half-tone display function
• Built-in reversed character display function
• Built-in Decoder (NTSC only)
• Built-in Encoder (NTSC only)
• Built-in synchronous correction circuit
• Built-in synchronous separation circuit APPLICATION TV, VCR, Movie PIN CONFIGURATION (TOP VIEW) REV.1.1 M X X X F P CP1 TESTA CS SCK SIN AC VDD2 CVIDEO LECHA CVIN VD D H O R C P 2 O S C I N VS S P 1 P 0 T E S T B E D O VS S M XXXSP CP1 TESTA CS SCK SIN AC VDD2 CVIDEO LECHA CVIN VD D H O R C P 2 O S C I N VS S P 1 P 0 E D O VS S O u t l i n e 2 0 P 4 B O u t l i n e 2 0 P 2 Q - A TESTB

SCREEN CHARACTER and PATTERN DISPLAY CONTROLLERS PIN DESCRIPTION Function This is the filter output pin 1. This is the pin for test. Connect this pin to GND during normal operation. This is the chip select pin, and when serial data transmission is being carried out, it goes to “L”. Hysteresis input. Includes built-in pull-up resistor. When CS pin is “L”, SIN serial data is taken in when SCK rises. Hysteresis input. Built-in pull-up resistor is included. This is the pin for serial input of data and addresses for the display control register and the display data memory. Also, serially outputs decode data according to the settings in the relevant registers (serial I/O). When “L”, this pin resets the internal IC circuit. Hysteresis input. Includes built-in pull-up resistor. Please connect to +5V with the analog circuit power pin. This is the output pin for composite video signals. It outputs 2V P-P composite video signals. In superimpose mode, character output etc. is superimposed on the external composite video signals from CVIN. This is the input pin which determines the “white” character color level in the composite video signal. This is the input pin for external composite video signals. In superimpose mode, character output etc. is superimposed on these external composite video signals. Please connect to GND using circuit earthing pin. This is the output pin for encode data. It outputs three-valve data. This is the pin for test. Connect this pin to GND during normal operation. This pin outputs the port output or BLNK1 (character background) signal. This pin outputs the port output or CO1(character) signal. Please connect to GND using circuit earthing pin (Analog side). This is the input pin for the sub-carrier frequency (f SC ) for generating a synchronous signal. A frequency of 3.580MHz is needed for NTSC, and a frequency of 4.434MHz in needed for PAL and 3.576MHz is needed for M-PAL. Filter output pin 2. This is the input pin for external composite video signals. This pin inputs the external video signal clamped sync-chip to 1.5V, and internally carries out synchronous separa- tion. Please connect to +5V with the digital circuit power pin. Symbol OSC1 TESTA CS SCK SIN AC V DD2 CVIDEO LECHA CVIN V SS EDO TESTB V SS OSCIN CP2 HOR VDD1 Pin name Clock input Test pin Chip select input Serial clock input/ output Serial data input Auto-clear input Power pin Composite video signal output Character level input Composite video signal input Earthing pin Encode data output Test pin Port P0 output Port P1 output Earthing pin f SC input pin for synchronous signal generation Filter output Horizontal synchro- nizing signal input Power pin Input/ Output Input Input Input Input/ Output Input Output Input Input Output Output Output Input Output Input

SCREEN CHARACTER and PATTERN DISPLAY CONTROLLERS BLOCK DIAGRAM D a t a c o n t r o l c i r c u i t A d d r e s s c o n t r o l c i r c u i t D i s p l a y c o n t r o l r e g i s t e r D i s p l a y R A M D i s p l a y c h a r a c t e r R O M T i m i n g g e n e r a t o r B l i n k i n g c i r c u i t S h i f t r e g i s t e r D i s p l a y c o n t r o l c i r c u i t R e a d i n g a d d r e s s c o n t r o l c i r c u i t H c o u n t e r N T S C P A L M P A L v i d e o o u t p u t c i r c u i t T i m i n g g e n e r a t o r S Y N C - S E P c i r c u i t 3 . 5 8 0 M H z ( N T S C ) M H z P A L M H z M P A L T E S T A T E S T B P o r t o u t p u t c i r c u i t D e c o d e r c i r c u i t C l o c k o s c i l l a t i o n c i r c u i t D a t a s l i c e r c i r c u i t S C K S I N C S C V I D E O C V I N L E C H AVD D A C VS S VD D H O R P P C P 1 VS S E D O O S C I N C P I / O c o n t r o l c i r c u i t O s c i l l a t i o n c i r c u i t f o r s y n c h r o n i z i n g s i g n a l g e n e r a t i o n D i s p l a y l o c a t i o n d e t e c t i o n c i r c u i t 1 6 1 1 2 0 1 3 1 1 9 1 7 1 8 1 0 1 2 1 4 1 5

SCREEN CHARACTER and PATTERN DISPLAY CONTROLLERS MEMORY CONSTITUTION Address 0016 to EF16 are assigned to the display RAM, address F016 to F816 are assigned to the display control registers. The internal circuit is reset and all display control registers (address F016 to F816) are set to “0” and display RAM (address 0016 to EF16) are RAM erased when the AC pin level is “L”. Set “0” in any of DA7, DAD through DAF of addresses 0016 through EF 16, and of DAE and DAF of addresses F016 through F816. Setting the blank code “FF16” as a character code is an exception. TESTn (n : a number) is MITSUBISHI test memory, so be sure to observe the setting conditions. DA5 SEPV1 HP5 VP5 VSZ11 DSP5 MPAL BG CURS5 STOP1 DAA EC2 EC2 TEST10 DVP2 EVP2 EFLD0 SPACE TEST17 TEST0 TEST22 EHP2 Bit Address 0016 EF 16 F016 F116 F216 F316 F416 F516 F616 F716 F816 DAF DAE DAD TEST25 TEST26 TEST27 TEST28 TEST29 TEST30 TEST31 TEST32 LEVEL1 DAC REV REV W/R DVP4 EVP4 TEST12 TEST14 TEST19 TEST2 TEST24 EHP4 BLINK TEST11 DVP3 EVP3 EFLD1 TEST13 MB/LB TEST1 RGBON EHP3 DAB BLINK Encode data or character color DA9 EC1 EC1 DECB1 DVP1 EVP1 DFLD1 DSP9 TEST16 LBLACK CL17/18 EHP1 DA8 EC0 EC0 DECB0 DVP0 EVP0 DFLD0 DSP8 TEST15 LIN24/32 CBLINK EHP0 DA7 SYSEP1 HP7 VP7 VSZ21 DSP7 EQP BLKHF CURS7 RAMERS DA6 SYSEP0 HP6 VP6 VSZ20 DSP6 PALH BB CURS6 DSPON DA4 SEPV0 HP4 VP4 VSZ10 DSP4 INT/NON BR CURS4 STOPIN DA3 PTD1 HP3 VP3 HSZ21 DSP3 N/P LEVEL0 CURS3 SCOR DA2 PTD0 HP2 VP2 HSZ20 DSP2 BLINK2 PHASE2 CURS2 EX DA1 PTC1 HP1 VP1 HSZ11 DSP1 BLINK1 PHASE1 CURS1 BLK1 DA0 PTC0 HP0 VP0 HSZ10 DSP0 BLINK0 PHASE0 CURS0 BLK0 Port output specify and so on Display mode specify Blinking specify and so on Raster color specify Cursor display specify Control display and so on Vertical display start position and Encode position specify Character size and EncodeEDecode specify Horizontal display start position and Decode position specify Remarks Display RAMCharacter codeReversed characterBlinking Fig. 1 Memory constitution (M35052-XXXSP/FP)

SCREEN CHARACTER and PATTERN DISPLAY CONTROLLERS SCREEN CONSTITUTION The screen lines and rows are determined from each address of the display RAM. The screen consitution (24 characters 5 10 lines) is shown in Figure 2 the screen constitution (32 characters 5 7 lines) is shown in 3. Note : The hexadecimal numbers in the boxes show the display RAM address. 1816 3016 4816 6016 7816 9016 A816 C0 16 D8 16 0116 1916 3116 4916 6116 7916 9116 A916 C116 D9 16 0216 1A16 3216 4A16 6216 7A16 9216 AA 16 C2 16 DA 16 0316 1B16 3316 4B16 6316 7B16 9316 AB 16 C3 16 DB 16 0416 1C 16 3416 4C 16 6416 7C 16 9416 AC 16 C4 16 DC 16 0516 1D 16 3516 4D 16 6516 7D 16 9516 AD 16 C5 16 DD 16 0616 1E16 3616 4E16 6616 7E16 9616 AE 16 C6 16 DE 16 0716 1F16 3716 4F16 6716 7F16 9716 AF 16 C7 16 DF 16 0816 2016 3816 5016 6816 8016 9816 B016 C8 16 E016 0916 2116 3916 5116 6916 8116 9916 B116 C9 16 E116 0A16 2216 3A16 5216 6A16 8216 9A16 B216 CA 16 E216 0B16 2316 3B16 5316 6B16 8316 9B16 B316 CB 16 E316 0C16 2416 3C16 5416 6C16 8416 9C16 B416 CC 16 E416 0D16 2516 3D16 5516 6D16 8516 9D16 B516 CD 16 E516 0E16 2616 3E16 5616 6E16 8616 9E16 B616 CE 16 E616 0F16 2716 3F16 5716 6F16 8716 9F16 B716 CF 16 E716 1016 2816 4016 5816 7016 8816 A016 B816 D0 16 E816 1116 2916 4116 5916 7116 8916 A116 B916 D116 E916 1216 2A16 4216 5A16 7216 8A16 A216 BA 16 D216 EA 16 1316 2B16 4316 5B16 7316 8B16 A316 BB 16 D316 EB 16 1416 2C16 4416 5C16 7416 8C16 A416 BC 16 D416 EC 16 1516 2D16 4516 5D16 7516 8D16 A516 BD 16 D516 ED 16 1616 2E16 4616 5E16 7616 8E16 A616 BE 16 D616 EE 16 1716 2F16 4716 5F16 7716 8F16 A716 BF16 D716 EF16 2016 4016 6016 8016 A016 C016 0116 2116 4116 6116 8116 A116 C116 0216 2216 4216 6216 8216 A216 C216 0316 2316 4316 6316 8316 A316 C316 0416 2416 4416 6416 8416 A416 C416 0516 2516 4516 6516 8516 A516 C516 0616 2616 4616 6616 8616 A616 C616 0716 2716 4716 6716 8716 A716 C716 0816 2816 4816 6816 8816 A816 C8 16 0916 2916 4916 6916 8916 A916 C916 0A16 2A16 4A16 6A16 8A16 AA 16 CA 16 0B16 2B16 4B16 6B16 8B16 AB 16 CB 16 0C16 2C16 4C16 6C16 8C16 AC 16 CC 16 0D16 2D16 4D16 6D16 8D16 AD 16 CD 16 0E16 2E16 4E16 6E16 8E16 AE 16 CE 16 0F16 2F16 4F16 6F16 8F16 AF16 CF 16 1016 3016 5016 7016 9016 B016 D016 1116 3116 5116 7116 9116 B116 D116 1216 3216 5216 7216 9216 B216 D216 1316 3316 5316 7316 9316 B316 D316 1416 3416 5416 7416 9416 B416 D416 1516 3516 5516 7516 9516 B516 D516 1616 3616 5616 7616 9616 B616 D616 1716 3716 5716 7716 9716 B716 D716 1816 3816 5816 7816 9816 B816 D816 1916 3916 5916 7916 9916 B916 D916 1A16 3A16 5A16 7A16 9A16 BA 16 DA 16 1B16 3B16 5B16 7B16 9B16 BB 16 DB 16 1C16 3C16 5C16 7C16 9C16 BC 16 DC 16 1D16 3D16 5D16 7D16 9D16 BD 16 DD 16 1E16 3E16 5E16 7E16 9E16 BE 16 DE 16 1F16 3F16 5F16 7F16 9F16 BF 16 DF 16 Notes 1. The hexadecimal numbers in the boxes show the display RAM address. Notes 2. When 32 characters 5 7 lines are displayed, set blank code “FF16” to character code of addresses E016 to EF16. Fig. 3 Screen constitution (32 characters 5 7 lines) Fig. 2 Screen constitution (24 characters 5 10 lines) Rows Rows Lines Lines

SCREEN CHARACTER and PATTERN DISPLAY CONTROLLERS Status DA 0~C A B C Name (LSB) (MSB) EC0 EC1 EC2 BLINK REV

Contents

Set ROM-held character code of a character needed to display. Set to “0” during normal operation Can not be used When EFILD1, 0=1, 0 or 0, 1, set code of the data needed to encode. When RGBON=1, set background color by character unit. No blinking Blinking Normal character Reversed character Remarks (Note 2) Refer to encode function. Refer to supplemental explanation (4). Refer to BLINK2 to 0 (address F516) Notes 1. Resetting at the AC pin RAM-erases the display RAM, and the status turns as indicated by the mark around in the status column. 2. Set to “1” only when you set a blank code. Display RAM DESCRIPTION Display RAM Address 0016 to EF16

SCREEN CHARACTER and PATTERN DISPLAY CONTROLLERS Status DA 0~D A B C D Register PTC0 PTC1 PTD0 PTD1 SEPV0 SEPV1 SYSEP0 SYSEP1 DECB0 DECB1 TEST10 TEST11 ____ W/R TEST25 P0 output (port 0) BLNK1 output P1 output (port 1) CO1 output It is negative polarity at P0 output “L”, BLINK1 output. It is positive polarity at P0 output “H”, BLINK1 output. It is negative polarity at P01 output “L”, CO1 output. It is positive polarity at P01 output “H”, CO1 output. It should be fixed to “0”. Can not be used. It should be fixed to “0”. Can not be used. SYSEP1 SYSEP0 Bias potential Can not be used. Can not be used. 1.75µ Can not be used. DECB1 Can not be used. It should be fixed to “1”. It should be fixed to “0”. Can not be used. Input data from SIN pin Output data from SIN pin (Note 2) It should be fixed to “0”. Can not be used. Port output control Refer to supplemental explanation (5). Control the port data Refer to supplemental explanation (5). Specifies the vertical synchronous separation criterion Refer to supplemental explanation (1). Specifies the sync-bias potential Specifies the decoding bias potential Control data I/O Refer to decode data output timing. Bias potential 2.35µ Can not be used. Can not be used. Can not be used. DECB0 Notes 1. The mark around the status value means the reset status by the “L” level is input to AC pin. Notes 2. Not necessary to release after setting W/R to “1”. Turn CS to “H” to switch over to input mode. Display control register (1) Address F016

SCREEN CHARACTER and PATTERN DISPLAY CONTROLLERS Function Let horizontal display start position be HS, HS = T 5 (Σ2nHPn+6) T : The oscillation cycle of display clock Let the slice lines be DVS, DVS = Σ2nDVPn+6 It should be fixed to “0”. Can not be used. V S H S H O R V E R T C h a r a c t e r d i s p l a y i n g a r e a Status Register HP0 (LSB) HP1 HP2 HP3 HP4 HP5 HP6 HP7 (MSB) DVP0 (LSB) DVP1 DVP2 DVP3 DVP4 (MSB) TEST26 Set the horizontal display start position by use of HP7 through HP0. HP7 to HP0 = (00000000) to (00001111) setting is forbidden. It can be set this up to 240 steps in increments of one T. Set the slice lines (horizontal scanning lines) under decoding by use of DVP4 through DVP0. DVP4 to DVP0 = (00000) to (00011) setting is forbidden. Thus, it can be defined a setting up to 26 steps covered by a range from line 10 to line 35. Refer to supplemental explanation (2) about slice lines (DVS). DA 0~D A B C D (2) Address F116 n=0 n=0

SCREEN CHARACTER and PATTERN DISPLAY CONTROLLERS Status Register VP0 (LSB) VP1 VP2 VP3 VP4 VP5 VP6 VP7 (MSB) EVP0 (LSB) EVP1 EVP2 EVP3 EVP4 (MSB) TEST27 0~D A B C D Function Let vertical display start position be VS, HS = T 5 Σ2 nVpn Let the encode lines be EVS, DVS= Σ2nEVpn+6 It should be fixed to “0”. Can not be used. (3) Address F216 Remarks Set the vertical display start position by use of VP7 through VP0. VP7 to VP0 = (00000000) to (00000110) setting is forbidden. It can be set this up to 249 steps in increments of one H. VP7 to VP0 = (00000000) to (00100011) setting is forbidden. Sets the lines (horizontal scanning lines) under encoding by use of EVP4 through EVP0. EVP4 to EVP0 = (00000) to (00011) setting is forbidden. Thus, it can be defined a setting up to 26 steps covered by a range from line 10 to line 35. Refer to supplemental explanation (2) about the encode lines (EVS). H : The oscillation cycle of horizontal synchronous signal n=0 n=0 V S H S H O R V E R T C h a r a c t e r d i s p l a y i n g a r e a

SCREEN CHARACTER and PATTERN DISPLAY CONTROLLERS Register HSZ10 HSZ11 HSZ20 HSZ21 VSZ10 VSZ11 VSZ20 VSZ21 DFLD0 DFLD1 EFILD0 EFLD1 TEST12 TEST28 0~D A B C D Function HSZ11 HSZ10 Horizontal direction size 1T/dot 2T/dot 3T/dot 4T/dot HSZ21 HSZ20 Horizontal direction size 1T/dot 2T/dot 3T/dot 4T/dot VSZ11 VSZ10 Vertical direction size 1H/dot 2H/dot 3H/dot 4H/dot VSZ21 VSZ20 Vertical direction size 1H/dot 2H/dot 3H/dot 4H/dot DFLD1 DFLD0 Field detection OFF The first field The second field Can not be used EFLD1 EFLD0 Field detection OFF The first field The second field Can not be used It should be fixed to “0”. Can not be used. It should be fixed to “0”. Can not be used. Status (4) Address F3 Remarks Character size setting in the horizontal direction for the first line. Character size setting in the horizontal direction for the 2nd line to 10th line. Character size setting in the vertical direction for the first line. Character size setting in the vertical direction for the 2nd line to 10th line. Specifies the field determination procedure in relation to the Decoding functions. Refer to supplemental explanation (2). Specifies the field determination procedure in relation to the Encoding functions. Refer to supplemental explanation (2).

SCREEN CHARACTER and PATTERN DISPLAY CONTROLLERS Register DSP0 DSP1 DSP2 DSP3 DSP4 DSP5 DSP6 DSP7 DSP8 DSP9 SPACE TEST13 TEST14 TEST29 0~D A B C D Function Normal display Put a space line between line 2 and line 3, and between line 8 and line 9. It should be fixed to “0”. Can not be used. It should be fixed to “0”. Can not be used. It should be fixed to “0”. Can not be used. DSPn= “0” Matrix-outline size Character size Border size Matrix-outline size BLK1 BLK0 DSPn= “1” Matrix-outline border size Border size Matrix-outline size Character size Status (5) Address F4 Depends on BLK0 and BLK1 (address F816) DSPn in the generic name for DSP0 to DSP9. DSP0 to DSP9 are each controlled independently. Remarks Set the display mode of line 1. Set the display mode of line 2. Set the display mode of line 3. Set the display mode of line 4. Set the display mode of line 5. Set the display mode of line 6. Set the display mode of line 7. Set the display mode of line 8. Set the display mode of line 9. Set the display mode of line 10. Put a space line between line 2 and line 3 in displaying 32 characters.

SCREEN CHARACTER and PATTERN DISPLAY CONTROLLERS Status Register BLINK0 BLINK1 BLINK2 N/P INT/NON MPAL PALH EQP TEST15 TEST16 TEST17 MB/LB TEST19 TEST30 ContentsDA 0~D A B C D Function BLINK0 BLINK1 Duty Blinking off 25% 50% 75% (6) Address F516 Remarks Blinking duty ratio can be altered. (Note) Blinking cycle can be altered. Refer to register MPAL Scanning lines control (only in internal synchronization) Synchronizing signal is selected with this register and N/P register. It should be fixed to “0” at NTSC Effective only at non-interlace Setting the decode data output form Division of vertical synchronizing signal into 1/64. Cycle approximately 1 second. Division of vertical synchronizing signal into 1/32. Cycle approximately 0.5 second. NTSC, M-PAL mode PAL mode Interlace Non interlace Not include the equivalent pulse. Include the equivalent pulse. It should be fixed to “0”. Can not be used. It should be fixed to “0”. Can not be used. It should be fixed to “0”. Can not be used. Output from MSB side Output from LSB side It should be fixed to “0”. Can not be used. It should be fixed to “0”. Can not be used. N/P MPAL Synchronous mode NTSC M-PAL PAL Not available PALH INT/NON Number of scanning lines 625H lines 626H lines 627H lines 628H lines Note. To flash a character, set 1 to DAB (the flash bit) of the display RAM.

SCREEN CHARACTER and PATTERN DISPLAY CONTROLLERS Register PHASE0 PHASE1 PHASE2 LEVEL0 BR BG BB BLKHF LIN24/32 LBLACK TEST0 TEST1 TEST2 TEST31 ContentsDA 0~D A B C D Function Internal bias off Internal bias on The halftone displaying “OFF” in superimpose The halftone displaying “ON” in superimpose 24 characters 5 10 lines display 32 characters 5 7 lines display Blanking level I 2.3V Blanking level II 2.1V It should be fixed to “0”. Can not be used. It should be fixed to “0”. Can not be used. It should be fixed to “0”. Can not be used. Can not be used. It should to be fixed to “1”. PHASE2 PHASE1 PHASE0 Raster Black Red Green Yellow Blue Magenta Cyan White BB BG BR Black Red Green Yellow Blue Magenta Cyan White Status Character back- ground color Remarks Raster color setting Refer to supplemental explanation (3) about video signal level Generates bias potential for composite video signals Character background color setting. Refer to supplemental explanation (3) about video signal level This register is available in the superimpose displaying only. (Note) “1” setting is forbidden under encoding. Set a blackness level (7) Address F6 Note. It is neccessary to input the external composite video signal to the CVIN pin, and externally connect a 100 to 200Ω register in series.

SCREEN CHARACTER and PATTERN DISPLAY CONTROLLERS Register CUR0 CUR1 CUR2 CUR3 CUR4 CUR5 CUR6 CUR7 CBLINK CL17/18 TEST22 RGBON TEST24 TEST32 0~D A B C D Function Let cursor displaying address be CURS, CURS = T 5 Σ2 nCURn No blinking Blinking Cursor displaying at the 17th dot by vertical direction. Cursor displaying at the 18th dot by vertical direction. It should be fixed to “0”. Can not be used. Normal Character background coloring It should be fixed to “0”. Can not be used. It should be fixed to “0”. Can not be used. Status (8) Address F716 Remarks Set the cursor displaying address by use of CUR7 through CUR0. CUR7 to CUR0 (11110000) setting is forbidden under 24 characters display. CUR7 to CUR0 (11100000) setting is forbidden under 32 characters display. Set CUR7 to CUR0 = (11111111) under cursor is not be displayed. The cursor displaying address (CURS) is correspond to display construction. The cursor blinking setting Refer to character construction. Refer to supplemental explanation (4). n=0

SCREEN CHARACTER and PATTERN DISPLAY CONTROLLERS Status Register BLK0 BLK1 EX SCOR STOPIN STOP1 DSPON RAMERS EHP0 EHP1 EHP2 EHP3 EHP4 LEVEL1 ContentsDA 0~D A B C D Function External synchronization Internal synchronization Superimpose monotone display Superimpose coloring display (only NTSC) f SC input mode Can not be used. Oscillation VCO for display Stop oscillation VCO for display Display OFF Display ON RAM not erased RAM erased Let encode data programming start position be EHS, EHS = T 5 Σ2 nEHPn+6 Internal bias OFF Internal bias ON DSPn= “0” Matrix-outline size Character size Border size Matrix-outline size BLK1 BLK0 DSPn= “1” Matrix-outline border size (9) Address F816 Remarks Display mode (BLNK output) variable Synchronizing signal switching (Note1) “1” setting is forbidden at internal synchronous or PAL, M-PAL mode displaying. OSCIN oscillation control Control oscillation VCO for display This register does not exist (Note 3). Set encode start position by use of EHP4 through EHP0. EHP4 to EHP0 = (00000) to (01111) is setting forbidden. Refer to encode function (3) Generates bias potential for decod- ing and synchronous separation. Notes 1.In dealing with the internal synchronization, cut off external video signals outside the IC. The leakage of external input video signals can be avoided. Notes 2. In displaying color superimposition, enter into the OSCIN pin the fSC signal that phase-synchronizes with the color burst of the composite video signals (input to the CVIN pin). Notes 3. Erases all the display RAM. The character code turns to blank-FF16, the encode data bit and the blinking bit turn to “1” respectively, and reversed character bit turns to “0”. Border size Matrix-outline size Character size n=0

SCREEN CHARACTER and PATTERN DISPLAY CONTROLLERS Supplemental explanation about display control register (1) How to effect synchronous separation from composite video signals Synchronous separation is effected as follows depending on the width of L-level of the vertical synchronous period. 1. Less than 8.4Ês ······ Not to be determined to be a vertical synchronous signal. 2. Equal to or higher than 8.4Ês but less than 15.6Ês ······ When two clocks continue, if take place, it is “L” period is determined to be a vertical synchronization signal. 3. Equal to or higher than 15.6Ês ······ It is “L” period is determined to be a vertical synchronous signal with no condition. The determination is made at the timing indicated by V in Fig.3 either in case 2 or in case 3. Fig. 4 The method of synchronous separation from composite video signal. Fig. 5 Field definition ]A horizontal scanning line number corresponds to slice lines DVP4 through DVP0 (address F116) and to encode lines EVP4 through EVP0 (address F216). stands for either an equalizing pulse or sequence of synchronizing pulse to be used as a trigger of a receiving set. H stands for a hori- zontal scanning period. (2) Field definition 8 . 4 m s 1 5 . 6 m s V e r t i c a l s y n c h r o n o u s s i g n a l C o m p o s i t e v i d e o s i g n a l V8 . 4 m s E q u a l i z i n g p u l s e S e q u e n c e o f s y n c h r o n i z i n g p u l s e F i r s t f i e l d P u l s e s d u r i n g a v e r t i c a l r e t r a c e l i n e e r a s u r e p e r i o d S e c o n d f i e l d 1 / 2 H1 H 123456 78 9 1 0 1 / 2 H1 H 8 – 1 2 H 1 1]

SCREEN CHARACTER and PATTERN DISPLAY CONTROLLERS Fig. 6 Bector phases VDD : 5.0V, Ta : 25°C(3) Video signal level (4) Setting RGBON (address F716) a) When encode is off .... EFILD1, 0 (address F316) = 0,0 Encode setting ... Not effected and BR (address F6 16), screen by screen. EC0 (address 0016 to EF16), character by char- acter. The color setting is shown below. b) When encode is on ... EFILD1, 0 (address F316) = 0, 1 or 1, 0 Encode setting ...Sets encode data depending on EC2 through EC0. (Refer to the encode functions for details.) and BR (address F616) screen by screen. (When encode is on, setting RGBON to “1” re- sults in setting both encode data and back- ground colors depending on the same memory (EC2 through EC0), so this setting can not be used. Amplitude ratio (to color burst) Max. 4.5 4.2 3.0 3.0 4.2 4.5 PAL, M-P AL method –4π/16 –7π/16–2π/16 5π/16–2π/16 –π/16–2π/16 15π/16–2π/16 –11π/16–2π/16 9π/16–2π/16 Color Sync-chip Pedestal Color burst Black Red Green Y ellow Blue Magenta Cyan White NTSC method 7π/16–2π/16 27π/16–2π/16 π/16–2π/16 17π/16–2π/16 11π/16–2π/16 23π/16–2π/16 Min. 1.3 1.9 1.9 2.1 2.3 2.7 3.1 2.0 2.5 2.9 3.1 Typ. 1.5 2.1 2.1 2.3 2.5 2.9 3.3 2.2 2.7 3.1 3.3 Max. 1.7 2.3 2.3 2.5 2.7 3.1 3.5 2.4 2.9 3.3 3.5 Min. 1.5 1.4 1.0 1.0 1.4 1.5 Typ. 1.0 3.0 2.8 2.0 2.0 2.8 3.0 Phase angle (rad) Brightness level (V) CB CB1 CB2 RS1 RS2 π/4 R-Y B-Y -π/4 CB Color burst under NTSC CB1,CB2 Color burst under PAL or M-PAL RS1,RS2 Color subcarrier under PAL or M-PAL EC2 EC1 EC0 Color Black Red Green Y ellow Blue Magenta Cyan White Color Setting

SCREEN CHARACTER and PATTERN DISPLAY CONTROLLERS (5) Port output and BLNK1, CO1 output Fig. 7 Example of port control STOP1 DSPON CS pin at display clock operating L at display clock stop H STOP1, DSPON (Address F816) (6) Setting conditions for oscillating or stopping the display clock LEVEL0 LEVEL1 External synchronous Operation state (Character display) Internal synchronous LEVEL0 (address F6 16), LEVEL1 (address F816) Now-working condition (no characters are displayed) (7) Setting condition at LEVEL0,1 P T D T D P o l a r i t y s w i t c h i n g B L N K O P T C 0 iP T C 1 j S e l e c t P T D T D P T D P T C d d r e s s F O u t p u t

SCREEN CHARACTER and PATTERN DISPLAY CONTROLLERS This display format allows each line to be controlled independently, so that two kinds of display formats can be combined on the same screen. DISPLAY FORMS M35052-XXXSP/FP has the following four display forms as the blank- ing function, when CO1 and BLNK1 are output. (1) Character size : Blanking same as the character size. (2) Border size : Blanking the background as a size from cha- racter. (3) Matrix-outline size: Blanking the background as a size from all character font size. (4) Matrix-outline : Blanking the background as a size from all border size character font size. Border display. Fig. 8 Display forms at each display mode S c a n n i n g l i n e C V I D E O 1 2 d o t s 1 4 d o t s a a c k g r o u n d c a r r i e r c o l o r s i g n a l C h a r a c t e r s i z e ( B o r d e r s i z e ( M a t r i x o u t l i n e s i z e C O B L N K aaaa N o t e I n t h i s c a s e t h e o u t p u t p o l a r i t y t h a t C O 1 @ a n d B L N K 1 @ i s p o s i t i v e 1 4 d o t s M a t r i x o u t l i n e b o r d e r s i z e 1 2 d o t s d o t s

SCREEN CHARACTER and PATTERN DISPLAY CONTROLLERS DATA INPUT EXAMPLE Data of display RAM and display control registers can be set by then serial input function. Example of data setting is shown in Figure 9. Owing to automatic address increment, not necessary to enter ad- dresses for the second and subsequent data. In automatically, the next of address F8 16 is assigned to address 0016. Fig. 9 shows an example of data serially entered. DA E DA D LEVEL DA C REV REV REV REV W/R DVP EVP EHP DA B BLINK BLINK BLINK BLINK DVP EVP EFLD MB/LB RGBON EHP DA A EC2 EC2 EC2 EC2 DVP EVP EFLD SPACE EHP DA EC1 EC1 EC1 EC1 DVP EVP DFLD DSP LBLACK EHP DA EC0 EC0 EC0 EC0 DVP EVP DFLD DSP LIN CBLINK EHP DA HP VP VSZ DSP EQP BLKHF CURS RAM ERS DA HP VP VSZ DSP PALH BB CURS DSPON DA HP VP VSZ DSP MPAL BG CURS STOP DA HP VP VSZ DSP INT /NON BR CURS STOP IN DA PTD HP VP HSZ DSP ____ N/P LEVEL CURS SCOR DA PTD HP VP HSZ DSP BLINK PHASE CURS EX DA PTC HP VP HSZ DSP BLINK PHASE CURS BLK DA PTC HP VP HSZ DSP BLINK PHASE CURS BLK Remarks Specify address Display OFF DA F Address (F816) Data (F816) Data (0116) Data (EE16) Data (EF16) Data (F016) Data (F116) Data (F216) Data (F316) Data (F416) Data (F516) Data (F616) Data (F716) Data (F816) Specify address display RAM 0 to EF 16. Specify address register F016 to F716. Display ON Fig. 9 Example of data setting serial input function

SCREEN CHARACTER and PATTERN DISPLAY CONTROLLERS SERIAL DATA INPUT TIMING (1) The address consists of 16 bits. (2) The data consists of 16 bits. (3) The 16 bits in the SCK after the CS signal has fallen are the ad- dress, and for succeeding input data, the address is incremented every 16 bits. Output timing of decode data (1) Setting “1” in the W/R register activates output mode. (2) Outputs decode data in 16 clocks of the SCK after switching over to output mode. (Don’t enter the SCK for more than 16 clocks.) (3) Raising the CS signal deactivates output mode. (To switch over to input mode, cause CS to fall.) (4) If no data are present, or if data have already been read, 000016 is output. Fig. 11 Decode data output timing Fig. 10 Serial input timing A d d r e s s ( 1 6 b i t ) N = 1 , 2 , 3 C S S C K L S BM S B S I N D a t a N ( 1 6 b i t ) D a t a N + 1 ( 1 6 b i t ) L S BM S BL S BM S B M S B L S B D e c o d e d a t a ( 1 6 b i t ) L S B A d d r e s s ( 1 6 b i t )D a t a ( 1 6 b i t ) C S S C K S I N M S B 1 21 51 6. . . O u t p u t m o d e W h e n r e g i s t e r M B L B A d d r e s s F ( R e g i s t e r W / R = “ 1 ” )

SCREEN CHARACTER and PATTERN DISPLAY CONTROLLERS Encode functions (effective for NTSC only) (1) Setting encode data Setting data code (000 – 111) in EC0 through EC2 (bits DA8 through DAA) of the display RAM (addresses 0 through EF16) encodes. A sample setting and data code are shown below. Fig. 12 An example of data code setting L EC2 EC1 EC0 L LH HL HH LHLH LH L Data Can not be used The oscillation frequency when encoding: 3 MHz] 1 clock cycle: 0.333µs 1 character (12 dots): 3.996µs 2 bits/1 character: 3.996µs 1 bit: 1.998µs  18 dots 12 dots An example of setting ]····· 192 5 fH (horizontal synchronous frequency) for f H = 15.625 kHz Note: Refer to the next page about address setting. No encoding A suite of data code (000 – 111) for encoding to be set in EC2 through EC0 are assigned as given below. fixed 2 bit / a character Set by every 2 bits (one character) with EC2 to EC0. 16 bit data 5 characters 8 characters EC2~EC0= (address) (Note) (1) (2) (3) 001 100 100 101 (4) (Set one code of 000 to 011)100 LSB MSB

SCREEN CHARACTER and PATTERN DISPLAY CONTROLLERS Fig.13 Display monitor (2) Setting addresses Set encode data in EC0 through EC2 of addresses (that correspond to an extent from the first character to the thirteenth character in each line as appearing on the screen.) Set “111” to EC2 through EC0 of all the addresses in which you set no encode data. 0D 16 2516 3D 16 5516 6D 16 8516 9D 16 B516 CD 16 E516 0E16 2616 3E16 5616 6E16 8616 9E16 B616 CE 16 E616 0F16 2716 3F16 5716 6F16 8716 9F16 B716 CF 16 E716 1016 2816 4016 5816 7016 8816 A016 B816 D0 16 E816 1116 2916 4116 5916 7116 8916 A116 B916 D1 16 E916 1216 2A16 4216 5A16 7216 8A16 A216 BA 16 D2 16 EA 16 1316 2B16 4316 5B16 7316 8B16 A316 BB 16 D3 16 EB 16 1416 2C 16 4416 5C 16 7416 8C 16 A416 BC 16 D4 16 EC 16 1516 2D 16 4516 5D 16 7516 8D 16 A516 BD 16 D5 16 ED 16 1616 2E16 4616 5E16 7616 8E16 A616 BE 16 D6 16 EE 16 1716 2F16 4716 5F16 7716 8F16 A716 BF 16 D7 16 EF 16 0016 1816 3016 4816 6016 7816 9016 A816 C016 D816 0216 1A16 3216 4A16 6216 7A16 9216 AA 16 C216 DA 16 0316 1B16 3316 4B16 6316 7B16 9316 AB 16 C316 DB 16 0416 1C16 3416 4C16 6416 7C16 9416 AC 16 C416 DC 16 0516 1D16 3516 4D16 6516 7D16 9516 AD 16 C516 DD 16 0616 1E16 3616 4E16 6616 7E16 9616 AE 16 C616 DE 16 0716 1F16 3716 4F16 6716 7F16 9716 AF16 C716 DF 16 0816 2016 3816 5016 6816 8016 9816 B016 C816 E016 0916 2116 3916 5116 6916 8116 9916 B116 C916 E116 0A16 2216 3A16 5216 6A16 8216 9A16 B216 CA 16 E216 0B16 2316 3B16 5316 6B16 8316 9B16 B316 CB 16 E316 0C 16 2416 3C 16 5416 6C 16 8416 9C 16 B416 CC 16 E416 0116 1916 3116 4916 6116 7916 9116 A916 C116 D916 Screen line 1 line 2 line 3 line 4 line 5 line 6 line 7 line 8 line 9 line 10 Useless area Start setting data from the first line. Data set in the lines specified by registers EVP0 through EVP3 (address F2 16) will be encoded. Setting data in the second and subsequent lines, it is possible to set encode data to ten consecutive lines from those secified by registers EVP0 to EVP2. Similarly to encode line N specified by registers EVP0 through EVP2, extending encode lines to line N-1 and to line N+1, it is possible to read encode data more certainly. Using area for encode data setting

SCREEN CHARACTER and PATTERN DISPLAY CONTROLLERS Fig. 14 Encode data output (3) Encode data output Symbol A B C D E H VOH VOM VOL Min. 1.5 Typ. (EHS+9)5 1/(fH5 192)* 6.5P 16P 1/fH 5.0 2.3 Unit µs µs µs µs µs µs V V V VDD : 5.0V, Ta : 25°C Digital 3 value output (EDO output) 1P = 1/(fH 5 32) fH : Horizontal synchronous frequency (MHz) * It is possible to make a fine adjustment (in increments of 1/(fH 5 192)) by use of EHS (registers EHP4 to EHP0 of address F816). (EHS ≤15 setting is forbidden.) H AB C D E VOH VOM VOL Clock run-in Start bit Character 1 Character 2 LSB1 LSB2 MSB1 MSB2 3.0 Max.

SCREEN CHARACTER and PATTERN DISPLAY CONTROLLERS Fig. 15 Character font and border CHARACTER FONT Images are composed on a 12 5 18 dot matrix, and characters can be linked vertically and horizontally with other characters to allow the display the continuous symbols. Character code “FF 16” is so fixed as to be blank and to have no background, thus cannot assign a character font to this code. 18 dots Note: Hatching represents border. 12 dots Register CL17/18 (address F716) = “0” Register CL17/18 = “1” Positioning the cursor at the 17th dot. Positioning the cursor at the 18th dot. Character Note: When the cursor positioning at the bottom (18th) dot, no border is left at the bottom. When the character extends to the top dot of the matrix, no border is left at the top. When the character extends to the bottom (18th) dot of the matrix, no border is left at the bottom. (1) Border display (set by register BLK0, 1 (address F816)) (2) Cursor display (Border display)

SCREEN CHARACTER and PATTERN DISPLAY CONTROLLERS M35052-XXXSP/FP PERIPHERAL CIRCUIT Fig. 16 M35052-XXXSP/FP example of peripheral circuit In displaying color superimposition, enterinto the OSCIN pin the f SC signal that phase-synchronizes with the color burst ofthe composite video signals (input to theCVIN pin). Note 7: In dealing with the internal synchronization,cut off external video signals outside the IC.The leakage of external input video signalscan be aoided. 220 2.2k 120 150 +7.0V Composite video signal input 10k 47µ From microcomputer Note 1 +5.0V 470 +7.0V External composite video signal input 47µ Note 2 1.50V 220µ Note 5 4700P Note 6 10 11 CP1 TESTA SIN CVIDEO LECHA CVIN SCK VDD 2 CS AC VDD 1 VSS HOR OSCIN TESTB CP2 EDO 1µ + 1µ100µ 0.01µ +5.0V + + Note 4 0.01µ 0.22µ 4700P 1.5k fsc Note 3 I/O +5.0V 0.1µ 1µ100µ + + VSS Note 7 Delay circuit NTSC=3.580MHzPAL=4.434MHz M-PAL=3.576MHz Note 4: Construct integral circuit by built-in 30k Ω of AC pin and an external condenser.Attention to supply voltage rise time aboutthis CR constant. Note 5: External loop filter 2 constant is provi-sional valve. Note 6: Connect f SC frequency. 0.3Vp-p OSCIN ≤4.0Vp-p Note 1: Clamp sync chip to 1.50V. Note 2: Set basic electric potential in consideration of dynamic range of the tran-sistor. Note 3: External loop filter 1 constant is pro-visional valve.

SCREEN CHARACTER and PATTERN DISPLAY CONTROLLERS

0 C 1

O u t s i d e o f d i s p l a y a r e a I n s i d e o f d i s p l a y S e t b l a n k c o d e F t o c h a r a c t e r c o d e o f p a r t O u t s i d e o f d i s p l a y a r e a I n s i d e o f d i s p l a y 0 01 1 81 0 B1 2 F1 1 71 N u m b e r s a r e a d r e s s e s 2 31 3 01 4 81 4 71 5 F1 C 01 D 81

6 E F1

Fig. 17 Example of display Precautions (1) Points to note in setting the display RAMs a) Be careful to the edges may sway depending on the combina- tion of character’s background color and raster color. b) If what display exceeds the display area in dealing with exter- nal synchronization, (if use double - size characters), set the character code of the addresses lying outside that display area blank code – “FF 16”. E d g e s w a y Fig. 18 Example of display

SCREEN CHARACTER and PATTERN DISPLAY CONTROLLERS (2) Before setting registers at the starting of system, be sure to reset the M35052-XXXSP/FP by applying “L” level to the AC pin. (3) Power supply noise When power supply noise is generated, the internal oscillator cir- cuit does not stabilize, whereby causing horizontal jitters across the picture display. Therefore, connect a bypass capacitor be- tween the power supply and GND. (4) Synchronous correction action When switching channel or in the special playback mode (quick playback, rewinding, and so on) of VTR, effect of synchronous correction becomes strong, and distortion of a character is apt to occur because the continuity of video signal is suddenly switched. When the continuity of video signal is out of order, erasure of displayed characters is recommended in a extreme short time to raise the quality of displayed characters. (5) Notes on f SC signal input This IC amplifies the subcarrier frequency (fSC ) signal (NTSC, M- PAL system: 3.58MHz, PAL system: 4.43MHz) input to the OSCIN pin (17-pin) and generates the composite video signal internally. The amplified f SC signal can be destabilized in the following cases. a) When the fSC signal is outside of recommended operating con- ditions. b) When the waveform of the fSC signal is distorted. c) When DC level in the fSC waveform fluctuates. When the amplified signal is unstable, the composite video signal generated inside the IC is also unstable in terms of syn- chronization with the subcarrier and phase. Consequently, this results in color flicker and lost synchroniza- tion when the composite video signal is generated. Make note of the fact that this may prevent a stable blue background from being formed. (6) Forbidding to stop entering the f SC signal This IC doesn’t properly work if the fSC signal is not entered into the OSCIN pin (pin 17), so don’t stop the fSC signal so as to work the IC. To stop the IC, turn the display off (set 0 in the register DSPON (address F816).) (7) Forbidding to set data during the period in which the internal oscillation circuit stabilizes a) To start entering the f SC signal when its input is stopped. b) To start oscillating the oscillation circuit for display when its oscillation is stopped. (to assign “1” to the register STOP1 (ad- dress F816) when it is assigned “0”, or the like.) c) To turn on the internal bias when it is turned off. (to assign “1” to the register LEVEL1 (address F816) when it is assigned “0”.) There can be instances in which data are not properly set in the registers until the internal oscillation circuit stabilizes, so follow the steps in sequence as given below. 1) Set “0” in the register DSPON (address F8 16). (the display is turned off) 2) Effect the settings a), b), and c) given above. 3) Wait 20 ms (the period necessary for the internal oscillation cir- cuit to stabilize) before entering data. 4) Set necessary data in other registers, and make the display RAM ready.

SCREEN CHARACTER and PATTERN DISPLAY CONTROLLERS Parameter SCK width CS setup time CS hold time SIN setup time SIN hold time 1 word writing time Symbol tw(SCK) tsu(CS) th(CS) tsu(SIN) th(SIN) t word Min. 400 200 200 200 12.8 Unit ns ns µs ns ns µs __ __ Note. When oscillation stop at register STOR1 (address F816), 1V (field term) or more of tSU(CS ) and th(CS ) are needed. Max. Typ. Limits TIMING REQUIREMENTS (Ta = –20°C to 70°C, VDD = 5±0.25V, unless otherwise noted) Fig. 19 Serial input timing requirements S C K C S C S 2 Ês m i n t w C S t w S C K t s u S I N h S I N t s u C S ) t h C S w S C K S I N S C K t w o r d 12 1 61 4. . . 1 53 12 1 61 4c 1 53

SCREEN CHARACTER and PATTERN DISPLAY CONTROLLERS Parameter Supply voltage “H” level input voltage AC, CS, SIN, SCK, TESTA, TESTB “L ” level input voltage AC, CS, SIN, SCK, TESTA, TESTB CVIN, HOR Input voltage OSCIN (Note) Synchronous signal oscillation frequency (Duty 40~60%) Display oscillation frequency 24 characters5 10 lines 32 characters5 7 lines Symbol VDD VI VO Pd Topr Tstg Parameter Supply voltage Input voltage Output voltage Power dissipation Operating temperature Storage temperature Conditions With respect to V SS Ta=25°C Ratings –0.3~6.0 VSS –0.3≤VI≤VDD +0.3 VSS ≤VO ≤VDD 300 –20~70 –40~125 Unit V V V mW Limits Min. 4.75

0.85 VDD

0.3VP-P Typ. 5.00 VDD 2.0VP-P 3.580 4.434 3.576 4805 fH 6405 fH Max. 5.25 VDD

0.25 VDD

4.0VP-P Unit V V V V V MHz MHz MHz Notes 1.Noise component is within 30mV. Notes 2.f H : Horizontal synchronous frequency (MHz). Symbol VDD IDD VOH VOL R I VOH VOM VOL Limits Min. 4.75 3.75 4.0 1.5 Typ. 5.00 2.3 Max. 5.25 0.4 100 3.0 0.4 Unit V mA V V kΩ V V V Parameter Supply voltage Supply current “H” level output voltage P0, P1, SIN “L ” level output voltage P0, P1, SIN Pull-up resistance AC, CS, SCK, SIN, TESTB “H” level output voltage EDO “M”level output voltage EDO “L ” level output voltage EDO Symbol VIN-SC Limits Min. Typ. 1.5 Max. Unit V Parameter Composite video signal input clamp voltage Test conditions Sync-chip voltage Symbol VDD VIH VIL VCVIN VOSCIN fOSCIN fOSC1 fOSC2 Test conditions Ta=–20~70°C VDD =5.00V VDD =4.75V , IOH =–0.4mA VDD =4.75V , IOL =–0.4mA VDD =5.00V VDD =5.00V , IOH =–0.04mA VDD =5.00V , IOM =–0.04mA VDD =5.00V , IOL =0.04mA ABSOLUTE MAXIMUM RATINGS (VDD = 5V, Ta = –20 to 70°C, unless otherwise noted) RECOMMENDED OPERATING CONDITIONS (VDD = 5V, Ta = –20 to 70°C, unless otherwise noted) ELECTRICAL CHARACTERISTICS (VDD = 5V, Ta = 25°C, unless otherwise noted) VIDEO SIGNAL INPUT CONDITIONS (VDD = 5V, Ta = –20 to 70°C, unless otherwise noted)

SCREEN CHARACTER and PATTERN DISPLAY CONTROLLERS Note for Supplying Power (1) Timing of power supplying to AC pin The internal circuit of M35052-XXXSP/FP is reset when the level of the auto clear input pin AC is “L”. This pin is hysteresis input with the pull-up resistor. The timing about power supplying of AC pin is shown in Figure 20. t W is the interval after the supply volt- age becomes 0.8 5 VDD or more and before the supply voltage to __ __ the AC pin (VAC ) becomes 0.2 5 VDD or more. After supplying the power (VDD and VSS ) to M35052-XXXSP/FP, the tW time must be reserved for 1ms or more. Before starting input from the microcomputer, the waiting time (ts) must be re- served for 500ms after the supply voltage to the AC pin becomes 0.8 5 VDD or more. (2) Timing of power supplying to VDD 1 pin and VDD 2 pin The power need to supply to VDD 1 and VDD 2 at a time, though it is separated perfectly between the VDD 1 as the digital line and the VDD 2 as the analog line. ROM ORDERING METHOD Please submit the information described below when ordering Mask ROM. (three sets containing the identical data) (4) Program for character font generating + froppy disk in which char- acter data is input PRECAUTION FOR USE Notes on noise and latch-up Connect a capacitor (approx. 0.1ÊF) between pins VDD and VSS at the shortest distance using relatively thick wire to prevent noise and latch up. Fig. 20 Timing of power supplying to AC pin S u p p l y v o l t a g e VD D 85 VD D 25 VD D tw V o l t a g e mV n T i m e t s VA C iA C p i n i n p u t v o l t a g e j t s

SCREEN CHARACTER and PATTERN DISPLAY CONTROLLERS 0016 0116 0216 0316 0416 0516 0616 0716 0816 0916 0A16 0B16 0C 16 0D 16 0E16 0F16 1016 1116 1216 1316 1416 1516 1616 1716 1816 1916 1A16 1B16 1C 16 1D 16 1E16 1F16 2016 2116 2216 2316 2416 2516 2616 2716 2816 2916 2A16 2B16 2C 16 2D 16 2E16 2F16 3016 3116 3216 3316 3416 3516 3616 3716 3816 3916 3A16 3B16 3C 16 3D 16 3E16 3F16 STANDARD ROM TYPE : M35052-001SP/FP M35052-001SP/FP is a standard ROM type of M35052-XXXSP/FP Character patterns are fixed to the contents of Figure 21 to 23. Fig. 21 M35052-001SP/FP character patterns (1)

SCREEN CHARACTER and PATTERN DISPLAY CONTROLLERS 4016 4116 4216 4316 4416 4516 4616 4716 4816 4916 4A16 4B16 4C 16 4D 16 4E16 4F16 5016 5116 5216 5316 5416 5516 5616 5716 5816 5916 5A16 5B16 5C 16 5D 16 5E16 5F16 6016 6116 6216 6316 6416 6516 6616 6716 6816 6916 6A16 6B16 6C 16 6D 16 6E16 6F16 7016 7116 7216 7316 7416 7516 7616 7716 7816 7916 7A16 7B16 7C 16 7D 16 7E16 7F16 blank Fig. 22 M35052-001SP/FP character patterns (2)

SCREEN CHARACTER and PATTERN DISPLAY CONTROLLERS Receipt Data : Supervisor signature Section head signature Mask ROM number Company name Framing Date : TEL Issuance signature ApprovalVerification Note : Please fill in all items marked h , . h h h Remarks l Return the Character Font Preparation Program after use. l Three EPROMs are required. Specify the type of EPROMs submitted. (All the three EPROMs must be same types. Check 4 in the appropriate box.) 27256 27512 (1) The font data prepared by the Character Font Preparation Program is saved as a binary type object file (addresses 0000h to 7FFFh). Three sets of these EPROMs are required. (2) Attach the erase protect seals on three EPROMs. Each seal bears the type name (M35052), and ROM No. (–...SP/FP). l Write the checksum code (hexadecimal notation) for entire EPROM areas. Checksum l Select the marking type (Check 4 in the appropriate box). M35052-XXXFP) and attach to the Mask ROM Order Confirmation Form. l The package type hl Comments Customer Data issued MASK ROM ORDER CONFIRMATION FORM GZZ-SH00-50B<69A0> MASK ROM ORDER CONFIRMATION FORM SCREEN DISPLAY IC M35052-XXXSP/FP MITSUBISHI ELECTRIC Program version name M052R V

SCREEN CHARACTER and PATTERN DISPLAY CONTROLLERS Mask ROM numberGZZ-SH00-50B<69A0> h 2.Character patterns (The patterns with the mark “#” are test patterns) (See the next page) (2/6)

SCREEN CHARACTER and PATTERN DISPLAY CONTROLLERS 0016 0116 0216 0316 0416 0516 0616 0716 0816 0916 0A16 0B16 0C 16 0D 16 0E16 0F16 1016 1116 1216 1316 1416 1516 1616 1716 1816 1916 1A16 1B16 1C 16 1D 16 1E16 1F16 2016 2116 2216 2316 2416 2516 2616 2716 2816 2916 2A16 2B16 2C 16 2D 16 2E16 2F16 3016 3116 3216 3316 3416 3516 3616 3716 3816 3916 3A16 3B16 3C 16 3D 16 3E16 3F16 (3/6)

SCREEN CHARACTER and PATTERN DISPLAY CONTROLLERS 4016 4116 4216 4316 4416 4516 4616 4716 4816 4916 4A16 4B16 4C 16 4D 16 4E16 4F16 5016 5116 5216 5316 5416 5516 5616 5716 5816 5916 5A16 5B16 5C 16 5D 16 5E16 5F16 6016 6116 6216 6316 6416 6516 6616 6716 6816 6916 6A16 6B16 6C 16 6D 16 6E16 6F16 7016 7116 7216 7316 7416 7516 7616 7716 7816 7916 7A16 7B16 7C 16 7D 16 7E16 7F16 (4/6)

SCREEN CHARACTER and PATTERN DISPLAY CONTROLLERS 8016 8116 8216 8316 8416 8516 8616 8716 8816 8916 8A16 8B16 8C 16 8D 16 8E16 8F16 9016 9116 9216 9316 9416 9516 9616 9716 9816 9916 9A16 9B16 9C 16 9D 16 9E16 9F16 A016 A116 A216 A316 A416 A516 A616 A716 A816 A916 AA 16 AB 16 AC 16 AD 16 AE 16 AF 16 B016 B116 B216 B316 B416 B516 B616 B716 B816 B916 BA 16 BB 16 BC 16 BD 16 BE 16 BF 16 (5/6)

SCREEN CHARACTER and PATTERN DISPLAY CONTROLLERS C0 16 C1 16 C2 16 C3 16 C4 16 C5 16 C6 16 C7 16 C8 16 C9 16 CA 16 CB 16 CC 16 CD 16 CE 16 CF 16 D0 16 D1 16 D2 16 D3 16 D4 16 D5 16 D6 16 D7 16 D8 16 D9 16 DA 16 DB 16 DC 16 DD 16 DE 16 DF 16 E016 E116 E216 E316 E416 E516 E616 E716 E816 E916 EA 16 EB 16 EC 16 ED 16 EE 16 EF 16 F016 F116 F216 F316 F416 F516 F616 F716 F816 F916 FA 16 FB 16 FC 16 FD 16 FE 16 FF16 Blank (6/6)

SCREEN CHARACTER and PATTERN DISPLAY CONTROLLERS 20P4B (20-PIN DIP) MARK SPECIFICATION FORM Mitsubishi IC catalog name Please choose one of the marking types below (A, B, C), and enter the Mitsubishi catalog name and the special mark (if needed). A. Standard Mitsubishi Mark Note1 : If the Special Mark is to be Printed, indicate the desired layout of the mark in the upper figure. The layout will be duplicated as close as possible. Mitsubishi lot number (6-digit or 7-digit) and Mask ROM number (3-digit) are always marked. 2 : If the customer s trade mark logo must be used in the Special Mark, check the box on the right. Please submit a clean original of the logo. For the new special character fonts a clean font original (ideally logo drawing) must be submitted. Special logo required Mitsubishi IC catalog name C. Special Mark Required B. Customer s Parts Number + Mitsubishi catalog name Customers Parts Number Note : The fonts and size of characters are standard Mitsubishi type. Mitsubishi IC catalog name Note1 : The mark field should be written right aligned. 2 : The fonts and size of characters are standard Mitsubishi type. 3 : Customer s Parts Number can be up to 15 characters : Only 0 ~ 9, A ~ Z, +, Ð, /, (, ), &,  ,. (periods), and , (commas) are usable. 4 : If the Mitsubishi logo is not required, check the box on the right. Mitsubishi logo is not required 20 11 101 Mitsubishi lot number (6-digit or 7-digit) Mitsubishi lot number (6-digit or 7-digit) 20 11 101 Mask ROM number (3-digit) 20 11 101

SCREEN CHARACTER and PATTERN DISPLAY CONTROLLERS Customer s Parts Number Note: The fonts and size of characters are standard Mitsubishi type. Mitsubishi IC catalog name and Mitsubishi lot number Notes 1 : The mark field should be written right aligned. 2 : The fonts and size of characters are standard Mitsubishi type. 3 : Customer s Parts Number can be up to 10 characters: Only 0 to 9, A to Z, +, -, /, (, ), &, ©, . (period), and , (comma) are usable. 4 : If the Mitsubishi logo is not required, check the box be- low. Mitsubishi logo is not required 20P2Q-A (20-PIN SSOP) MARK SPECIFICATION FORM Mitsubishi IC catalog name Please choose one of the marking types below (A, B, C), and enter the Mitsubishi IC catalog name and the special mark (if needed). B. Customer s Parts Number + Mitsubishi IC Catalog Name Mitsubishi IC catalog name Mitsubishi IC catalog name Note 1 : If the Special Mark is to be Printed, indicate the desired layout of the mark in the left figure. The layout will be du- plicated as close as possible. Mitsubishi lot number (4-digit) and Mask ROM number (3-digit) are always marked. 2 : If the customer s trade mark logo must be used in the Special Mark, check the box below. Please submit a clean original of the logo. For the new special character fonts, a clean font original (ideally logo drawing) must be submitted. Special logo required Special Mark (Customer s Trade Mark) Mitsubishi IC catalog name Mitsubishi lot number (6-digit or 7-digit) 101 20 11 101 20 11 ROM number (3-digit) Mitsubishi lot number (4-digit) 101 20 11 A. Standard Mitsubishi Mark C. Special Mark Required

SCREEN CHARACTER and PATTERN DISPLAY CONTROLLERS PACKAGE OUTLINE

© 2000 MITSUBISHI ELECTRIC CORP. New publication, effective July. 2000. Specifications subject to change without notice. Notes regarding these materials

• These materials are intended as a reference to assist our customers in the selection of the Mitsubishi semiconductor product best suited to the customer’s application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Mitsubishi Electric Corporation or a third party.
• Mitsubishi Electric Corporation assumes no responsibility for any damage, or infringement of any third-party’s rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials.
• All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by Mitsubishi Electric Corporation without notice due to product improvements or other reasons. It is therefore recommended that customers contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for the latest product information before purchasing a product listed herein. The information described here may contain technical inaccuracies or typographical errors. Mitsubishi Electric Corporation assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. Please also pay attention to information published by Mitsubishi Electric Corporation by various means, including the Mitsubishi Semiconductor home page (http://www.mitsubishichips.com).
• When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. Mitsubishi Electric Corporation assumes no responsibility for any damage, liability or other loss resulting from the information contained herein.
• Mitsubishi Electric Corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use.
• The prior written approval of Mitsubishi Electric Corporation is necessary to reprint or reproduce in whole or in part these materials.
• If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited.
• Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for further details on these materials or the products contained therein. Keep safety first in your circuit designs!
• Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non-flammable material or (iii) prevention against any malfunction or mishap. HEAD OFFICE: 2-2-3, MARUNOUCHI, CHIYODA-KU, TOKYO 100-8310, JAPAN MITSUBISHI MICROCOMPUTERS M35052-XXXSP/FP SCREEN CHARACTER and PATTERN DISPLAY CONTROLLERS

Rev. Rev. No. date

1.0 First Edition 980402

1.1 P41 20P2Q-A (20-PIN SSOP) MARK SPECIFICATION FORM 000707

B: Note 4 added REVISION DESCRIPTION LIST M35052-XXXSP/FP DATA SHEET (1/1) Revision Description