M35046 MITSUBISHI | Alldatasheet
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Technical content
SCREEN CHARACTER and PATTERN DISPLAY CONTROLLERS
DESCRIPTION
The M35046-XXXSP/FP is a character pattern display control IC can display on the liquid crystal display and the plasma display. It uses a silicon gate CMOS process and it housed in a 20-pin shrink DIP pack- age (M35046-XXXSP) or a 20-pin shrink SOP package (M35046- XXXFP). For M35046-001SP/FP that is a standard ROM version of M35046- XXXSP/FP respectively, the character pattern is also mentioned.
FEATURES
- Display locations available Cycle : division of vertical synchronization signal into 32 or 64 Duty : 25%, 50%, or 75%
- Coloring Specified by register Specified by register Specified by register
- Blanking Character size blanking Border size blanking Matrix-outline blanking All blanking (all raster area)
- Output ports 4 shared output ports (toggled between RGB output) 4 dedicated output ports
- Display RAM erase function
- Horizontal synchronous input frequency
- Display oscillation stop function APPLICATION Liquid crystal display, Plasma display, Video projecter Outline 20P4B PIN CONFIGURATION (TOP VIEW) CPOUT ← @ VDD2 ← VERT ← HOR → P5/B → P4 → P3/G → P2 → P1/R → P0/BLNK0 @ VSS VSS2 @ AC → CS → SCK → SIN → TCK → VDD1 @ P6 ← P7 ← M35046 - XXXSP Outline 20P2Q-A CPOUT ← @ VDD2 ← VERT ← HOR → P5/B → P4 → P3/G → P2 → P1/R → P0/BLNK0 @ VSS1 VIR @ AC → CS → SCK → SIN → TCK → VDD1 @ P6 ← P7 ← M35046 - XXXFP
SCREEN CHARACTER and PATTERN DISPLAY CONTROLLERS Symbol CPOUT VSS2 AC CS SCK SIN TCK V DD1 V SS1 P0/BLNK0 P1/R P3/G P5/B HOR VERT V DD2 Input/ Output Output Input Input Input Input Input Output Output Output Output Output Output Output Output Input Input Function Connect loop filter to this pin. Connect to GND. When “L”, this pin resets the internal IC circuit. Hysteresis input. Built-in pull-up resistor. This is the chip select input pin, and when serial data transmission is being carried out, it goes to “L”. Hysteresis input. Built-in pull-up resistor. When CS pin is “L”, SIN serial data is taken in when SCK rises. Hysteresis input. Built-in pull-up resistor. This is the pin for serial input of data and addresses for the display control register and the display data memory. Hysteresis input. Built-in pull-up resistor. This is the pin for external clock input. Please connect to +5V with the power pin. This is the output port. Port data is set by PTD6. This is the output port. Port data is set by PTD7. Please connect to GND using circuit earthing pin. This pin can be toggled between port pin output and BLNK0 signal output. This pin can be toggled between port pin output and R signal output. This is the output port. Port data is set by PTD2. This pin can be toggled between port pin output and G signal output. This is the output port. Port data is set by PTD4. This pin can be toggled between port pin output and B signal output. This pin inputs the horizontal synchronous signal. Hysteresis input. This pin inputs the vertical synchronous signal. Hysteresis input. Please connect to +5V with the power pin. Pin name Phase difference Earthing pin Auto-clear input Chip select input Serial clock input Serial data input External clock Power pin Port P6 output Port P7 output Earthing pin Port P0 output Port P1 output Port P2 output Port P3 output Port P4 output Port P5 output Horizontal synchro- nous signal input Vertical synchro- nous signal input Power pin Pin Number PIN DESCRIPTION 1.0kΩ ∗1 0.01µF∗2 47pF CPOUT ∗1 Use at 1% precision ∗2 Use at 10% precision 1pin
SCREEN CHARACTER and PATTERN DISPLAY CONTROLLERS BLOCK DIAGRAM CS SCK SIN VDD1 VDD2 AC VSS VIR Clock oscillation circuit for display Timing generator Polarity switching circuit Address control circuit Data control circuit Display control register Display RAM Display character ROM Shift register Blinking circuitReading address control circuit Display location detection circuit H counter CPOUT TCK HOR VERT Synchronous signal switching circuit Display control circuit Port output control circuit Polarity switching circuti Input control circuit P0/BLNK0
13 P1/R
15 P3/G
17 P5/B
SCREEN CHARACTER and PATTERN DISPLAY CONTROLLERS DAF DAE DAD DAC DAB DAA DA9 DA8 DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0
0 BB BG BR BLINK B G R C7 C6 C5 C4 C3 C2 C1 C0
0 EXCK0 VJT DIVS1 DIVS0 DIV10 DIV9 DIV8 DIV7 DIV6 DIV5 DIV4 DIV3 DIV2 DIV1 DIV0
0 RSEL0 PTD7 PTD6 PTD5 PTD4 PTD3 PTD2 PTD1 PTD0 PTC5 PTC4 PTC3 PTC2 PTC1 PTC0
0 RSEL1
SPACE2 SPACE1 SPACE0 TEST9 HP9 HP8 HP7 HP6 HP5 HP4 HP3 HP2 HP1 HP0
0 EXCK1 TEST3 TEST2 TEST1 TEST0 VP9 VP8 VP7 VP6 VP5 VP4 VP3 VP2 VP1 VP0
TEST14 TEST5 TEST4 DSP11 DSP10 DSP9 DSP8 DSP7 DSP6 DSP5 DSP4 DSP3 DSP2 DSP1 DSP0
0 TEST10 VSZ1H1 VSZ1H0 VSZ1L1 VSZ1L0 V1SZ1 V1SZ0 LIN9 LIN8 LIN7 LIN6 LIN5 LIN4 LIN3 LIN2
0 TEST11 VSZ2H1 VSZ2H0 VSZ2L1 VSZ2L0 V18SZ1 V18SZ0 LIN17 LIN16 LIN15 LIN14 LIN13 LIN12 LIN11 LIN10
0 TEST12 HSZ21 HSZ20 HSZ11 HSZ10 BETA14 TEST8 TEST7 TEST6 FB FG FR RB RG RR
0 TEST13 BLINK2 BLINK1 BLINK0 DSPON STOP RAMERS SYAD BLK1 BLK0 POLH POLV VMASK
The screen lines and rows are determined from each address of the display RAM. The screen constitution is shown in Figure 2. MEMORY CONSTITUTION Address 00016 to 11F16 are assigned to the display RAM, address 12016 to 12816 are assigned to the display control registers. The in- ternal circuit is reset and all display control registers (address 12016__ to 12816) are set to “0” when the AC pin level is “L”. And then RAM is erased. Memory constitution is shown in Figure 1. ……… ……… Background coloring Character color Character code Row Line 00016 00116 00216 00316 00416 00516 00616 00716 00816 00916 00A16 00B16 00C16 00D16 00E16 00F16 01016 01116 01216 01316 01416 01516 01616 01716 01816 01916 01A16 01B16 01C16 01D16 01E16 01F16 02016 02116 02216 02316 02416 02516 02616 02716 02816 02916 02A16 02B16 02C16 02D16 02E16 02F16 03016 03116 03216 03316 03416 03516 03616 03716 03816 03916 03A16 03B16 03C16 03D16 03E16 03F16 04016 04116 04216 04316 04416 04516 04616 04716 04816 04916 04A16 04B16 04C16 04D16 04E16 04F16 05016 05116 05216 05316 05416 05516 05616 05716 05816 05916 05A16 05B16 05C16 05D16 05E16 05F16 06016 06116 06216 06316 06416 06516 06616 06716 06816 06916 06A16 06B16 06C16 06D16 06E16 06F16 07016 07116 07216 07316 07416 07516 07616 07716 07816 07916 07A16 07B16 07C16 07D16 07E16 07F16 08016 08116 08216 08316 08416 08516 08616 08716 08816 08916 08A16 08B16 08C16 08D16 08E16 08F16 09016 09116 09216 09316 09416 09516 09616 09716 09816 09916 09A16 09B16 09C16 09D16 09E16 09F16 0A016 0A116 0A216 0A316 0A416 0A516 0A616 0A716 0A816 0A916 0AA 16 0AB 16 0AC 16 0AD 16 0AE 16 0AF16 0B016 0B116 0B216 0B316 0B416 0B516 0B616 0B716 0B816 0B916 0BA 16 0BB 16 0BC 16 0BD 16 0BE 16 0BF16 0C016 0C116 0C216 0C316 0C416 0C516 0C616 0C716 0C816 0C916 0CA 16 0CB 16 0CC 16 0CD 16 0CE 16 0CF 16 0D016 0D116 0D216 0D316 0D416 0D516 0D616 0D716 0D816 0D916 0DA 16 0DB 16 0DC 16 0DD 16 0DE 16 0DF 16 0E016 0E116 0E216 0E316 0E416 0E516 0E616 0E716 0E816 0E916 0EA 16 0EB 16 0EC 16 0ED 16 0EE 16 0EF16 0F016 0F116 0F216 0F316 0F416 0F516 0F616 0F716 0F816 0F916 0FA16 0FB16 0FC 16 0FD 16 0FE16 0FF16 10016 10116 10216 10316 10416 10516 10616 10716 10816 10916 10A16 10B16 10C16 10D16 10E16 10F16 11016 11116 11216 11316 11416 11516 11616 11716 11816 11916 11A16 11B16 11C16 11D16 11E16 11F16 123456789 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 ¦ The hexadecimal numbers in the boxes show the display RAM address. Fig. 2 Screen constitution Fig. 1 Memory constitution Blink- ing
SCREEN CHARACTER and PATTERN DISPLAY CONTROLLERS For details, see (2) Setting display frequencies under Register Supplementary Description. It should be fixed to “0”. Alleviates continuous vertical jitters. DIV0 DIV1 DIV2 DIV3 DIV4 DIV5 DIV6 DIV7 DIV8 DIV9 DIV10 DIVS0 DIVS1 VJT EXCK0 A B C D E REGISTERS DESCRIPTION (1) Address 12016 Set display frequency by frequency value setting. Set N1 to be “N1=fOSC / fH”. fOSC (MHz) : External clock frequency for TCK pin (=display fre- quency) f H (kHz) : Horizontal synchronous sig- nal frequency for HOR pin Set registers DIVS0, DIVS1 (address 120 16), RSEL0 (address 12116) and RSEL1 (address 12216) according to external clock frequency. For details, see (2) Setting display fre- quencies under Register Supplemen- tary Description. Any of this settings above is reguired only when EXCK1=1, EXCK0=1. RegisterDA Status
Contents
Set display frequency area. See setting External Clock Input Mode (to be input from the TCK terminal). EXCK1 : address 123 H C l o c k n u m b e r N E x t e r n a l c l o c k H o r i z o n t a l s y n c h r o n i z e d s i g n a l Set external clock frequency value of horizontal oscillation fre- quency. N1 = (DIVn × 2n) N1: frequency value Σ n = 0
SCREEN CHARACTER and PATTERN DISPLAY CONTROLLERS (2) Address 12116 P0 output (port P0). Port data is set by PTD0. BLNK0 output. Polarity is set by PTD0. P1 output (port P1). Port data is set by PTD1. R signal output. Polarity is set by PTD1. P2 output (port P2). Port data is set by PTD2. Can not be used. P3 output (port P3). Port data is set by PTD3. G signal output. Polarity is set by PTD3. P4 output (port P4). Port data is set by PTD4. Can not be used. P5 output (port P5). Port data is set by PTD5. B signal output. Polarity is set by PTD5. “L” output (P0 output) or negative polarity output (BLNK0 output). “H” output (P0 output) or positive polarity output (BLNK0 output). “L” output (P1 output) or negative polarity output (R signal output). “H” output (P1 output) or positive polarity output (R signal output). “L” output (P2 output). “H” output (P2 output). “L” output (P3 output) or negative polarity output (G signal output). “H” output (P3 output) or positive polarity output (G signal output). “L” output (P2 output). “H” output (P2 output). “L” output (P5 output) or negative polarity output (B signal output). “H” output (P5 output) or positive polarity output (B signal output). “L” output (P6 output). “H” output (P6 output). “L” output (P7 output). “H” output (P7 output). For details, see (2) Setting display frequencies under Register Supplementary Description. To be used when EXCK0=1 and EXCK1=1. BLNK0 outputs blanking signal. Blanking status is determined by BLK0, BLK1, and DSP0 to DSP11 settings. P0 pin data control. P1 pin data control. P2 pin exclusive port output state con- trol. P3 pin data control. P4 pin exclusive port output state con- trol. P5 pin data control. P6 pin exclusive port output state con- trol. P7 pin exclusive port output state con- trol. Set display frequency area. A B C D E (Note) (Note) (Note) (Note) (Note) (Note) (Note) (Note) Note. To determined this register, input clock (at least one clock) to the external clock pin (TCK). PTC0 PTC1 PTC2 PTC3 PTC4 PTC5 PTD0 PTD1 PTD2 PTD3 PTD4 PTD5 PTD6 PTD7 RSEL0
SCREEN CHARACTER and PATTERN DISPLAY CONTROLLERS (3) Address 12216 Horizontal display start location is specified using the 10 bits from HP9 to HP0. HP9 to HP0 = (0000000000 2) and (00000101112) setting is forbidden.___ Note : In case of B/F register is “0”. Register Function RemarksDA Status A B C D E If HS is the horizontal display start location, HS = T × 2nHP n + 6 T: The cycle of display frequency 1000 settings are possible. Leave one line worth of space in the ver- tical direction. For example, 6 ê 6 indicates two sets of 6 lines with a line of spaces between lines 6 and 7. A line is 18 × N horizontal scan lines. N is determined by the character size in the vertical direction as follows: … N = 1 ×2 … N = 2 Set display frequency area. HP1 HP2 HP3 HP4 HP5 HP6 HP7 HP8 TEST9 SPACE0 SPACE1 SPACE2 RSEL1 HP9 (MSB) HP0 (LSB) SPACE Number of Lines and Space (ê represents space) 1 ê 10 Í 1 2 ê 8 Í 2 3 ê 6 Í 3 4 ê 4 Í 4 5 ê 2 Í 5 6 ê 6 6 ê Í 6 ê represents one line worth of spaces. It should be fixed to “0”. Can not be used. For details, see (2) Setting display frequencies under Register Supplementary Description. To be used when EXCK0=1 and EXCK1=1. Σ n = 0 H O R N o t e H P V P D i s p l a y a r e a V E R T
SCREEN CHARACTER and PATTERN DISPLAY CONTROLLERS (4) Address 12316 The vertical start location is specified using the 10 bits from VP9 to VP0. VP9 to VP0 = (0000000000 2) setting is forbidden. _ Note : In case of B/F register is “0”. RegisterDA Status A B C D E VP1 VP2 VP3 VP4 VP5 VP6 VP7 VP8 TEST0 TEST1 TEST2 TEST3 EXCK1 If VS is the vertical display start location, VS = H × 2nVP n H: Cycle with the horizontal synchronizing pulse 1023 settings are possible. VP9 (MSB) VP0 (LSB) Function Remarks Σ n = 0 It should be fixed to “0”. Can not be used. It should be fixed to “0”. Can not be used. It should be fixed to “0”. Can not be used. It should be fixed to “0”. Can not be used. For setting. See Register EXCK0 (address 120 16). Sets input mode of external clock (input from TCK pin). H O R N o t e H P V P D i s p l a y a r e a V E R T
SCREEN CHARACTER and PATTERN DISPLAY CONTROLLERS Blanking is in the display mode specified by BLK0 and BLK1. (Note) Blanking is in the display mode specified by except BLK0 and BLK1. (Note) Blanking is in the display mode specified by BLK0 and BLK1. (Note) Blanking is in the display mode specified by except BLK0 and BLK1. (Note) Blanking is in the display mode specified by BLK0 and BLK1. (Note) Blanking is in the display mode specified by except BLK0 and BLK1. (Note) Blanking is in the display mode specified by BLK0 and BLK1. (Note) Blanking is in the display mode specified by except BLK0 and BLK1. (Note) Blanking is in the display mode specified by BLK0 and BLK1. (Note) Blanking is in the display mode specified by except BLK0 and BLK1. (Note) Blanking is in the display mode specified by BLK0 and BLK1. (Note) Blanking is in the display mode specified by except BLK0 and BLK1. (Note) Blanking is in the display mode specified by BLK0 and BLK1. (Note) Blanking is in the display mode specified by except BLK0 and BLK1. (Note) Blanking is in the display mode specified by BLK0 and BLK1. (Note) Blanking is in the display mode specified by except BLK0 and BLK1. (Note) Blanking is in the display mode specified by BLK0 and BLK1. (Note) Blanking is in the display mode specified by except BLK0 and BLK1. (Note) Blanking is in the display mode specified by BLK0 and BLK1. (Note) Blanking is in the display mode specified by except BLK0 and BLK1. (Note) Blanking is in the display mode specified by BLK0 and BLK1. (Note) Blanking is in the display mode specified by except BLK0 and BLK1. (Note) Blanking is in the display mode specified by BLK0 and BLK1. (Note) Blanking is in the display mode specified by except BLK0 and BLK1. (Note) It should be fixed to “0”. Can not be used. It should be fixed to “0”. Can not be used. Can not be used. It should be fixed to “1”. (5) Address 124 A B C D E DSP0 DSP1 DSP2 DSP3 DSP4 DSP5 DSP6 DSP7 DSP8 DSP9 DSP10 DSP11 TEST4 TEST5 TEST14 RegisterDA Status Note: Refer to DISPLAY FORM1. Sets the display mode of line 1. Sets the display mode of line 2. Sets the display mode of line 3. Sets the display mode of line 4. Sets the display mode of line 5. Sets the display mode of line 6. Sets the display mode of line 7. Sets the display mode of line 8. Sets the display mode of line 9. Sets the display mode of line 10. Sets the display mode of line 11. Sets the display mode of line 12. Remarks
SCREEN CHARACTER and PATTERN DISPLAY CONTROLLERS Character size setting in the vertical direction for the 2nd line. Character size setting in the vertical direction for the 3rd line. Character size setting in the vertical direction for the 4th line. Character size setting in the vertical direction for the 5th line. Character size setting in the vertical direction for the 6th line. Character size setting in the vertical direction for the 7th line. Character size setting in the vertical direction for the 8th line. Character size setting in the vertical direction for the 9th line. Character size setting in the vertical direction for the 1st line. (display monitor 1 to 12 line) Character size setting in the vertical direction (display monitor 1 line) at “0” state in register LIN2 to LIN17. Character size setting in the vertical direction (display monitor 1 line) at “1” state in register LIN2 to LIN17. (6) Address 125 A B C D E LIN2 LIN3 LIN4 LIN5 LIN6 LIN7 LIN8 LIN9 V1SZ0 V1SZ1 VSZ1L0 VSZ1L1 VSZ1H0 VSZ1H1 TEST10 RegisterDA Status The first line is set by VSZ1L0 and VSZ1L1. The second to 12th lines are set by VSZ2L0 and VSZ2L1. The first line is set by VSZ1H0 and VSZ1H1. The second to 12th lines are set by VSZ2H0 and VSZ2H1. The first line is set by VSZ1L0 and VSZ1L1. The second to 12th lines are set by VSZ2L0 and VSZ2L1. The first line is set by VSZ1H0 and VSZ1H1. The second to 12th lines are set by VSZ2H0 and VSZ2H1. The first line is set by VSZ1L0 and VSZ1L1. The second to 12th lines are set by VSZ2L0 and VSZ2L1. The first line is set by VSZ1H0 and VSZ1H1. The second to 12th lines are set by VSZ2H0 and VSZ2H1. The first line is set by VSZ1L0 and VSZ1L1. The second to 12th lines are set by VSZ2L0 and VSZ2L1. The first line is set by VSZ1H0 and VSZ1H1. The second to 12th lines are set by VSZ2H0 and VSZ2H1. The first line is set by VSZ1L0 and VSZ1L1. The second to 12th lines are set by VSZ2L0 and VSZ2L1. The first line is set by VSZ1H0 and VSZ1H1. The second to 12th lines are set by VSZ2H0 and VSZ2H1. The first line is set by VSZ1L0 and VSZ1L1. The second to 12th lines are set by VSZ2L0 and VSZ2L1. The first line is set by VSZ1H0 and VSZ1H1. The second to 12th lines are set by VSZ2H0 and VSZ2H1. The first line is set by VSZ1L0 and VSZ1L1. The second to 12th lines are set by VSZ2L0 and VSZ2L1. The first line is set by VSZ1H0 and VSZ1H1. The second to 12th lines are set by VSZ2H0 and VSZ2H1. The first line is set by VSZ1L0 and VSZ1L1. The second to 12th lines are set by VSZ2L0 and VSZ2L1. The first line is set by VSZ1H0 and VSZ1H1. The second to 12th lines are set by VSZ2H0 and VSZ2H1. H: Cycle with the horizontal synchronizing pulse V1SZ1 V1SZ0 Vertical direction size 1H/dot 2H/dot 3H/dot 4H/dot H: Cycle with the horizontal synchronizing pulse VSZ1L1 VSZ1L0 Vertical direction size 1H/dot 2H/dot 3H/dot 4H/dot H: Cycle with the horizontal synchronizing pulse It should be fixed to “0”. Test mode VSZ1H1 VSZ1H0 Vertical direction size 1H/dot 2H/dot 3H/dot 4H/dot
SCREEN CHARACTER and PATTERN DISPLAY CONTROLLERS Character size setting in the vertical direction for the 10th line. Character size setting in the vertical direction for the 11th line. Character size setting in the vertical direction for the 12th line. Character size setting in the vertical direction for the 13th line. Character size setting in the vertical direction for the 14th line. Character size setting in the vertical direction for the 15th line. Character size setting in the vertical direction for the 16th line. Character size setting in the vertical direction for the 17th line. Character size setting in the vertical direction for the 18th line. (display monitor 1 to 12 line) Character size setting in the vertical direction (display monitor for 2 to 12 line) at “0” state in register LIN2 to LIN17. Character size setting in the vertical direction (display monitor for 2 to 12 line) at “1” state in register LIN2 to LIN17. (7) Address 126 A B C D E LIN10 LIN11 LIN12 LIN13 LIN14 LIN15 LIN16 LIN17 V18SZ0 V18SZ1 VSZ2L0 VSZ2L1 VSZ2H0 VSZ2H1 TEST11 RegisterDA Status The first line is set by VSZ1L0 and VSZ1L1. The second to 12th lines are set by VSZ2L0 and VSZ2L1. The first line is set by VSZ1H0 and VSZ1H1. The second to 12th lines are set by VSZ2H0 and VSZ2H1. The first line is set by VSZ1L0 and VSZ1L1. The second to 12th lines are set by VSZ2L0 and VSZ2L1. The first line is set by VSZ1H0 and VSZ1H1. The second to 12th lines are set by VSZ2H0 and VSZ2H1. The first line is set by VSZ1L0 and VSZ1L1. The second to 12th lines are set by VSZ2L0 and VSZ2L1. The first line is set by VSZ1H0 and VSZ1H1. The second to 12th lines are set by VSZ2H0 and VSZ2H1. The first line is set by VSZ1L0 and VSZ1L1. The second to 12th lines are set by VSZ2L0 and VSZ2L1. The first line is set by VSZ1H0 and VSZ1H1. The second to 12th lines are set by VSZ2H0 and VSZ2H1. The first line is set by VSZ1L0 and VSZ1L1. The second to 12th lines are set by VSZ2L0 and VSZ2L1. The first line is set by VSZ1H0 and VSZ1H1. The second to 12th lines are set by VSZ2H0 and VSZ2H1. The first line is set by VSZ1L0 and VSZ1L1. The second to 12th lines are set by VSZ2L0 and VSZ2L1. The first line is set by VSZ1H0 and VSZ1H1. The second to 12th lines are set by VSZ2H0 and VSZ2H1. The first line is set by VSZ1L0 and VSZ1L1. The second to 12th lines are set by VSZ2L0 and VSZ2L1. The first line is set by VSZ1H0 and VSZ1H1. The second to 12th lines are set by VSZ2H0 and VSZ2H1. The first line is set by VSZ1L0 and VSZ1L1. The second to 12th lines are set by VSZ2L0 and VSZ2L1. The first line is set by VSZ1H0 and VSZ1H1. The second to 12th lines are set by VSZ2H0 and VSZ2H1. H: Cycle with the horizontal synchronizing pulse V18SZ1 V18SZ0 Vertical direction size 1H/dot 2H/dot 3H/dot 4H/dot H: Cycle with the horizontal synchronizing pulse VSZ2L1 VSZ2L0 Vertical direction size 1H/dot 2H/dot 3H/dot 4H/dot H: Cycle with the horizontal synchronizing pulse It should be fixed to “0”. Test mode VSZ2H1 VSZ2H0 Vertical direction size 1H/dot 2H/dot 3H/dot 4H/dot
SCREEN CHARACTER and PATTERN DISPLAY CONTROLLERS Color Black Red Green Yellow Blue Magenta Cyan White Sets the color of all blankings. Sets the blanking color of the Border size, or the shadow size. Set this register to the character font set by display RAM BR, BG and BB. Character size setting in the horizontal direction for the first line. Character size setting in the horizontal direction for the 2nd line to 12th line. (8) Address 12716 A B C D E RR RG RB FR FG FB TEST6 TEST7 TEST8 BETA14 HSZ10 HSZ11 HSZ20 HSZ21 TEST12 RegisterDA Status T: Display frequency cycle HSZ11 HSZ10 Horizontal direction size 1T/dot 2T/dot 3T/dot 4T/dot T: Display frequency cycle It should be fixed to “0”. Test mode VSZ21 HSZ20 Horizontal direction size 1T/dot 2T/dot 3T/dot 4T/dot It should be fixed to “0”. Can not be used. It should be fixed to “0”. Can not be used. It should be fixed to “0”. Can not be used. Matrix-outline display (12 × 18 dot) Matrix-outline display (14 × 18 dot) RB RG RR Color Black Red Green Yellow Blue Magenta Cyan White BB BG BR
SCREEN CHARACTER and PATTERN DISPLAY CONTROLLERS Sets all raster blanking Synchronize with the front porch or back porch of the horizontal synchronazation signal. This register has or do not have mask at phase comparison operating. Set VERT pin polarity. Set HOR pin polarity. Set blanking mode. (Note 1) An example of blanking mode at BCOL = “0”, DSPn = “0” (n = 0 to 11) shown left. (Note 2) There is no need to reset because there is no register for this bit. R, G, B and BLNK0 output can be altered. Display can be altered. Blinking duty ratio can be altered. Blinking frequency can be altered. (9) Address 128 A B C D E BCOL B/F VMASK POLV POLH BLK0 BLK1 SYAD RAMERS STOP DSPON BLINK0 BLINK1 BLINK2 TEST13 RegisterDA Status 25% 50% 75% Blanking mode Matrix-outline size Character size Border size Matrix-outline size BLK Notes 1: Refer to DISPLAY FORM 1 2: Refer to DISPLAY FORM 3 Blanking of BLK0, BLK1 All raster blanking Synchronize with the leading edge of horizontal synchronization. Synchronize with the trailing edge of horizontal synchronization. Do not mask by VERT input signal Mask by VERT input signal VERT pin is negative polarity VERT pin is positive polarity HOR pin is negative polarity HOR pin is positive polarity Border display of character Shadow display of character RAM not erased RAM erased Oscillation of clock for display Stop the oscillation of clock for display Display OFF Display ON Divided into 64 of vertical synchronous signal Divided into 32 of vertical synchronous signal It should be fixed to “0”. Test mode
SCREEN CHARACTER and PATTERN DISPLAY CONTROLLERS REGISTER SUPPLEMENTARY DESCRIPTION (1) Setting external clock input mode (by use of EXCK0 (12016) and EXCK1 (12316)) Two modes given below are available for the external clock sig- nal input. (the settings (EXCK1, EXCK0) = (0, 1), (1, 0) are forbid- den.) (a) When (EXCK1, EXCK0) = (0, 0), F OSC = 20 to 30 MHz Input from the TCK pin a constant-period continuous external clock that synchronizes with the horizontal synchronization signal. And input from HOR pin a constant-period continuous horizontal synchronous signal. Never stop inputting the clock while displaying. Do not have to set a display frequency because the clock just as it is entered from outside is used as the display clock. (b) When (EXCK1, EXCK0) = (1, 1), F OSC = 20 to 80 MHz Input from the TCK pin a constant-period continuous external clock that synchronizes with the horizontal synchronization signal. Never stop inputting the clock while displaying. Be sure to set a display frequency because the internal clock made to synchronize with the clock input from outside is used as the display clock (see the next page). E x t e r n a l c l o c k H o r i z o n t a l s y n c h r o n o u s s i g n a l E x a m p l e f o r i n p u t
SCREEN CHARACTER and PATTERN DISPLAY CONTROLLERS (2) Setting display frequencies Set a display frequency by setting a frequency value for the hori- zontal synchronization signal by use of DIV10 to DIV0 (120 16). Set display frequency area in conformity with the frequency of the external clock signal. Set display frequency area by use of DIVS0, DIVS1 (120 16), RSEL0 (12116), and RSEL1 (12216). Frequency area are as fol- lows. RSEL1 RSEL0 DIVS1 DIVS0 Display frequency area 0 1 0 0 70.0 to 80.0 0 0 0 0 63.0 to 70.0 1 0 0 1 56.6 to 63.0 0 1 0 1 46.6 to 56.6 0 0 0 1 45.0 to 46.6 1 0 1 0 42.5 to 45.0 0 1 1 0 35.0 to 42.5 0 0 1 0 31.5 to 35.0 1 0 1 1 28.3 to 31.5 0 1 1 1 23.3 to 28.3 0 0 1 1 20.0 to 23.3 Cautions in setting a display frequency To change the external clock frequency or the horizontal synchroni- zation frequency, follow the steps in sequence given below. (a) Display OFF (DSPON = 0) (b) Set the display frequency(Use DIV10 to DIV0 (120 16), DIVS0, DIVS1 (120 16), RSEL0 (12116), and RSEL1 (12216).) (c) 20-ms waiting time with the horizontal synchronization signal and the external clock signal being input (d) Display ON (DSPON = 1)
Table 1 shows display form of blanking. Table 1. Display mode Matrix-outline and border display. Matrix-outline and border display. Matrix-outline and border display. Matrix-outline and border display. Notes 1: Color setting of raster area is set by register RR, RG and RB. 4: Set border by register FR, FG and FB. Set matrix-outline by BR, BG and BB of display RAM.
SCREEN CHARACTER and PATTERN DISPLAY CONTROLLERS Fig. 3 Display form DISPLAY FORM 2 M35046-XXXSP/FP has the following four display forms. (1) Character size : Blanking same as the character size. (2) Border size : Blanking the background as a size from character. (3) Matrix-outline size : Blanking the background 12 × 18 dot. When set register BETA14 to “1”, setting of blanking the background 14 × 18 dot is possible. (4) All blanking size : When set register BCOL to “1”, all raster area is blanking. 12dots 12dots 12dots 12dots Set character color by display RAM (Note 1) (address 0 to 11F16) Scanning Scanning Set border color by register FR,FG and FB Set border color by display RAM (Note 1) Set border color by display RAM (Note 1) Set matrix - outline color (Note 1) by display RAM (Note 3) Set matrix - outline color (Note 1) by RAM for display (Note 3) R,G or B output BLNK0 output (1) Character display (character size) (Note 2) (2) Border display (border size) (Note 2) (3) Matrix - outline display (matrix-outline size) (Note 2) (4) Matrix - outline and border display (matrix-outline size) (Note 2) 12dots 12dots 12dots 12dots Set character color by display RAM (Note 1) (address 0 to 11F 16) Set border color by register FR,FG and FB Set raster area color by register RR,RG and RB Set matrix - outline color (Note 1) by display RAM (Note 3) Set matrix - outline color (Note 1) by display RAM (Note 3) R,G or B output BLNK0 output (1) Character display (all blanking size) (Note 2) (2) Border display (all blanking size) (Note 2) (3) Matrix - outline display (all blanking size) (Note 2) (4) Matrix - outline and border display (all blanking size) (Note 2) Notes 1 : Red,Blue,Yellow,Green,Magenta,Cyan, White and Black are set possible. 2 : ( ) is blanking mode. 3 : All matrix - outline horizontal direction size is able to set to 14dots by register BETA14 (BLNK0 output by 14dots). 〈 Register BCOL = “0” 〉 〈 Register BCOL = “1” 〉 “H” level GND level
SCREEN CHARACTER and PATTERN DISPLAY CONTROLLERS DISPLAY FORM 3 When border display mode, if set SYAD = “0” to “1”, it change to shadow display mode. Border and shadow display are shown below. Fig. 4 Border and shadow display Set shadow display color by display RAM or register FR, FG and FB. Border display Shadow display
SCREEN CHARACTER and PATTERN DISPLAY CONTROLLERS DATA INPUT EXAMPLE Data of display RAM and display control registers can be set by the serial input function. Example of data setting is shown in Figure 5 and Figure 6. (1) At EXCK0 = “0”, EXCK1 = “0” setting 297 298 299 300 Example of data setting by the serial input function (M35046-XXXSP/FP) 200 msec hold ……… ………… ………… address 12016 data 120 16 data 121 16 data 122 16 data 123 16 data 124 16 data 125 16 data 126 16 data 127 16 data 128 16 data 000 16 data 11F 16 address 12816 data 128 16 Notes 1 : Input the horizontal synchronous signal to the HOR pin and the vertical synchronous signal to the VERT pin. If serrated pulses are present in the vertical synchronous signal, set the register VMASK to 1. 2 : Matrix-outline display in this data. Fig. 5 Example of data setting by the serial input function (1) DAF DAE DAD DAC DAB DAA DA9 DA8 DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0 0000000100100000 0010000000000000
00 PTD7 PTD6 1 PTD4 1 PTD2 11101011
0 0 0 0 0 0 HP9 HP8 HP7 HP6 HP5 HP4 HP3 HP2 HP1 HP0 0 0 0 0 0 0 VP9 VP8 VP7 VP6 VP5 VP4 VP3 VP2 VP1 VP0 0000000000000000 0000000000000000 0000000000000000 0000000000000000 00000001011 POLH POLV 000 0B B B G B R BLINK BGR C 7 C6 C 5 C 4 C3 C 2 C 1 C0 0B B B G B R BLINK BGR C 7 C6 C 5 C 4 C3 C 2 C 1 C0 0000000100101000
00000100011 POLH POLV 000
(Note 1) Output setting Horizontal display location setting Vertical display location setting Display form setting Character size setting Character size setting Color, character size setting Display OFF, display form (Note 2) Character setting Address setting Display ON, display form (Note 2)
SCREEN CHARACTER and PATTERN DISPLAY CONTROLLERS DAF DAE DAD DAC DAB DAA DA9 DA8 DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0 0000000100100000
011 DIVS1 DIVS0 DIV10 DIV9 DIV8 DIV7 DIV6 DIV5 DIV4 DIV3 DIV2 DIV1 DIV0
0 RSEL0 PTD7 PTD6 1 PTD4 1 PTD2 11101011
0 RSEL1 0 0 0 0 HP9 HP8 HP7 HP6 HP5 HP4 HP3 HP2 HP1 HP0
0 1 0 0 0 0 VP9 VP8 VP7 VP6 VP5 VP4 VP3 VP2 VP1 VP0 0100000000000000 0000000000000000 0000000000000000 0000000000000000 00000001011 POLH POLV 000 0B B B G B R BLINK BGR C 7 C6 C 5 C 4 C3 C 2 C 1 C0 0B B B G B R BLINK BGR C 7 C6 C 5 C 4 C3 C 2 C 1 C0 0000000100101000 Hold the time length as 1V of vertical synchronous signal 200 msec hold 297 298 299 300 address 12016 data 120 16 data 121 16 data 122 16 data 123 16 data 124 16 data 125 16 data 126 16 data 127 16 data 128 16 data 000 16 data 11F 16 address 12816 data 128 16 ……… ……… ……… Character code Addition System set-up Address set Set frequency value of horizontal synchronous frequency(Note 1) Output setting Oscillation circuit setting Character setting Notes 1 : From this time, input clock to TCK pin. And, input the horizontal synchronous signal to the HOR pin and the vertical synchronous signal to the VERT pin. If serrated pulses are present in the vertical synchronous signal, set the register VMASK to 1. 2 : Matrix-outline display in this data. (2) At EXCK0 = “1”, EXCK1 = “1” setting Fig. 6 Example of data setting by the serial input function (2) Character background color Character color Horizontal display location setting Oscillation circuit setting Vertical display location setting Display form setting Character size setting Character size setting Color, character size setting Display OFF, display form (Note 2) BLINK -ING Address setting Display ON, display form (Note 2)
SCREEN CHARACTER and PATTERN DISPLAY CONTROLLERS SERIAL DATA INPUT TIMING (1) Serial data should be input with the LSB first. (2) The address consists of 16 bits. (3) The data consists of 16 bits. (4) The 16 bits in the SCK after the CS signal has fallen are the address, and for succeeding input data, the address is incremented every 16 bits. Therefore, it is not necessary to in- put the address from the second data. Fig. 7 Serial input timing CS N = 1,2,3……… SCK SIN LSB MSB LSB MSB LSB MSB Address(16 bits) Data(16 bits) N Data(16 bits) N + 1
SCREEN CHARACTER and PATTERN DISPLAY CONTROLLERS CHARACTER FONT Images are composed on a 12 × 18 dot matrix, and characters can be linked vertically and horizontally with other characters to allow the display the continuous symbols. Fig. 8 Example for displaying a continuous pattern after combining characters in the horizontal or vertical direction Character code FF16 is fixed as a blank without background. Therefore, cannot register a character font in this code. When the character extends to the top line of the matrix, no border is left at the top. When the character extends to the bottom (18th) line of the matrix, no border is left at the bottom. Note : Hatching represents border. 12 dots 18 dots
SCREEN CHARACTER and PATTERN DISPLAY CONTROLLERS Symbol tw (SCK) tsu(CS) th(CS) tsu(SIN) th(SIN) tword TIMING REQUIREMENTS (Ta = –20°C to + 85°C, VDD = 5±0.25V, unless otherwise noted) Unit ns ns µs ns ns µs Parameter SCK width CS setup time CS hold time SIN setup time SIN hold time 1 word writing time Min. 200 200 200 200 Typ. Max. Remarks See Figure 9 Limits Fig. 9 Serial input timing requirements tsu(CS) tw(SCK) tw(SCK) tsu(SIN) th(SIN) th(CS) tw(CS) 1µs(min.) tword more than 2 µs 1 2 12 13 14 15 16… 1 1 21 31 41 51 6… CS SCK SIN SCK CS
SCREEN CHARACTER and PATTERN DISPLAY CONTROLLERS Unit V mA V V kΩ VPP Min. 4.75 3.5 0.7VDD Parameter Supply voltage Supply current “H” level output voltage “L” level output voltage __ __ Pull-up resistance SCK, AC, CS, SIN External clock input width Test conditions Ta = –20 to +85°C VDD = 5.25V VDD = 4.75V, IOH = 0.4mA VDD = 4.75V, IOH = 0.05mA VDD = 4.75V, IOL = 0.4mA VDD = 4.75V, IOL = 0.05mA VDD = 5.0V 4.75V < VDD ≤ 5.25V Unit V V V MHz kHz Parameter Supply voltage __ __ “H” level input voltage SIN, SCK, CS, AC HOR, VERT __ __ “L” level input voltage SIN, SCK, CS, AC HOR, VERT Oscillating frequency for display Horizontal synchronous signal input frequeney Symbol VDD VIH VIL FOSC Hsync Symbol VDD VI VO Pd Topr Tstg ABSOLUTE MAXIMUM RATINGS Parameter Supply voltage Input voltage Output voltage Power dissipation Operating temperature Storage temperature Conditions With respect to VSS . Ta = 25°C Ratings –0.3 to +6.0 VSS –0.3 ≤ VI ≤ VDD +0.3 VSS ≤ VO ≤ VDD 300 –20 to +85 –40 to +125 Unit V V V mW Typ. 5.0 VDD Min. 4.75 0.8VDD 20.0 15.0 Max. 5.25 VDD 0.2VDD 80.0 130.0 Limits RECOMMENDED OPERATING CONDITIONS (VDD = 5V, Ta = –20 to +85°C, unless otherwise noted) ELECTRICAL CHARACTERISTICS (VDD = 5V, Ta = 25°C, unless otherwise noted) Symbol VDD IDD VOH VOL RI VTCK Limits Max. 5.25 0.4 100 0.9V DD P0 to P7 CPOUT P0 to P7 CPOUT Typ. 5.0
SCREEN CHARACTER and PATTERN DISPLAY CONTROLLERS NOTE FOR SUPPLYING POWER__ Timing of power supplying to AC pin The internal circuit of M35046-XXXSP/FP is reset when the level of__ the auto clear input pin AC is “L”. This pin in hysteresis input with the__ pull-up resistor. The timing about power supplying of AC pin is shown in Figure 11. Timing of power supplying to V DD1 and VDD2 . Supply power to VDD1 and VDD2 at the same time. DATA REQUIRED FOR MASK ROM ORDERING Please send the following data for mask orders. (1) M35046-XXXSP/FP mask ROM order confirmation form (2) 20P4B mask specification form (3) 20P2Q-A mask specification from (4) ROM data (EPROM 3 sets) (5) Floppy disks containing the character font generating program + character data Supply voltage VAC (AC pin input voltage) 0.8 × VDD 0.2 × VDD tW tS VDD Time t[s] more than 1ms Voltage [V] After supplying the power (VDD and VSS ) to M35046-XXXSP/FP and the supply voltage becomes more than 0.8 × VDD , it needs to keep VIL time; tw of the AC pin for more than 1ms. Start inputting from microcomputer after AC pin supply voltage becomes more than 0.8 × VDD and keeping 200ms wait time. PRECAUTION FOR USE Notes on noise and latch-up In order to avoid noise and latch-up, connect a bypass capacitor (≈0.1µF) directly between the V DD1 pin and VSS pin, and the VDD2 pin and VSS pin using a heavy wire. Fig. 11 Timing of power supplying to AC pin
SCREEN CHARACTER and PATTERN DISPLAY CONTROLLERS STANDARD ROM TYPE : M35046-001SP/FP M35046-001SP/FP is a standard ROM type of M35046-XXXSP/FP. The character patterns are fixed to the contents of Figure 12 to 15.
SCREEN CHARACTER and PATTERN DISPLAY CONTROLLERS 0016 0116 0216 0316 0416 0516 0616 0716 0816 0916 0A16 0B16 0C16 0D16 0E16 0F16 1016 1116 1216 1316 1416 1516 1616 1716 1816 1916 1A16 1B16 1C16 1D16 1E16 1F16 2016 2116 2216 2316 2416 2516 2616 2716 2816 2916 2A16 2B16 2C16 2D16 2E16 2F16 3016 3116 3216 3316 3416 3516 3616 3716 3816 3916 3A16 3B16 3C16 3D16 3E16 3F16 Fig. 12 M35046-001SP/FP character pattern (1)
SCREEN CHARACTER and PATTERN DISPLAY CONTROLLERS 4016 4116 4216 4316 4416 4516 4616 4716 4816 4916 4A16 4B16 4C16 4D16 4E16 4F16 5016 5116 5216 5316 5416 5516 5616 5716 5816 5916 5A16 5B16 5C16 5D16 5E16 5F16 6016 6116 6216 6316 6416 6516 6616 6716 6816 6916 6A16 6B16 6C16 6D16 6E16 6F16 7016 7116 7216 7316 7416 7516 7616 7716 7816 7916 7A16 7B16 7C16 7D16 7E16 7F16 blank Fig. 13 M35046-001SP/FP character pattern (2)
SCREEN CHARACTER and PATTERN DISPLAY CONTROLLERS 8016 8116 8216 8316 8416 8516 8616 8716 8816 8916 8A16 8B16 8C16 8D16 8E16 8F16 9016 9116 9216 9316 9416 9516 9616 9716 9816 9916 9A16 9B16 9C16 9D16 9E16 9F16 A016 A116 A216 A316 A416 A516 A616 A716 A816 A916 AA16 AB16 AC16 AD16 AE16 AF16 B016 B116 B216 B316 B416 B516 B616 B716 B816 B916 BA16 BB16 BC16 BD16 BE16 BF16 Fig. 14 M35046-001SP/FP character pattern (3)
SCREEN CHARACTER and PATTERN DISPLAY CONTROLLERS C016 C116 C216 C316 C416 C516 C616 C716 C816 C916 CA16 CB16 CC16 CD16 CE16 CF16 D016 D116 D216 D316 D416 D516 D616 D716 D816 D916 DA16 DB16 DC16 DD16 DE16 DF16 E016 E116 E216 E316 E416 E516 E616 E716 E816 E916 EA16 EB16 EC16 ED16 EE16 EF16 F016 F116 F216 F316 F416 F516 F616 F716 F816 F916 FA16 FB16 FC16 FD16 FE16 FF16 blank Fig. 15 M35046-001SP/FP character pattern (4)
SCREEN CHARACTER and PATTERN DISPLAY CONTROLLERS 0016 0116 0216 0316 0416 0516 0616 0716 0816 0916 0A16 0B16 0C16 0D16 0E16 0F16 1016 1116 1216 1316 1416 1516 1616 1716 1816 1916 1A16 1B16 1C16 1D16 1E16 1F16 2016 2116 2216 2316 2416 2516 2616 2716 2816 2916 2A16 2B16 2C16 2D16 2E16 2F16 3016 3116 3216 3316 3416 3516 3616 3716 3816 3916 3A16 3B16 3C16 3D16 3E16 3F16
SCREEN CHARACTER and PATTERN DISPLAY CONTROLLERS 4016 4116 4216 4316 4416 4516 4616 4716 4816 4916 4A16 4B16 4C16 4D16 4E16 4F16 5016 5116 5216 5316 5416 5516 5616 5716 5816 5916 5A16 5B16 5C16 5D16 5E16 5F16 6016 6116 6216 6316 6416 6516 6616 6716 6816 6916 6A16 6B16 6C16 6D16 6E16 6F16 7016 7116 7216 7316 7416 7516 7616 7716 7816 7916 7A16 7B16 7C16 7D16 7E16 7F16 blank
SCREEN CHARACTER and PATTERN DISPLAY CONTROLLERS 8016 8116 8216 8316 8416 8516 8616 8716 8816 8916 8A16 8B16 8C16 8D16 8E16 8F16 9016 9116 9216 9316 9416 9516 9616 9716 9816 9916 9A16 9B16 9C16 9D16 9E16 9F16 A016 A116 A216 A316 A416 A516 A616 A716 A816 A916 AA16 AB16 AC16 AD16 AE16 AF16 B016 B116 B216 B316 B416 B516 B616 B716 B816 B916 BA16 BB16 BC16 BD16 BE16 BF16
SCREEN CHARACTER and PATTERN DISPLAY CONTROLLERS C016 C116 C216 C316 C416 C516 C616 C716 C816 C916 CA16 CB16 CC16 CD16 CE16 CF16 D016 D116 D216 D316 D416 D516 D616 D716 D816 D916 DA16 DB16 DC16 DD16 DE16 DF16 E016 E116 E216 E316 E416 E516 E616 E716 E816 E916 EA16 EB16 EC16 ED16 EE16 EF16 F016 F116 F216 F316 F416 F516 F616 F716 F816 F916 FA16 FB16 FC16 FD16 FE16 FF16 blank
SCREEN CHARACTER and PATTERN DISPLAY CONTROLLERS
SCREEN CHARACTER and PATTERN DISPLAY CONTROLLERS
SCREEN CHARACTER and PATTERN DISPLAY CONTROLLERS PACKAGE OUTLINE
SCREEN CHARACTER and PATTERN DISPLAY CONTROLLERS MEMO
SCREEN CHARACTER and PATTERN DISPLAY CONTROLLERS