M34282M1-XXXGP

M34282M1 MITSUBISHI | Alldatasheet

Document overview

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Technical content

(× 4 bits) 48 words 64 words 64 words PIN CONFIGURATION (TOP VIEW) ROM (PROM) size (× 9 bits) 1024 words 2048 words 2048 words Product M34282M1-XXXGP M34282M2-XXXGP M34282E2GP

DESCRIPTION

The 4282 Group enables fabrication of 8 × 7 key matrix and has the followin timers;

• an 8-bit timer which can be used to set each carrier wave and has two reload register
• an 8-bit timer which can be used to auto-control and has a reload register.

FEATURES

µs (at f(XIN) = 4.0 MHz, system clock = f(XIN)/8)

• Timer (This has a reload register and carrier wave output auto-control function) (This has two reload registers and carrier wave output function)
• Logic operation function (XOR, OR, AND)
• RAM back-up function
• Key-on wakeup function (ports D
• Watchdog timer
• Power-on reset circuit (system reset) APPLICATION Various remote control transmitters

4282 Group

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS VS S 1 9 1 6 1 4 1 3 1 2 1 1 D D 2 D 3 D 4 D 5 D 1 D 0 CARR VDD D 6 G 3 G 2 XIN XO U T G 0 G 1 M 3 4 2 8 2 M x - X X X G P Outline 20P2E/F-A

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER BLOCK DIAGRAM R A M w o r d s b i t s R O M w o r d s b i t s s e r i e s C P U c o r e M e m o r y I / O p o r t I n t e r n a l p e r i p h e r a l f u n c t i o n T i m e r R e m o t e c o n t r o l c a r r i e r w a v e o u t p u t T i m e r b i t s c a r r i e r w a v e o u t p u t c o n t r o l T i m e r b i t s c a r r i e r w a v e g e n e r a t i o n S y s t e m c l o c k g e n e r a t i o n c i r c u i t X I N X O U T ( N o t e R e g i s t e r B b i t s R e g i s t e r A b i t s R e g i s t e r D b i t s R e g i s t e r E b i t s S t a c k r e g i s t e r S K l e v e l s A L U b i t s P o r t P o r t P o r t W a t c h d o g t i m e r b i t s R e s e t v o l t a g e d r o p d e t e c t i o n c i r c u i t N o t e P R O M w o r d s b i t s R A M w o r d s b i t s f o r b u i l t i n P R O M v e r s i o n

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER PERFORMANCE OVERVIEW Function 8.0 µs (f(XIN) = 4.0 MHz, system clock = f(XIN)/8, VDD = 3 V) 2048 words ✕ 9 bits 1024 words ✕ 9 bits 64 words ✕ 4 bits 48 words ✕ 4 bits Four independent output ports Four independent I/O ports with the pull-down function 3-bit input port with the pull-down function 2-bit output port (E 0, E1) 4-bit I/O port with the pull-down function 1-bit output port; CMOS output 8-bit timer with a reload register 8-bit timer with two reload registers 4 levels (However, only 3 levels can be used when the TABP p instruction is executed) CMOS silicon gate 20-pin plastic molded SSOP (20P2E/F-A) –20 °C to 85 °C 1.8 V to 3.6 V 400 µA (f(X IN) = 4.0 MHz, system clock = f(XIN)/8, VDD = 3 V) 0.1 µA (at room temperature, VDD = 3 V) Parameter Number of basic instructions Minimum instruction execution time Memory sizes Input/Output ports Timer Subroutine nesting Device structure Package Operating temperature range Supply voltage Power dissipation (typical value) ROM RAM D 0–D 3 D 4–D 7 E0–E2 E0, E1 G 0–G 3 CARR Timer 1 Timer 2 Active mode RAM back-up mode M34282M2/E2 M34282M1 M34282M2/E2 M34282M1 Output I/O Input Output I/O Output PIN DESCRIPTION Name Power supply Ground System clock input System clock output Output port D I/O port D I/O port E I/O port G Carrier wave output for remote control Input/Output Input Output Output I/O Output Input I/O Output Function Connected to a plus power supply. Connected to a 0 V power supply. I/O pins of the system clock generating circuit. Connect a ceramic resonator between pins X IN and XOUT . The feedback resistor is built-in between pins XIN and XOUT . Each pin of port D has an independent 1-bit wide output function. The output structure is P-channel open-drain. 1-bit I/O port. For input use, set the latch of the specified bit to “0.” When the built- in pull-down transistor is turned on, the key-on wakeup function using “H ” level sense and the pull-down transistor become valid. The output structure is P-channel open-drain. 2-bit (E 0, E1) output port. The output structure is P-channel open-drain. 3-bit input port. For input use (E0, E1), set the latch of the specified bit to “0.” When the built-in pull-down transistor is turned on, the key-on wakeup function using “H ” level sense and the pull-down transistor become valid. Port E 2 has an input-only port and has a key-on wakeup function using “H ” level sense and pull- down transistor. 4-bit I/O port. For input use, set the latch of the specified bit to “0.” The output structure is P-channel open-drain. When the built-in pull-down transistor is turned on, the key- on wakeup function using “H ” level sense and pull-down transistor become valid. Carrier wave output pin for remote control. The output structure is CMOS circuit. Pin VDD VSS XIN XOUT D 0–D 3 D 4–D 7 E0–E2 G 0–G 3 CARR

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER CONNECTIONS OF UNUSED PINS Pin D 0–D 7 E0, E1 G 0–G 3 Connection Open or connect to VDD pin (Note 1). Set the output latch to “1” and open, or connect to VDD pin (Note 2). Open or connect to VSS pin. Set the output latch to “1” and open, or connect to VDD pin (Note 2). Notes 1: Ports D4–D 7: Set the bit 2 (PU02) of the pull-down control register PU1 to “0” by software and turn the pull-down transistor OFF. 2: Set the corresponding bits of the pull-down control register PU0 to “0” by software and turn the pull-down transistor OFF. (Note in order to set the output latch to “1” to make pins open)

• After system is released from reset, a port is in a high-impedance state until the output latch of the port is set to “1” by software. Accordingly, the voltage level of pins is undefined and the excess of the supply current may occur.
• To set the output latch periodically is recommended because the value of output latch may change by noise or a program run away (caused by noise). (Note when connecting to VSS and VDD )
• Connect the unused pins to VSS or VDD at the shortest distance and use the thick wire against noise. PORT FUNCTION Control bits 1 bit Output: 2 bits Input: 3 bits 4 bits 1 bit Control instructions SD RD CLD SD RD CLD SZD OEA IAE IAE OGA IAG SCAR RCAR Control registers PU1 PU0 PU0 Output structure P-channel open-drain P-channel open-drain P-channel open-drain CMOS Input/ Output Output (4) I/O (4) I/O (2) Input (1) I/O (4) Output (1) Remark Pull-down function and key-on wakeup function (programmable) Pull-down function and key-on wakeup function (programmable) Pull-down function and key-on wakeup function (programmable) Pin D 0–D 3 D 4–D 7 G 0–G 3 CARR Port Port D Port E Port G Port CARR DEFINITION OF CLOCK AND CYCLE
• System clock (STCK) The system clock is the source clock for controlling this product. It can be selected as shown below whether to use the CCK instruction. CCK instruction When not using When using Instruction clock f(XIN)/32 f(XIN)/4 System clock f(XIN)/8 f(XIN)
• Instruction clock (INSTCK) The instruction clock is a signal derived by dividing the system clock by 4, and is the basic clock for controlling CPU. The one instruction clock cycle is equivalent to one machine cycle.
• Machine cycle The machine cycle is the cycle required to execute the instruction.

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER PORT BLOCK DIAGRAMS CLD instruction SD instruction RD instruction Ports D0–D 3 S R Q DecoderRegister Y (Note 1) Port E2 (Note 5) Key-on wakeup input IAE instruction Register A Skip decision (SZD instruction) CLD instruction SD instruction RD instruction S R Q DecoderRegister Y PU1 i Pull-down transistorKey-on wakeup (Note 2) Ports E0, E1 (Note 5)OEA instruction Register A Aj Aj D T Q PU0 j Key-on wakeup input IAE instruction (Note 3) (Note 3) Ports G0, G1 (Note 5) Key-on wakeup input OGA instruction IAG instruction Register A Aj Aj D T Q (Note 3) PU0 2 Port CARR (Note 1) Timer 1 underflow signal D T Q R V10 Carrier wave output control signal CARRY (to timer 1) V12 CARRYD (from timer 2) S R QSCAR instruction RCAR instruction CAR flag PU0 3 Key-on wakeup input OGA instruction IAG instruction Register A Ak Ak D T Q (Note 1) (Note 4) (Note 1) Ports D4–D 7 (Note 5) Pull-down transistor (Note 1) (Note 1) (Note 1) Pull-down transistor Pull-down transistor Pull-down transistor Ports G2, G3 (Note 5) Notes 1: 2: i represents bits 0 to 3. 3: j represents bits 0, 1. 4: k represents bits 2, 3. 5: Applied voltage must be less than VDD. This symbol represents a parasitic diode.

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER Fig. 1 AMC instruction execution example Fig. 2 RAR instruction execution example Fig. 3 Registers A, B and register E FUNCTION BLOCK OPERATIONS CPU (1) Arithmetic logic unit (ALU) The arithmetic logic unit ALU performs 4-bit arithmetic such as 4-bit data addition, comparison, and bit manipulation. (2) Register A and carry flag Register A is a 4-bit register used for arithmetic, transfer, exchange, and I/O operation. Carry flag CY is a 1-bit flag that is set to “1” when there is a carry with the AMC instruction (Figure 1). It is unchanged with both A n instruction and AM instruction. The value of A 0 is stored in carry flag CY with the RAR instruction (Figure 2). Carry flag CY can be set to “1” with the SC instruction and cleared to “0” with the RC instruction. (3) Registers B and E Register B is a 4-bit register used for temporary storage of 4- bit data, and for 8-bit data transfer together with register A. Register E is an 8-bit register. It can be used for 8-bit data transfer with register B used as the high-order 4 bits and register A as the low-order 4 bits (Figure 3). (4) Register D Register D is a 3-bit register. It is used to store a 7-bit ROM address together with register A and is used as a pointer within the specified page when the TABP p, BLA p, or BMLA p instruction is executed (Figure 4). Fig. 4 TABP p instruction execution example (CY) (M(DP)) (A) Addition ALU <Carry> <Result> CY A 3 A2 A1 A0 A0 CY A 3 A2 A1 <Rotation> RAR instruction <Set> SC instruction <Clear> RC instruction A3 A2 A1 A0B3 B2 B1 B0 ER 7ER 6ER 5ER 4ER 3ER 2ER 1ER 0 A3 A2 A1 A0B3 B2 B1 B0 TAB instruction TEAB instruction TABE instruction TBA instruction Register B Register A Register B Register A Register E Specifying address p3 p2 p1 p0 PC H DR 2 DR 1 DR 0 A3 A2 A1 A0 PC L Immediate field value p The contents of register D The contents of register A ROM 8 40 TABP p instruction Low-order 4 bits Middle-order 4 bits Most significant 1 bit URS flag (1) URSC instruction Register A (4) Register B (4) Carry flag CY (1)

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER Fig. 5 Stack registers (SKs) structure Fig. 6 Example of operation at subroutine call (5) Most significant ROM code reference enable flag (URS) URS flag controls whether to refer to the contents of the most significant 1 bit (bit 8) of ROM code when executing the TABP p instruction. If URS flag is “0,” the contents of the most significant 1 bit of ROM code is not referred even when executing the TABP p instruction. However, if URS flag is “1,” the contents of the most significant 1 bit of ROM code is set to flag CY when executing the TABP p instruction (Figure 4). URS flag is “0” after system is released from reset and returned from RAM back-up mode. It can be set to “1” with the URSC instruction, but cannot be cleared to “0.” (6) Stack registers (SKs) and stack pointer (SP) Stack registers (SKs) are used to temporarily store the contents of program counter (PC) just before branching until returning to the original routine when;

• performing a subroutine call, or
• executing the table reference instruction (TABP p). Stack registers (SKs) are four identical registers, so that subroutines can be nested up to 4 levels. However, one of stack registers is used when executing a table reference instruction. Accordingly, be careful not to over the stack. The contents of registers SKs are destroyed when 4 levels are exceeded. The register SK nesting level is pointed automatically by 2-bit stack pointer (SP). Figure 5 shows the stack registers (SKs) structure. Figure 6 shows the example of operation at subroutine call. (7) Skip flag Skip flag controls skip decision for the conditional skip instructions and continuous described skip instructions. Note : The 4282 Group just invalidates the next instruction when a skip is performed. The contents of program counter is not increased by 2. Accordingly, the number of cycles does not change even if skip is not performed. However, the cycle count becomes “1” if the TABP p, RT, or RTS instruction is skipped. SK 0 SK 1 SK 2 SK 3 (SP) = 0 (SP) = 1 (SP) = 2 (SP) = 3 Program counter (PC) Executing RT instruction Executing BM instruction Stack pointer (SP) points “3” at reset or returning from RAM back-up mode. It points “0” by executing the first BM instruction, and the contents of program counter is stored in SK When the BM instruction is executed after four stack registers are used ((SP) = 3), (SP) = 0 and the contents of SK 0 is destroyed. Returning to the BM instruction execution address with the RT instruction, and the BM instruction is equivalent to the NOP instruction. (SP) ← 0 (SK0) ← 000116 (PC) ← SUB1 Main program

000216 NOP

000016 NOP

000116 BM SUB1

SUB1 : NOP RT (PC) ← (SK0) (SP) ← 3 Note:

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER Fig. 7 Program counter (PC) structure Fig. 8 Data pointer (DP) structure Fig. 9 SD instruction execution example (8) Program counter (PC) Program counter (PC) is used to specify a ROM address (page and address). It determines a sequence in which instructions stored in ROM are read. It is a binary counter that increments the number of instruction bytes each time an instruction is executed. However, the value changes to a specified address when branch instructions, subroutine call instructions, return instructions, or the table reference instruction (TABP p) is executed. Program counter consists of PC H (most significant bit to bit 7) which specifies to a ROM page and PCL (bits 6 to 0) which specifies an address within a page. After it reaches the last address (address 127) of a page, it specifies address 0 of the next page (Figure 7). Make sure that the PC H does not exceed after the last page of the built-in ROM. (9) Data pointer (DP) Data pointer (DP) is used to specify a RAM address and consists of registers X and Y. Register X specifies a file and register Y specifies a RAM digit (Figure 8). Register Y is also used to specify the port D bit position. When using port D, set the port D bit position to register Y certainly and execute the SD, RD, or SZD instruction (Figure 9). p3 p2 p1 p0 a6 a5 a4 a3 a2 a1 a0 Program counter (PC) PC H Specifying page PC L Specifying address 0 1 01 D 5D 7 D 0 Specifying bit position Set Register Y (4) Port D output latch X1 X0 Y3 Y2 Y1 Y0 Data pointer (DP) Register X (2) Register Y (4)Specifying RAM digit Specifying RAM file

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER Fig. 10 ROM map of M34282M2/E2 PROGRAM MEMORY (ROM) The program memory is a mask ROM. 1 word of ROM is composed of 9 bits. ROM is separated every 128 words by the unit of page (addresses 0 to 127). Table 1 ROM size and pages Fig. 11 RAM map Page 2 (addresses 010016 to 017F16) is the special page for subroutine calls. Subroutines written in this page can be called from any page with the 1-word instruction (BM). Subroutines extending from page 2 to another page can also be called with the BM instruction when it starts on page 2. ROM pattern of all addresses can be used as data areas with the TABP p instruction. DATA MEMORY (RAM) 1 word of RAM is composed of 4 bits, but 1-bit manipulation (with the SB j, RB j, and SZB j instructions) is enabled for the entire memory area. A RAM address is specified by a data pointer. The data pointer consists of registers X and Y. Set a value to the data pointer certainly when executing an instruction to access RAM. Table 2 shows the RAM size. Figure 11 shows the RAM map. Product M34282M2/E2 M34282M1 ROM size (✕ 9 bits) 2048 words 1024 words Pages 16 (0 to 15) 8 (0 to 7) Product M34282M2/E2 M34282M1 RAM size 64 words ✕ 4 bits (256 bits) 48 words ✕ 4 bits (192 bits) Table 2 RAM size Register Y Register X 0 1 RAM 64 words ✕ 4 bits (256 bits) 64 words M34282M2/E2 48 words M34282M1 087654321 000016 008016 017F16 Subroutine special page 007F16 00FF16 010016 07FF16 018016 Page 1 Page 2 Page 0 Page 3 Page 15

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER Fig. 12 Auto-reload function TIMERS The 4282 Group has the programmable timer.

• Programmable timer The programmable timer has a reload register and enables the frequency dividing ratio to be set. It is decremented from a setting value n. When it underflows (count to n + 1), a timer 1 underflow flag is set to “1,” new data is loaded from the reload register, and count continues (auto-reload function). FF16 n 0016 n: Counter initial value Count starts Reload Reload 1st underflow 2nd underflow n+1 count n+1 count Time A skip instruction is executed Timer 1 underflow flag The contents of counter “1” “0” The 4282 Group timer consists of the following circuit.
• Timer 1 : 8-bit programmable timer
• Timer 2 : 8-bit programmable timer These timers can be controlled with the timer control registers V1 and V2. Each timer function is described below. Table 3 Function related timer Circuit Timer 1 Timer 2 14-bit timer Structure 8-bit programmable binary down counter 8-bit programmable binary down counter 14-bit fixed frequency Count source
• Carrier wave output (CARRY)
• Bit 5 of watchdog timer
• f(X IN)
• f(XIN)/2
• Instruction clock Frequency dividing ratio 1 to 256 1 to 256 16384 Use of output signal
• Carrier wave output control
• Carrier wave output
• Watchdog timer
• Timer 1 count source Control register

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER Fig. 13 Timers structure XIN Frequency divider (divided by 4) INSTCK (Instruction clock) Frequency divider (divided by 8) STCK (System clock) Initializing signal WRST instruction System reset INSTCK QS R CCK instruction Initializing signal (Note 4) (Note 3) Synchronous circuit 14-bit timer (WDT) 130 5 Initializing signal(Note 4) WDF1 WDF2 (Note 1) V10 CARRY V11 Reload register R1 (8) Timer 1 (8) Register B Register A (T1AB) (TAB1) (Note 2) T1F SNZT1 instruction Timer 1 underflow signal (to port CARR) Register A Register A Reload control circuit (TAB2) V22 Q R T T2F Register B (T2AB) Reload register R2L (8) Timer 2(8) Register B (T2HAB) Reload register R2H (8) V20 (Note 1)V21 (TAB2) (T2AB) CARRYD (to port CARR) T2F V23 SNZT2 instruction XIN D T Q R V10 Carrier wave output control signal V12 Port CARR SCAR instruction SQ RRCAR instruction CAR flag CARRY (to timer 1) Timer 1 underflow signal (T2R2L) (TAB1) (Note 3) Notes 1: Counting is stopped by clearing to “0.” 2: When the T1AB instruction is executed after V10 is set to “1,” writing is performed only to reload register R1. 3: The data of reload register R2L set with the T2AB instruction can be also written to timer 2 with the T2R2L instruction. 4: The initializing signal is output at reset or RAM back-up mode.

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER Table 4 Control registers related to timer V12 V11 V10 Timer control register V1 Auto-control output by timer 1 is invalid Auto-control output by timer 1 is valid Carrier wave output (CARRY) Bit 5 of watchdog timer (WDT) Stop (Timer 1 state retained) Operating Carrier wave output auto-control bit Timer 1 count source selection bit Timer 1 control bit at reset : 0002 Wat RAM back-up : 0002 V13 V12 V11 V10 Timer control register V1 To expand “H ” interval is invalid To expand “H ” interval is valid (when V22=1 selected) Carrier wave generation function invalid Carrier wave generation function valid f(X IN) f(XIN)/2 Stop (Timer 2 state retained) Operating Carrier wave “H ” interval expansion bit Carrier wave generation function control bit Timer 2 count source selection bit Timer 2 control bit at reset : 00002 Wat RAM back-up : 00002 Note: “W ” represents write enabled. (1) Control registers related to timer

• Timer control register V1 Register V1 controls the timer 1 count source and auto- control function of carrier wave output from port CARR by timer 1. Set the contents of this register through register A with the TV1A instruction.
• Timer control register V2 Register V2 controls the timer 2 count source and the carrier wave generation function by timer. Set the contents of this register through register A with the TV2A instruction. (2) Precautions Note the following for the use of timers.
• Count source Stop timer 1 or timer 2 counting to change its count source.
• Watchdog timer Be sure that the timing to execute the WRST instruction in order to operate WDT efficiently.
• Writing to reload register R1 When writing data to reload register R1 while timer 1 is operating, avoid a timing when timer 1 underflows.
• Timer 1 count operation When the bit 5 of the watchdog timer (WDT) is selected as the timer 1 count source, the error of maximum ± 256 µs (at the minimum instruction execution time : 8 µs) is generated from timer 1 start until timer 1 underflow. When programming, be careful about this error.
• Stop of timer 2 Avoid a timing when timer 2 underflows to stop timer 2.
• Writing to reload register R2H When writing data to reload register R2H while timer 2 is operating, avoid a timing when timer underflows.
• Timer 2 carrier wave output function When to expand “H ” interval of carrier wave is valid, set “1” or more to reload register R2H.

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER (3) Timer 1 Timer 1 is an 8-bit binary down counter with the timer 1 reload register (R1). When timer is stopped, data can be set simultaneously in timer 1 and the reload register (R1) with the T1AB instruction. When timer is operating, data can be set to only reload register R1 with the T1AB instruction. When setting the next count data to reload register R1 at operating, set data before timer 1 underflows. Timer 1 starts counting after the following process; ➀ set data in timer 1, ➁ select the count source with the bit 1 of register V1, and ➂ set the bit 0 of register V1 to “1.” Once count is started, when timer 1 underflows (the next count pulse is input after the contents of timer 1 becomes “0”), the timer 1 underflow flag (T1F) is set to “1,” new data is loaded from reload register R1, and count continues (auto-reload function). When a value set in reload register R1 is n, timer 1 divides the count source signal by n + 1 (n = 0 to 255). When the bit 2 of register V1 is set to “1,” the carrier wave output enable/disable interval of port CARR is alternately generated each timer 1 underflows (Figure 14). Data can be read from timer 1 to registers A and B. When reading the data, stop the counter and then execute the TAB1 instruction. (4) Timer 2 Timer 2 is an 8-bit binary down counter with the timer 2 reload registers (R2H and R2L). Data can be set simultaneously in timer 2 and the reload register (R2L) with the T2AB instruction. The contents of reload register (R2L) set with the T2AB instruction can be set again to timer 2 with the T2R2L instruction. Data can be set to reload register (R2H) with the T2HAB instruction. Timer 2 starts counting after the following process; ➀ set data in timer 2, ➁ select the count source with the bit 1 of register V2, and ➂ select the valid/invalid of the carrier wave generation function by bit 2 of register V1 (when this function is valid, select the valid/invalid of the carrier wave “H ” interval expansion by bit 3), and ➃ set the bit 0 of register V1 to “1.” When the carrier wave generation function is invalid (V2 2=“0”), the following operation is performed; Once count is started, when timer 2 underflows (the next count pulse is input after the contents of timer 2 becomes “0”), the timer 2 underflow flag (T2F) is set to “1,” new data is loaded from reload register R2L, and count continues (auto-reload function). When a value set in reload register R2L is n, timer 2 divides the count source signal by n + 1 (n = 0 to 255). When the carrier wave generation function is valid (V2 2=“1”), the carrier wave which has the “L” interval set to the reload register R2L and “H ” interval set to the reload register R2H can be output (Figure 15). After the count of the “L” interval of carrier wave is started, timer 2 underflows and the timer 2 underflow flag (T2F) is set to “1”. Then, the “H ” interval data of carrier wave is reloaded from the reload register R2H, and count continues. When timer underflows again after auto-reload, the T2F flag is set to “1”. And then, the “L” interval data of carrier wave is reloaded from the reload register R2L, and count continues. After that, each timer underflows, data is reloaded from reload register R2H and R2L alternately. When a value set in reload register R2H is n, “H ” interval of carrier wave is as follows; ➀ When to expand “H ” interval is invalid (V2 3 = “0”), Count source ✕ (n+1), n = 0 to 255 ➁ When to expand “H ” interval is valid (V23 = “1”), Count source ✕ (n+1.5), n = 1 to 255 When a value set in reload register R2L is m, “L” interval of carrier wave is as follows; Count source ✕ (m+1), m = 0 to 255 Data can be read from timer 2 to registers A and B. When reading the data, stop the counter and then execute the TAB2 instruction. (5) Timer underflow flags (T1F, T2F) Timer 1 underflow flag or timer 2 underflow flag is set to “1” when the timer 1 or timer 2 underflows. The state of flags T1F and T2F can be examined with the skip instruction (SNZT1, SNZT2). Flags T1F and T2F are cleared to “0” when the next instruction is skipped with a skip instruction.

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER Fig. 15 Carrier wave generation example by timer 2 Fig. 14 Port CARR output control by timer 1 Port CARR output R e g i s t e r V 12 a b c S e t t h e i n t e r v a l “ a ” t o t i m e r 1 . S e t t h e i n t e r v a l “ b ” t o r e l o a d r e g i s t e r R Set the interval “c” to reload register R1. Set the interval “d” to reload register R1. d T i m e r u n d e r f l o w Port CARR output Carrier wave output start T i m e r 1 s t a r t s C a r r i e r w a v e o u t p u t s t a r t C o u n t s o u r c e C A R R Y s e l e c t e d A u t o - c o n t r o l v a l i d A u t o - c o n t r o l i n v a l i dAuto-control invalid T i m e r 1 s t o p Carrier wave output stop ( N o t e ) ( V 11)← 0 (V10)← 1 ( V 12)← 1 ( V 10)← 0 C A R R Y T i m e r u n d e r f l o w “ H ” “L” “1” “0” “H ” “ L ” “ 1 ” “ 0 ” “H ” “ L ” “ 1 ” “ 0 ” N o t e : W h e n t i m e r 1 i s s t o p p e d , t h e p o r t C A R R o u t p u t a u t o - c o n t r o l i s t e r m i n a t e d r e g a r d l e s s o f b i t 2 ( V 12) o f r e g i s t e r V 1 . LL L L (R2L) R H ) ( R L ) (R2H) ( R L ) ( R H C A R R Y D (R2L) R H ) (R2L) (R2H) (R2L) ( R H T i m e r c o u n t s o u r c e T i m e r c o u n t v a l u e (Reload register) T i m e r u n d e r f l o w s i g n a l C A R R Y D T i m e r s t a r t s C a r r i e r w a v e p e r i o d c l o c k s T o e x p a n d H i n t e r v a l o f c a r r i e r w a v e i s i n v a l i d V 23= C o u n t s o u r c e M H z R e s o l u t i o n n s T o e x p a n d H i n t e r v a l o f c a r r i e r w a v e i s v a l i d V 23= h e n c o u n t s o u r c e i s M H z c a r r i e r w a v e i s e x p a n d e d f o r n s 0216 0 6 0 60316 0216 0 60216 0116 0 6 0 6 0 6 0 6 0116 0 603160 6 0 6 0 6 0 6 0 60316 0 60216 0 6 0 6 0 6 0 6 0216 0 6 00160 6 0 6 00160 c l o c k s i n t e r v a l T i m e r c o u n t s o u r c e T i m e r c o u n t v a l u e R e l o a d r e g i s t e r T i m e r u n d e r f l o w s i g n a l T i m e r s t a r t s 3 clocks interval C a r r i e r w a v e p e r i o d c l o c k s C a r r i e r w a v e p e r i o d c l o c k s c l o c k s i n t e r v a l c l o c k s i n t e r v a l C a r r i e r w a v e p e r i o d c l o c k s N o t e W h e n t o e x p a n d H i n t e r v a l o f t h e c a r r i e r w a v e i s v a l i d s e t o r m o r e t o r e l o a d r e g i s t e r R H G I n t h i s c a s e t h e f o l l o w i n g i s s e t T i m e r c a r r i e r w a v e g e n e r a t i o n f u n c t i o n i s v a l i d V 22= L i n t e r v a l o f c a r r i e r w a v e i s s e t t o r e l o a d r e g i s t e r R L H i n t e r v a l o f c a r r i e r w a v e i s s e t t o r e l o a d r e g i s t e r R H

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER Fig. 16 Timer 2 count start/stop timing (R2L) (R2H) (R2L) Timer 2 count value (Reload register) Timer 2 underflow signal CARRYD Timer 2 count start timing Timer 2 count start timing Instruction clock =f(XIN)/8 Machine cycle TV2A instruction execution cycle (V20) ← 1 XIN XIN/2 (Count source selected) 0216 0116 0016 021603160216 0116 00160316 Timer 2 count value (Reload register) Timer 2 underflow signal CARRYD Timer 2 count stop timing Timer 2 count stop timing Machine cycle TV2A instruction execution cycle (V20)← 0 XIN/2 (Count source selected) 02160216 0116 00160216 0116 0016 0216 0116 0016 03160016 (R2H)(R2L) 0316 (R2H)(R2L) (Note 1) Mi Mi + 1 Mi + 2 Mi Mi + 1 Mi + 2 Instruction clock =f(XIN)/8 Register V20 Register V20 XIN G In this case, the following is set;

• To expand “H ” interval of carrier wave is invalid (V23 = “0”),
• Timer 2 carrier wave generation function is valid (V22=“1”),
• Count source XIN/2 selected (V21=“1”),
• “L” interval (0316) of carrier wave is set to reload register R2L
• “H ” interval (0216) of carrier wave is set to reload register R2H Notes 1: When the carrier wave generation function is vaild (V22=“1”), avoid a timing when timer 2 underflows to stop timer 2. When the timer 2 count stop occurs at the same timing with the timer 2 underflows, hazard may occur in the carrier wave output waveform. 2: When the timer 2 is stopped during “H ” output of carrier wave while the carrier wave generation function is valid, it is stopped after the “H ” interval set by reload register R2H is output.

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER LOGIC OPERATION FUNCTION The 4282 Group has the 4-bit logic operation function. The logic operation between the contents of register A and the low-order 4 bits of register E is performed and its result is stored in register Each logic operation can be selected by setting logic operation selection register LO. Set the contents of this register through register A with the TLOA instruction. The logic operation selected by register LO is executed with the LGOP instruction. Table 5 shows the logic operation selection register LO. Table 5 Logic operation selection register LO at reset : 002 at RAM back-up : 002 W LO1 LO LO 1 LO 0 Logic operation selection bits Logic operation selection register LO Logic operation function Exclusive logic OR operation (XOR) OR operation (OR) AND operation (AND) Not available Note: “W” represents write enabled. WATCHDOG TIMER Watchdog timer provides a method to reset and restart the system when a program runs wild. Watchdog timer consists of 14-bit timer (WDT) and watchdog timer flags (WDF1, WDF2). Watchdog timer downcounts the instruction clock (INSTCK) as the count source immediately after system is released from reset. When the timer WDT count value becomes 0000 16 and underflow occurs, the WDF1 flag is set to “1.” Then, when the WRST instruction is not executed before the timer WDT counts 16383, WDF2 flag is set to “1” and internal reset signal is generated and system reset is performed. Execute the WRST instruction at period of 16383 machine cycle or less to keep the microcomputer operation normal. Timer WDT is also used for generation of oscillation stabilization time. When system is returned from reset and from RAM back- up mode by key-input, software starts after the stabilization oscillation time until timer WDT downcounts to 3E00 16 elapses. Fig. 17 Watchdog timer function Value of timer WDT WDF2 flag WRST instruction execution S y s t e m r e s e t Return

3 E 0 01

3 F F F1

r e s e t S o f t w a r e s t a r t Software start S o f t w a r e s t a r t POF instruction execution I n t e r n a l r e s e t s i g n a l “1” “ 0 ” “ 1 ” “0” “H ” “L”

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER Fig. 18 Reset release timing RESET FUNCTION The 4282 Group has the power-on reset circuit, though it does not have RESET pin. System reset is performed automatically at power-on, and software starts program from address 0 in page In order to make the built-in power-on reset circuit operate efficiently, set the voltage rising time until VDD = 0 to 2.2 V is obtained at power-on 1ms or less. Fig. 19 Power-on reset circuit example f(XIN) Internal reset signal f(XIN) 16384 pulses Software operation starts (address 0 in page 0) “H ” “L” VDD Internal reset signal Power-on reset circuit Voltage drop detection circuit Watchdog timer output Power-on reset circuit output voltage Reset state Internal reset signal Reset released Power-on

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER (1) Internal state at reset Table 6 shows port state at reset, and Figure 20 shows internal state at reset (they are retained after system is released from reset). The contents of timers, registers, flags and RAM except shown in Figure 20 are undefined, so set the initial value to them. 00000000000 000 0000 0000 0000 1111 1111 0000 Fig. 20 Internal state at reset Table 6 Port state at reset Name D 0–D 3 D 4–D 7 G 0–G 3 E0, E1 CARR State at reset High impedance state High impedance state (Pull-down transistor OFF) High impedance state (Pull-down transistor OFF) High impedance state (Pull-down transistor OFF) “L” output Note: The contents of all output latch is initialized to “0.” VOLTAGE DROP DETECTION CIRCUIT The built-in voltage drop detection circuit is designed to detect a drop in voltage at operating and to reset the microcomputer if the supply voltage drops below the specified value (Typ. 1.50 V) or less. Fig. 21 Voltage drop detection circuit operation waveform The voltage drop detection circuit is stopped and power dissipation is reduced in the RAM back-up mode with the initialized CPU stopped. Address 0 in page 0 is set to program counter.

• Most significant ROM code reference enable flag (URS) VDD Internal reset signal Reset voltage TYP 1.5V (Note) Note: The voltage drop detection circuit does not have the hysteresis characteristics in the detected voltage. Microcomputer starts operation after f(XIN) is counted to 16384 times.

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER RAM BACK-UP MODE The 4282 Group has the RAM back-up mode. When the POF instruction is executed, system enters the RAM back-up state. As oscillation stops retaining RAM, the functions and states of reset circuit at RAM back-up mode, power dissipation can be reduced without losing the contents of RAM. Table 7 shows the function and states retained at RAM back-up. Figure 22 shows the state transition. (1) Warm start condition When the external wakeup signal is input after the system enters the RAM back-up state by executing the POF instruction, the CPU starts executing the software from address 0 in page 0. In this case, the P flag is “1.” (2) Cold start condition The CPU starts executing the software from address 0 in page 0 when any of the following conditions is satisfied .

• reset by power-on reset circuit is performed
• reset by watchdog timer is performed
• reset by voltage drop detection circuit is performed In this case, the P flag is “0.” (3) Identification of the start condition Warm start (return from the RAM back-up state) or cold start (return from the normal reset state) can be identified by examining the state of the power down flag (P) with the SNZP instruction. Table 7 Functions and states retained at RAM back-up RAM back-up O O O O O Function Program counter (PC), registers A, B, carry flag (CY), stack pointer (SP) (Note 2) Contents of RAM Port CARR Ports D 0–D 7 Ports E0, E1 Port G Timer control registers V1, V2 Pull-down control registers PU0, PU1 Logic operation selection register LO Timer 1 function, Timer 2 function Timer underflow flags (T1F, T2F) Watchdog timer (WDT) Watchdog timer flags (WDF1, WDF2) Most significant ROM code reference enable flag (URS) Notes 1: “O ” represents that the function can be retained, and “✕ ” represents that the function is initialized. Registers and flags other than the above are undefined at RAM back-up, and set an initial value after returning. 2:The stack pointer (SP) points the level of the stack register and is initialized to “112” at RAM back-up. Fig. 22 State transition Fig. 23 Set source and clear source of the P flag Fig. 24 Start condition identified example using the SNZP instruction : Microcomputer starts its operation after f(XIN) is counted to16384 times.Stabilizing time a POF instruction is executed A f(XIN) oscillationReturn input B (RAM back-up mode) f(XIN) stop Reset (Stabilizing time a ) (Stabilizing time a ) S R Q Power down flag P POF instruction Reset input G Set source POF instruction is executed G Clear source Reset input Software start P = “1” Yes Warm startCold start No

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER Remarks Only key-on wakeup function of the port whose pull-down transistor is turned ON by register PU1 is valid. Only key-on wakeup function of the port whose pull-down transistor is turned ON by register PU0 is valid. Key-on wakeup function is always valid. Return source Ports D4–D 7 Ports E0, E1, G Ports E2 Return condition Return by an external “H ” level input. Return by an external “H ” level input. Return by an external “H ” level input. Table 8 Return source and return condition (5) Pull-down control register Registers PU0 and PU1 are 4-bit registers and control the ON/OFF of pull-down transistor and key-on wakeup function for ports E 0, E1, G and ports D4–D 7. Table 9 Pull-down control registers PU0 3 PU0 2 PU0 1 PU0 0 Pull-down transistor OFF, key-on wakeup invalid Pull-down transistor ON, key-on wakeup valid Pull-down transistor OFF, key-on wakeup invalid Pull-down transistor ON, key-on wakeup valid Pull-down transistor OFF, key-on wakeup invalid Pull-down transistor ON, key-on wakeup valid Pull-down transistor OFF, key-on wakeup invalid Pull-down transistor ON, key-on wakeup valid Ports G 2, G3 pull-down transistor control bit Ports G 0, G1 pull-down transistor control bit Port E1 pull-down transistor control bit Port E0 pull-down transistor control bit Pull-down control register PU0 at reset : 00002 at RAM back-up : state retained W Note: “W ” represents write enabled. Set the contents of register PU0 or PU1 through register A with the TPU0A or TPU1A instruction, respectively. (4) Return signal An external wakeup signal is used to return from the RAM back-up mode. Table 8 shows the return condition for each return source. PU1 3 PU1 2 PU1 1 PU1 0 Pull-down transistor OFF, key-on wakeup invalid Pull-down transistor ON, key-on wakeup valid Pull-down transistor OFF, key-on wakeup invalid Pull-down transistor ON, key-on wakeup valid Pull-down transistor OFF, key-on wakeup invalid Pull-down transistor ON, key-on wakeup valid Pull-down transistor OFF, key-on wakeup invalid Pull-down transistor ON, key-on wakeup valid Port D 7 pull-down transistor control bit Port D6 pull-down transistor control bit Port D5 pull-down transistor control bit Port D4 pull-down transistor control bit Pull-down control register PU1 at reset : 00002 at RAM back-up : state retained W

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER Fig. 25 Clock control circuit structure System clock signal f(XIN) is obtained by externally connecting a ceramic resonator. Connect this external circuit to pins XIN and XOUT at the shortest distance as shown Figure 26. A feedback resistor is built-in between XIN pin and XOUT pin. ROM ORDERING METHOD Please submit the information described below when ordering Mask ROM. (1) Mask ROM Order Confirmation Form (2) Mark Specification Form (3) Data to be written to ROM, in EPROM form (three identical copies) or one floppy disk. * For the mask ROM confirmation, refer to the “Mitsubishi MCU Technical Information” Homepage (http:// Fig. 26 Ceramic resonator external circuit CLOCK CONTROL The clock control circuit consists of the following circuits.

• System clock generating circuit
• Control circuit to stop the clock oscillation
• Control circuit to return from the RAM back-up state 4282 XIN XOUT C IN C OUT Use the resonator manufacturer’s recommended value because constants such as capacitance depend on the resonator. O S C R S Q POF instruction XI N XOUT P o r t s E0, E1, G 0– G 3P u l l - d o w n c o n t r o l r e g i s t e r P U P o r t E2 I n t e r n a l c l o c k g e n e r a t i o n c i r c u i t d i v i d e d b y F r e q u e n c y d i v i d e r d i v i d e d b y C C K i n s t r u c t i o n STCK INSTCK I n t e r n a l p o w e r - o n r e s e t c i r c u i t Ports D4–D 7Pull-down control register 1 M u l t i - p l e x e r

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER LIST OF PRECAUTIONS ➀ Noise and latch-up prevention Connect a capacitor on the following condition to prevent noise and latch-up;

• connect a bypass capacitor (approx. 0.01 µF) between pins VDD and VSS at the shortest distance,
• equalize its wiring in width and length, and
• use the thickest wire. In the One Time PROM version, port E2 is also used as VPP pin. Connect this pin to VSS through the resistor about 5 kΩ which is assigned to E2/VPP pin as close as possible at the shortest distance. ➁ Notes on unused pins (Note in order to set the output latch to “0” to make pins open)
• After system is released from reset, a port is in a high- impedance state until the output latch of the port is set to “0” by software. Accordingly, the voltage level of pins is undefined and the excess of the supply current may occur.
• To set the output latch periodically is recommended because the value of output latch may change by noise or a program run away (caused by noise). (Note when connecting to V SS and VDD )
• Connect the unused pins to VSS and VDD at the shortest distance and use the thick wire against noise. ➂ Timer
• Count source Stop timer 1 or timer 2 counting to change its count source.
• Watchdog timer Be sure that the timing to execute the WRST instruction in order to operate WDT efficiently.
• Writing to reload register R1 When writing data to reload register R1 while timer 1 is operating, avoid a timing when timer 1 underflows.
• Timer 1 count operation When the bit 5 of the watchdog timer (WDT) is selected as the timer 1 count source, the error of maximum ± 256 µs (at the minimum instruction execution time : 8 µs) is generated from timer 1 start until timer 1 underflow. When programming, be careful about this error.
• Stop of timer 2 Avoid a timing when timer 2 underflows to stop timer 2.
• Writing to reload register R2H When writing data to reload register R2H while timer 2 is operating, avoid a timing when timer underflows.
• Timer 2 carrier wave output function When to expand “H ” interval of carrier wave is valid, set “1” or more to reload register R2H. ➃ Program counter Make sure that the program counter does not specify after the last page of the built-in ROM.

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER INSTRUCTIONS The 4282 Group has the 68 instructions. Each instruction is described as follows; (1) List of instruction function (2) Machine instructions (index by alphabet) (3) Machine instructions (index by function) (4) Instruction code table SYMBOL The symbols shown below are used in the following list of instruction function and the machine instructions. Symbol A B DR ER PU0 PU1 LO X Y DP PC PC H PC L SK SP CY T1F R2H R2L T2F WDT WDF1 WDF2 URS P STCK INSTCK

Contents

Register A (4 bits) Register B (4 bits) Register D (3 bits) Register E (8 bits) Timer control register V1 (3 bits) Timer control register V2 (4 bits) Pull-down control register PU0 (4 bits) Pull-down control register PU1 (4 bits) Logic operation selection register LO (2 bits) Register X (2 bits) Register Y (4 bits) Data pointer (6 bits) (It consists of registers X and Y) Program counter (11 bits) High-order 4 bits of program counter Low-order 7 bits of program counter Stack register (11 bits ✕ 4) Stack pointer (2 bits) Carry flag Timer 1 reload register Timer 1 Timer 1 underflow flag Timer 2 reload register Timer 2 reload register Timer 2 Timer 2 underflow flag Watchdog timer Watchdog timer flag 1 Watchdog timer flag 2 Most significant ROM code reference enable flag Power down flag System clock Instruction clock Port D (8 bits) Port E (3 bits) Port G (4 bits) Port CARR (1 bit) CAR flag (1 bit) Hexadecimal variable Hexadecimal variable Hexadecimal variable Hexadecimal constant which represents the immediate value Hexadecimal constant which represents the immediate value Binary notation of hexadecimal variable A (same for others) Direction of data movement Data exchange between a register and memory Decision of state shown before “?” Contents of registers and memories Negate, Flag unchanged after executing instruction RAM address pointed by the data pointer Label indicating address a 6 a5 a4 a3 a2 a1 a0 Label indicating address a6 a5 a4 a3 a2 a1 a0 in page p3 p2 p1 p0 Hex. number C + Hex. number x (also same for others) Symbol D E G CARR CAR x y p n j A 3A2A1A0 ( ) M(DP) a p, a C x Note :The 4282 Group just invalidates the next instruction when a skip is performed. The contents of program counter is not increased by 2. Accordingly, the number of cycles does not change even if skip is not performed. However, the cycle count becomes “1” if the TABP p, RT, or RTS instruction is skipped.

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER Function (A) ← n n = 0 to 15 (SP) ← (SP) + 1 (SK(SP)) ← (PC) (PCH ) ← p p=0 to 15 (PCL) ← (DR2–DR 0, A3–A0) When URS=0 (B) ← (ROM(PC)) 7 to 4 (A) ← (ROM(PC))3 to 0 When URS=1 (CY) ← (ROM(PC))8 (B) ← (ROM(PC))7 to 4 (A) ← (ROM(PC))3 to 0 (PC) ← (SK(SP)) (SP) ← (SP) – 1 (A) ← (A) + (M(DP)) (A) ← (A) + (M(DP)) + (CY) (CY) ← Carry (A) ← (A) + n n = 0 to 15 (CY) ← 1 (CY) ← 0 (CY) = 0 ? (A) ← (A) → CY → A3A2A1A0 Logic operation instruction XOR, OR, AND (Mj(DP)) ← 1 j = 0 to 3 (Mj(DP)) ← 0 j = 0 to 3 (Mj(DP)) = 0 ? j = 0 to 3 LIST OF INSTRUCTION FUNCTION Arithmetic operation Register to register transfer GroupingMnemonic TAB TBA TAY TYA TEAB TABE TDA LXY x, y INY DEY TAM j XAM j XAMD j XAMI j Function (A) ← (B) (B) ← (A) (A) ← (Y) (Y) ← (A) (ER 7–ER 4) ← (B) (ER3–ER 0) ← (A) (B) ← (ER7–ER 4) (A) ← (ER3–ER 0) (DR2–DR 0) ← (A2–A0) (X) ← x, x = 0 to 3 (Y) ← y, y = 0 to 15 (Y) ← (Y) + 1 (Y) ← (Y) – 1 (A) ← (M(DP)) (X) ← (X) EXOR(j) j = 0 to 3 (A) ←→ (M(DP)) (X) ← (X) EXOR(j) j = 0 to 3 (A) ←→ (M(DP)) (X) ← (X) EXOR(j) j = 0 to 3 (Y) ← (Y) – 1 (A) ←→ (M(DP)) (X) ← (X) EXOR(j) j = 0 to 3 (Y) ← (Y) + 1 GroupingMnemonic LA n TABP p AM AMC A n SC RC SZC CMA RAR LGOP SB j RB j SZB j RAM to register transfer RAM addresses Bit operation Page Page

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER Comparisonoperation GroupingMnemonic SEAM SEA n B a BL p, a BA a BLA p, a BM a BML p, a BMLA p, a RT RTS Function (A) = (M(DP)) ? (A) = n ? n = 0 to 15 (PC L) ← a6–a0 (PCH ) ← p (PCL) ← a6–a0 (PCL) ← (a6–a4, A3–A0) (PCH ) ← p (PCL) ← (a6–a4, A3–A0) (SP) ← (SP) + 1 (SK(SP)) ← (PC) (PCH ) ← 2 (PCL) ← a6–a0 (SP) ← (SP) + 1 (SK(SP)) ← (PC) (PCH ) ← p p= 0 to 15 (PCL) ← a6–a0 (SP) ← (SP) + 1 (SK(SP)) ← (PC) (PCH ) ← p p= 0 to 15 (PCL) ← (a6–a4, A3–A0) (PC) ← (SK(SP)) (SP) ← (SP) – 1 (PC) ← (SK(SP)) (SP) ← (SP) – 1 Subroutine operation Return operation Branch operation GroupingMnemonic TV1A TAB1 T1AB SNZT1 TV2A TAB2 T2AB T2HAB T2R2L SNZT2 Function (V1 2–V10) ← (A2–A0) (B) ← (T17–T14) (A) ← (T13–T10) at timer 1 stop (V10=0): (R17–R1 4) ← (B) (T17–T14) ← (B) (R13–R1 0) ← (A) (T13–T10) ← (A) at timer 1 operating (V10=1): (R17–R1 4) ← (B) (R13–R1 0) ← (A) (T1F) = 1 ? After skipping the next instruction (T1F) ← 0 (V2 3–V20) ← (A3–A0) (B) ← (T27–T24) (A) ← (T23–T20) (R2L7–R2L 4) ← (B) (T27–T24) ← (B) (R2L3–R2L 0) ← (A) (T23–T20) ← (A) (R2H7–R2H 4) ← (B) (R2H3–R2H 0) ← (A) (T27–T24) ← (R2L7–R2L 4) (T27–T24) ← (R2L3–R2L 0) (T2F) = 1 ? After skipping the next instruction (T2F) ← 0 Timer operation Page Page

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER LIST OF INSTRUCTION FUNCTION (CONTINUED) Input/Output operation GroupingMnemonic CLD RD SD SZD OEA IAE OGA IAG SCAR RCAR NOP POF SNZP CCK TLOA URSC TPU0A TPU1A WRST Function (D) ← 0 (D(Y)) ← 0 (Y) = 0 to 7 (D(Y)) ← 1 (Y) = 0 to 7 (D(Y)) = 0 ? (Y) = 4 to 7 1, E0) ← (A1, A0) (A2–A0) ← (E2–E0) (G) ← (A) (A) ← (G) (CAR) ← 1 (CAR) ← 0 (PC) ← (PC) + 1 RAM back-up (P) = 1 ? STCK changes to f(XIN) (LO1, LO0) ← (A1, A0) (URS) ← 1 (PU03–PU0 0) ← (A3–A0) (PU13–PU1 0) ← (A3–A0) (WDF1) ← 0 Other operation Carrier wave control operation Page

MACHINE INSTRUCTIONS (INDEX BY ALPHABET) A n (Add n and accumulator) 01010 n 3 n2 n1 n0 0An 11 – Overflow = 0 Grouping: Arithmetic operation Description:Adds the value n in the immediate field to register A. The contents of carry flag CY remains un- changed. Skips the next instruction when there is no overflow as the result of operation. Operation: (A) ← (A) + n n = 0 to 15 AM (Add accumulator and Memory) 000001010 00A 11 – – Grouping: Arithmetic operation Description:Adds the contents of M(DP) to register A. Stores the result in register A. The contents of carry flag CY remains unchanged. Operation: (A) ← (A) + (M(DP)) AMC (Add accumulator, Memory and Carry) 000001011 00B 11 0/1 – Grouping: Arithmetic operation Description:Adds the contents of M(DP) and carry flag CY to register A. Stores the result in regis- ter A and carry flag CY. Operation: (A) ← (A) + (M(DP)) + (CY) (CY) ← Carry B a (Branch to address a) 11a 6 a5 a4 a3 a2 a1 a0 1a 11 – – Grouping: Branch operation Description:Branch within a page : Branches to address a in the identical page. Operation: (PCL) ← a6–a0

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS Flag CY 2 16 Skip conditionNumber of cycles Number of words Instrunction code D 8 D 0 Flag CY 2 16 Skip conditionNumber of cycles Number of words Instrunction code D 8 D 0 Flag CY 2 16 Skip conditionNumber of cycles Number of words Instrunction code D 8 D 0 Flag CY 2 16 BM a (Branch and Mark to address a in page 2) 10a 6 a5 a4 a3 a2 a1 a0 1aa 11 – – Grouping: Subroutine call operation Description:Call the subroutine in page 2 : Calls the subroutine at address a in page 2. Operation: (SK(SP)) ← (PC) (SP) ← (SP) + 1 (PCH ) ← 2 (PCL) ← a6–a0 BL p, a (Branch Long to address a in page p) 00011p 3 p2 p1 p0 03p 22 – – Grouping: Branch operation Description:Branch out of a page : Branches to address a in page p. Note: p is 0 to 7 for M34282M1, p is 0 to 15 for M34282M2/E2. Operation: (PCH ) ← (P) (PCL) ← a6–a0 BLA p, a (Branch Long to address a in page p) 000010000 010 22 – – Grouping: Branch operation Description:Branch within a page : Branches to address (a6 a5 a4 A3 A2 A1 A0) determined by replac- ing the low-order 4 bits of the address a in page p with register A. Note: p is 0 to 7 for M34282M1, p is 0 to 15 for M34282M2/E2. 2 1611a 6 a5 a4 a3 a2 a1 a0 1a 8 Operation: (PCH ) ← (P) (PCL) ← (a6–a4, A3–A0) 2 1611a 6 a5 a4 p3 p2 p1 p0 1p BA a (Branch to address a + Accumulator) 000000001 001 22 – – Grouping: Branch operation Description:Branch within a page : Branches to address (a6 a5 a4 A3 A2 A1 A0) determined by replac- ing the low-order 4 bits of the address a in the identical page with register A. Operation: (PC L) ← a6–a4, A3–A0 2 1611a 6 a5 a4 a3 a2 a1 a0 1a 8

BML p, a (Branch and Mark Long to address a in page p) 00111p 3 p2 p1 p0 07p 22 – – Grouping: Subroutine call operation Description:Call the subroutine : Calls the subroutine at address a in page p. Note: p is 0 to 7 for M34282M1, p is 0 to 15 for M34282M2/E2. Operation: (SK(SP)) ← (PC) (SP) ← (SP) + 1 (PCH ) ← p (PCL) ← a6–a0 BMLA p, a (Branch and Mark Long to address a in page p) 001010000 050 22 – – Grouping: Subroutine call operation Description:Call the subroutine : Calls the subroutine at address (a6 a5 a4 A3 A2 A1 A0) determined by replacing the low-order 4 bits of address a in page p with register A. Note: p is 0 to 7 for M34282M1, p is 0 to 15 for M34282M2/E2. CCK (Change system Clock to f(XIN)) 001011001 059 11 – – Grouping: Other operation Description:Changes system clock (STCK) from f(XIN)/8 to f(XIN). Execute this instruction at address 0 in page 0. Operation: Change to STCK = f(XIN) 2 1610a 6 a5 a4 a3 a2 a1 a0 1aa Operation: (SK(SP)) ← (PC) (SP) ← (SP) + 1 (PCH ) ← p (PCL) ← (a6–a4, A3–A0) 2 1610a 6 a5 a4 p3 p2 p1 p0 1ap CLD (CLear port D) 000010001 011 11 – – Grouping: Input/Output operation Description:Clears (0) to port D (high-impedance state). Operation: (D) ← 1

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS Flag CY 2 16 Skip conditionNumber of cycles Number of words Instrunction code D 8 D 0 Flag CY 2 16 Skip conditionNumber of cycles Number of words Instrunction code D 8 D 0 Flag CY 2 16 Skip conditionNumber of cycles Number of words Instrunction code D 8 D 0 Flag CY 2 16 IAE (Input Accumulator from port E) 001010110 056 11 – – Grouping: Input/Output operation Description:Transfers the contents of port E to register Operation: (A2–A0) ← (E2–E0) IAG (Input Accumulator from port G) 000101000 028 11 – – Grouping: Input/Output operation Description:Transfers the contents of port G to register Operation: (A) ← (G) CMA (CoMplement of Accumulator) 000011100 01C 11 – – Grouping: Arithmetic operation Description:Stores the one’s complement for register A’s contents in register A. Operation: (A) ← (A) DEY (DEcrement register Y) 000010111 017 11 – (Y) = 15 Grouping: RAM addresses Description:Subtracts 1 from the contents of register Y. As a result of subtraction, when the con- tents of register Y is 15, the next instruction is skipped. Operation: (Y) ← (Y) – 1

INY (INcrement register Y) 000010011 013 11 – (Y) = 0 Grouping: RAM addresses Description:Adds 1 to the contents of register Y. As a re- sult of addition, when the contents of register Y is 0, the next instruction is skipped. Operation: (Y) ← (Y) + 1 LGOP (LoGic OPeration between accumulator and register E) 001000001 041 11 – – Grouping: Arithmetic operation Description:Executes the logic operation selected by logic operation selection register LO be- tween the contents of register A and register E, and stores the result in register Operation: Logic operation XOR, OR, AND LXY x, y (Load register X and Y with x and y) 011x 1 x0 y3 y2 y1 y0 0y 11 – Continuous Grouping: RAM addresses Description:Loads the value x in the immediate field to register X, and the value y in the immediate field to register Y. When the LXY instruc- tions are continuously coded and executed, only the first LXY instruction is executed and other LXY instructions coded continu- ously are skipped. Operation: (X) ← x, x = 0 to 3 (Y) ← y, y = 0 to 15 C LA n (Load n in Accumulator) 01011n 3 n2 n1 n0 0Bn 11 – Continuous Grouping: Arithmetic operation Description:Loads the value n in the immediate field to register A. When the LA instructions are continuously coded and executed, only the first LA in- struction is executed and other LA instructions coded continuously are skipped. Operation: (A) ← n n = 0 to 15

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS Flag CY 2 16 Skip conditionNumber of cycles Number of words Instrunction code D 8 D 0 Flag CY 2 16 Skip conditionNumber of cycles Number of words Instrunction code D 8 D 0 Flag CY 2 16 Skip conditionNumber of cycles Number of words Instrunction code D 8 D 0 Flag CY 2 16 POF (Power OFf1) 000001101 00D 11 – – Grouping: Other operation Description:Puts the system in RAM back-up state. Operation: RAM back-up NOP (No OPeration) 000000000 000 11 – – Grouping: Other operation Description:No operation Operation: (PC) ← (PC) + 1 OEA (Output port E from Accumulator) 010000100 084 11 – – Grouping: Input/Output operation Description:Outputs the contents of register A to port E. OGA (Output port G from Accumulator) 010000000 080 11 – – Grouping: Input/Output operation Description:Outputs the contents of register A to port G. Operation: (G) ← (A) Operation: (E1, E0) ← (A1, A0)

RAR (Rotate Accumulator Right) 000011101 01D 11 0/1 – Grouping: Arithmetic operation Description:Rotates 1 bit of the contents of register A in- cluding the contents of carry flag CY to the right. Operation: → CY → A 3A2A1A0 RB j (Reset Bit) 0010011j 1 j0 04 11 – – Grouping: Bit operation Description:Clears (0) the contents of bit j (bit specified by the value j in the immediate field) of M(DP). Operation: (Mj(DP)) ← 0 j = 0 to 3 C RC (Reset Carry flag) 000000110 006 11 0 – Grouping: Arithmetic operation Description:Clears (0) to carry flag CY . Operation: (CY) ← 0 RCAR (Reset CAR flag) 010000110 086 11 – – Grouping: Carrier wave control operation Description:Clears (0) to port CARR output flag. Operation: (CAR) ← 0

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS Flag CY 2 16 Skip conditionNumber of cycles Number of words Instrunction code D 8 D 0 Flag CY 2 16 Skip conditionNumber of cycles Number of words Instrunction code D 8 D 0 Flag CY 2 16 Skip conditionNumber of cycles Number of words Instrunction code D 8 D 0 Flag CY 2 16 RTS (ReTurn form subroutine and Skip) 001000101 045 12 – Skip at uncondition Grouping: Return operation Description:Returns from subroutine to the routine called the subroutine, and skips the next in- struction at uncondition. Operation: (SP) ← (SP) – 1 (PC) ← (SK(SP))SB j (Set Bit) 0010111j 1 j0 05 11 – – Grouping: Bit operation Description:Sets (1) the contents of bit j (bit specified by the value j in the immediate field) of M(DP). Operation: (Mj(DP)) ← 0 j = 0 to 3 C RD (Reset port D specified by register Y) 000010100 014 11 – – Grouping: Input/Output operation Description:Clears (0) to a bit of port D specified by reg- ister Y (high-impedance state). Operation: (D(Y)) ← 0 However, (Y) = 0 to 7RT (ReTurn from subroutine) 001000100 044 12 – – Grouping: Return operation Description:Returns from subroutine to the routine called the subroutine. Operation: (SP) ← (SP) – 1 (PC) ← (SK(SP))

SC (Set Carry flag) 000000111 007 11 1 – Grouping: Arithmetic operation Description:Sets (1) to carry flag CY . Operation: (CY) ← 1 SEA n (Skip Equal, Accumulator with immediate data n) 000100101 025 22 – (A) = n, n = 0 to 15 Grouping: Comparison operation Description:Skips the next instruction when the con- tents of register A is equal to the value n in the immediate field. Operation: (A) = n ? n = 0 to 15 SCAR (Set CAR flag) 010000111 087 11 – – Grouping: Carrier wave control operation Description:Sets (1) to port CARR output flag (CAR). Operation: (CAR) ← 1 SD (Set port D specified by register Y) 000010101 015 11 – – Grouping: Input/Output operation Description:Sets (1) to a bit of port D specified by regis- ter Y. Operation: (D(Y)) ← 1 (Y) = 0 to 7 2 1601011n 3 n2 n1 n0 0Bn

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS Flag CY 2 16 Skip conditionNumber of cycles Number of words Instrunction code D 8 D 0 Flag CY 2 16 Skip conditionNumber of cycles Number of words Instrunction code D 8 D 0 Flag CY 2 16 Skip conditionNumber of cycles Number of words Instrunction code D 8 D 0 Flag CY 2 16 SNZP (Skip if Non Zero condition of Power down flag) 000000011 003 11 – (P) = 1 Grouping: Other operation Description:Skips the next instruction when P flag is “1”. After skipping, P flag remains unchanged. SNZT1 (Skip if Non Zero condition of Timer 1 underflow flag) 001000010 042 11 – (T1F) = 1 Grouping: Timer operation Description:Skips the next instruction when the con- tents of T1F flag is “1.” After skipping, clears (0) to T1F flag. Operation: (T1F) = 1 ? After skipping, (T1F) ← 0 SNZT2 (Skip if Non Zero condition of Timer 2 inerrupt request flag) 001010010 052 11 – (T2F) = 1 Grouping: Timer operation Description:Skips the next instruction when the con- tents of T2F flag is “1.” After skipping, clears (0) to T2F flag. Operation: (T2F) = 1 ? After skipping, (T2F) ← 0 Operation: (P) = 1 ? SEAM (Skip Equal, Accumulator with Memory) 000100110 026 Grouping: Comparison operation Description:Skips the next instruction when the con- tents of register A is equal to the contents of M(DP). Operation: (A) = (M(DP)) ?

SZB j (Skip if Zero, Bit) 0001000j 1 j0 02j 11 – (Mj(DP)) = 0 j = 0 to 3 Grouping: Bit operation Description:Skips the next instruction when the con- tents of bit j (bit specified by the value j in the immediate field) of M(DP) is “0.” Operation: (Mj(DP)) = 0 ? j = 0 to 3 SZC (Skip if Zero, Carry flag) 000101111 02F 11 – (CY) = 0 Grouping: Arithmetic operation Description:Skips the next instruction when the con- tents of carry flag CY is “0.” Operation: (CY) = 0 ? SZD (Skip if Zero, port D specified by register Y) 000100100 024 22 – (D(Y)) = 0 (Y) = 4 to 7 Grouping: Input/Output operation Description:Skips the next instruction when a bit of port D specified by register Y is “0.” T1AB (Transfer data to timer 1 and register R1 from Accumulator and register B) 001000111 047 11 – – Grouping: Timer operation Description:At timer 1 stop (V10 = 0), transfers the con- tents of register A and register B to timer 1 and reload register R1. At timer 1 operating (V1 0 = 1), transfers the contents of register A and register B to re- load register R1. Operation: at timer 1 stop (V10=0) at timer 1 operating (V10=1) Operation: (D(Y)) = 0 ? (Y) = 4 to 7 2 16000101011 02B

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS Flag CY 2 16 Skip conditionNumber of cycles Number of words Instrunction code D 8 D 0 Flag CY 2 16 Skip conditionNumber of cycles Number of words Instrunction code D 8 D 0 Flag CY 2 16 Skip conditionNumber of cycles Number of words Instrunction code D 8 D 0 Flag CY 2 16 T2HAB (Transfer data to register R2H Accumulator from register B) 010001001 089 11 – – Grouping: Timer operation Description:Transfers the contents of register A and register B to reload register R2H. T2R2L (Transfer data to timer 2 from register R2L) 001010011 053 11 – – Grouping: Timer operation Description:Transfers the contents of reload register R2L to timer 2. Operation: (T27–T24) ← (R2L7–R2L 4) (T23–T20) ← (R2L3–R2L 0) Operation: (R2H 7–R2H 4) ← (B) (R2H 3–R2H 0) ← (A) TAB (Transfer data to Accumulator from register B) 000011110 01E 11 – – Grouping: Register to register transfer Description:Transfers the contents of register B to reg- ister A. Operation: (A) ← (B) T2AB (Transfer data to timer 2 and register R2L from Accumulator and register B) 010001000 088 11 – – Grouping: Timer operation Description:Transfers the contents of registers A and B to timer 2 and timer 2 reload register R2L. Operation: (R2L7–R2L 4) ← (B) (R2L3–R2L 0) ← (A) (T27–T24) ← (B) (T23–T20) ← (A)

TAB1 (Transfer data to Accumulator and register B from timer 1) 001010111 057 11 – – Grouping: Timer operation Description:Transfers the contents of timer 1 to regis- ters A and B. Operation: (B) ← (T17–T14) (A) ← (T13–T10) TABE (Transfer data to Accumulator and register B from register E) 000101010 02A 11 – – Grouping: Register to register transfer Description:Transfers the contents of register E to reg- isters A and B. Operation: (B) ← (ER7–ER 4) (A) ← (ER3–ER 0) TABP p (Transfer data to Accumulator and register B from Program memory in page p) 01001p 3 p2 p1 p0 09p 13 – Grouping: Arithmetic operation Description: Transfers bits 7 to 4 to register B and bits 3 to 0 to register A when URS flag is cleared to “0.” These bits 7 to 0 are the ROM pattern in address (DR

2 DR1 DR0 A3 A2 A1 A0) speci-

fied by registers A and D in page p. Transfers bit 8 of ROM pattern is transferred to flag CY when URS flag is set to “1” (after the URSC instruction is executed). (One of stack is used when the TABP p instruction is executed.) Operation: SK(SP)) ← (PC) , (SP) ← (SP) + 1 (PC H ) ← p, p = 0 to 7, (PCL) ← (DR2–DR 0, A3–A0) When URS = 0, (B) ← (ROM(PC))7 to 4, (A) ← (ROM(PC))3 to 0 When URS = 1, (CY) ← (ROM(PC))8 (B) ← (ROM(PC))7 to 4, (A) ← (ROM(PC))3 to 0 (SP) ← (SP) – 1, (PC) ← (SK(SP)) Note: p is 0 to 7 for M34282M1, p is 0 to 15 for M34282M2/E2. TAB2 (Transfer data to Accumulator and register B from timer 2) 001000000 040 11 – – Grouping: Timer operation Description:Transfers the contents of timer 2 to regis- ters A and B. Operation: (B) ← (T27–T24) (A) ← (T23–T20)

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS Flag CY 2 16 Skip conditionNumber of cycles Number of words Instrunction code D 8 D 0 Flag CY 2 16 Skip conditionNumber of cycles Number of words Instrunction code D 8 D 0 Flag CY 2 16 Skip conditionNumber of cycles Number of words Instrunction code D 8 D 0 Flag CY 2 16 TAM j (Transfer data to Accumulator from Memory) 0011001j 1 j0 06j 11 – – Grouping: RAM to register transfer Description:After transferring the contents of M(DP) to register A, an exclusive OR operation is performed between register X and the value j in the immediate field, and stores the re- sult in register X. Operation: (A) ← (M(DP)) (X) ← (X)EXOR(j) j = 0 to 3 TAY (Transfer data to Accumulator from register Y) 000011111 01F 11 – – Grouping: Register to register transfer Description:Transfers the contents of register Y to regis- ter A. Operation: (A) ← (Y) TBA (Transfer data to register B from Accumulator) 000001110 00E 11 – – Grouping: Register to register transfer Description:Transfers the contents of register A to regis- ter B. TDA (Transfer data to register D from Accumulator) 000101001 029 11 – – Grouping: Register to register transfer Description:Transfers the contents of register A to regis- ter D. Operation: (DR2–DR 0) ← (A2–A0) Operation: (B) ← (A)

TEAB (Transfer data to register E from Accumulator and register B) 000011010 01A 11 – – Grouping: Register to register transfer Description:Transfers the contents of register A and register B to register E. Operation: (ER7–ER 4) ← (B) (ER3–ER 0) ← (A) TLOA (Transfer data to register LO from Accumulator) 001011000 058 11 – – Grouping: Other operation Description:Transfers the contents of register A to logic operation selection register LO. Operation: (LO1, LO0) ← (A1, A0) TPU0A (Transfer data to register PU0 from Accumulator) 010001111 08F 11 – – Grouping: Other operation Description:Transfers the contents of register A to pull- up control register PU0. Operation: (PU03–PU0 0) ← (A3–A0) TPU1A (Transfer data to register PU1 from Accumulator) 010001110 08E 11 – – Grouping: Other operation Description:Transfers the contents of register A to pull- up control register PU1. Operation: (PU13–PU1 0) ← (A3–A0)

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS Flag CY 2 16 Skip conditionNumber of cycles Number of words Instrunction code D 8 D 0 Flag CY 2 16 Skip conditionNumber of cycles Number of words Instrunction code D 8 D 0 Flag CY 2 16 Skip conditionNumber of cycles Number of words Instrunction code D 8 D 0 Flag CY 2 16 TV1A (Transfer data to register V1 from Accumulator) 001010111 05B 11 – – Grouping: Timer operation Description:Transfers the contents of register A to regis- ter V1. Operation: (V12–V10) ← (A2–A0) TV2A (Transfer data to register V2 from Accumulator) 001011010 05A 11 – – Grouping: Timer operation Description:Transfers the contents of register A to regis- ter V2. Operation: (V23–V2 0) ← (A3–A0) URSC (Sets Upper ROM Code reference enable flag) 010000010 082 11 – – Grouping: Other operation Description:Sets the most significant ROM code refer- ence enable flag (URS) to “1.” Operation: (URS) ← 1 TYA (Transfer data to regiser Y from Accumulator) 000001100 00C 11 – – Grouping: Register to register transfer Description:Transfers the contents of register A to regis- ter Y. Operation: (Y) ← (A)

WRST (Watchdog timer ReSeT) 000001111 00F 11 – – Grouping: Other operation Description:Initializes the watchdog timer flag (WDF1). Operation: (WDF1) ← 0 XAM j (eXchange Accumulator and Memory data) 0011000j 1 j0 06j 11 – – Grouping: RAM to register transfer Description:After exchanging the contents of M(DP) with the contents of register A, an exclusive OR operation is performed between regis- ter X and the value j in the immediate field, and stores the result in register X. Operation: (A) ←→ (M(DP)) (X) ← (X)EXOR(j) j = 0 to 3 XAMD j (eXchange Accumulator and Memory data and Decrement register Y and skip) 0011011j 1 j0 06 11 – (Y) = 15 Grouping: RAM to register transfer Description:After exchanging the contents of M(DP) with the contents of register A, an exclusive OR operation is performed between regis- ter X and the value j in the immediate field, and stores the result in register X. Subtracts 1 from the contents of register Y. As a result of subtraction, when the con- tents of register Y is 15, the next instruction is skipped. Operation: (A) ←→ (M(DP)) (X) ← (X)EXOR(j) j = 0 to 3 (Y) ← (Y) – 1 C XAMI j (eXchange Accumulator and Memory data and Increment register Y and skip) 0011010j 1 j0 06 11 – (Y) = 0 Grouping: RAM to register transfer Description:After exchanging the contents of M(DP) with the contents of register A, an exclusive OR operation is performed between regis- ter X and the value j in the immediate field, and stores the result in register X. Adds 1 to the contents of register Y . As a re- sult of addition, when the contents of register Y is 0, the next instruction is skipped. Operation: (A) ←→ (M(DP)) (X) ← (X)EXOR(j) j = 0 to 3 (Y) ← (Y) + 1

FunctionMnemonic Hexadecimal notation Number of words Number of cycles Parameter Type of instructions D 8 D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 MITSUBISHI ELECTRIC44 MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER (A) ← (B) (B) ← (A) (A) ← (Y) (Y) ← (A) (ER7–ER 4) ← (B) (ER3–ER 0) ← (A) (B) ← (ER7–ER 4) (A) ← (ER3–ER 0) (DR2–DR 0) ← (A2–A0) (X) ← x, x = 0 to 3 (Y) ← y, y = 0 to 15 (Y) ← (Y) + 1 (Y) ← (Y) – 1 (A) ← (M(DP)) (X) ← (X) EXOR(j) j = 0 to 3 (A) ←→ (M(DP)) (X) ← (X) EXOR(j) j = 0 to 3 (A) ←→ (M(DP)) (X) ← (X) EXOR(j) j = 0 to 3 (Y) ← (Y) – 1 (A) ←→ (M(DP)) (X) ← (X) EXOR(j) j = 0 to 3 (Y) ← (Y) + 1 TAB TBA TAY TYA TEAB TABE TDA LXY x, y INY DEY TAM j XAM j XAMD j XAMI j Register to register transfer 01 E 00 E 01 F 00 C 01 A 02 A 02 9 0C y 01 3 017 06 4 06 j 06 C 06 8 RAM addresses 000011110 000001110 000011111 000001100 000011010 000101010 000101001 011x 1 x0 y3 y2 y1 y0 000010011 000010111 0011001j 1 j0 0011000j 1 j0 0011011j 1 j0 0011010j 1 j0 MACHINE INSTRUCTIONS (INDEX BY FUNCTION) RAM to register transfer

Skip condition Detailed description Carry flag CY MITSUBISHI ELECTRIC 45 MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER Transfers the contents of register B to register A. Transfers the contents of register A to register B. Transfers the contents of register Y to register A. Transfers the contents of register A to register Y. Transfers the contents of registers A and B to register E. Transfers the contents of register E to registers A and B. Transfers the contents of register A to register D. Loads the value x in the immediate field to register X, and the value y in the immediate field to register When the LXY instructions are continuously coded and executed, only the first LXY instruction is executed and other LXY instructions coded continuously are skipped. Adds 1 to the contents of register Y. As a result of addition, when the contents of register Y is 0, the next instruction is skipped. Subtracts 1 from the contents of register Y. As a result of subtraction, when the contents of register Y is 15, the next instruction is skipped. After transferring the contents of M(DP) to register A, an exclusive OR operation is performed between register X and the value j in the immediate field, and stores the result in register X. After exchanging the contents of M(DP) with the contents of register A, an exclusive OR operation is performed between register X and the value j in the immediate field, and stores the result in register X. After exchanging the contents of M(DP) with the contents of register A, an exclusive OR operation is performed between register X and the value j in the immediate field, and stores the result in register X. Subtracts 1 from the contents of register Y. As a result of subtraction, when the contents of register Y is 15, the next instruction is skipped. After exchanging the contents of M(DP) with the contents of register A, an exclusive OR operation is performed between register X and the value j in the immediate field, and stores the result in register X. Adds 1 to the contents of register Y. As a result of addition, when the contents of register Y is 0, the next instruction is skipped. Continuous (Y) = 0 (Y) = 15 (Y) = 15 (Y) = 0

FunctionMnemonic Hexadecimal notation Number of words Number of cycles Parameter Type of instructions D 8 D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 MITSUBISHI ELECTRIC46 MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER LA n TABP p AM AMC A n SC RC SZC CMA RAR LGOP (A) ← n n = 0 to 15 (SK(SP)) ← (PC) (SP) ← (SP) + 1 (PC H ) ← p, p=0 to 7 (Note) (PCL) ← (DR2–DR 0, A3–A0) When URS=0, (B) ← (ROM(PC))7 to 4 (A) ← (ROM(PC))3 to 0 When URS=1, (CY) ← (ROM(PC))8 (B) ← (ROM(PC))7 to 4 (A) ← (ROM(PC))3 to 0 (SP) ← (SP) – 1 (PC) ← (SK(SP)) (A) ← (A) + (M(DP)) (A) ← (A) + (M(DP))+ (CY) (CY) ← Carry (A) ← (A) + n n = 0 to 15 (CY) ← 1 (CY) ← 0 (CY) = 0 ? (A) ← (A) → CY → A 3A2A1A0 Logic operation instruction XOR, OR, AND Arithmetic operation 0B n 09 p 00 A 00 B 0A n 00 7 00 6 02 F 01 C 01 D 04 1 01011n 3 n2 n1 n0 01001p 3 p2 p1 p0 000001010 000001011 01010n 3 n2 n1 n0 000000111 000000110 000101111 000011100 000011101 001000001 MACHINE INSTRUCTIONS (CONTINUED) Note: p is 0 to 7 for M34282M1, p is 0 to 15 for M34282M2/E2.

Skip condition Detailed description Carry flag CY MITSUBISHI ELECTRIC 47 MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER Continuous Overflow = 0 (CY) = 0 Loads the value n in the immediate field to register A. When the LA instructions are continuously coded and executed, only the first LA instruction is executed and other LA instructions coded continuously are skipped. Transfers bits 7 to 4 to register B and bits 3 to 0 to register A when URS flag is cleared to “0.” These bits 7 to 0 are the ROM pattern in address (DR

2 DR1 DR0 A3 A2 A1 A0) specified by registers A and D in

page p. Transfers bit 8 of ROM pattern is transferred to flag CY when URS flag is set to “1” (after the URSC instruction is executed). (One of stack is used when the TABP p instruction is executed.) Adds the contents of M(DP) to register A. Stores the result in register A. The contents of carry flag CY remains unchanged. Adds the contents of M(DP) and carry flag CY to register A. Stores the result in register A and carry flag CY. Adds the value n in the immediate field to register A. The contents of carry flag CY remains unchanged. Skips the next instruction when there is no overflow as the result of operation. Sets (1) to carry flag CY. Clears (0) to carry flag CY. Skips the next instruction when the contents of carry flag CY is “0.” Stores the one‘s complement for register A‘s contents in register A. Rotates 1 bit of the contents of register A including the contents of carry flag CY to the right. Executes the logic operation selected by logic operation selection register LO between the contents of register A and register E, and stores the result in register A.

FunctionMnemonic Hexadecimal notation Number of words Number of cycles Parameter Type of instructions D 8 D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 MITSUBISHI ELECTRIC48 MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER SB j RB j SZB j SEAM SEA n B a BL p, a BA a BLA p, a (Mj(DP)) ← 1 j = 0 to 3 (Mj(DP)) ← 0 j = 0 to 3 (Mj(DP)) = 0 ? j = 0 to 3 (A) = (M(DP)) ? (A) = n ? n = 0 to 15 (PC L) ← a6–a0 (PCH ) ← p (PCL) ← a6–a0 (Note) (PCL) ← (a6–a4, A3–A0) (PCH ) ← p (PCL) ← (a6–a4, A3–A0) (Note) 0010111j 1 j0 0010011j 1 j0 0001000j 1 j0 000100110 000100101 01011n 3 n2 n1 n0 11a 6 a5 a4 a3 a2 a1 a0 00011p 3 p2 p1 p0 11a 6 a5 a4 a3 a2 a1 a0 000000001 11a 6 a5 a4 a3 a2 a1 a0 000010000 11a 6 a5 a4 p3 p2 p1 p0 05 C 04 C 02 j 02 6 02 5 0B n 18 a 03 p 18 a 00 1 18 a 01 0 18 p Bit operation Comparisonoperation Note: p is 0 to 7 for M34282M1, p is 0 to 15 for M34282M2/E2. Branch operation MACHINE INSTRUCTIONS (CONTINUED)

Skip condition Detailed description Carry flag CY MITSUBISHI ELECTRIC 49 MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER Sets (1) the contents of bit j (bit specified by the value j in the immediate field) of M(DP). Clears (0) the contents of bit j (bit specified by the value j in the immediate field) of M(DP). Skips the next instruction when the contents of bit j (bit specified by the value j in the immediate field) of M(DP) is “0.” Skips the next instruction when the contents of register A is equal to the contents of M(DP). Skips the next instruction when the contents of register A is equal to the value n in the immediate field. Branch within a page : Branches to address a in the identical page. Branch out of a page : Branches to address a in page p. Branch within a page : Branches to address (a 6 a5 a4 A3 A2 A1 A0) determined by replacing the low- order 4 bits of the address a in the identical page with register A. Branch out of a page : Branches to address (a6 a5 a4 A3 A2 A1 A0) determined by replacing the low- order 4 bits of the address a in page p with register A. (Mj(DP)) = 0 j = 0 to 3 (A) = (M(DP)) (A) = n n = 0 to 15

FunctionMnemonic Hexadecimal notation Number of words Number of cycles Parameter Type of instructions D 8 D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 MITSUBISHI ELECTRIC50 MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER BM a BML p, a BMLA p, a RT RTS T1AB TAB1 TV1A SNZT1 T2AB 1a a 07 p 1aa 05 0 1a p 04 4 04 5 047 057 05B 042 088 (SK(SP)) ← (PC) (SP) ← (SP) + 1 (PC H ) ← 2 (PCL) ← a6–a0 (SK(SP)) ← (PC) (SP) ← (SP) + 1 (PCH ) ← p (PCL) ← a6–a0 (Note) (SK(SP)) ← (PC) (SP) ← (SP) + 1 (PCH ) ← p (PCL) ← (a6–a4, A3–A0) (Note) (SP) ← (SP) – 1 (PC) ← (SK(SP)) (SP) ← (SP) – 1 (PC) ← (SK(SP)) at timer 1 stop (V10=0) at timer 1 operating (V10=1) (B) ← (T17–T14) (A) ← (T13–T10) (T1F) = 1 ? After skipping the next instruction (T1F) ← 0 (R2L7–R2L 4) ← (B) (R2L3–R2L 0) ← (A) (T27–T24) ← (B), (T23–T20) ← (A) 10a 6 a5 a4 a3 a2 a1 a0 00111p 3 p2 p1 p0 10a 6 a5 a4 a3 a2 a1 a0 001010000 10a 6 a5 a4 p3 p2 p1 p0 001000100 001000101 001000111 001010111 001011011 001000010 010001000 Subroutine operation Return operation MACHINE INSTRUCTIONS (CONTINUED) Note : p is 0 to 7 for M34282M1, and p is 0 to 15 for M34282M2/E2. Timer operation

Skip condition Detailed description Carry flag CY MITSUBISHI ELECTRIC 51 MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER Skip at uncondition (T1F) = 1 Call the subroutine in page 2 : Calls the subroutine at address a in page 2. Call the subroutine : Calls the subroutine at address a in page p. Call the subroutine : Calls the subroutine at address (a 6 a5 a4 A3 A2 A1 A0) determined by replacing the low-order 4 bits of address a in page p with register A. Returns from subroutine to the routine called the subroutine. Returns from subroutine to the routine called the subroutine, and skips the next instruction at uncondition. At timer 1 stop (V1 0 = 0), transfers the contents of register A and register B to timer 1 and reload register R1. At timer 1 operating (V10 = 1), transfers the contents of register A and register B to reload register R1. Transfers the contents of timer 1 to registers A and B. Transfers the contents of register A to registers V1. Skips the next instruction when the contents of T1F flag is “1.” After skipping, clears (0) to T1F flag. Transfers the contents of register A and register B to timer 2 and reload register R2L.

FunctionMnemonic Hexadecimal notation Number of words Number of cycles Parameter Type of instructions D 8 D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 MITSUBISHI ELECTRIC52 MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER MACHINE INSTRUCTIONS (CONTINUED) Carrier wave control operation TAB2 TV2A SNZT2 T2HAB T2R2L SCAR RCAR CLD RD SD SZD OEA IAE OGA IAG 001000000 001011010 001010010 010001001 001010011 010000111 010000110 000010001 000010100 000010101 000100100 000101011 010000100 001010110 010000000 000101000 040 05A 052 089 053 087 086 011 014 015 024 02B 084 056 080 028 (B) ← (T2 (T2F) = 1 ? After skipping the next instruction (T2F) ← 0 (R2H 7–R2H 4) ← (B) (R2H 3–R2H 0) ← (A) (T27–T24) ← (R2L7–R2L 4) (T23–T20) ← (R2L3–R2L 0) (CAR) ← 1 (CAR) ← 0 (D) ← 0 (D(Y)) ← 0 (Y) = 0 to 7 (D(Y)) ← 1 (Y) = 0 to 7 (D(Y)) = 0 ? (Y) = 4 to 7 (A2–A0) ← (E2–E0) (G) ← (A) (A) ← (G) Input/Output operation Timer operation

Skip condition Detailed description Carry flag CY MITSUBISHI ELECTRIC 53 MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER Transfers the contents of timer 2 to registers A and B. Transfers the contents of register A to registers V2. Skips the next instruction when the contents of T2F flag is “1.” After skipping, clears (0) to T2F flag. Transfers the contents of register A and register B to reload register R2H. Transfers the contents of reload register R2L to timer 2. Sets (1) to port CARR output flag (CAR). Clears (0) to port CARR output flag (CAR). Clears (0) to port D (high-impedance state). Clears (0) to a bit of port D specified by register Y (high-impedance state). Sets (1) to a bit of port D specified by register Y. Skips the next instruction when a bit of port D specified by register Y is “0.” Outputs the contents of register A to port E. Transfers the contents of port E to register A. Outputs the contents of register A to port G. Transfers the contents of port G to register A. (T2F) = 1 (D(Y)) = 0 (Y) = 4 to 7

FunctionMnemonic Hexadecimal notation Number of words Number of cycles Parameter Type of instructions D 8 D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 MITSUBISHI ELECTRIC54 MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER 000 00 D 00 3 05 9 05 8 08 2 08 F 08 E 00 F NOP POF SNZP CCK TLOA URSC TPU0A TPU1A WRST 000000000 000001101 000000011 001011001 001011000 010000010 010001111 010001110 000001111 (PC) ← (PC) + 1 RAM back-up (P) = 1 ? STCK changes to f(X IN) (LO1, LO0) ← (A1, A0) (URS) ← 1 (PU03–PU0 0) ← (A3–A0) (PU13–PU1 0) ← (A3–A0) (WDF1) ← 0 Other operation

Skip condition Detailed description Carry flag CY MITSUBISHI ELECTRIC 55 MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER (P) = 1 No operation Puts the system in RAM back-up state. Skips the next instruction when P flag is “1.” After skipping, P flag remains unchanged. System clock (STCK) changes to f(X IN) from f(XIN)/8. Execute this CCK instruction at address 0 in page Transfers the contents of register A to the logic operation selection register LO. Sets the most significant ROM code reference enable flag (URS) to “1.” Transfers the contents of register A to register PU0. Transfers the contents of register A to register PU1. Initializes the watchdog timer flag (WDF1).

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER INSTRUCTION CODE TABLE D 3– D 0 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 A B C D E F XAM D 8–D 4 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10000 11000 10111 11111 10–17 NOP RC SC AM AMC TYA TBA BLA CLD INY RD SD DEY TEAB CMA RAR TAB TAY SZB SZB SZB SZB SEAn SEAM TDA TABE SZC RT RTS RB RB RB RB IAE SB SB SB SB TABP TABP TABP TABP OEA BM B BM B BM B BM B BM B BM B BM B BM B BM B BM B BM B BM B BM B BM B BM B BM B BA BL BL BL BL TAB2 TV2A BMLA XAM XAM XAM TAM TAM TAM TAM XAMI XAMI XAMI XAMI XAMD XAMD XAMD XAMD BML BML BML BML A LA A A A A A A A A A A A A A A A LA LA LA LA LA LA LA LA LA LA LA LA LA LA LA 18–1F LXY 0,0 LXY 1,0 LXY 2,0 LXY 0,1 LXY 1,1 LXY 2,1 LXY 0,2 LXY 1,2 LXY 2,2 LXY 0,3 LXY 1,3 LXY 2,3 LXY 0,4 LXY 1,4 LXY 2,4 LXY 0,5 LXY 1,5 LXY 2,5 LXY 0,6 LXY 1,6 LXY 2,6 LXY 0,7 LXY 1,7 LXY 2,7 SNZP OGA IAG RCAR POF LXY 3,0 LXY 3,1 LXY 3,2 LXY 3,3 LXY 3,4 LXY 3,5 LXY 3,6 LXY 3,7 CCK TPU0A LXY 0,8 LXY 1,8 LXY 2,8 LXY 0,9 LXY 1,9 LXY 2,9 LXY 0,10 LXY 1,10 LXY 2,10 LXY 011 LXY 1,11 LXY 2,11 LXY 0,12 LXY 1,12 LXY 2,12 LXY 0,13 LXY 1,13 LXY 2,13 LXY 0,14 LXY 1,14 LXY 2,14 LXY 0,15 LXY 1,15 LXY 2,15 LXY 3,8 LXY 3,9 LXY 3,10 LXY 3,11 LXY 3,12 LXY 3,13 LXY 3,14 LXY 3,15 TABP TABP TABP TABP 7BL BL BL BL BML BML BML BML LGOP SZD SNZT1 TV1A WRST BL BML BLA BMLA SEA 1 1 a a a a a a a 1 0 a a a a a a a 1 1 a a a p p p p 1 0 a a a p p p p 0 1 0 1 1 n n n n BA 1 1 a a a a a a a 0 0 0 1 0 1 0 1 1 SZD TLOA T1AB TAB1 URSC Hex. notation The above table shows the relationship between machine language codes and machine language instructions. D3–D 0 show the low-order 4 bits of the machine language code, and D8–D 4 show the high-order 5 bits of the machine language code. The hexadecimal representation of the code is also provided. There are one-word instructions and two-word instructions, but only the first word of each instruction is shown. Do not use the code marked “–.” The codes for the second word of a two-word instruction are described below. The second word BL* BL* BL* BL* BL* BL* BL* BL* SNZT2 T2R2L BML* BML* BML* BML* BML* BML* BML* BML* TPU1A SCAR T2AB T2HAB TABP TABP TABP 10* TABP 11* TABP 12* TABP 13* TABP 14* TABP 15* * cannot be used in the M34282M1.

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER REGISTER STRUCTURE V12 V11 V10 Timer control register V1 Auto-control output by timer 1 is invalid Auto-control output by timer 1 is valid Carrier wave output (CARRY) Bit 5 of watchdog timer (WDT) Stop (Timer 1 state retained) Operating Carrier wave output auto-control bit Timer 1 count source selection bit Timer 1 control bit at reset : 0002 Wat RAM back-up : 0002 V13 V12 V11 V10 Timer control register V1 To expand “H” interval is invalid To expand “H” interval is valid (when V22=1 selected) Carrier wave generation function invalid Carrier wave generation function valid f(X IN) f(XIN)/2 Stop (Timer 2 state retained) Operating Carrier wave “H” interval expansion bit Carrier wave generation function control bit Timer 2 count source selection bit Timer 2 control bit at reset : 00002 Wat RAM back-up : 00002 at reset : 002 at RAM back-up : 002 W LO1 LO LO 1 LO 0 Logic operation selection bits Logic operation selection register LO Logic operation function Exclusive logic OR operation (XOR) OR operation (OR) AND operation (AND) Not available PU0 3 PU0 2 PU0 1 PU0 0 Pull-down transistor OFF, key-on wakeup invalid Pull-down transistor ON, key-on wakeup valid Pull-down transistor OFF, key-on wakeup invalid Pull-down transistor ON, key-on wakeup valid Pull-down transistor OFF, key-on wakeup invalid Pull-down transistor ON, key-on wakeup valid Pull-down transistor OFF, key-on wakeup invalid Pull-down transistor ON, key-on wakeup valid Ports G 2, G3 pull-down transistor control bit Ports G0, G1 pull-down transistor control bit Port E1 pull-down transistor control bit Port E0 pull-down transistor control bit Pull-down control register PU0 at reset : 0000 2 at RAM back-up : state retained W PU1 3 PU1 2 PU1 1 PU1 0 Pull-down transistor OFF, key-on wakeup invalid Pull-down transistor ON, key-on wakeup valid Pull-down transistor OFF, key-on wakeup invalid Pull-down transistor ON, key-on wakeup valid Pull-down transistor OFF, key-on wakeup invalid Pull-down transistor ON, key-on wakeup valid Pull-down transistor OFF, key-on wakeup invalid Pull-down transistor ON, key-on wakeup valid Port D 7 pull-down transistor control bit Port D6 pull-down transistor control bit Port D5 pull-down transistor control bit Port D4 pull-down transistor control bit Pull-down control register PU1 at reset : 00002 at RAM back-up : state retained W

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER ABSOLUTE MAXIMUM RATINGS Parameter Supply voltage Input voltage Output voltage Power dissipation Operating temperature range Storage temperature range Conditions Ta = 25 °C Unit V V V mW Ratings –0.3 to 5 –0.3 to V DD +0.3 –0.3 to VDD +0.3 300 –20 to 85 –40 to 125 Symbol V DD VI VO Pd Topr Tstg RECOMMENDED OPERATING CONDITIONS (Ta = –20 °C to 85 °C, VDD = 1.8 V to 3.6 V, unless otherwise noted) Parameter Supply voltage RAM back-up voltage (at RAM back-up mode) Supply voltage “H” level input voltage Ports D 4–D 7, E, G “H” level input voltage XIN “L” level input voltage Ports D4–D 7, E, G “L” level input voltage XIN “H” level peak output current Ports D, E1, G “H” level peak output current Port E0 “H” level peak output current CARR “L” level peak output current CARR “H” level average output current Ports D, E1, G “H” level average output current Port E0 “H” level average output current CARR “L” level average output current CARR System clock frequency Voltage drop detection circuit detection voltage Voltage drop detection circuit low voltage determination time Power-on reset circuit valid power source rising time Limits Max. 3.6 3.6 VDD VDD 0.2VDD 0.2VDD –24 –20 –12 –10 500 1.80 1.56 1.2 Typ. 1.50 0.2 Min. 1.8 1.1 0.7VDD 0.8VDD 1.10 1.40 Symbol VDD VRAM VSS VIH VIH VIL VIL IOH (peak) IOH (peak) IOH (peak) IOL (peak) IOH (avg) IOH (avg) IOH (avg) IOL (avg) f(XIN) VDET TDET TPON Unit V V V V V V V mA mA mA mA mA mA mA mA MHz kHz V ms ms when STCK = f(XIN)/8 selected when STCK = f(XIN) selected Note: The average output current ratings are the average current value during 100 ms. Conditions VDD = 3.0 V VDD = 3.0 V VDD = 3.0 V VDD = 3.0 V VDD = 3.0 V VDD = 3.0 V VDD = 3.0 V VDD = 3.0 V VDD = 3.0 V VDD = 3.0 V VDD = 3.0 V VDD = 3.0 V Ceramic resonance Ceramic resonance Ta=25 °C When supply voltage passes the detected voltage at ±50V/s. VDD = 0 to 2.2 V

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER Parameter “L” level output voltage Port CARR “L” level output voltage XOUT “H” level output voltage Ports D, E1, G “H” level output voltage Port E0 “H” level output voltage CARR “H” level output voltage X OUT “L” level input current Ports D4–D 7, E, G “H” level input current Ports E0, E1 Output current at off-state Ports D, E0, E1, G Supply current (when operating) Supply current (at RAM back-up) Pull-down resistor value Ports D4–D 7, E, G Feedback resistor value between XIN–XOUT Test conditions IOL = 2 mA IOL = 0.2 mA IOH = –2 mA IOH = –12 mA IOH = –10 mA IOH = –0.2 mA VI = VSS VI = VDD Pull-down transistor in off-state V O = VSS f(XIN) = 4.0 MHz f(XIN) = 500 kHz Ta = 25 °C VDD = 3 V, VI = 3 V LimitsSymbol VOL VOL VOH VOH VOH VOH IIL IIH IOZ IDD R PH R OSC Unit V V V V V V µA µA µA µA µA µA µA kΩ kΩ Max. 0.9 0.9 800 500 0.5 300 3200 Typ.Min. 2.1 1.5 1.0 2.1 700

ELECTRICAL CHARACTERISTICS

(Ta = –20 °C to 85 °C, VDD = 3 V, unless otherwise noted) BASIC TIMING DIAGRAM System clock Ports D, E, G output Ports D, E, G input STCK Parameter Pin name Machine cycle Mi Mi+1 D 0–D 7,E0,E1 G 0–G 3 D 4–D 7 E0–E2 G 0–G 3 400 250 0.1 150

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER Table 10 Product of built-in PROM version PROM size (✕ 9 bits) 2048 words RAM size (✕ 4 bits) 64 words Product M34282E2GP ROM type One Time PROM [shipped in blank] Package 20P2E/F-A BUILT-IN PROM VERSION In addition to the mask ROM versions, the 4282 Group has the One Time PROM versions whose PROMs can only be written to and not be erased. The built-in PROM version has functions similar to those of the mask ROM versions, but it has PROM mode that enables writing to built-in PROM. Table 10 shows the product of built-in PROM version. Figure 27 and 28 show the pin configurations of built-in PROM versions. The One Time PROM version has pin-compatibility with the mask ROM version. Fig. 27 Pin configuration of built-in PROM version PIN CONFIGURATION (TOP VIEW) VSS D D 2 D 3 D 4 D 5 D 1 D 0 CARR VDD D 6 G 3 G 2 XIN XOUT G 0 G 1 M34282E2GP Outline 20P2E/F-A

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER (1) PROM mode (serial input/output) The M34282E2GP has a PROM mode in addition to a normal operation mode. It has a function to serially input/output the command codes, addresses, and data required for operation (e.g., read and program) on the built-in PROM using only a few pins. This mode can be selected by setting pins SDA (serial data input/output), SCLK (serial clock input), PGM and V PP to “H” after connecting wires as shown in Figure 28 and powering on the VDD pin, and then applying 12.5V to the VPP pin. In the PROM mode, three types of software commands (read, program, and program verify) can be used. Clock-synchronous serial I/O is used, beginning from the LSB (LSB first). Refer to the “Mitsubishi Microcomputer Development Support Tools” Hompage (http://www.tool-spt.maec.co.jp/ index_e.htm). about the serial programmer for the Mitsubishi single-chip microcomputers. Fig. 28 Pin configuration of built-in PROM version (continued) PIN CONFIGURATION (TOP VIEW) SDA SCLK PGM Vpp Vss VDD D 0 D 1 D 2 D 3 VDD CARR D 7 D 6 D 5 D 4 20V SS G 1 G 2 G 3 G 0 XIN XOUT M34282E2GP * : connected to the ceramic resonance circuit. Note: The state of disconnected pins are the same as that at reset. Outline 20P2E/F-A

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER Number of transfer In the first transfer, the command code is input. Then, address input or data input/output is performed according to the contents of the command code. Table 11 shows the software command used in the PROM mode. The following explains each software command. (2) Functional outline In the PROM mode, data is transferred with the clock- synchronous serial input/output. The input data is read through the SDA pin into the internal circuit synchronously with the rising edge of the serial clock pulse. The output data is output from the SDA pin synchronously with the falling edge of the serial clock pulse. Data is transferred in units of 8 bits. Table 11 Software command Command Read Program Program verify First command code input 1516 2516 3516 Second Read address L (input) Program address L (input) Program address L (input) Fourth Read data L (output) Program data L (input) Program data L (input) Third Read address H (input) Program address H (input) Program address H (input) Number of transfer Command Read Program Program verify Fifth Read data H (output) Program data H (input) Program data H (input) Seventh Verify data H (output) Sixth Verify data L (output) (3) Read Input the command code 1516 in the first transfer. Proceed and input the low-order 8 bits and the high-order 8 bits of the address and pull the PGM pin to “L.” When this is done, the contents of input address is read and stored into the internal data latch. When the PGM pin is released back to “H ” and serial clock is input to the SCLK pin, the low-order 8 bits and high-order 8 bits of read data which have been stored into the data latch, are serially output from the SDA pin. Note: When outputting the read data, the SDA pin is switched for output at the first falling of the serial clock. The SDA pin is placed in the high-impedance state during the th(C–E) period after the last rising edge of the serial clock (at the 16th bit). Fig. 29 Timing at reading tCR tRC 10101000 A0 A7 Command code input (1516) Read address input (L) Read address input (H) SCLK SDA PGM Read tWR tCH D0 D7 Read data output (L) tCH Read data output (H) tCH 0000000 A8A9 00000 A10

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER Fig. 31 Timing at program verifying and pull the PGM pin to “L.” When this is done, the program data is programmed to the specified address. (4) Program Input command code 2516 in the first transfer. Proceed and input the low-order 8 bits and high-order 8 bits of the address and the low-order 8 bits and high-order 8 bits of program data, Fig. 30 Timing at programming (5) Program verify Input command code 3516 in the first transfer. Proceed and input the low-order 8 bits and high-order 8 bits of the address and the low-order 8 bits and high-order 8 bits of program data, and pull the PGM pin to “L.” When this is done, the program data is programmed to the specified address. Then, when the PGM pin is pulled to “L” again after it is released back to “H,” the address programmed with the program command is read and verified and stored into the internal data latch. When the PGM pin is released back to “H ” and serial clock is input to the SCLK pin, the verify data that has been stored into the data latch is serially output from the SDA pin. Note: When outputting the verify data, the SDA pin is switched for output at the first falling of the serial clock. The SDA pin is placed in the high-impedance state during the th(C–E) period after the last rising edge of the serial clock (at the 16th bit). 10100100 A0 A7 Commanf code input (2516)Program address input (L)Program address input (H) SCLK SDA PGM Program tCH D0 D7 Program data input (L) tCP tWP tCH Program data input (H) tCH 0000000 tCH A8A9 00000 A10 10101100 A0 A7 Command code input (3516) Program address input (L)Program address input (H) SCLK SDA PGM tCH D0 D7 Program data input (L) tCP tWP tCH Program data input (H) tCH 0000000 tCH A8 A9 00000 Program tCR tRC SCLK SDA PGM Verify tWR D0 D7 Verify data output (L) Verify data output (H) tCH 0000000 A10

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER PROGRAM ALGORITHM FLOW CHART START VDD = 4V,VPP = 12.5V ADRS = first location X=0 WRITE PROGRAM DATA X = X + 1 PROGRAM ONE PULSE OF 0.2ms X = 25? VERIFY BYTE? YES NO FAIL PASS LAST ADRS? NO YES READ COMMAND DEVICE PASSED VERIFY BYTE? PASS FAIL DEVICE FAILED INC ADRS 3516 DIN WRITE PROGRAM-VERIFY COMMAND VERIFY ALL BYTE? FAIL PASS 1516 PROGRAM PULSE OF 0.2Xms DURATION WRITE PROGRAM COMMAND 2516 WRITE PROGRAM DATA DIN VDD = 4V,VPP = 4V

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER TIMING REQUIREMENT CONDITION AND SWITCHING CHARACTERISTICS (Ta = 25 °C, VDD = 4.0 V, VPP = 12.5 V) Max. 0.21 5.25 180 TIMING DIAGRAM Symbol tCH tCR tWR tRC tCP tWP tOWP tC(CK) tW(CKH) tW(CKL) tr(CK) tf(CK) td(C–Q) th(C–Q) th(C–E) tsu(D–C) th(C–D) Parameter Serial transfer width time Read wait time after transfer Read pulse width Transfer wait time after read Program wait time after transfer Program pulse width Added program pulse width SCLK input cycle time SCLK “H ” pulse width SCLK “L” pulse width SCLK rising time SCLK falling time SDA output delay time SDA output hold time SDA output hold time (only for 16th bit) SDA input set-up time SDA input hold time Unit µs µs ns µs µs ms ms µs ns ns ns ns ns ns ns ns ns Min. 2.0 2.0 500 2.0 2.0 0.19 0.19 1.0 450 450 100 180 Limits tC(CK) tW(CKH)tW(CKL) td(C-Q) th(C-E) tf(CK) tr(CK) tsu(D-C) th(C-D) SCLK SDA output SDA input th(C-Q) Measurement condition Output timing voltage: VOL = 0.8 V, VOH = 2.0 V Input timing voltage: VIL = 0.2 VD D, VIH = 0.8 VDD

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER Fig. 32 Flow of writing and test of the product shipped in blank (6) Notes on handling ➀ A high-voltage is used for writing. Take care that overvoltage is not applied. Take care especially at turning on the power. ➁ For the One Time PROM version, Mitsubishi Electric corp. does not perform PROM writing test and screening in the assembly process and following processes. In order to improve reliability after writing, performing writing and test according to the flow shown in Figure 32 before using is recommended. Writing with PROM programmer Screening (Leave at 150 °C for 40 hours) (Note) Verify test with PROM programmer Function test in target device Since the screening temperature is higher than storage temperature, never expose the microcomputer to 150 °C exceeding 100 hours. Note:

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER PACKAGE OUTLINE SSOP20-P-225-0.65 Weight(g) JEDEC Code 0.08 Alloy 42/Cu Alloy 20P2E/F-A Plastic 20pin 225mil SSOP Symbol Min Nom Max A b c D E L y Dimension in Millimeters H E .170 .130 .46 .34 .26 .30 .01 .10 .151 .220 .150 .56 .44 .650 .46 .50 .01 .85 .20 .451 .320 .20 .66 .54 .66 .70 .10 b2 – .350 – 0° – 10° e 20 11 101 H E E D e y F A A2 A1 L c e b2 Recommended Mount Pad Detail F x –Z1 0.325 0.475 0.13 z G b x M Detail G z

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER Customer’s Parts Number Note: The fonts and size of characters are standard Mitsubishi type. Mitsubishi IC catalog name and Mitsubishi lot number Mitsubishi IC catalog name and Mitsubishi lot number Notes 1 : The mark field should be written right aligned. 2 : The fonts and size of characters are standard Mitsubishi type. 3 : Customer’s Parts Number can be up to 4 characters: Only 0 to 9, A to Z, +, -, /, (, ), &, ©, . (period), and , (comma) are usable. 20P2E/F-A (20-PIN SSOP) MARK SPECIFICATION FORM Mitsubishi IC catalog name Please choose one of the marking types below (A, B), and enter the Mitsubishi IC catalog name and the special mark (if needed). A. Standard Mitsubishi Mark B. Customer’s Parts Number + Mitsubishi IC Catalog Name Mitsubishi IC catalog name Mitsubishi IC catalog name 20 11 101 Mitsubishi lot number (4-digit or 5-digit) 20 11 101 ROM number (3-digit) Mitsubishi lot number (4-digit or 5-digit)

© 2001 MITSUBISHI ELECTRIC CORP. New publication, effective July. 2001. Specifications subject to change without notice. Notes regarding these materials

• These materials are intended as a reference to assist our customers in the selection of the Mitsubishi semiconductor product best suited to the customer’s application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Mitsubishi Electric Corporation or a third party.
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• Mitsubishi Electric Corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use.
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• Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for further details on these materials or the products contained therein. Keep safety first in your circuit designs!
• Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non-flammable material or (iii) prevention against any malfunction or mishap. SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

Rev. Rev. No. date

1.0 First Edition 000619

1.1 Page 12 (2) Precautions revised. 000725 Page 13 (3) Timer 1, (4) Timer 2 revised. Page 22 ➂ Timer revised. 1.2 Pages 7, 8, 14, 18, 21: Character fonts errors revised. 000823

1.3 All pages: 010703

“PRELIMINARY Notice: This is not a final specification. Some parametric limits are subject to change.” eliminated. Page 1: Product name table; “Under development” eliminated. Page 9: 48 words ✕ 4 bits (128 bits) → 48 words ✕ 4 bits (192 bits) Page 21: ROM ORDERING METHOD revised. Page 61: “Mitsubishi Microcomputer Development Support Tools” Hompage (http://www.tool-spt.m esc.co.jp/index_e.htm) REVISION DESCRIPTION LIST 4282 GROUP DATA SHEET (1/1) Revision Description